JP6836982B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and relates to a technique effective when applied to a semiconductor device including, for example, a semiconductor chip made of silicon carbide and having a reference voltage generation circuit formed therein.

Patent Document 1 (Japanese Unexamined Patent Publication No. 2003-258105) describes a technique capable of reducing the temperature dependence of the output voltage from the reference voltage generation circuit. In this technique, in order to reduce the temperature dependence of the output voltage, an example is described in which a polysilicon resistor or an on-resistance of a field effect transistor is used as a resistor which is a component of a reference voltage generation circuit.

Japanese Unexamined Patent Publication No. 2003-258105

As a semiconductor device capable of operating at a high temperature, there is a semiconductor device having a semiconductor chip made of silicon carbide (hereinafter, may be referred to as SiC). In a semiconductor device using silicon carbide, the bandgap of silicon carbide, which exhibits heat resistance, is about three times the bandgap of silicon (Si), so that it is carbonized as a component of the information processing device even under high temperature conditions. A semiconductor device using silicon can be adopted. Then, a reference voltage generation circuit having high heat resistance for supplying electric power to this information processing device can also be realized. In this regard, in order to enable the reference voltage generation circuit to be used even in a high temperature environment, a reference voltage generation circuit capable of supplying a stable output voltage even in a high temperature environment is desired. That is, it is desired that the temperature dependence of the output voltage output from the reference voltage generation circuit is small even in a high temperature environment.

An object of the present invention is to provide a technique capable of reducing the temperature dependence of the output voltage output from the reference voltage generation circuit in a semiconductor device including the reference voltage generation circuit.

Other challenges and novel features will become apparent from the description and accompanying drawings herein.

The semiconductor device in one embodiment includes a semiconductor chip containing silicon carbide as a main component and having a reference voltage generation circuit formed therein. Here, the reference voltage generation circuit includes a resistance element and a diode, and the resistance element is composed of a diffusion resistance element into which an acceptor is introduced.

According to one embodiment, the temperature dependence of the output voltage output from the reference voltage generation circuit can be reduced in a wide temperature range.

It is a circuit diagram which shows the structural example of the reference voltage generation circuit. It is a graph which shows the relationship between temperature and activation rate. In acceptor concentration in the silicon carbide (N _A) introduced the aluminum 3 × 10 ¹⁷ cm ^-3 p-type diffused resistor element is a graph showing the relationship between temperature and the sheet resistance. It is a graph which shows typically the IV characteristic of the diode using silicon. It is a graph which shows typically the IV characteristic of the diode using silicon carbide. It is a graph which shows the temperature dependence of the forward voltage of the diode using silicon carbide when the load current is 1 μA. FIG. 5 is a graph showing the relationship between temperature and load current when the resistance element R1 shown in FIG. 1 is composed of a p-type diffusion resistance element composed of a p-type semiconductor region in which aluminum is introduced into silicon carbide. A graph showing the relationship between the temperature and the forward voltage VF when the load current is controlled to be constant, and a graph showing the relationship between the temperature and the forward voltage VF when the load current is changed as shown in FIG. It is a figure which shows. It is a graph which shows the temperature dependence of the output voltage output from the output terminal of the reference voltage generation circuit shown in FIG. It is sectional drawing explaining the device structure of the semiconductor device in embodiment. It is a figure which shows the circuit structure of the reference voltage generation circuit in the modification 1. It is sectional drawing explaining the device structure of the semiconductor device in the modification 1. FIG. It is sectional drawing explaining the device structure of the semiconductor device in the modification 2. FIG. It is sectional drawing explaining another device structure which embodies the technical idea in the modification 2. It is sectional drawing explaining another device structure which embodies the technical idea in the modification 2.

In the following embodiments, when necessary for convenience, the description will be divided into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is the other. It is related to some or all of the modified examples, details, supplementary explanations, etc.

In addition, in the following embodiments, when the number of elements (including the number, numerical value, quantity, range, etc.) is referred to, when it is specified in particular, or when it is clearly limited to a specific number in principle, etc. Except, the number is not limited to the specific number, and may be more than or less than the specific number.

Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or clearly considered to be essential in principle. Needless to say.

Similarly, in the following embodiments, when the shape, positional relationship, etc. of the components or the like are referred to, they are substantially the same unless otherwise specified or when it is considered that this is not the case in principle. It shall include those that are similar to or similar to the shape, etc. This also applies to the above numerical values and ranges.

Further, in all the drawings for explaining the embodiment, the same members are, in principle, given the same reference numerals, and the repeated description thereof will be omitted. In addition, in order to make the drawing easy to understand, hatching may be added even if it is a plan view.

<Configuration example of reference voltage generation circuit>
FIG. 1 is a circuit diagram showing a configuration example of a reference voltage generation circuit. The reference voltage generation circuit shown in FIG. 1 includes a power supply line VL, a ground line GL, a resistance group 100 composed of two resistance elements R1 and a resistance element R2, a diode group 200 consisting of three diodes Q1 to Q3, and a diode group 200. It is composed of five field effect transistors M1 to M5. In the reference voltage generation circuit shown in FIG. 1, of the five field-effect transistors M1 to M5, the field-effect transistor M1 and the field-effect transistor M3 are composed of n-channel field-effect transistors. On the other hand, the field effect transistor M2, the field effect transistor M4, and the field effect transistor M5 are composed of a p-channel field effect transistor.

Here, for example, when the reference voltage generation circuit is integrated in one semiconductor chip, the diodes Q1 to Q3 often adopt a configuration in which the base and collector of the npn bipolar transistor are short-circuited, and the occupied area of the diode Q2 is adopted. Is larger by "K times" the occupied area of the diode Q1 and the occupied area of the diode Q3. At this time, in the reference voltage generation circuit shown in FIG. 1, each cathode of the diodes Q1 to Q3 is connected to the ground wire GL to which the reference potential is supplied.

Further, in the reference voltage generation circuit shown in FIG. 1, the field effect transistor M1 and the field effect transistor M3 form an n-channel current mirror circuit, and the field effect transistor M2 and the field effect transistor M4 form a p-channel current mirror. It constitutes a circuit. Then, in the reference voltage generation circuit shown in FIG. 1, an n-channel current mirror circuit composed of the field-effect transistor M1 and the field-effect transistor M3, and a p-channel current composed of the field-effect transistor M2 and the field-effect transistor M4. Two stages of mirror circuits are stacked in series. The current mirror circuit is a circuit that supplies the same current from the power supply line VL, and has a configuration in which a common potential is supplied to the gate electrode of the field effect transistor M1 and the gate electrode of the field effect transistor M3. The potential of point A and the potential of point B shown in FIG. 1 are equal to each other. As a result, the voltage applied to the circuit composed of the resistor group 100 and the diode group 200 can be made equal. In particular, since the gate electrode of the field-effect transistor M5 is short-circuited with the gate electrode of the field-effect transistor M2 and the gate electrode of the field-effect transistor M4, the field-effect transistor M5 functions as a current source and the field-effect transistor M2 A current having the same current value as the current flowing through the field effect transistor M4 and the current flowing through the field effect transistor M4 can be supplied to the output terminal OT.

The output voltage Vref output from the reference voltage generation circuit configured in this way can be expressed by the following equation (1).

Vref = V _BE3 + (kT / q) × (r2 / r1) × ln (K) ・ ・ ・ Equation (1)
Here, "V _BE3 " represents the base-emitter voltage of the diode Q3, "k" represents the Boltzmann constant, "T" represents the absolute temperature, and "q" represents the elementary charge. .. Further, "r1" indicates the resistance value of the resistance element R1, and "r2" indicates the resistance value of the resistance element R2. Further, "K" indicates the area ratio of the occupied area of the diode Q2 to the occupied area of the diode Q1.

Next, the load current in the reference voltage generation circuit shown in FIG. 1 will be described. The load current is a factor that affects the power consumption of the reference voltage generation circuit, and can be expressed by, for example, the following equation (2).

I = (kT / q) × ln (K) / r1 ・ ・ ・ Equation (2)
From this equation (2), the load current in the reference voltage generation circuit shown in FIG. 1 is the area ratio of the resistance value “r1” of the resistance element R1 and the occupied area of the diode Q2 to the occupied area of the diode Q1 “K”. It can be seen that it is determined by. However, since the design range of the area ratio “K” is narrow, the load current is mainly adjusted by the resistance value “r1” of the resistance element R1. For example, when the load current is set to 1 μA or less in order to reduce the power consumption of the reference voltage generation circuit, the resistance value r1 of the resistance element R1 is several tens, although it depends on the temperature range in which the reference voltage generation circuit is used. Designed from kΩ to several hundred kΩ.

As described above, when the load current is determined by the equation (2), the output voltage Vref is substantially adjusted by the resistance value r2 of the resistance element R2 from the equation (1).

<First basic idea in the embodiment>
As described above, the output voltage Vref output from the reference voltage generation circuit is represented by the equation (1). _{At this time, the "V BE3} ", which is the base-emitter voltage of the diode Q3, has a negative temperature characteristic because it depends on the built-in potential (forward voltage VF) of the pn junction. That is, the higher the temperature, the smaller the built-in potential, so the base-emitter voltage of the diode Q3, "V _BE3, " becomes smaller.

In this regard, the basic idea in the present embodiment is to change _{the temperature dependence of "VBE3} " shown in the first term of the equation (1) to "(kT / q) shown in the second term of the equation (2). ) × (r2 / r1) × ln (K) ”, the idea is to reduce the temperature dependence of the output voltage Vref output from the reference voltage generation circuit.

Here, if the load current is determined by the equation (2), "K" and "r1" in the equation (1) are determined. Therefore, the adjustment of the second term of the equation (1) is substantially performed. It will be adjusted only by the resistance value "r2" of the resistance element R2. Then, in order to cancel the temperature dependence of the first term of the formula (1) in the second term of the formula (1), the first term of the formula (1) has a negative temperature characteristic. Considering the above, the second term of the equation (1) also needs to have a negative temperature characteristic. This is because, at high temperatures, the _{built-in potential that affects "V BE3} " in the first term of equation (1) becomes smaller, and as a result, "V _BE3 " becomes smaller, but in the molecule of the second term in equation (2). This is because the resistance value r2 of the existing resistance element R2 has a negative temperature characteristic. That is, the fact that the resistance value r2 of the resistance element R2 existing in the molecule of the second term of the equation (2) has a negative temperature characteristic means that in the reference voltage generation circuit shown in FIG. 1, the higher the temperature, the higher the temperature. This means that the current flowing through the resistance element R2 becomes large, which means that the current flowing through the diode Q3 becomes large. The increase in the current flowing through the diode Q3 means that the forward voltage of the diode Q3 increases according to Ohm's law, and the increase in the forward voltage lowers the built-in potential of the "_VBE3". As a result, the temperature dependence of the output voltage Vref from the reference voltage generation circuit becomes small.

Therefore, in order to realize the first basic idea in the present embodiment, the resistance element R2 needs to be composed of a resistance element having a negative temperature characteristic. As described above, the first basic idea in the present embodiment is to change _{the temperature dependence of "V BE3} " shown in the first term of the equation (1) to the "(kT) shown in the second term of the equation (2). / Q) × (r2 / r1) × ln (K) ”is the idea of canceling due to the temperature dependence, and in order to embody this first basic idea, the resistance element R2 has a negative temperature characteristic. It must be composed of resistance elements.

<Examination for embodying the first basic idea>
As described above, in order to embody the first basic idea in the present embodiment, it is necessary to adopt the resistance element R2 having a negative temperature characteristic. Therefore, a metal resistance element cannot be used as the resistance element R2. This is because the metal resistance element has a positive temperature characteristic. Next, for example, it is conceivable to adopt a polysilicon resistance element made of a polysilicon film as the resistance element R2. However, the polysilicon resistance element is a unipolar device, and when the temperature becomes high, the influence of electron scattering due to lattice vibration is exerted. growing. As a result, the polysilicon resistance element cannot be adopted as the resistance element R2 because it has a positive temperature characteristic that the resistance value increases as the temperature increases. For the same reason, a diffusion resistor having a semiconductor region made of silicon as a component cannot be used.

In this regard, the situation changes completely in semiconductor devices that use silicon carbide. That is, the diffusion resistance element having a semiconductor region made of silicon carbide as a constituent element has different temperature characteristics from the diffusion resistance element having a semiconductor region made of silicon as a constituent element. That is, the diffusion resistance element having a semiconductor region made of silicon carbide as a constituent element has a negative temperature characteristic.

<Reason why diffusion resistance elements in which conductive impurities are introduced into silicon carbide have negative temperature characteristics>
The reason why the diffusion resistance element in which the conductive impurities are introduced into silicon carbide has a negative temperature characteristic is that the activation rate of the conductive impurities introduced into the semiconductor region made of silicon carbide has a large temperature dependence. Because. FIG. 2 is a graph showing the relationship between temperature and activation rate. In FIG. 2, the broken line shows the temperature dependence of the activation rate of nitrogen when nitrogen (N), which is an n-type impurity (donor), is introduced into the semiconductor region made of silicon carbide. On the other hand, in FIG. 2, the solid line shows the temperature dependence of the activation rate of aluminum when aluminum (Al), which is a p-type impurity (acceptor), is introduced into the semiconductor region made of silicon carbide. At this time, for example, the activation rate of the acceptor is smaller than the activation rate of the donor.

As shown in FIG. 2, it can be seen that the activation rate of both the donor nitrogen and the acceptor aluminum increases as the temperature increases. As a result, for example, in a diffusion resistance device consisting of an n-type semiconductor region in which nitrogen is introduced into silicon carbide, the activation rate of nitrogen increases as the temperature rises, and the conduction band from the donor nitrogen to silicon carbide. As a result of increasing the number of electrons supplied to the device, the resistance value of the diffusion resistance element composed of the n-type semiconductor region becomes low. Therefore, the n-type diffusion resistance device composed of the n-type semiconductor region in which nitrogen is introduced into silicon carbide has a negative temperature characteristic.

On the other hand, for example, even in a p-type diffusion resistance device composed of a p-type semiconductor region in which aluminum is introduced into silicon carbide, the activation rate of aluminum increases as the temperature rises, and the acceptor aluminum has the value of silicon carbide. The amount of electrons filled in the electron band is increased, and many holes are generated in the valence band. As a result, the resistance value of the p-type diffusion resistance element becomes low. Therefore, the p-type diffusion resistance element also has a negative temperature characteristic.

By the above mechanism, the diffusion resistance element (both the n-type diffusion resistance element and the p-type diffusion resistance element) in which conductive impurities are introduced into silicon carbide exhibits negative temperature characteristics.

<Reason for adopting p-type diffusion resistance element>
Here, as shown in FIG. 2, the temperature dependence of the activation rate of aluminum, which is a p-type impurity (acceptor), is greater than the temperature dependence of the activation rate of nitrogen, which is an n-type impurity (donor). You can see that it is. This is because the energy difference between the donor level of nitrogen, which is an n-type impurity (donor), and the lower end of the conduction band of silicon carbide is 0.09 eV, whereas that of aluminum, which is a p-type impurity (acceptor). This is because the energy difference between the acceptor level and the upper end of the valence band of silicon carbide is 0.19 eV. That is, the acceptor level of aluminum, which is a p-type impurity (acceptor), is deeper than the donor level of nitrogen, which is an n-type impurity (donor), and activates the p-type impurity (acceptor). The energy for activating the n-type impurity (donor) is larger than the energy for activating the n-type impurity (donor).

This means that the energy required for the electrons existing in the valence band of silicon carbide to be captured by the acceptor level of the p-type impurity (acceptor) is from the donor level of the n-type impurity (donor) to the conduction band of silicon carbide. It means that it will be greater than the energy that reaches up to. As a result, as shown in FIG. 2, the activation rate of nitrogen, which is an n-type impurity (donor), tends to saturate at a relatively low temperature, whereas the activation of aluminum, which is a p-type impurity (acceptor). The rate tends to be less likely to saturate up to relatively high temperatures.

At this time, the greater the temperature dependence of the activation rate, the greater the difference between the resistance value at low temperature and the resistance value at high temperature. From this, the fluctuation range of the resistance value of the p-type diffusion resistance element becomes larger than the fluctuation range of the resistance value of the n-type diffusion resistance element with respect to the temperature change.

From the above, both the n-type diffusion resistance element and the p-type diffusion resistance element have negative temperature characteristics, and thus satisfy the requirements for embodying the first basic idea in the above-described embodiment. .. However, from the viewpoint of realizing the first basic idea in the above-described embodiment, it is desirable that the adjustment range of the resistance value is large. Therefore, in the present embodiment, for example, the resistance element R2 shown in FIG. 1 is used. A p-type diffusion resistance element is adopted.

Figure 3 is the acceptor concentration (N _A) in the silicon carbide was introduced aluminum 3 × 10 ¹⁷ cm ^-3 p-type diffused resistor element is a graph showing the relationship between temperature and the sheet resistance. In FIG. 3, it can be seen that the sheet resistance of the p-type diffusion resistance element decreases as the temperature increases. That is, it can be seen that the p-type diffusion resistance element in which aluminum is introduced into silicon carbide has a negative temperature characteristic. Specifically, as shown in FIG. 3, the sheet resistance is 140 kΩ ^□ when the temperature is about 40 ° C., whereas the sheet resistance is significantly reduced to ^{30 kΩ □} when the temperature is about 300 ° C. You can see that.

<First feature point in the embodiment>
Summarizing the above, the first characteristic point in the present embodiment is that _{the temperature dependence of "VBE3} " shown in the first term of the above-mentioned formula (1) is changed to the second term of the formula (2). In order to embody the first basic idea in the present embodiment of canceling by the temperature dependence of “(kT / q) × (r2 / r1) × ln (K)” shown, for example, in FIG. The point is that the resistance element R2 shown is composed of a resistance element having a negative temperature characteristic. Specifically, the first characteristic point in the present embodiment is that, for example, the resistance element R2 shown in FIG. 1 is composed of a p-type diffusion resistance element composed of a p-type semiconductor region in which aluminum is introduced into silicon carbide. .. As a result, as a result of embodying the first basic idea in the above-described embodiment, the temperature dependence of the output voltage Vref from the reference voltage generation circuit can be reduced according to the present embodiment.

The semiconductor device according to the present embodiment includes a semiconductor chip containing silicon carbide as a main component and having a reference voltage generation circuit formed therein. At this time, the reference voltage generation circuit includes a resistance element and a diode, and the resistance element is composed of a diffusion resistance element into which an acceptor is introduced.

<Considerations for diodes>
Next, the diodes Q1 to Q3 shown in FIG. 1 are composed of, for example, an n-type bipolar transistor in which an n-type collector in which a donor is introduced and a p-type base in which an acceptor is introduced are short-circuited. At this time, the p-type base of the npn-type bipolar transistor is composed of a diffusion region formed on the silicon carbide substrate. That is, the diodes Q1 to Q3 shown in FIG. 1 also have a p-type base composed of the same conductive type diffusion region as the p-type diffusion resistance element described above. Here, for example, the acceptor introduced in the p-type diffusion resistance element and the acceptor introduced in the p-type base are elements of the same type. Specifically, the acceptor introduced in the p-type diffusion resistance element is aluminum, and the acceptor introduced in the p-type base is also aluminum.

Therefore, even in the p-type base of the diodes Q1 to Q3 shown in FIG. 1, the temperature dependence of the activation rate of aluminum, which is a p-type impurity (acceptor), becomes large as in the p-type diffusion resistance element (see FIG. 2). ). Since the temperature dependence of the activation rate of the p-type impurity (acceptor) becomes large, silicon (silicon) is used for the IV characteristic (current-voltage characteristic) of the diode using silicon carbide. It will be different from the IV characteristic of the diode. This point will be described below.

FIG. 4 is a graph schematically showing the IV characteristics of a diode using silicon. In FIG. 4, the horizontal axis represents the cathode voltage and the vertical axis represents the anode current. As shown in FIG. 4, the IV characteristic of the diode using silicon is that the higher the temperature, the lower the rising voltage (forward voltage) at which the anode current rises, while the gradient of the anode current after the rising voltage is The higher the temperature, the smaller the size.

On the other hand, FIG. 5 is a graph schematically showing the IV characteristics of a diode using silicon carbide. In FIG. 5, the horizontal axis represents the cathode voltage and the vertical axis represents the anode current. As shown in FIG. 5, the IV characteristic of a diode using silicon carbide is that the higher the temperature, the lower the rising voltage (forward voltage) at which the anode current rises, while the gradient of the anode current after the rising voltage is , Unlike diodes using silicon, the higher the temperature, the larger the size. This is because, in the p-type base of a diode using an npn-type bipolar transistor, when the temperature rises, the activation rate of p-type impurities (acceptors) increases, and as a result, the injection of a small number of carriers is promoted and the electrical resistance becomes small. It is probable that it became. As described above, the IV characteristic of the diode using silicon carbide is due to the temperature dependence of the activation rate of the p-type impurity (acceptor) introduced in the diffusion region constituting the p-type base. Will be different from the IV characteristics of the diode using.

As a result, the temperature dependence of the forward voltage of the diode using silicon carbide is different from the temperature dependence of the forward voltage of the diode using silicon. Specifically, FIG. 6 is a graph showing the temperature dependence of the forward voltage of the diode using silicon carbide when the load current is 1 μA. In FIG. 6, the horizontal axis represents the temperature and the vertical axis represents the forward voltage VF. As shown in FIG. 6, the temperature coefficient of the forward voltage in the diode using silicon carbide is -3.7 mV / ° C, which is the temperature coefficient of the forward voltage in the diode using silicon -1.5 mV /. It is about twice as large as that of ° C. to −2.0 mV / ° C. At this time, the fact that the temperature coefficient of the forward voltage increases means that the temperature dependence _{of the base-emitter voltage “V BE3” in the equation (1) increases.} The fact that the temperature dependence of the base-emitter voltage "V _BE3 " in the equation (1) increases means that the temperature dependence of the _{"V BE3} " shown in the first term of the equation (1) is changed to the equation (1). The resistance value "r2" of the resistance element R2 in the first basic idea of canceling due to the temperature dependence of "(kT / q) x (r2 / r1) x ln (K)" shown in the second term of 2). It means that it is necessary to increase the temperature dependence of. This means that the fluctuation range of the resistance value “r2” of the resistance element R2 becomes large, and that the fluctuation range of the resistance value “r2” of the resistance element R2 becomes large means that the size of the resistance element R2 becomes large. It means that there is a need to do it. This leads to an increase in the size of the semiconductor chip forming the reference voltage generation circuit, which leads to an increase in manufacturing cost. Therefore, in the present embodiment, further measures are taken to reduce the temperature coefficient of the forward voltage in the diode using silicon carbide.

<Second basic idea in the embodiment>
The second basic idea in the present embodiment is an idea that the forward voltage increases or decreases depending on the current density in order to reduce the temperature coefficient of the forward voltage in the diode using silicon carbide. That is, since the temperature coefficient of the forward voltage in the diode using silicon carbide is "negative", the forward voltage at low temperature is relatively high, while the forward voltage at high temperature is relatively low. .. On the other hand, the forward voltage of a diode using silicon carbide is relatively small when the current flowing through the diode is small, while it is relatively large when the current flowing through the diode is large. Therefore, the second basic idea in the present embodiment is to reduce the current flowing through the diode using silicon carbide at low temperature to shift the forward voltage in the low temperature direction, while at high temperature, it is carbonized. The idea is to shift in the direction of increasing the forward voltage at high temperatures by increasing the current flowing through the diode using silicon. According to the second basic idea in the present embodiment as described above, the temperature coefficient of the forward voltage in the diode using silicon carbide can be reduced (the slope can be made gentle).

By adopting the second basic idea in the present embodiment as described above, the need to increase the temperature dependence of the resistance value "r2" of the resistance element R2 is reduced, and thereby the resistance element R2 The need to increase the size of the As a result, adopting the second basic idea in the present embodiment leads to the suppression of the increase in size of the semiconductor chip forming the reference voltage generation circuit, and by extension, the manufacture of the semiconductor device including the reference voltage generation circuit. It will be possible to reduce costs.

<Second feature point in the embodiment>
Next, a second feature point that embodies the second basic idea in the above-described embodiment will be described. The second characteristic point in the present embodiment is that, for example, not only the resistance element R2 shown in FIG. 1 but also the resistance element R1 shown in FIG. 1 is composed of a resistance element having a negative temperature characteristic. Specifically, the second characteristic point in the present embodiment is that, for example, the resistance element R1 shown in FIG. 1 is composed of a p-type diffusion resistance element composed of a p-type semiconductor region in which aluminum is introduced into silicon carbide. ..

Here, according to the above equation (2), the load current is inversely proportional to the resistance value “r1” of the resistance element R1. Then, in the present embodiment, the resistance element R1 is composed of a resistance element having a negative temperature characteristic. As a result, the load current at a low temperature becomes smaller because the resistance value “r1” of the resistance element R1 becomes relatively larger. On the other hand, the load current at a high temperature becomes large because the resistance value “r1” of the resistance element R1 becomes relatively small. In this way, at low temperatures, the current flowing through the diode using silicon carbide is automatically reduced to shift the forward voltage at low temperatures in the direction of lowering, while at high temperatures, silicon carbide is used. By increasing the current flowing through the diode, the second basic idea of shifting in the direction of increasing the forward voltage at high temperature can be realized. As a result, according to the second feature point in the present embodiment, it is possible to suppress the increase in size of the semiconductor chip forming the reference voltage generation circuit, which in turn reduces the manufacturing cost of the semiconductor device including the reference voltage generation circuit. It will be possible to reduce the amount.

Specifically, FIG. 7 is a graph showing the relationship between temperature and load current when the resistance element R1 shown in FIG. 1 is composed of a p-type diffusion resistance element composed of a p-type semiconductor region in which aluminum is introduced into silicon carbide. Is. In FIG. 7, the horizontal axis represents the temperature and the vertical axis represents the load current. As shown in FIG. 7, the resistance element R1 shown in FIG. 1 is composed of a p-type diffusion resistance element composed of a p-type semiconductor region in which aluminum is introduced into silicon carbide to obtain a load current value at room temperature (25 ° C.). On the other hand, it can be seen that the load current value at 500 ° C. increases 24 times. In this way, at low temperatures, the current flowing through the diode using silicon carbide is reduced to shift the forward voltage in the direction of lowering the forward voltage at low temperatures, while at high temperatures, the current flowing through the diode using silicon carbide It can be seen that by increasing the value of, the second basic idea of shifting in the direction of increasing the forward voltage at high temperature can be realized.

Specifically, FIG. 8 shows a graph showing the relationship between the temperature and the forward voltage VF when the load current is controlled to be constant, and the temperature and the forward voltage when the load current is changed as shown in FIG. It is a figure which shows the graph which shows the relationship with VF. In FIG. 8, the horizontal axis represents the temperature and the vertical axis represents the forward voltage VF. As shown in FIG. 8, the temperature coefficient when the load current is constant (1 μA) is -3.7 mV / ° C., whereas the temperature coefficient when the load current is changed as shown in FIG. 7 is Is −3.0 mV / ° C, and it can be seen that the temperature is gentle.

<Innovativeness of the second basic idea>
As described above, the second basic idea in the present embodiment is an idea that the forward voltage increases or decreases depending on the current density in order to reduce the temperature coefficient of the forward voltage in the diode using silicon carbide. is there.

The forward voltage of the diode has not only temperature dependence but also current density dependence. In this regard, the conventional reference voltage generation circuit is designed to control the load current to be constant. This is because only the temperature dependence of the forward voltage of the diode becomes apparent. However, in a diode using silicon carbide, if the load current is controlled to be constant, the slope of the temperature coefficient of the forward voltage becomes large as shown in FIG. Therefore, in the present embodiment, in order to make the slope of the temperature coefficient of the forward voltage gentle, it is utilized that the forward voltage increases or decreases depending on the current density. Specifically, in the present embodiment, at a low temperature, the current flowing through the diode using silicon carbide is reduced to shift the forward voltage at a low temperature in a downward direction, while at a high temperature, silicon carbide is used. By increasing the current flowing through the diode, it shifts in the direction of increasing the forward voltage at high temperature. As described above, in the present embodiment, the load current is not controlled to be constant, but the load current is relatively small at low temperature and the load current is relatively large at high temperature. Fluctuation of load current. In this respect, the technical idea in the present embodiment has novelty with respect to the conventional techniques on the premise that the load current is controlled to be constant. Then, as a means for embodying the second basic idea in the present embodiment, for example, the resistance element R1 shown in FIG. 1 is a p-type diffusion resistance element composed of a p-type semiconductor region in which aluminum is introduced into silicon carbide. It consists of. As a result, due to the fact that the p-type diffusion resistance element has a negative temperature characteristic, the load current at a low temperature automatically increases the resistance value "r1" of the resistance element R1. Therefore, it becomes smaller. On the other hand, the load current at a high temperature becomes large because the resistance value “r1” of the resistance element R1 becomes relatively small. In this way, by adopting the second feature point in the present embodiment, the forward voltage at low temperature is automatically lowered by reducing the current flowing through the diode using silicon carbide at low temperature. On the other hand, by increasing the current flowing through the diode using silicon carbide at high temperature, the second basic idea of shifting in the direction of increasing the forward voltage at high temperature can be realized. That is, in the present embodiment, the load current is intentionally increased or decreased by simply configuring the resistance element R1 shown in FIG. 1 with a p-type diffusion resistance element composed of a p-type semiconductor region in which aluminum is introduced into silicon carbide. It is not necessary to provide a large-scale control circuit to control the above. That is, according to the second characteristic point in the present embodiment in which the resistance element R1 shown in FIG. 1 is composed of a p-type diffusion resistance element composed of a p-type semiconductor region in which aluminum is introduced into silicon carbide, the load current is purposely applied. It can be seen that it is a useful technical idea in that the second basic idea in the present embodiment can be realized without providing a large-scale control circuit for controlling the increase / decrease of.

<Effect in the embodiment>
Next, the effect in this embodiment will be described. FIG. 9 is a graph showing, for example, the temperature dependence of the output voltage Vref output from the output terminal OT of the reference voltage generation circuit shown in FIG. In FIG. 9, the horizontal axis represents the temperature and the vertical axis represents the output voltage Vref. As shown in FIG. 9, by adopting the first feature point that embodies the first basic idea in the present embodiment and the second feature point that embodies the second basic idea in the present embodiment, For example, it can be seen that the temperature dependence of the output voltage Vref output from the reference voltage generation circuit shown in FIG. 1 can be reduced.

<Device structure>
Subsequently, the device structure of the semiconductor device according to the present embodiment will be described. FIG. 10 is a cross-sectional view illustrating the device structure of the semiconductor device according to the present embodiment. In FIG. 10, in the region A1, the device structures of the resistance element R1 and the resistance element R2, which are the components of the reference voltage generation circuit shown in FIG. 1, are shown. On the other hand, in the region A2, the device structure of the diodes Q1 to Q3, which are the components of the reference voltage generation circuit shown in FIG. 1, is shown.

First, the device structure of the p-type diffusion resistance element formed in the region A1 of FIG. 10 will be described. As shown in FIG. 10, the region A1 of the semiconductor chip is provided on the n-type silicon carbide substrate 1S, the p-type semiconductor layer PSL provided on the n-type silicon carbide substrate 1S, and the p-type semiconductor layer PSL. An n-type semiconductor layer EPI is formed. A back surface electrode BE is formed on the back surface (lower surface) of the n-type silicon carbide substrate 1S. On the other hand, the p-type semiconductor region PR1 included in the n-type semiconductor layer EPI is formed in the n-type semiconductor layer EPI, and this p-type semiconductor region PR1 functions as a p-type diffusion resistance element. Further, an interlayer insulating film IL is formed over the surface of the n-type semiconductor layer EPI and the surface of the p-type semiconductor region PR1. The interlayer insulating film IL is formed with an opening OP1 and an opening OP2 that penetrate the interlayer insulating film IL and expose the surface of the p-type semiconductor region PR1. The wiring WL1 and the wiring WL2 are electrically connected to the p-type semiconductor region PR1 and are formed from the inside of the opening OP1 over the interlayer insulating film IL. As described above, the p-type diffusion resistance element is formed in the region A1 of the semiconductor chip.

Subsequently, the device structure of the diode formed in the region A2 of FIG. 10 will be described. As shown in FIG. 10, the region A2 of the semiconductor chip is provided on the n-type silicon carbide substrate 1S, the p-type semiconductor layer PSL provided on the n-type silicon carbide substrate 1S, and the p-type semiconductor layer PSL. An n-type semiconductor layer EPI serving as an n-type collector is formed. A back surface electrode BE is formed on the back surface (lower surface) of the n-type silicon carbide substrate 1S. On the other hand, in the n-type semiconductor layer EPI, a trench TR that penetrates the n-type semiconductor layer EPI and reaches the p-type semiconductor layer PSL is formed, and inside the trench TR, for example, from the p-type semiconductor layer. The embedded layer BSL is embedded. Then, in a plan view, the n-type semiconductor layer EPI is surrounded by an embedded layer BSL embedded in the trench TR. At this time, the n-type semiconductor layer EPI surrounded by the embedded layer BSL is contained in the p-type semiconductor region PR2 which is the p-type base and the p-type semiconductor region PR2 in the plan view, and is the n-type emitter. A type semiconductor region NR2 is formed. Further, an interlayer insulating film IL is formed on the n-type semiconductor layer EPI in which the embedded layer BSL embedded in the trench TR, the p-type semiconductor region PR2, and the n-type semiconductor region NR2 are formed. Here, the interlayer insulating film IL has an opening OP3 that penetrates the interlayer insulating film IL and exposes the surface of the n-type semiconductor region NR2, and the interlayer insulating film IL that penetrates the p-type semiconductor region PR2. The opening OP4 that exposes the surface of the n-type semiconductor layer EPI and the opening OP5 that penetrates the interlayer insulating film IL and exposes the surface of the n-type semiconductor layer EPI are formed. Then, the wiring WL3 is electrically connected to the n-type semiconductor region NR2 and is formed from the opening OP3 over the interlayer insulating film IL. Similarly, it is electrically connected to the p-type semiconductor region PR2 and extends from the opening OP4 to the interlayer insulating film IL, and is electrically connected to the n-type semiconductor layer EPI2, and is electrically connected to the interlayer insulating film from the opening OP5. Wiring WL4 over the IL is formed. In this way, in the region A2 of FIG. 10, the n-type semiconductor layer EPI is an n-type collector, the p-type semiconductor region PR2 is a p-type base, and the n-type semiconductor region NR2 is an n-type emitter. A diode having a configuration in which the p-type base of the npn bipolar transistor and the n-type collector are short-circuited is formed.

The diode formed in the region A2 of FIG. 10 is separated from the n-type silicon carbide substrate 1S to which the power supply potential is applied by the embedded layer BSL and the p-type semiconductor layer PSL. Therefore, the potential of the n-type semiconductor layer EPI of the diode formed in the region A2 of FIG. 10 can be set to an arbitrary potential. Therefore, depending on the device structure of the diode formed in the region A2 of FIG. 10, FIG. The diodes Q1 to Q3 of the reference voltage generation circuit shown in the above can be realized.

<Modification example 1>
FIG. 11 is a diagram showing a circuit configuration of the reference voltage generation circuit in the first modification. In FIG. 11, the anodes of the diodes Q1 to Q3 are electrically connected to the power supply line VL to which the power supply potential is supplied. In the reference voltage generation circuit configured in this way, a negative bias output voltage can be output from the output terminal OT.

Here, FIG. 12 is a cross-sectional view illustrating the device structure of the semiconductor device according to the first modification. In FIG. 12, the device structure of the resistance element R1 and the resistance element R2, which are the components of the reference voltage generation circuit shown in FIG. 11, is shown in the region A1. On the other hand, in the region A2, the device structure of the diodes Q1 to Q3, which are the components of the reference voltage generation circuit shown in FIG. 11, is shown. In FIG. 12, an n-type semiconductor layer EPI is formed on the n-type silicon carbide substrate 1S, and a p-type semiconductor region PR2 is formed so as to be included in the n-type semiconductor layer EPI, and the p-type semiconductor region PR2 is formed. The n-type semiconductor region NR2 is formed so as to be included in the p-type semiconductor region PR2. The diode formed in the region A2 of FIG. 12 is different from the diode formed in the region A2 of FIG. 10, and the diode is not separated from the n-type silicon carbide substrate 1S. This is because the power supply potential is applied to the n-type silicon carbide substrate 1S and the power supply potential is also supplied to the anode of the diode which is a component of the reference voltage generation circuit shown in FIG. This is because it is not necessary to separate the n-type semiconductor layer EPI and the n-type silicon carbide substrate 1S. This simplifies the device structure of the diode in the first modification.

<Modification 2>
FIG. 13 is a cross-sectional view illustrating the device structure of the semiconductor device according to the second modification. In FIG. 13, the device structure of the resistance element R1 and the resistance element R2, which are the components of the reference voltage generation circuit shown in FIG. 1, is shown in the region A1. On the other hand, in the region A2, the device structure of the diodes Q1 to Q3, which are the components of the reference voltage generation circuit shown in FIG. 1, is shown. In FIG. 13, unlike FIG. 10, the insulating layer OXL is embedded in the trench TR. For example, in the device structure shown in FIG. 10, a parasitic pnp-type bipolar having a p-type semiconductor region PR2 as a p-type emitter, an n-type semiconductor layer EPI as an n-type base, and an embedded layer BSL as an n-type collector. Transistors are formed. On the other hand, in the device structure shown in FIG. 13, since the layer embedded in the trench TR is not the embedded layer (p-type semiconductor layer) BSL but the insulating layer OXL, the parasitic pnp-type bipolar transistor is not formed. As a result, according to the semiconductor device in the second modification, it is possible to prevent an erroneous arc caused by the parasitic pnp-type bipolar transistor, thereby improving the reliability of the semiconductor device.

The technical idea of the present modification 2 that the formation of the parasitic pnp type bipolar transistor is prevented by embedding the insulating layer OXL inside the trench TR is not limited to this, and for example, as shown in FIG. The insulating film OXF may be formed on the inner wall of the trench TR, and the embedded layer BSL may be embedded inside the trench TR via the insulating film OXF. Further, for example, as shown in FIG. 15, the device structure shown in FIG. 14 is said to prevent the formation of a parasitic pnp-type bipolar transistor even in a configuration in which the insulating film OXF formed at the bottom of the trench TR is removed. The technical idea of this modification 2 can be embodied.

Although the invention made by the present inventor has been specifically described above based on the embodiment thereof, the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. Needless to say.

For example, in the reference voltage generation circuit shown in FIG. 1, a configuration example in which an n-type current mirror circuit and a p-type current mirror circuit are connected in series is shown, but the technical idea in the above embodiment is not limited to this. It can also be applied to a reference voltage generation circuit using an operational amplifier. Further, in the above-described embodiment, the reference voltage generation circuit has been described, but the technical idea in the above-described embodiment can also be applied to the reference current generation circuit that operates on the same principle.

In the above-described embodiment, a diode having a configuration in which the p-type base of the npn bipolar transistor and the n-type collector are short-circuited is given as an example, but the technical idea in the above-described embodiment is not limited to this, and for example, it is simple. It can also be applied to a pn junction diode. However, the advantage of adopting a diode having a configuration in which the p-type base of the npn bipolar transistor and the n-type collector are short-circuited is that all terminals (anode terminals) from the surface side (surface side of the semiconductor chip) of the n-type silicon carbide substrate are used. Since the cathode terminal) can be taken out, there is an advantage that the mounting configuration of the semiconductor device becomes easy.

1S n-type silicon carbide substrate BE back electrode BSL embedded layer EPI n-type semiconductor layer M1 field-effect transistor M2 field-effect transistor M3 field-effect transistor M4 field-effect transistor M5 field-effect transistor NR2 n-type semiconductor region PR1 p-type semiconductor region PR2 p-type Semiconductor region PSL p-type semiconductor layer Q1 diode Q2 diode Q3 diode R1 resistance element R2 resistance element TR trench

Claims (14)

It is equipped with a semiconductor chip containing silicon carbide as the main component and having a reference voltage generation circuit formed.
The reference voltage generation circuit includes a resistance element and a diode.
The resistance element is composed of a diffusion resistance element in which an acceptor is introduced into the silicon carbide .
The temperature dependence of the output voltage output from the reference voltage generation circuit is
The temperature dependence due to the built-in potential of the diode and
The temperature dependence caused by the resistance value of the diffusion resistance element and
Including
A semiconductor device in which the temperature dependence caused by the built-in potential of the diode is compensated by the negative temperature dependence caused by the resistance value of the diffusion resistance element . In the semiconductor device according to claim 1,
The diode is a semiconductor device composed of an n-type collector in which a donor is introduced and an npn-type bipolar transistor in which a p-type base in which an acceptor is introduced is short-circuited. In the semiconductor device according to claim 2,
A semiconductor device in which the acceptor introduced in the diffusion resistance element and the acceptor introduced in the p-type base are elements of the same type. In the semiconductor device according to claim 3,
The acceptor introduced in the diffusion resistance element is aluminum.
A semiconductor device in which the acceptor introduced in the p-type base is also aluminum. In the semiconductor device according to claim 2,
A semiconductor in which the energy difference between the acceptor level of the acceptor and the upper end of the valence band of silicon carbide is greater than the energy difference between the donor level of the donor and the lower end of the conduction band of silicon carbide. apparatus. In the semiconductor device according to claim 2,
The donor is a semiconductor device, which is nitrogen. In the semiconductor device according to claim 2,
A semiconductor device in which the activation rate of the acceptor is smaller than the activation rate of the donor. In the semiconductor device according to claim 2,
A semiconductor device in which the temperature dependence of the activation rate of the acceptor is greater than the temperature dependence of the activation rate of the donor. In the semiconductor device according to claim 1,
A semiconductor device in which the load current in the reference voltage generation circuit is a first current value at room temperature, and is 20 times or more the first current value at 500 ° C. In the semiconductor device according to claim 1,
A semiconductor device in which the cathode of the diode is connected to a ground wire to which a reference potential is supplied. In the semiconductor device according to claim 1,
The anode of the diode is a semiconductor device connected to a power supply line to which a power supply potential is supplied. In the semiconductor device according to claim 2,
The semiconductor chip is
n-type silicon carbide substrate and
The p-type semiconductor layer formed on the n-type silicon carbide substrate and
An n-type semiconductor layer formed on the p-type semiconductor layer and serving as the n-type collector,
A trench that penetrates the n-type semiconductor layer and reaches the p-type semiconductor layer,
An embedded layer embedded inside the trench and
Have,
In a plan view, the n-type semiconductor layer is surrounded by the embedded layer.
The n-type semiconductor layer surrounded by the embedded layer includes the n-type semiconductor layer.
The p-type semiconductor region, which is the p-type base, and
In a plan view, an n-type semiconductor region included in the p-type semiconductor region and serving as an n-type emitter, and an n-type semiconductor region.
Is formed, a semiconductor device. In the semiconductor device according to claim 12,
The embedded layer is a semiconductor device composed of a p-type embedded semiconductor layer. In the semiconductor device according to claim 12,
The embedded layer is a semiconductor device composed of an insulating layer.

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