JP6838126B2 - Semiconductor device - Google Patents

Description

The present invention relates to a configuration of a light emitting device. The present invention particularly relates to the configuration of an active matrix type light emitting device having a thin film transistor (hereinafter referred to as TFT) formed on an insulator such as glass or plastic. The present invention also relates to an electronic device using a light emitting device as a display unit.

In recent years, the development of display devices using light emitting elements such as electroluminescence elements (EL elements) has become active. Here, the EL element includes both an element that utilizes light emission (fluorescence) from a singlet exciton and an element that utilizes light emission (phosphorescence) from a triplet exciton. In this specification, an EL display device is mentioned as an example of a light emitting device, but
A display device using another light emitting element shall also be included.

The EL element is configured such that a light emitting layer is sandwiched between a pair of electrodes (anode and cathode), and usually has a laminated structure. A typical example is a laminated structure called "hole transport layer / light emitting layer / electron transport layer" proposed by Tang et al. Of Eastman Kodak Company. This structure has extremely high luminous efficiency, and most of the EL devices currently under study adopt this structure.

In addition to this, "hole injection layer / hole transport layer / light emitting layer / electron transport layer" or "hole injection layer / hole transport layer / light emitting layer / electron transport layer / electron injection layer" on the anode There is a structure in which they are stacked in this order. As the structure of the EL element in the present specification, any of the above structures may be adopted. Further, the light emitting layer may be doped with a fluorescent dye or the like.

In the present specification, all the layers provided between the anode and the cathode are collectively referred to as an EL layer. Therefore, the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer are all E.
An element included in the L layer and composed of an anode, an EL layer, and a cathode is called an EL element.

FIG. 3A shows a schematic view of the light emitting device. The pixel portion 301 is arranged in the central portion of the substrate 300. A source signal line drive circuit 302 for controlling the source signal line and a gate signal line drive circuit 303 for driving the gate signal line are arranged around the pixel unit 301. In FIG. 3A, the gate signal line drive circuit 303 is symmetrically arranged on both sides of the pixel portion 301, but only one of them may be arranged on one side. However, considering the reliability and efficiency of circuit operation, it is desirable to arrange them on both sides.

Flexible printed circuit boards (Flexible) for clock signals, start pulses, video signals, etc.
It is input to the source signal line drive circuit 302 and the gate signal line drive circuit 303 via Print Circuit (FPC) or the like.

The operation of the drive circuit will be described. In the gate signal line drive circuit, a pulse for sequentially selecting the gate signal line is output by the shift register 321 according to the clock signal and the start pulse. After that, after an operation such as receiving a conversion of the voltage amplitude of the signal by the level shifter 322, the signal is output to the gate signal line via the buffer 323, and the gate signal line is sequentially selected.

In the source signal line drive circuit, sampling pulses are sequentially output by the shift register 311 according to the clock signal and the start pulse. First latch circuit 312
In, the digital video signal is held according to the timing of the sampling pulse. When the operation for one horizontal period is completed, a latch pulse is input during the subsequent return period, and the digital video signals for one line held by the first latch circuit 312 are simultaneously subjected to the second latch. It is transferred to the circuit 313, and one line is simultaneously written to the pixels of the line in which the gate signal line is selected.

Subsequently, the operation of the pixel unit will be described. FIG. 3B is an extracted one pixel shown by 310 in FIG. 3A. Source signal line (S (n)), gate signal line (G (m)
)), Current supply line (Curent), TFT 351 for switching, TFT 35 for EL drive
2. It has a holding capacity of 353, an EL element 354 which is a typical light emitting element, and the like.

When the gate signal line is in the selected state, the switching TFT 351 is turned on.
Meanwhile, the digital video signal held in the second latch circuit is output to the source signal line. The output digital video signal passes between the source and drain of the switching TFT 351 and is input to the gate electrode of the EL drive TFT 352 to be turned ON, and the EL element 3
A current flows through 54. On the other hand, the electric charge is retained in the holding capacity 353. Even after the gate signal line selection period ends and the switching TFT 351 is turned off, the potential of the gate electrode of the EL drive TFT 352 is maintained by the electric charge held by the holding capacity 353, and the EL element 35
Current continues to flow in 4.

In the present specification, the operation of the TFT may be described when the circuit operation is described, but when the TFT is turned on, the absolute value of the voltage between the gate and the source of the TFT is the absolute value of the threshold voltage of the TFT. It means that the source region and drain region of the TFT exceed the value and become conductive through the channel formation region. When the TFT is turned off, the absolute value of the voltage between the gate and source of the TFT is the threshold voltage of the TFT. It means that the source region and the drain region of the TFT are in a non-conducting state when the value is less than the absolute value of.

Further, in the present specification, the connection of the TFT is described as "gate electrode, input electrode,
The notation "output electrode" and "gate electrode, source region, drain region" are used properly.
This often considers the gate-source voltage when explaining the operation of the TFT, but T
Since it is difficult to clearly distinguish between the source region and drain region of the FT due to the structure of the TFT, when explaining the input and output of signals, they are called input electrodes and output electrodes, and the relationship between the potentials of the electrodes of the TFT. In the description of the above, one of the input electrode and the output electrode will be referred to as a source region, and the other will be referred to as a drain region.

When expressing multiple gradations using a light emitting device, an analog gradation method and a digital gradation method can be mentioned. In the case of the former analog gradation, the current flowing through the EL element is controlled in an analog manner to control the brightness to obtain the gradation. However, minute variations in the characteristics of the TFTs constituting the pixel portion cause EL. It greatly affects the variation in brightness. That is, if the characteristics of the driving TFT 352 vary, the value of the source-drain current in both will be different even when the same potential is applied to the gate electrodes of different driving TFTs. That is, since the value of the current flowing through the EL element is different, the brightness varies.

There is a digital gradation method as a method in which variations in the characteristics of the elements constituting the pixels do not easily affect the image quality. In the digital gradation method, the EL element is driven only by two states, an ON state (a state in which its brightness is approximately 100%) and an OFF state (a state in which its brightness is approximately 0%). That is, it can be said that it is a drive method in which it is difficult to discriminate the variation in the brightness of the EL element even if the current between the source and the drain of the drive TFT varies.

However, in the case of the digital gradation method, since only two gradations can be displayed as it is,
A plurality of techniques have been proposed to realize multi-gradation in combination with another method.

As one of the methods for realizing multi-gradation, there is a method of combining a digital gradation method and a time gradation method. The time gradation method is a method of expressing gradation by controlling the time during which the EL element emits light. Specifically, one frame period is divided into a plurality of subframe periods having different lengths, and the EL element is selected to emit light or not to emit light in each period.
The gradation is expressed by the difference in the length of time that the light is emitted within the frame period.

As a method for combining a digital gradation method and a time gradation method, Japanese Patent Application Laid-Open No. 2001-542
The method published in No. 6 will be described. Here, the case of 3-bit gradation expression will be described as an example.

Refer to FIGS. 9A to 9C. Usually, in a display device such as a liquid crystal display or an EL display, the frame frequency is about 60 [Hz]. That is, as shown in FIG. 9 (A).
The screen is drawn about 60 times per second. This makes it possible to prevent the human eye from feeling flicker (flickering on the screen).
At this time, the period in which the screen is drawn once is called a one-frame period.

In the time gradation method published in Japanese Patent Application Laid-Open No. 2001-5426, one frame period is divided into a plurality of subframe periods. The number of divisions at this time is usually equal to the number of bits of the input digital video signal. Here, since it is a 3-bit gradation, it is divided into three subframe periods SF1 to SF3.

However, among the driving methods aimed at improving the display quality, there is a method in which the number of divisions of the frame period is larger than the number of bits of the digital video signal. Such a driving method is described in, for example, Japanese Patent Application No. 2000-267164.

Further, each subframe period has an address (write) period Ta and a sustain (emission) period Ts. The address (writing) period is a period for writing a digital video signal to a pixel, and the length in each subframe period is the same. What is the sustain period?
This is the period during which the EL element emits light based on the digital video signal written to the pixels during the (writing) period. At this time, the sustain (emission) periods Ts1 to Ts3 have a length ratio of Ts1: Ts2: Ts3 = 4: 2: 1. In other words, in representing an n-bit gray scale, the ratio of the length of the n sustain (light emission) ^{period, 2 n-1: 2 n} -2: ···: 2 1: is a 2 ^0. Then, the length of the period in which each pixel emits light is determined per frame period depending on which sustain (light emission) period the EL element emits light, and gradation expression is performed by this. That is, in FIG. 9B, by taking either a light emitting state or a non-light emitting state in each of the sustain (light emitting) periods Ts1 to Ts3, the brightness is 0% by utilizing the length of the total light emitting time. , 14%, 28%, 43%, 57%, 71%, 86%, 100% can be expressed in 8 gradations. When Ts1 emits light and Ts2 and Ts3 do not emit light, the brightness is 57%.
When Ts1 and Ts3 emit light and Ts2 does not emit light, the brightness is 71%.
That is, in the analog gradation method, when it is desired to obtain 71% brightness, it is controlled by a voltage or the like according to it, and 71% brightness is maintained over the entire one frame period, whereas in the time gradation method, it is maintained. In this case, the same gradation is expressed by emitting light for 71% of the entire light emission period with 100% brightness.

The operation will be specifically described. Continue to refer to FIGS. 9 (A) to 9 (C) and FIG. 3 (B).
First, when a selection pulse is input to the gate signal line, the switching TFT 351 is turned on. Next, a digital video signal is input from the source signal line, and the drive T is determined by the potential.
ON and OFF of FT352 are controlled, and the electric charge is held in the holding capacity 353.

At this time, even if the driving TFT 352 is turned on, the anode (cathode) 355 and the cathode of the EL element 354
No voltage is applied between the (anode) and 356 to prevent light emission. As a method, the potential of the cathode (anode) 356 may be made equal to the potential of the anode (cathode) 355, that is, the potential of the current supply line (Curent). Since the cathode (anode) 356 is usually short-circuited in all pixels, this operation is performed simultaneously in all pixels.

From the first line to the last line, the address (write) period ends when the write operation is completed, and all pixels simultaneously move to the sustain (light emission) period. A voltage difference is generated between the anode (cathode) 355 and the cathode (anode) 356 of the EL element 354, and light is emitted when a current flows.

By performing the above operation in all subframe periods, one frame period is configured.
According to this method, if it is desired to increase the number of display gradations, the number of divisions in the subframe period may be increased. Further, as shown in FIGS. 9B and 9C, the order of the subframe periods does not necessarily have to be the order of high-order bits → low-order bits, and may be randomly arranged during one frame period. Further, the order may be changed within each frame period.

By the way, in a display device manufactured by forming a TFT on an insulator, the complicated process causes a decrease in yield and an increase in cost. Therefore, simplifying the process as much as possible is the main issue for cost reduction. Therefore, it is considered that the pixel portion and the peripheral drive circuits (source signal line drive circuit, gate signal line drive circuit, etc.) are configured only by the unipolar TFT.

Here, the operating voltage of the pixel and the drive circuit will be considered again. See FIG. 5 here.
FIG. 5A shows the configuration of the pixel portion of the EL element, and FIG. 5B schematically shows the connection of the switching TFT 501, the driving TFT 502, and the EL element 504.

First, in the EL element 504, consider the case where 505 is an anode and 506 is a cathode. Now, assuming that the potential of the electrode 505 is V ₅₀₅ and the potential of the electrode 506 is V ₅₀₆ , it is necessary to give a potential difference between the two electrodes in order for the EL element 504 to emit light. Therefore, V ₅₀₅ > V ₅₀₆ .
In order to ensure that the drive TFT 502 is an N-channel type and to apply a voltage normally between the electrodes of the EL element 504, the potential applied to the gate electrode of the drive TFT 502 is V _50.
It needs to be even higher than 5 (at least by the threshold of TFT 502). That is, it is necessary to widen the amplitude of the signal written from the source signal line. On the other hand, the driving TFT 5
In order to ensure that 02 is ON when the P channel type is used and to apply a voltage normally between the electrodes of the EL element 504, the potential applied to the gate electrode of the driving TFT 502 is at least that of the TFT 502 rather than _{the V 505.} It suffices if it is lowered by the threshold value. Therefore, it is not necessary to widen the signal amplitude written from the source signal line. Therefore, the electrode 5 of the EL element 504
When 05 is an anode and 506 is a cathode, it is desirable to use a P-channel type for the driving TFT 502.

Subsequently, in the EL element 504, when 505 is a cathode and 506 is an anode, it is necessary to give a potential difference between both electrodes in order for the EL element 504 to emit light. Therefore, in this case, V ₅₀₅ <V ₅₀₆ . When the drive TFT 502 is an N-channel type, it surely turns on and turns on.
In order to normally apply a voltage between the electrodes of the EL element 504, the potential applied to the gate electrode of the driving TFT 502 _{may be higher than that of the V 505} by at least the threshold value of the TFT 502. Therefore, the amplitude of the signal written from the source signal line does not need to be so wide. On the other hand, when the driving TFT 502 is a P-channel type, the potential applied to the gate electrode of the driving TFT 502 is higher than that of _{V 505 in order to surely turn on and apply a voltage normally between the electrodes of the EL element 504.} It needs to be even lower (at least by the threshold of TFT 502). That is, it is necessary to widen the amplitude of the signal written from the source signal line. Therefore, when the electrode 505 of the EL element 504 is a cathode and 506 is an anode, the driving TFT 50
It is desirable to use the N channel type for 2.

Next, the relationship between the polarity of the driving TFT 502, the configuration of the EL element 504, and the emission direction will be described. FIG. 8A shows an EL element 5 when the driving TFT 502 is an N-channel type.
FIG. 8B shows the configuration of 04, in which the EL element 5 when the driving TFT 502 is a P-channel type.
The configuration of 04 is schematically shown in a cross-sectional view.

Since the cathode of the EL element 504 is required to have the ability to inject electrons into the light emitting layer,
Since it is desirable to use a metal material, the electrode using a transparent electrode is usually an anode. Therefore, in FIG. 8A, the driving TFT is an N-channel type, a current supply line is connected to the source region of the driving TFT 502, and the cathode of the EL element 504 is connected to the drain region. Therefore, since the light generated in the light emitting layer is emitted to the anode side, which is a transparent electrode, the emission direction is the substrate on which the TFT is formed (hereinafter referred to as the TFT substrate) as shown in the figure. It will be on the other side.

On the other hand, in FIG. 8B, the driving TFT 502 is a P-channel type, and the driving TFT 5
A current supply line is connected to the source region of 02, and an anode of the EL element 504 is connected to the drain region. Therefore, the light generated in the light emitting layer is emitted to the anode side, which is a transparent electrode, and the emission direction is toward the TFT substrate side as shown in the figure.

In the present specification, the emission direction shown in FIG. 8 (A) is referred to as top surface emission, and the emission direction shown in FIG. 8 (B) is referred to as bottom surface emission. In the case of bottom emission, the area occupied by the elements constituting the pixel portion affects the light emitting area, whereas in the case of top emission, light can be extracted regardless of the region occupied by the elements constituting the pixel portion. It is advantageous for increasing the aperture ratio. However, when the light emitting device is manufactured with the configuration of top emission as shown in FIG. 8 (A), it is necessary to form the anode using the transparent electrode after forming the EL layer in the process. Since the EL layer is easily damaged and such a process is difficult at present, a bottom-side emission configuration as shown in FIG. 8B is generally adopted.

Here, the polarity of the switching TFT 501 with respect to the polarity of the driving TFT 502 will be considered. First, when the drive TFT 502 is a P-channel type, the condition that the drive TFT 502 is turned on is that _{the absolute value of the gate-source voltage V GS2} of the drive TFT 502 is the absolute value of the threshold voltage of the drive TFT 502. To surpass. That is, the potential of the L level of the digital video signal input from the source signal line (here, the potential of the digital video signal is L).
At the level, the EL element emits light), which is lower than the potential in the source region of the driving TFT 502 by a threshold value or more.

At this time, when the switching TFT 501 has the same polarity as the driving TFT 502, that is, it is a P channel type, the condition that the switching TFT 501 is turned on is the switching T.
The absolute value of the gate-source voltage V _GS1 of the FT501 exceeds the absolute value of the threshold voltage of the switching TFT 501. That is, the potential of the L level of the pulse that selects the gate signal line (here, since the switching TFT 501 is a P channel type, when the L level is input to the gate signal line, it is in the selected state. However, it is lower than the potential of the source region of the switching TFT 501 by a threshold value or more.
Therefore, it is necessary to make the voltage amplitude on the gate signal line side wider than the voltage amplitude of the source signal line.
This means increasing the operating voltage of the gate signal line drive circuit.

The same can be said when the switching TFT 501 and the driving TFT 502 are N-channel type. Therefore, when considering the power consumption, it is desirable that the TFT of the pixel portion is configured by using both the N channel type and the P channel type.

From the above, if the pixel unit and the drive circuit are configured by the unipolar TFT by the conventional method, the process can be reduced, but the power consumption is increased.

The present invention has been made in view of the above-mentioned problems, and it is necessary to reduce the number of steps by configuring the pixel portion and the drive circuit with a single-polarity TFT, and to keep the power consumption low by using a new circuit configuration. It is an object of the present invention to provide a realized light emitting device.

In the pixel of the conventional configuration, in order to surely turn on the switching TFT, the switching TFT is more than the voltage amplitude of the signal input to the input electrode of the switching TFT, that is, the signal output to the source signal line. It was necessary to increase the voltage amplitude of the signal input to the gate electrode of the above, that is, the signal for selecting the gate signal line.

Here, consider the case where the voltage amplitude of the signal output to the source signal line is equal to the voltage amplitude of the signal for selecting the gate signal line. See FIG. 5 again. It is assumed that all the TFTs constituting the pixels are N-channel type.

The gate signal line is selected and the switching TFT is turned on. The potential of the gate electrode of the switching TFT at this time is V ₁ . The switching TFT is turned on, and the video signal output to the source signal line is input to the gate electrode of the driving TFT. At this time, assuming that the video signal is at H level, the potentials of the input electrode and the gate electrode of the switching TFT are equal, and V ₁ , the potential of the signal appearing on the output electrode side of the switching TFT is
The _{potential (V 1 −} Vth N) is obtained by subtracting the threshold value of the switching TFT from _{V 1.} When the video signal is L level, the threshold value of the switching TFT has no effect, and the L level is equally input to the gate electrode of the driving TFT.

That is, the switching TFT attenuates the voltage amplitude of the video signal by the threshold value. As a result, the potential of the gate electrode of the driving TFT may not rise sufficiently, and a desired drain current may not be obtained. As a result, the current flowing through the EL element is insufficient.

Therefore, in the present invention, a voltage compensation circuit is provided between the output electrode of the switching TFT and the gate electrode of the driving TFT. The voltage compensation circuit is an application of a bootstrap circuit, and has a role of returning the voltage amplitude of the signal attenuated by the threshold value of the switching TFT to the original amplitude.

As a result, even when the voltage amplitude of the video signal output to the source signal line and the voltage amplitude of the signal for selecting the gate signal line are equal, a normal potential is given to the gate electrode of the driving TFT. Can be done. Therefore, the drive voltage of the gate signal line drive circuit can be lowered, which contributes to the reduction of power consumption of the light emitting device.

Further, the pixel having the voltage compensation circuit of the present invention is composed of a single-polarity TFT, and the pixel portion of the light emitting device is configured by using this pixel, and the peripheral drive circuit constitutes the pixel portion. By configuring the TFT with the same polarity as the TFT, it contributes to the simplification of the manufacturing process.

The configuration of the present invention is described below.

The light emitting device of the present invention is a light emitting device configured by using a plurality of transistors of one conductive type, and the pixels of the light emitting device are a source signal line, a gate signal line, a current supply line, and the like, respectively. It is characterized by having a switching transistor, a driving transistor, a light emitting element, and a voltage compensation circuit.

The light emitting device of the present invention is a light emitting device configured by using a plurality of transistors of one conductive type, and the pixels of the light emitting device include a source signal line, a gate signal line, and a current supply line, respectively. It has a switching transistor, a driving transistor, a light emitting element, and a voltage compensation circuit. The gate electrode of the switching transistor is electrically connected to the gate signal line, and the input electrode is the source signal line. The output electrode is electrically connected to the gate electrode of the driving transistor, the input electrode of the driving transistor is electrically connected to the current supply line, and the output electrode is electrically connected to the current supply line. It is electrically connected to one electrode of the light emitting element, and the voltage compensation circuit is characterized in that it is arranged between the output electrode of the switching transistor and the gate electrode of the driving transistor.

The light emitting device of the present invention is a light emitting device configured by using a plurality of transistors of one conductive type, and is scanned in the mth row (m is a natural number, 1 ≦ m) among the pixels of the light emitting device. The pixels are the source signal line, the gate signal line selected on the mth line, the current supply line, and so on.
It has a switching transistor, a driving transistor, a light emitting element, and a voltage compensation circuit, and the gate electrode of the switching transistor is electrically connected to the gate signal line selected on the m-th row and is input. The electrode is electrically connected to the source signal line, the output electrode is electrically connected to the gate electrode of the drive transistor, and the input electrode of the drive transistor is electrically connected to the current supply line. The output electrode is electrically connected to one electrode of the light emitting element, and the voltage compensation circuit includes a refresh transistor, a compensation transistor, a first capacitance means, and a second capacitance means. The first electrode of the first capacitance means is electrically connected to the output electrode of the switching transistor, and the second electrode is electrically connected to the first electrode of the second capacitance means. The second electrode is connected to
It is electrically connected to the current supply line, the gate electrode of the refresh transistor is electrically connected to the gate signal line selected in the (m-1) line, and the input electrode is the first power supply potential. The output electrode is electrically connected to the output electrode of the switching transistor and the gate electrode of the driving transistor, and the gate electrode of the compensation transistor is electrically connected to the signal line or the power supply line. , The first electrode of the first capacitive means,
The output electrode of the switching transistor and the gate electrode of the drive transistor are electrically connected, the input electrode is electrically connected to the signal line or power supply line that supplies the second power supply potential, and the output electrode is , The second electrode of the first capacitance means and the first electrode of the second capacitance means are electrically connected.

The light emitting device of the present invention is a light emitting device configured by using a plurality of transistors of one conductive type, and the pixels of the light emitting device are a source signal line for inputting a video signal to the pixels and the pixels. A gate signal line that selects any one of the lines, a light emitting element that emits light according to the input of the video signal, a current supply line that supplies a current to the light emitting element, and a current supplied to the light emitting element. A driving transistor to be controlled, a switching transistor for controlling the input of the video signal from the source signal line to the gate electrode of the driving transistor, and a signal input to the gate electrode of the driving transistor according to the video signal. It is characterized by having a voltage compensation circuit that compensates or converts the voltage amplitude of the above.

The light emitting device of the present invention is a light emitting device configured by using a plurality of transistors of one conductive type, and the pixels of the light emitting device are a source signal line for inputting a video signal to the pixels and the pixels. A gate signal line that selects any one of the lines, a light emitting element that emits light according to the input of the video signal, a current supply line that supplies a current to the light emitting element, and a current supplied to the light emitting element. A driving transistor to be controlled, a switching transistor for controlling the input of the video signal from the source signal line to the gate electrode of the driving transistor, and a signal input to the gate electrode of the driving transistor according to the video signal. The gate electrode of the switching transistor is electrically connected to the gate signal line, and the input electrode is electrically connected to the source signal line. The output electrode is electrically connected to the gate electrode of the driving transistor, the input electrode of the driving transistor is electrically connected to the current supply line, and the output electrode is one of the light emitting elements. It is electrically connected to the electrode, and the voltage compensation circuit is characterized in that it is arranged between the output electrode of the switching transistor and the gate electrode of the driving transistor.

The light emitting device of the present invention is a light emitting device configured by using a plurality of transistors of one conductive type, and is scanned in the mth row (m is a natural number, 1 ≦ m) among the pixels of the light emitting device. The pixels are the source signal line that inputs the video signal to the pixel and the pixel.
A gate signal line that selects the m-th line, a light emitting element that emits light according to the input of the video signal, and a light emitting element.
The current supply line that supplies the current to the light emitting element, the drive transistor that controls the current supplied to the light emitting element, and the input of the video signal from the source signal line to the gate electrode of the drive transistor are input. The gate electrode of the switching transistor has a switching transistor to be controlled and a voltage compensation circuit that compensates or converts the voltage amplitude of the signal input to the gate electrode of the driving transistor according to the video signal.
It is electrically connected to the gate signal line that selects the m-th line, the input electrode is electrically connected to the source signal line, and the output electrode is electrically connected to the gate electrode of the drive transistor. The input electrode of the drive transistor is electrically connected to the current supply line, the output electrode is electrically connected to one electrode of the light emitting element, and the voltage compensation circuit is the gate of the drive transistor. A refreshing transistor that gives a constant potential to the electrodes, a compensating transistor that compensates for the voltage amplitude of the video signal input to the gate electrode of the driving transistor, and a capacitance between the gate electrode and the output electrode of the compensating transistor. It has a first capacitive means for forming a coupling and a second capacitive means for forming a capacitive coupling between the output electrode of the compensating transistor and the current supply line, and is a first of the first capacitive means. The electrode is electrically connected to the output electrode of the switching transistor, the second electrode is electrically connected to the first electrode of the second capacitance means, and the second electrode is the current supply. Electrically connected to the wire, the gate electrode of the refreshing transistor is electrically connected to the gate signal wire selected in line (m-1), and the input electrode supplies the first power potential. It is electrically connected to the signal line or the power supply line, the output electrode is electrically connected to the output electrode of the switching transistor and the gate electrode of the driving transistor, and the gate electrode of the compensation transistor is the first. Electrically connected to the first electrode of the capacitive means 1, the output electrode of the switching transistor, and the gate electrode of the driving transistor, the input electrode is a signal line or power line that supplies a second power potential. The output electrode is electrically connected to the second electrode of the first capacitance means and the first electrode of the second capacitance means.

In the light emitting device of the present invention, the signal line or power supply line that supplies the first power supply potential is
It is characterized in that it is the gate signal line or the current supply line selected on the m-th line.

In the light emitting device of the present invention, the signal line or power supply line that supplies the second power supply potential is
It is characterized in that it is the gate signal line or the current supply line selected on the m-th line.

In the light emitting device of the present invention, the first capacitance means is a capacitance means having a capacitance between the gate electrode of the compensation transistor and the input electrode or output electrode of the compensation transistor. ..

In the light emitting device of the present invention, the first and second capacitance means have a capacitance including any two materials of an active layer material, a gate electrode material, or a wiring material, and an insulating layer between the two materials. It is characterized by being a means.

In the light emitting device of the present invention, the one-conductive type is characterized by being an N-channel type.

In the light emitting device of the present invention, the one-conductive type is characterized by being a P-channel type.

The light emitting device of the present invention can be applied to electronic devices such as an OLED display, a video camera, a notebook personal computer, a personal digital assistant, a sound reproduction device, a digital camera, and a mobile phone shown in FIG.

In the light emitting device of the present invention, a pixel portion and a peripheral drive circuit are integrally formed by using a unipolar TFT. This reduces a part of the doping process and also reduces the number of masks, which contributes to the improvement of yield and cost reduction.

Further, the light emitting device of the present invention has a pixel having a structure to which the bootstrap method is applied, and can reduce the voltage amplitude of the signal for driving the pixel. This contributes to lower power consumption of the light emitting device.

The figure which shows the embodiment of this invention. The figure which shows one Example of this invention. The figure which shows one configuration example of the light emitting device used conventionally. The figure which shows one configuration example of the light emitting device of this invention. The figure explaining the operation of the TFT of the pixel part and the light emitting element. The figure which shows the manufacturing process of the light emitting device of this invention. The figure which shows the manufacturing process of the light emitting device of this invention. The figure which shows the cross section of the pixel part of the light emitting device in the case of an upward emission and a downward emission. The figure which shows the timing chart about the drive of a light emitting device. The figure which shows the cross section of the dual gate type TFT and the manufacturing process example. The figure which shows the electric potential in each node at the time of pixel driving of the light emitting device of this invention. The block diagram of the gate signal line drive circuit which comprises the light emitting device of this invention. The block diagram of the source signal line drive circuit which comprises the light emitting device of this invention. Circuit configuration diagram of the shift register. The figure which shows the timing chart about the drive of a shift register. Circuit block diagram of the buffer. Circuit configuration diagram of the level shifter. The circuit block diagram of the latch circuit. The figure which shows the example of the electronic device to which this invention is applied.

FIG. 1 shows the configuration of a pixel having the voltage compensation circuit of the present invention. As shown in FIG. 1A, switching TFT 101, driving TFT 102, EL element 104, source signal line.
(S (n)), gate signal line (G (m)), and current supply line (Curent) are provided as in the conventional case. The features of the present invention are the output electrode of the switching TFT 101 and the driving TFT.
It is characterized in that a voltage compensation circuit 110 is provided between the gate electrode of 102 and the gate electrode.

FIG. 1B is a circuit diagram including the configuration of the voltage compensation circuit 110. The voltage compensation circuit 110
First TFT 151, second TFT 152, first capacitance means 153, second capacitance means 15
Has 4. Further, in FIG. 1B, G (m) is a gate signal line scanned on the m-th line, and G (m-1) is a gate signal line scanned on the m-1 line.

The first capacitance means 153 and the second capacitance means 154 are arranged in series. The first electrode of the first capacitance means 153 is connected to the output electrode of the switching TFT 101, and the second electrode of the first capacitance means 153 is connected to the first electrode of the second capacitance means 154. , The second electrode of the second capacitance means 154 is connected to the current supply line.

The gate electrode of the first TFT 151 is connected to the gate signal line G (m-1), the input electrode is connected to the signal line or power line that supplies _{the first power potential (V 1), and the output electrode is} , Connected to the output electrode of the switching TFT 101

The gate electrode of the second TFT 152 is connected to the output electrode of the switching TFT 101 and the first electrode of the first capacitance means, and the input electrode is a signal line or a signal line for supplying the _{second power supply potential (V 2).} Connected to the power line, the output electrode is connected to the second electrode of the first capacitance means and the first electrode of the second capacitance means.

In the future, regarding the two TFTs included in the voltage compensation circuit, the first TFT 151 will be referred to as a refreshing TFT, and the second TFT 152 will be referred to as a compensation TFT.

The TFTs 101, 102, 151, and 152 that make up the pixel are all TFTs with the same polarity.
Is used, and the polarity may be N-channel type or P-channel type.

However, the first power supply potential (V ₁ ) and the second power supply potential (V ₂ ) differ depending on the polarities of the TFTs constituting the pixels. When the TFTs that make up the pixels are N-channel type, V ₁ <
When V ₂ is set and the TFT constituting the pixel is a P channel type, V ₁ > V ₂ is set.

When V ₁ <V ₂ , _{the potential of V 1} is sufficiently below the threshold value of the N-channel TFT,
The potential of V _{2 is set to} a potential sufficiently higher than the threshold value of the N-channel TFT. For example, _{the potential of V 1} is about the L level _{of the signal line, and the potential of V 2} is about the H level of the signal line. V ₁ > V
_In the case of 2, the potential may be reversed.

The operation of the circuit will be described. Here, the case where all the TFTs constituting the pixels are N-channel type is taken as an example. As the input signal, both the digital video signal output to the source signal line and the signal for selecting the gate signal line are VDD at the H level and VSS at the L level. Here, V ₁ = VSS and V ₂ = VDD. In addition, the current supply line (Curr)
potential of ent) is set to V _C.

FIG. 11 shows a timing chart for explaining the operation of the circuit of the present invention. (
A) is the potential of the gate signal line (G (m-1)) on the m-1 line, and (B) is the gate signal line (G (G ()) on the m-1 line.
m))), (C) shows the potential of the source signal line (S (n)), and (D) shows the potential of the gate electrode of the driving TFT 102. Further, the period 1101 from the selection of the gate signal line on the m-th line to the selection of the gate signal line on the m-th line is the subframe period (S) shown in FIG. 9 (B).
In F #), the period indicated by 1102 is one horizontal period. 1 and 11 are used for the explanation of the operation, and the switching TFT 101 is used according to the gate signal line selected on the m-th line.
The pixel in which is controlled will be described.

First, during the period when the gate signal line on the m-1 line is selected, that is, during the period when the video signal is written on the m-1 line, the gate signal line on the m-1 line has an H level.
The gate signal line on the mth line is at L level. Therefore, the switching TFT 101 is turned off, and the refreshing TFT 151 is turned on.
_{At this time, V 1} = VSS is input to the gate electrode of the driving TFT 102, and the drive TFT 102 is turned off.
In FIG. 11, it is an operation performed during the period shown by 1103.

Subsequently, the horizontal period of the m-1th line ends, and the gate signal line (G (m-1)) becomes the L level. Along with this, the refresh TFT 151 is turned off. Entering the horizontal period on the mth line, the gate signal line (G (m)) becomes the H level. Along with this, the switching TFT 101 is turned on.
To do. At this time, the digital video signal output to the source signal line is written to the pixels. When the digital video signal is at H level, the potential of the gate electrode of the driving TFT 102 rises because the switching TFT is ON.

However, now that the gate signal line (G (m)) is at H level, its potential is VDD, and the digital video signal is H level, and its potential is also VDD, the potential that appears on the output electrode of the switching TFT. Is affected by the threshold value, so that the switching TFT is turned off at the point of (VDD-VthN), and the output electrode of the switching TFT, that is, the gate electrode of the driving TFT 102 is in a floating state.

On the other hand, since the potential of the output electrode of the switching TFT 101 rises to (VDD-VthN), the compensation TFT 152 is turned on, and the potential of the output electrode rises to approach VDD. At this time, there is a capacitive coupling by the first capacitive means 153 between the output electrode of the compensating TFT 152 and the gate electrode. Now, the gate electrode of the compensation TFT 152 is (VDD-VthN).
Since it is in a floating state with the potential of, the potential further rises as the potential of the output electrode of the compensation TFT 152 rises, and the potential becomes higher than VDD.

As a result, the digital video signal once attenuated by VthN through the switching TFT 10 receives its amplitude compensation by the voltage compensation circuit 110 and is input to the gate electrode of the driving TFT 102. Therefore, the drive TFT 102 can be turned on normally, and a desired drain current can flow.

After that, the potential applied to the gate electrode of the driving TFT 102 is maintained by the first and second capacitance means 153 and 154 even after the selection of the gate signal line is completed and the address (writing) period is further completed. As a result, a drain current flows, and the EL element 104 emits light. In the next subframe period, when the gate signal line (G (m-1)) on the m-1th line is selected and reaches the H level, the refresh TFT 151 is turned on and the potential of the gate electrode of the drive TFT 102 is changed. It becomes L level and turns off. After that, the above operation is repeated to draw the screen.

Here, the first and second capacitance means 153 and 154 will be added.

The first capacitive means 153 is arranged between the gate electrode and the output electrode of the compensating TFT 152, and is a capacitive means for raising the potential of the gate electrode by capacitive coupling by utilizing the potential increase of the output electrode. The second capacitance means 154 is arranged in series with the first capacitance means 153, and is capacitively coupled between the current supply line having a constant potential and the gate electrode of the drive TFT 102 to form a gate electrode of the drive TFT 102. It is a capacitive means for holding an electric potential.

Here, it should be added that as another role of the second capacitance means 154, it is used as a load for surely performing the bootstrap operation of the voltage guarantee circuit 110. Without this load, the potential of the gate electrode of the compensation TFT 152 starts to rise due to the input of the digital video signal from the source signal line, and when the threshold value is exceeded, the potential of the output electrode of the compensation TFT 152 rises immediately. .. If the potential of the output electrode rises too quickly, the bootstrap may not work properly. Therefore, by using the second capacitance means 154 as a load, the potential rise of the output electrode of the compensating TFT 152 is intentionally delayed, and the gate electrode is brought into a floating state before the potential rise of the output electrode is stopped. As a result, the bootstrap operation can be performed more reliably.

By the above method, the voltage amplitude of the gate signal line selection pulse, which requires a voltage amplitude larger than the voltage amplitude of the digital video signal normally input to the source signal line, can be made equal to the voltage amplitude of the digital video signal. It will be possible. Therefore, it is possible to reduce the power consumption of the gate signal line drive circuit.

Further, according to the present invention, the potential of the gate electrode of the driving TFT 102 can be made higher than the H level of the digital video signal input from the source signal line by the bootstrap operation. Since the potential of the gate electrode of the driving TFT 102 usually needs to rise to VDD at the H level, the potential rise due to capacitive coupling can be estimated in detail.
Further, the voltage amplitude of the gate signal line selection pulse can be reduced.

Examples of the present invention will be described below.

In the present invention, regarding the first power supply potential (V ₁ ) and the second power supply potential (V ₂ ), when the polarity of the TFTs constituting the pixels is N channel type, V ₁ = VSS and V ₂ = VDD. When the polarity of the TFTs that make up the pixels is a P-channel type, V ₁ = VDD and V ₂ = VSS may be set, and a power supply line may be routed to the pixel portion, respectively. Will decrease.

In this embodiment, existing signal lines such as a source signal line, a gate signal line, and a current supply line are used.
The connection between the elements for supplying the desired power potential to V ₁ and V _{2 is shown.}

2 (A) to 2 (C) show an example of connection.

In the case of FIG. 2A, the input electrode of the refresh TFT 151 is connected to the current supply line (Curren).
At t), the input electrode of the compensation TFT 152 is connected to the gate signal line (G (m)) on the mth line. In the case of FIG. 2B, the input electrode of the refreshing TFT 151 and the input electrode of the compensating TFT 152 are both connected to the gate signal line (G (m)) on the mth line. In the case of FIG. 2 (C)
The input electrode of the refresh TFT 151 is connected to the gate signal line (G (m)) on the mth line, and the compensation TF.
The input electrode of T152 is connected to the current supply line (Curent).

At this time, the polarity and the emission direction of the EL element in each case will be described.

First, in the pixel scanned in the m-th row, the refresh TFT 151 is turned on only during the selection period in the m-1th row, and the potential of the gate electrode of the driving TFT 102 is lowered to the L level.
In the case of FIG. 2A, since the current supply line has a substantially fixed potential, the potential may be set to correspond to the L level. In the case of FIGS. 2B and 2C, the gate signal line on the m-th line has an L level in a period other than the selection period on the m-th line.

On the other hand, in the pixel scanned in the m-th row, the compensation TFT 152 is turned on during the selection period in the m-th row, and the potential of the output electrode rises, so that the driving TF utilizing the capacitive coupling is used.
The potential of the gate electrode of T102 is raised. Therefore, the signal line to which the input electrode of the compensation TFT 152 is connected needs to be at the H level during the selection period of the m-th line. Figure 2 (
In the cases of A) and (B), the input electrode of the compensation TFT 152 is connected to the gate signal line (G (m)) on the mth line, and the gate signal line selection pulse is input during the selection period on the mth line. Therefore, the gate signal line (G (m)) on the mth line has an H level. In the case of FIG. 2C, the input electrode of the compensation TFT 152 is connected to the current supply line (Curent). Since the current supply line has a substantially fixed potential, the potential may be set to correspond to the H level.

The above is an example of the case where the TFTs constituting the pixels are N-channel type. However, even when the TFTs constituting the pixels are of the P channel type, the H level and L level of each node and each power supply potential may be reversed, so the connections shown in FIGS. 2 (A) to 2 (C) are shown. Can be applied as it is.

From the above, when the TFT constituting the pixel is an N-channel type, in FIGS. 2A and 2B, the potential of the current supply line (Curent) may be near the L level. Therefore, since the potential can be set low in the circuit, the electrode on the side connected to the driving TFT 102 in the EL element may be the cathode and the common electrode may be the anode. In this case, the emission direction is the anode side,
That is, it is emitted upward. On the other hand, in FIG. 2C, the potential of the current supply line (Curent) may be near the H level. Therefore, it is possible to set a high potential in the circuit, so E
The electrode on the side of the L element connected to the driving TFT 102 may be an anode, and the common electrode may be a cathode. In this case, the emission direction is the anode side, that is, the downward emission.

On the other hand, when the TFT constituting the pixel is a P-channel type, the potential is opposite to that described above.
That is, in the case of FIGS. 2 (A) and 2 (B), the electrode on the side of the EL element connected to the driving TFT 102 may be the anode and the common electrode may be the cathode, resulting in downward emission. In the case of FIG. 2C, EL
The electrode on the side of the element connected to the driving TFT 102 may be a cathode and the common electrode may be an anode, and the light is emitted downward.

In this embodiment, the T of the drive circuit provided on the same substrate as the pixel portion and around the pixel portion.
A method of simultaneously producing FT will be described.

First, as shown in FIG. 6 (A), a silicon oxide film and silicon nitride are formed on a substrate 5001 made of barium borosilicate glass typified by Corning's # 7059 glass, # 1737 glass, or aluminoborosilicate glass. A base film 5002 made of a film or an insulating film such as a silicon oxide nitride film is formed. Although not particularly shown, for the formation of the undercoat film 5002, for example, a _{silicon oxynitride film produced from SiH 4} , NH ₃ , N ₂ O by a plasma CVD method is used at 10 to 200 [nm] (preferably 50 to 50 to 5). Formed to a thickness of 100 [nm]) and similarly Si
A _{silicon oxide hydrogenated silicon film made from H 4} , N ₂ O is 50 to 200 [nm] (preferably 1).
It is laminated to a thickness of 00 to 150 [nm]).

Subsequently, the island-shaped semiconductor layers 5003 to 5005 form a semiconductor film having an amorphous structure. It is formed of a crystalline semiconductor film produced by using a laser crystallization method or a known thermal crystallization method. The island-shaped semiconductor layers 5003 to 5005 are formed to have a thickness of 25 to 80 [nm] (preferably 30 to 60 [nm]). The material of the crystalline semiconductor layer is not particularly limited, but it is preferably formed of silicon, a silicon germanium (SiGe) alloy, or the like.

To produce a crystalline semiconductor film by the laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser is used. When these lasers are used, it is preferable to use a method in which the laser light emitted from the laser oscillator is linearly focused by an optical system and irradiated to the semiconductor film. The crystallization conditions are appropriately selected by the practitioner, but when using an excimer laser, the pulse oscillation frequency is set to 30 [Hz] and the laser energy density is set to 100 to 400 [mJ / cm ² ] (typically). Is 200 to 300 [mJ / cm ² ]). Also,
When using a YAG laser, use its second harmonic and pulse oscillation frequency 1-10 [kHz.
], And the laser energy density is 300 to 600 [mJ / cm ² ] (typically 350 to 500 [m].
J / cm ² ]) is good. Then, a laser beam focused linearly with a width of 100 to 1000 [μm], for example, 400 [μm] is irradiated over the entire surface of the substrate, and the superposition rate of the linear laser at this time (
The overlap rate) is set to 80 to 98 [%].

Subsequently, a gate insulating film 5006 covering the island-shaped semiconductor layers 5003 to 5005 is formed.
The gate insulating film 5006 uses a plasma CVD method or a sputtering method and has a thickness of 40 to 15.
It is formed of an insulating film containing silicon as 0 [nm]. In this embodiment, it is formed of a silicon oxide film having a thickness of 120 [nm]. Of course, the gate insulating film is not limited to such a silicon oxide nitride film, and an insulating film containing other silicon may be used as a single layer or a laminated structure. For example, when silicon oxide is used, TEOS (Tetraethyl) is used by the plasma CVD method.
Orthosilicate) and O ₂ are mixed to set a reaction pressure of 40 [Pa], a substrate temperature of 300 to 400 [° C], and a high frequency (13.56 [MHz]) power density of 0.5 to 0.8 [W / cm ^2]. ] Can be formed by discharging. The silicon oxide film thus produced can be subsequently subjected to thermal annealing at 400 to 500 [° C.] to obtain good characteristics as a gate insulating film.

Then, the first conductive film 5007 for forming the gate electrode on the gate insulating film 5006
And the second conductive film 5008 are laminated and formed. In this embodiment, the first conductive layer 5007 is formed of tantalum (Ta) to a thickness of 50 to 100 [nm], and the second conductive layer 5009 is made of tungsten (Tungsten (Ta)).
W) is formed to a thickness of 100 to 300 [nm] (FIG. 6 (A)).

The Ta film is formed by sputtering a target of Ta with Ar by a sputtering method.
In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relaxed and the film can be prevented from peeling. Further, the resistivity of the Ta film of the α phase is about 20 [μΩcm] and can be used as a gate electrode, but the resistivity of the Ta film of the β phase is about 180 [μΩcm], which is not suitable for the gate electrode. is there. In order to form the α phase Ta film, tantalum nitride (TaN) having a crystal structure close to the α phase of Ta is formed on the base of Ta with a thickness of about 10 to 50 [nm] to form the α phase. A Ta film can be easily obtained.

When forming a W film, it is formed by a sputtering method targeting W. Besides 6
It can also be formed by a thermal CVD method using tungsten fluoride (WF _6). In any case, in order to use it as a gate electrode, it is necessary to reduce the resistivity, and the resistivity of the W film is 20 [
It is desirable to make it less than μΩcm]. The resistivity of the W film can be reduced by enlarging the crystal grains, but when there are many impurity elements such as oxygen in W, crystallization is inhibited and the resistivity is increased. From this, in the case of the sputtering method, a W target having a purity of 99.9999 [%] is used, and the W film is formed with sufficient consideration to prevent impurities from being mixed in the gas phase during film formation. A resistivity of 9 to 20 [μΩcm] can be realized.

In this embodiment, the first conductive film 5007 is Ta and the second conductive film 5008 is W.
However, the present invention is not particularly limited, and all of them may be formed of an element selected from Ta, W, Mo, Al, and Cu, or an alloy material or compound material containing the element as a main component. Further, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. As an example of a combination other than this embodiment, a combination in which the first conductive film is TaN and the second conductive film is W, the first conductive film is TaN, and the second conductive film is Al. ,
A combination in which the first conductive film is TaN and the second conductive film is Cu is desirable.

Next, a first mask 5009 made of resist is formed to form electrodes and wiring.
Etching process is performed. In this example, an ICP (Inductively coupled plasma) etching method is used _{to mix CF 4} and Cl ₂ with the etching gas and 1 [Pa].
At the pressure of, 500 [W] RF (13.56 [MHz]) power is applied to the coil type electrode to generate plasma. RF power of 100 [W] is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. When CF ₄ and Cl ₂ are mixed, both the W film and the Ta film are etched to the same extent.

Under the above etching conditions, the end portions of the first conductive film and the second conductive film have a tapered shape due to the suitable shape of the mask made of resist and the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °.
In order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of 10 to 20 [%]. The selection ratio of the silicon oxide film to the W film is 2 to
Since it is 4 (typically 3), the exposed surface of the silicon oxide nitride film is etched by about 20 to 50 [nm] by the overetching treatment. In this way, the first conductive layers 5010a to 5013a and the second conductive layers 5010b to 5013 are subjected to the first etching process.
The first-shaped conductive layer 501 to 5013 made of b is formed. At this time, in the gate insulating film 5006, the region not covered by the conductive layers 501 to 5013 of the first shape is 20 to 20 to
A region thinned by etching by about 50 [nm] is formed (FIG. 6 (B)).

Then, the first doping treatment is performed, and an impurity element that imparts N-type is added (FIG. 6 (B).
)). The doping treatment may be carried out by an ion doping method or an ion implantation method. The conditions for the ion doping method are that the dose amount is 1 × 10 ^{13 to} 5 × 10 ¹⁴ [atoms / cm ² ] and the acceleration voltage is 60 to 100 [keV]. As the impurity element that imparts N-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used, but P is used here. In this case, the conductive layers 501 to 5013 serve as a mask for the impurity element that imparts N-type, and the first impurity regions 5014 to 5016 are formed in a self-aligned manner. This first impurity region 50
To 14 to 5016, an impurity element that imparts N-type is added in a concentration range of ^{1 × 10 20} to 1 × 10 ²¹ [atoms / cm ^3].

Next, a second etching process is performed (FIG. 6 (C)). Similarly, using the ICP etching method, CF ₄ , Cl ₂ and O ₂ are mixed with the etching gas, and the coil type electrode is 5 at a pressure of 1 [Pa].
It supplies 00 [W] RF power to generate plasma. 50 on the substrate side (sample stage)
The RF power of [W] is applied, and a self-bias voltage lower than that of the first etching process is applied. Under such conditions, W, which is the second conductive layer, is anisotropically etched, and Ta, which is the first conductive layer, is anisotropically etched at a slower etching rate to obtain a conductive layer having a second shape. 5017 to 5020 (first conductive layer 5017a to 5020a and second conductive layer 5017
b ~ 5020b) is formed. At this time, in the gate insulating film 5006, the region not covered by the conductive layers 5017 to 5020 of the second shape is further etched by about 20 to 50 [nm] to form a thinned region.

The etching reaction of the W film or Ta film with _{a mixed gas of CF 4} and Cl ₂ can be inferred from the generated radicals or ionic species and the vapor pressure of the reaction product. Comparing the vapor pressures of fluoride and chloride of W and Ta, the vapor pressure of WF ₆ , which is the fluoride of W, is extremely high, and the vapor pressures of other WCl ₅ , TaF ₅ , and TaCl ₅ are similar. Therefore, in _{the mixed gas of CF 4} and Cl ₂ , both the W film and the Ta film are etched. However, an appropriate amount of O _{2 for this mixed gas}
When is added, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high vapor pressure of fluoride increases. on the other hand,
For Ta, even if F increases, the increase in etching rate is relatively small. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding _{O 2.} Since the oxide of Ta does not react with fluorine and chlorine, the etching rate of the Ta film is further reduced. Therefore, it is possible to make a difference in the etching rate between the W film and the Ta film.

Then, a second doping treatment is performed (FIG. 6 (D)). In this case, the impurity element doping is performed by lowering the dose amount as compared with the first doping treatment and imparting N-type as a condition of a high acceleration voltage. For example, the acceleration voltage is 70 to 120 [keV], ^{the dose is 1 × 10 13} [atoms / cm ² ], and the first impurity region formed on the island-shaped semiconductor layer in FIG. 6 (B) is formed. A new impurity region is formed inside. For doping, the second conductive layers 5017b to 5020b are used as a mask for impurity elements, and the impurity elements are also added to the lower region of the first conductive layers 5017a to 5020a.
In this way, the second impurity regions 5021 to 5023 that overlap the first conductive layer are formed.

Subsequently, a third etching process is performed (FIG. 7 (A)). Here, Cl is used as the etching gas.
₂ is used and an ICP etching apparatus is used. In this embodiment, the gas flow rate ratio of _{Cl 2 is set to 60.}
It was set to [sccm], and an RF power of 350 [W] was applied to the coil-shaped electrode at a pressure of 1 [Pa] to generate plasma, and etching was performed for 70 seconds. RF power is also applied to the substrate side (sample stage),
A substantially negative self-bias voltage is applied. By the third etching, the first conductive layer recedes to form the third conductive layers 5024 to 5027 (first conductive layers 5024a to 5027a and second conductive layers 5024b to 5027b), and the second Impurity region 5021-5
023 is a second impurity region 5028a to 5030a that overlaps with the first conductive layer and a third impurity region 5028b to 5030b that does not overlap with the first conductive layer.

In the steps up to the above, impurity regions are formed in each island-shaped semiconductor layer. The third-shaped conductive layers 5024 to 5026 that overlap the island-shaped semiconductor layer function as the gate electrodes of the TFT. Further, the conductive layer 5027 having a third shape functions as a source signal line.

Subsequently, for the purpose of controlling the conductive type, a step of activating the impurity element added to each island-shaped semiconductor layer is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method and a rapid thermal annealing method (RTA method) can be applied. The thermal annealing method is carried out at 400 to 700 [° C.], typically 500 to 600 [° C.] in a nitrogen atmosphere having an oxygen concentration of 1 [ppm] or less, preferably 0.1 [ppm] or less.
In this example, the heat treatment is performed at 500 [° C.] for 4 hours. However, when the wiring material used for 5024 to 5027 is sensitive to heat, it is desirable to perform thermal activation after forming an interlayer insulating film (mainly composed of silicon) in order to protect the wiring and the like.

Further, in an atmosphere containing 3 to 100 [%] of hydrogen, heat treatment is performed at 300 to 450 [° C.] for 1 to 12 hours to hydrogenate the island-shaped semiconductor layer. This step is a step of terminating the dangling bond of the semiconductor layer with thermally excited hydrogen. As another method of thermal hydrogenation for hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be used.

Next, as shown in FIG. 7B, the first interlayer insulating film 5031 is formed with a silicon oxide nitride film having a thickness of 100 to 200 [nm]. After forming a second interlayer insulating film 5032 made of an organic insulating material on the interlayer insulating film 5032, contact holes are opened in the first interlayer insulating film 5031, the second interlayer insulating film 5032, and the gate insulating film 5006. After forming a film of wiring material and patterning each wiring 5033 to 5037 and the connection electrode 5038, the connection electrode 5
The pixel electrode 5039 is patterned and formed so as to be in contact with 038.

In this specification, the substrate in which the wirings 5033 to 5037 and the connection electrodes 5038 are formed is referred to as an active matrix substrate.

As the second interlayer insulating film 5032, a film made of an organic resin such as polyimide, polyamide, acrylic, or BCB (benzocyclobutene) is used. In particular, the second interlayer insulating film 50
Since 32 has a strong meaning of flattening, acrylic having excellent flatness is desirable. In this embodiment, the acrylic film is formed with a film thickness capable of sufficiently flattening the step formed by the TFT. It may be preferably 1 to 5 [μm] (more preferably 2 to 4 [μm]).

For the formation of contact holes, dry etching or wet etching is used, and N
Impurity regions of the mold 5014-5016, and reach source signal lines 5027, gate signal lines (not shown), current supply lines (not shown) and gate electrodes 5024-5026 (not shown).
Each contact hole is formed.

Further, as wirings 5033 to 5038, the Ti film is 100 [nm] and the Al film containing Ti is 30.
A 0 [nm], Ti film of 150 [nm] is formed by patterning a three-layer laminated film continuously formed by a sputtering method into a desired shape. Of course, other conductive materials may be used.

Further, in this embodiment, 200 by using MgAg or the like as the pixel electrode (reflection electrode) 5039.
Form and pattern with a thickness of [nm]. The pixel electrode 5039 is arranged so as to overlap the connection electrode 5038 to make contact.

Next, as shown in FIG. 7 (C), an insulating film of 1 to 3 [μm] is formed using an organic material such as acrylic.
It is formed to a thickness of about the same degree, and an opening is formed at a position corresponding to the pixel electrode 5039 to form a third interlayer insulating film 5040. When forming the opening, it is desirable to perform etching so that the shape of the side wall is tapered. If the side wall is not sufficiently gentle, E due to the step
Deterioration of the L layer, step breakage, and the like become significant problems.

Subsequently, after forming the EL layer 5041 by using a vacuum vapor deposition method, the counter electrode (transparent electrode) 50
Form 42. The film thickness of the EL layer may be 80 to 200 [um] (typically 100 to 120 [nm]), and the film thickness of the pixel electrode (transparent electrode) 5042 may be 110 [nm].

In this step, an EL layer and a pixel electrode (transparent electrode) are sequentially formed on the pixel corresponding to red, the pixel corresponding to green, and the pixel corresponding to blue. However, since the EL layer has poor resistance to solution, it must be formed individually for each color without using photolithography technology. Therefore, it is desirable to hide the pixels other than the desired pixels with a metal mask or the like, and selectively form the EL layer and the pixel electrodes (transparent electrodes) only in the necessary places.

Here, a method of forming three types of EL elements corresponding to RGB is used, but a method of combining an EL element that emits white light and a color filter, an EL element that emits blue or blue-green light, and a phosphor (fluorescent). A method or the like in combination with a color conversion layer (CCM) may be used.

A known material can be used as the EL layer 5041. As a known material, it is desirable to use an organic material in consideration of the driving voltage.

In the steps up to this point, a cathode made of MgAg, an EL layer, and an anode made of a transparent conductive film are formed. Next, the passivation film made of the silicon nitride film is used as the protective film 5043, and is 50 to 300.
Form to a thickness of [nm]. The protective film 5043 protects the EL layer from moisture and the like.

In fact, when the state shown in FIG. 7C is completed, a protective film (laminated film, ultraviolet curable resin film, etc.) with high airtightness and little degassing and translucency so as not to be further exposed to the outside air. It is preferable to package (enclose) with a sealing material. At that time, if the inside of the sealing material is made into an inert atmosphere or a hygroscopic material (for example, barium oxide) is arranged inside, the reliability of the EL element is improved.

After improving the airtightness by processing such as packaging, attach a connector (flexible printed circuit: FPC) for connecting the terminal routed from the element or circuit formed on the board and the external signal terminal. Completed as a product.
Such a state in which the product can be shipped is referred to as a light emitting device in the present specification.

Further, according to the process shown in this embodiment, the number of photomasks required for producing the active matrix substrate is four (island-shaped semiconductor layer pattern, first wiring pattern (gate wiring, island-shaped source wiring, capacitive wiring). ), Contact hole pattern, second wiring pattern (including connection electrode)). As a result, the process can be shortened, which can contribute to the reduction of manufacturing cost and the improvement of yield.

In the step shown in Example 2, the TFT constituting the drive circuit and the pixel is a TFT having a normal single gate structure, but in the present invention, as shown in FIG. 10C, an active layer is sandwiched between the TFTs. It may be carried out using a TFT having a structure having a plurality of gate electrodes. The manufacturing process will be described below.

A conductive film made of a conductive material is formed on a substrate 7001 made of barium borosilicate glass typified by Corning's # 7059 glass, # 1737 glass, or the like, or aluminoborosilicate glass, and by patterning, FIG. Lower gate electrode 7 as shown in A)
Form 002. The material constituting the lower gate electrode is not particularly limited as long as it is a conductive material, but Ta, W or the like is typically used.

Next, the first insulating film 7003 is formed. The first insulating film 7003 is formed with a thickness of 10 to 50 [nm] using silicon oxide nitride.

As shown in FIG. 10A, the surface at the time when the first insulating film 7003 is formed has irregularities due to the lower gate electrode 7002. Considering the subsequent manufacturing process, it is desirable to flatten this unevenness. Here, as a flattening method, CMP (Chemical Mechanical)
Polishing) is used. CMP is one of the polishing methods for obtaining a precise smooth surface by applying a chemical treatment to the surface of an object to be polished to make it easy to polish, and then mechanically polishing the surface.

A silicon oxide film or a silicon nitride nitride film is formed as a flattening film 7004 on the first insulating film 7003 to a thickness of 0.5 to 1 [μm]. As the CMP abrasive (slurry) for the flattening film 7004, for example, it is preferable to use one in which fumed silica particles obtained by thermally decomposing silicon chloride gas are dispersed in a KOH-added aqueous solution. Flattening film 700 by CMP
4 is polished and removed by about 0.5 to 1 [μm] to flatten the surface.

In this way, as shown in FIG. 10B, a state in which the surface is flattened is obtained. After that, the TFT may be formed according to the fourth embodiment to form peripheral circuits and pixels.

The TFT produced here has a gate electrode and a lower gate electrode that overlap each other so as to sandwich the active layer. Here, when quick response is required as in a switching circuit or the like, signals are input to both the lower gate electrode 7002 and the gate electrode 7006. By inputting the same signal to both gate electrodes, the depletion of the channel region in the active layer progresses quickly, the electric field effect mobility increases, and the current capacity can be increased, so that quick response can be expected. ..

On the other hand, when uniform characteristics and reduction of off-leakage current are required as in the driving TFT in the pixel section, a signal is input to the gate electrode and the lower gate electrode is fixed at a certain constant potential. It is used in this way. The constant potential at this time is a potential that is surely turned off when the potential is applied to the gate electrode of the TFT. Typically, when the TFT is an N-channel type, it is used as a low-potential side power supply such as VSS, and when the TFT is a P-channel type, it is used as a power source on the low potential side.
It is good to connect to a high potential power supply such as VDD. In this case, the variation in the threshold voltage can be reduced as compared with the TFT having the structure without the lower gate electrode. Furthermore, it is effective because it can be expected to reduce the off-leakage current.

In this embodiment, an example in which a light emitting device having the pixels shown in the embodiment is manufactured will be described.

FIG. 4 shows a schematic view of the light emitting device. The pixel portion 401 is arranged in the central portion of the substrate 400. Although not particularly shown in FIG. 4, the configuration of one pixel is as shown in FIG. A source signal line drive circuit 402 for controlling the source signal line and a gate signal line drive circuit 407 for controlling the gate signal line are arranged around the pixel unit 401. Although the gate signal line drive circuit 407 is symmetrically arranged on both sides of the pixel portion 401 in FIG. 4,
It may be arranged on only one side. However, from the viewpoint of circuit operation efficiency and reliability, it is desirable to arrange them symmetrically on both sides.

The signal input from the outside for driving the source signal line drive circuit 402 and the gate signal line drive circuit 407 is input via the FPC 410. In this embodiment, FPC41
The signal input from 0 is in line with the drive voltage of a commonly used IC.
Since the voltage amplitude is small, the voltage amplitude is converted by the level shifter 406, and then
It is input to the source signal line drive circuit 402 and the gate signal line drive circuit 407.

FIG. 13 shows the configuration of the source signal line drive circuit. Shift register 1303
, Buffer 1304, first latch circuit 1305, second latch circuit 1306.
Although the buffer is not shown in FIG. 20, a buffer may be provided as shown in FIG. 13 when the load below the shift register is large.

The source signal line drive circuit includes a source side clock signal (SCLK), a source side clock inversion signal (SCLKb), a source side start pulse (SSP), a scanning direction switching signal (LR), and a scanning direction switching inversion signal (LRb). Digital video signals (Data1 to 3) are input. this house,
The clock signal and start pulse are input after undergoing amplitude conversion by the level shifters 1301 and 1302.

FIG. 14 shows the configuration of the shift register. In the block diagram shown in FIG. 14 (A), 1
The block shown by 400 is a pulse output circuit that outputs a sampling pulse for one stage, and the shift register of FIG. 14A is composed of an n-stage (n is a natural number, 1 <n) pulse output circuit. There is.

FIG. 14B shows in detail the configuration of the pulse output circuit. Here, TFT 14
07, 1408, 1409, and 1410 are switch Ts provided for switching the scanning direction.
It is an FT, and the left and right scanning directions are switched by the scanning direction switching signal (LR) and the scanning direction switching inversion signal (LRb).

In the case of forward scanning, the output of the sampling pulse is in the order of the first stage, the second stage, ..., N-1st stage, and the nth stage, and in the case of reverse scanning, the output of the sampling pulse is. nth stage, n-
The first stage, ..., the second stage, and the first stage.

The pulse output circuit main body includes TFTs 1401-1406 and a capacitance 1411. In a certain k-th stage (k is a natural number, 1 <k <n) pulse output circuit, TFTs 1401 and 140
Either the output pulse from the pulse output circuit of the k-1st stage or the output pulse from the pulse output circuit of the k + 1th stage is input to the gate electrode of No. 4 and the gate electrode of the TFTs 1402 and 1403, respectively. In addition, k = 1, that is, TF in the pulse output circuit of the first stage.
A start pulse (SP) is input to the gate electrodes of T1401 and 1404 and k = n, that is, the gate electrodes of TFTs 1402 and 1403 in the pulse output circuit of the final stage.

In the forward scanning direction, the scanning direction switching signal (LR) is the Hi potential and the scanning direction switching inversion signal (L).
The Lo potential is input to Rb). Therefore, TFT1407 and 1410 are turned on, and TFT14
The output pulse from the pulse output circuit of the k-1st stage is input to the gate electrodes 01 and 1404. On the other hand, the output pulse from the k + 1st stage pulse output circuit is input to the gate electrode of TFT 1402 and 1403.

Here, detailed circuit operation will be described by taking the case of forward scanning as an example. Refer to the timing chart shown in FIG.

In a certain k-th stage pulse output circuit, k- is applied to the gate electrodes of TFTs 1401 and 1404.
The output pulse from the first-stage pulse output circuit is input (k = 1, that is, the start pulse is input in the case of the first stage), and the TFTs 1401 and 1404 are turned on (see FIG. 15 1501). As a result, the potential of the gate electrode of TFT 1405 is raised to the VDD side (see FIG. 15 1502), and when the potential becomes VDD-VthN, TF
T1401 turns off and becomes a floating state. At this point, the gate-source voltage of the TFT 1405 has exceeded the threshold value, and the TFT 1405 is turned on. On the other hand, TFT14
Since there is no pulse input at the gate electrodes of 02 and 1403 and the Lo potential remains.
It is off. Therefore, since the potential of the gate electrode of the TFT 1406 is the Lo potential and is OFF, the output terminal (SR Out) has the Hi potential of the clock signal (either SCLK or SCLKb) input to the input electrode of the TFT 1405. As a result, the potential of the output terminal (SR Out) of the pulse output circuit is raised to the VDD side (see FIG. 15 1503).
.. However, in the state up to this point, the potential of the output terminal (SR Out) of the pulse output circuit is T.
With respect to the potential VDD-VthN of the gate electrode of the FT1405, it can only rise to VDD-2 (VthN), which is further lowered by the threshold value.

Here, a capacitance 1411 is provided between the gate electrode and the output electrode of the TFT 1405, and further, since the gate electrode of the TFT 1405 is in a floating state, the potential of the output terminal (SR Out) of the pulse output circuit is present. As the potential of the output electrode of the TFT 1405 rises, the potential of the gate electrode of the TFT 1405 rises due to the action of the capacitance 1411.
It is further pulled up from VDD-VthN. By this operation, the potential of the gate electrode of the TFT 1405 finally becomes a potential higher than VDD + VthN (FIG. 15 1502).
reference). The potential of the output terminal (SR Out) of the pulse output circuit normally rises to VDD without being affected by the threshold value of TFT 1405 (see FIG. 15 1503).

Similarly, a pulse is output from the pulse output circuit of the k + 1st stage (FIG. 15 150).
4). The output pulse of the k + 1st stage returns to the kth stage and is input to the gate electrode of the TFTs 1402 and 1403. The potential of the gate electrode of TFT 1402 and 1403 becomes Hi and O
N, the potential of the gate electrode of the TFT 1405 is lowered to the VSS side, and the TFT 1405 is turned off. At the same time, the potential of the gate electrode of the TFT 1406 becomes the Hi potential and turns ON, and the potential of the output terminal (SR Out) of the k-th stage pulse output circuit becomes the Lo potential.

After that, pulses having an amplitude between VDD and VSS are sequentially output by the same operation until the final stage. The operation of the circuit is the same in the reverse scanning.

In the final stage, since there is no pulse to be input back from the next stage, the clock signal continues to be output through the TFT 1405 as it is (see FIG. 15 1507).
Therefore, the output pulse of the pulse output circuit in the final stage cannot be used as a sampling pulse. Similarly, in the case of reverse scanning, since the output pulse of the first stage is the final output, it cannot be used as a sampling pulse as well.
Therefore, in the circuit shown in this embodiment, the shift register is configured by using the required number of stages + 2 stages of pulse output circuits, and both ends are treated as dummy stages (in FIG. 13, the buffer 1304 is not connected). The pulse output circuits at both ends correspond to the dummy stage). Still,
The final output must somehow be stopped before the next horizontal period begins.
The start pulse is used as the input of the first stage and the period input of the final stage, and the output of the final stage is stopped when the start pulse is input in the next horizontal period.

FIG. 16 shows the configuration of the buffer 1304 used in the light emitting device of this embodiment. As shown in FIG. 16 (A), it has a four-stage configuration of 1601 to 1604, and only the first stage has one input 1
The output type is a 2-input 2-output type for the second and subsequent stages.

The circuit configuration of the first stage unit 1601 is shown in FIG. 16 (B). The signals are TFT1652, 16
It is input to the gate electrode of 54. The gate electrode of TFT1651 is connected to the input electrode. When the Hi potential is input to the gate electrodes of TFTs 1652 and 1654 and turned on, T
The potential of the gate electrode of the FT1653 becomes the Lo potential, and as a result, the output terminal (Out) becomes Lo.
It becomes an electric potential. When the Lo potential is input to the gate electrodes of the TFTs 1652 and 1654 and is turned off, the TFT 1651 is always on because the gate electrode and the input electrode are connected.
The potential of the gate electrode of the TFT 1653 rises, and the output becomes the Hi potential due to the coupling due to the capacitance 1655 as in the case of the shift register described above.

As for the relationship between the TFT 1651 and the TFT 1652, since the gate electrode and the input electrode of the TFT 1651 are connected, when the TFT 1652 is turned on, the TFT 1651,
Both TFT 1652 are ON. In this state, the potential of the gate electrode of the TFT 1653 needs to be the Lo potential, so the channel width of the TFT 1651 is set to the TFT 16
It is necessary to design it smaller than 52. The channel width of the TFT 1651 may be minimal, as it is sufficient to have the capacity to charge one of the gate electrodes of the TFT 1653. Also, T
By making the FT1651 smaller, the VDD-TFT during the period when the TFT 1652 is ON
The increase in current consumption due to the through path between 1651-TFT1652-VSS can be minimized.

FIG. 16C shows the circuit configuration of the unit used in the second and subsequent stages. TFT16
The input to the gate electrode of 52 is the same as that of the first stage, and in addition, the input of the previous stage is used as the inverting input for the gate electrode of TFT 1651. By doing this, TFT1651
, 1652 are exclusively turned ON and OFF, and VDD-TFT16 in the configuration of FIG. 16B.
The penetration path between 51-TFT1652-VSS can be eliminated.

FIG. 17 shows the configurations of the clock signal level shifter (A) and the start pulse level shifter (B) used in the light emitting device of this embodiment. The basic configuration is level shifter for the first stage, 2
It has a four-stage configuration with the first and subsequent stages as buffers, and is the same as the buffer circuit described above. VD
A signal having an amplitude between D _{LO and} VSS is input, and an output signal having an amplitude between VDD and VSS is obtained (where | VDD _LO | <| VDD |).

In the case of the clock signal level shifter, the first stage is a 1-input 1-output type, and the second and subsequent stages are a 2-input 1-output type. For each input, each other's input is used as an inverted input.

The start pulse level shifter has the same configuration as the buffer described above.

The circuit configuration of the unit used in the first stage of the level shifter is shown in FIG. 17 (C), and the circuit configuration of the unit used in the second and subsequent stages is shown in FIG. 17 (D).
The circuit configurations and operations of the respective circuits are the same as those shown in FIGS. 16 (B) and 16 (C), except that _{the amplitude of the signal input to the first stage is between VDD LO and VSS.}

When the signal input to the gate electrode of TFT1752 is Hi potential, TFT1752 is O.
N (however, when the absolute value | VDD _{LO −} VSS | of the amplitude of the input signal is definitely larger than the absolute value | VthN | of the threshold value of TFT1752), the potential of the gate electrode of TFT1753 is lowered to the VSS side. Be done. Therefore, the Lo potential appears at the output terminal (Out). On the other hand, TF
When the signal input to the gate electrode of T1752 has a Lo potential, TFT1752 is turned off.
Then, through TFT1751, the potential of the gate electrode of TFT1753 is raised to the VDD side. Subsequent operations are the same as for the buffer described above.

As a feature of the level shifter of this configuration, the TFT 175 connected to the high potential side (VDD side)
One of the controls is that the input signal is not directly input to the gate electrode. Therefore, even when the amplitude of the input signal is small, the potential of the gate electrode of the TFT 1753 can be raised regardless of the threshold value of the TFT 1751, so that a high amplitude conversion gain can be obtained.

FIG. 18 shows the configuration of the first and second latch circuits used in the light emitting device of this embodiment. As a configuration example of a conventional CMOS-configured latch circuit, as shown in FIG. 21 (A), 2
It is generally composed of a holding unit in which three inverters are connected in a loop and a switch for controlling the holding timing, and further, FIG. 2 using a D-FF (flip-flop) circuit is used.
The configuration of 1 (B) can also be mentioned. FIG. 21C shows the simplest DRAM configuration.
The holding unit is composed of an inverter and a capacitance, and the capacitance holds the potential of a signal input to the inverters of the first latch circuit (LAT1) and the second latch circuit (LAT2). In this embodiment, the configuration shown in FIG. 21 (C), which has the simplest configuration, was used.

The latch circuit shown in FIG. 18 uses the analog switch shown in FIG. 21C as one N-channel type TF.
Replaced with T, the CMOS inverter is replaced with an NMO consisting of four N-channel TFTs and capacitance.
It has a configuration in which it is replaced with an S inverter.

A digital video signal is input from the input electrode of the TFT 1850 (Data In), a sampling pulse is input to the gate electrode (Pulse In), and when the TFT 1850 is turned on, the digital video signal is input to the inverter having TFTs 1851 to 1854 and a capacity of 1855. And the polarity is inverted and output. The digital video signal has a capacity of 1856.
Is held using.

In the second latch circuit, the digital video signal is written and held according to the input timing of the latch pulse (LAT) by the same operation.

FIG. 12 shows the circuit configuration of the gate signal line drive circuit. Shift register 12
03, has buffer 1204.

A gate-side clock signal (GCLK), a gate-side clock inversion signal (GLKb), and a gate-side start pulse (GSP) are input to the gate signal line drive circuit. These input signals are
Input after undergoing amplitude conversion by level shifters 1201 and 1202.

The shift register 1203, buffer 1204, and start pulse level shifter 1
201. The configuration and operation of the clock signal level shifter 1202 are the same as those used for the source signal line drive circuit, and thus the description thereof will be omitted here.

In FIG. 19, the gate signal line in the row indicated by α cannot obtain the gate signal line selection pulse input in the previous row in the pixel in the first row, so that the dummy stage (refresh operation in the pixel in the first row). It is provided as a dedicated).

The display device manufactured by using the drive circuit introduced here and the pixels shown in the embodiment of the invention is configured by using only a unipolar TFT, so that a part of the doping process in the process can be performed. It has become possible to reduce the number of photomasks and further reduce the number of photomasks. Furthermore, the problem of increasing current consumption by widening the signal amplitude, which was described in the above-mentioned problem section, can be solved by using a circuit to which the bootstrap method is applied.

The light emitting device of the present invention can be applied to the production of display devices used in various electronic devices. Examples of such electronic devices include mobile information terminals (electronic organizers, mobile computers, mobile phones, etc.), video cameras, digital cameras, personal computers, televisions, mobile phones, and the like. An example of them is shown in FIG.

FIG. 19A shows an OLED display, which includes a housing 3001, a support base 3002, and a display unit 3.
It is composed of 003 and the like. The present invention can be applied to the display unit 3003.

FIG. 19B shows a video camera, which is a main body 3011, a display unit 3012, and an audio input unit 301.
3. It is composed of an operation switch 3014, a battery 3015, an image receiving unit 3016, and the like. The present invention can be applied to the display unit 3012.

FIG. 19C shows a notebook-type personal computer, which has a main body 3021 and a housing 3022.
, Display unit 3023, keyboard 3024, and the like. In the present invention, the display unit 30
It can be applied to 23.

FIG. 19D shows a mobile information terminal, which includes a main body 3031, a stylus 3032, and a display unit 303.
3. It is composed of an operation button 3034, an external interface 3035, and the like. The present invention can be applied to the display unit 3033.

FIG. 19 (E) shows an audio reproduction device, specifically an in-vehicle audio device, which is a main body 3041.
, Display unit 3042, operation switches 3043, 3044 and the like. The present invention can be applied to the display unit 3042. Further, in this embodiment, an in-vehicle audio device is taken as an example, but it may be used for a portable or home-use audio device.

FIG. 19F is a digital camera, which includes a main body 3051, a display unit (A) 3052, and an eyepiece 30.
It is composed of 53, an operation switch 3054, a display unit (B) 3055, a battery 3056, and the like. The present invention can be applied to the display unit (A) 3052 and the display unit (B) 3055.

FIG. 19 (G) shows a mobile phone, which is a main body 3061, a voice output unit 3062, and a voice input unit 306.
3. It is composed of a display unit 3064, an operation switch 3065, an antenna 3066, and the like. The present invention can be applied to the display unit 3064.

It should be noted that the examples shown in this example are only examples and are not limited to these uses.

Claims (3)

It has first to twelfth transistors and
The first to twelfth transistors have the same polarity and have the same polarity.
One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor.
One of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor.
One of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the sixth transistor.
One of the source or drain of the seventh transistor is electrically connected to one of the source or drain of the eighth transistor.
One of the source or drain of the ninth transistor is electrically connected to one of the source or drain of the tenth transistor.
One of the source or drain of the eleventh transistor is electrically connected to one of the source or drain of the twelfth transistor.
The gate of the first transistor is electrically connected to the other of the source or drain of the first transistor.
The gate of the second transistor is electrically connected to the gate of the fourth transistor.
The gate of the third transistor is electrically connected to one of the source or drain of the first transistor.
The gate of the fifth transistor is electrically connected to the other of the source or drain of the fifth transistor.
The gate of the sixth transistor is electrically connected to the gate of the eighth transistor.
The gate of the seventh transistor is electrically connected to one of the source or drain of the fifth transistor.
The gate of the ninth transistor is electrically connected to one of the source or drain of the third transistor.
The gate of the tenth transistor is electrically connected to one of the source or drain of the seventh transistor.
The gate of the eleventh transistor is electrically connected to one of the source or drain of the ninth transistor.
A semiconductor device in which the gate of the twelfth transistor is electrically connected to one of the source and drain of the seventh transistor. It has first to twelfth transistors and
The first to twelfth transistors have the same polarity and have the same polarity.
One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor.
One of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor.
One of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the sixth transistor.
One of the source or drain of the seventh transistor is electrically connected to one of the source or drain of the eighth transistor.
One of the source or drain of the ninth transistor is electrically connected to one of the source or drain of the tenth transistor.
One of the source or drain of the eleventh transistor is electrically connected to one of the source or drain of the twelfth transistor.
The other of the source or drain of the second transistor, the other of the source or drain of the fourth transistor, the other of the source or drain of the sixth transistor, the other of the source or drain of the eighth transistor, and the second. The other of the source or drain of the ten transistors and the other of the source or drain of the twelfth transistor are electrically connected to each other.
The gate of the first transistor is electrically connected to the other of the source or drain of the first transistor.
The gate of the second transistor is electrically connected to the gate of the fourth transistor.
The gate of the third transistor is electrically connected to one of the source or drain of the first transistor.
The gate of the fifth transistor is electrically connected to the other of the source or drain of the fifth transistor.
The gate of the sixth transistor is electrically connected to the gate of the eighth transistor.
The gate of the seventh transistor is electrically connected to one of the source or drain of the fifth transistor.
The gate of the ninth transistor is electrically connected to one of the source or drain of the third transistor.
The gate of the tenth transistor is electrically connected to one of the source or drain of the seventh transistor.
The gate of the eleventh transistor is electrically connected to one of the source or drain of the ninth transistor.
A semiconductor device in which the gate of the twelfth transistor is electrically connected to one of the source and drain of the seventh transistor. It has first to twelfth transistors and
The first to twelfth transistors have the same polarity and have the same polarity.
One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor.
One of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor.
One of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the sixth transistor.
One of the source or drain of the seventh transistor is electrically connected to one of the source or drain of the eighth transistor.
One of the source or drain of the ninth transistor is electrically connected to one of the source or drain of the tenth transistor.
One of the source or drain of the eleventh transistor is electrically connected to one of the source or drain of the twelfth transistor.
The other of the source or drain of the second transistor, the other of the source or drain of the fourth transistor, the other of the source or drain of the sixth transistor, the other of the source or drain of the eighth transistor, and the second. The same potential is supplied to the other of the source or drain of the ten transistors and the other of the source or drain of the twelfth transistor.
The gate of the first transistor is electrically connected to the other of the source or drain of the first transistor.
The gate of the second transistor is electrically connected to the gate of the fourth transistor.
The gate of the third transistor is electrically connected to one of the source or drain of the first transistor.
The gate of the fifth transistor is electrically connected to the other of the source or drain of the fifth transistor.
The gate of the sixth transistor is electrically connected to the gate of the eighth transistor.
The gate of the seventh transistor is electrically connected to one of the source or drain of the fifth transistor.
The gate of the ninth transistor is electrically connected to one of the source or drain of the third transistor.
The gate of the tenth transistor is electrically connected to one of the source or drain of the seventh transistor.
The gate of the eleventh transistor is electrically connected to one of the source or drain of the ninth transistor.
A semiconductor device in which the gate of the twelfth transistor is electrically connected to one of the source and drain of the seventh transistor.

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