JP6848746B2 - Semiconductor device - Google Patents

Description

The techniques disclosed herein relate to semiconductor devices.

FIG. 2 shows a semiconductor device 100 disclosed in Non-Patent Document 1. The semiconductor device 100 includes an n-type nitride semiconductor substrate 110, a nitride semiconductor layer 120 laminated on the surface of the nitride semiconductor substrate 110, a drain electrode 132 that covers the back surface of the nitride semiconductor substrate 110, and a nitride semiconductor layer 120. The source electrode 134 is provided so as to cover a part of the surface of the nitride semiconductor layer 120, and the insulating gate portion 136 is provided so as to cover a part of the surface of the nitride semiconductor layer 120. The nitride semiconductor layer 120 has an n-type drift region 121, an n-type current constriction region 122, a p-type p-type buried region 123, an n-type source region 124, and a heterojunction region 127. The heterojunction 127 has an n-type lower hetero region 125 and an undoped upper hetero region 126. The bandgap of the upper heteroregion 126 is wider than the bandgap of the lower heteroregion 125. As a result, a two-dimensional electron gas is generated on the lower hetero region 125 side of the heterojunction surfaces of the lower hetero region 125 and the upper hetero region 126. The insulated gate portion 136 is arranged over the entire surface of the heterojunction region 127, and has a gate insulating film 136a and a gate electrode 136b.

When the semiconductor device 100 is on, electrons flow from the source region 124 into the current constriction region 122 via the two-dimensional electron gas generated in the lower hetero region 125. The electrons that have flowed into the current constriction region 122 flow vertically through the current constriction region 122 and head toward the drain electrode 132. As a result, the drain electrode 132 and the source electrode 134 become conductive.

When the semiconductor device 100 is off, the depletion layer extends from the p-type buried region 123 into the current constriction region 122. The current constriction region 122 is designed so that the depletion layers extending from both sides are connected to each other in a pinch-off state. By pinching off the current constriction region 122, the electric field applied to the gate insulating film 136a of the insulating gate portion 136 is relaxed, and dielectric breakdown of the gate insulating film 136a is suppressed.

Masakazu KANECHIKA et al. (2007) A Vertical Insulated Gate AlGaN / GaN Heterojunction Field-Effect Transistor, Japanese Journal of Applied Physics, Vol. 46, No. 21, pp.L503-L505

However, if the impurity concentration in the current constriction region is higher than the design value, the current constriction region is not satisfactorily pinched off when the semiconductor device is turned off, and there is a concern about dielectric breakdown of the gate insulating film. A semiconductor device having high reliability for variations in impurity concentration in the current constriction region is required.

The semiconductor device disclosed in the present specification includes a nitride semiconductor layer, an insulating gate portion provided on one main surface of the nitride semiconductor layer, and p provided on the main surface of the nitride semiconductor layer. A mold gate portion can be provided. The nitride semiconductor layer has an n-type drift region, an n-type current constriction region, a p-type p-type embedded region, a heterojunction region, and an n-type source region. The current constriction region is provided on the drift region. The p-type buried region is provided on the drift region, and is arranged with the current constriction region in between. The heterojunction region is provided on the current constriction region and the p-type buried region and has a heterojunction. The source region is provided on the p-type buried region and is separated from the current constriction region by a heterojunction region. The insulated gate portion is provided on the heterojunction region, and is arranged on the source region side of the p-type gate portion. The p-type gate portion has a p-type p-type gate region in contact with the heterojunction region. The p-type gate region has a portion arranged at least at a position overlapping the p-type buried region when observed from a direction orthogonal to the main surface of the nitride semiconductor layer.

In the semiconductor device, the p-type gate portion is provided on the heterojunction region, and when the semiconductor device is off, the depletion layer extends from the p-type gate region of the p-type gate portion into the heterojunction region. Further, the p-type gate region of the p-type gate portion has a portion arranged at least at a position overlapping the p-type buried region when observed from a direction orthogonal to the main surface of the nitride semiconductor layer. Therefore, at least a part of the heterojunction region is sandwiched between the p-type buried region and the p-type gate region, and this portion is satisfactorily depleted when the semiconductor device is off. Since the insulated gate portion is arranged closer to the source region than the portion of the heterojunction region sandwiched between the p-type buried region and the p-type gate region, a high electric field is generated in the insulated gate portion when the semiconductor device is off. Is suppressed. That is, even if the semiconductor device is manufactured in a state where the impurity concentration in the current constriction region is higher than the design value, it is possible to suppress the application of a high electric field to the insulating gate portion and suppress the dielectric breakdown of the insulating gate portion. As described above, the semiconductor device can have high reliability with respect to the variation in the impurity concentration in the current constriction region.

In the semiconductor device disclosed in the present specification, when the p-type gate region of the p-type gate portion is observed from a direction orthogonal to the main surface of the nitride semiconductor layer, the p-type embedded region overlaps with the current constriction region. It may be extended to a position overlapping with. When the p-type gate region of the p-type gate portion is provided in a wide range in this way, when the semiconductor device is turned off, the p-type gate region of the p-type gate portion is moved into the heterojunction region and the current constriction region. The depletion layer can be spread over a wide area, and the dielectric breakdown of the insulating gate can be further suppressed.

The semiconductor device disclosed herein may further include a drive unit. The drive unit is configured to apply a first drive voltage to the insulated gate portion and a second drive voltage to the p-type gate portion when it is in the ON state. The first drive voltage is larger than the second drive voltage. The switching operation of this semiconductor device is controlled based on the first drive voltage applied to the insulated gate portion. That is, this semiconductor device has a high threshold voltage, and malfunction due to noise can be suppressed.

The cross-sectional view of the main part of the semiconductor device is schematically shown. The cross-sectional view of the main part of the conventional semiconductor device is schematically shown.

As shown in FIG. 1, the semiconductor device 1 includes an n-type nitride semiconductor substrate 10, a nitride semiconductor layer 20 laminated on the surface of the nitride semiconductor substrate 10, and a drain electrode covering the back surface of the nitride semiconductor substrate 10. 32, a source electrode 34 provided so as to cover a part of the surface of the nitride semiconductor layer 20, an insulating gate portion 36 provided so as to cover a part of the surface of the nitride semiconductor layer 20, and , A p-type gate portion 38 provided so as to cover a part of the surface of the nitride semiconductor layer 20 is provided. The nitride semiconductor layer 20 has an n-type drift region 21, an n-type current constriction region 22, a p-type p-type buried region 23, an n-type source region 24, and a heterojunction region 27. The heterojunction region 27 has an n-type lower hetero region 25 and an undoped upper hetero region 26.

The nitride semiconductor substrate 10 is made of gallium nitride (GaN) containing silicon as an n-type impurity at a high concentration. The drain electrode 32 is provided so as to cover the entire back surface of the nitride semiconductor substrate 10, and is in ohmic contact with the nitride semiconductor substrate 10. The drain electrode 32 is a laminated electrode of titanium and aluminum. The nitride semiconductor substrate 10 is also a base substrate for epitaxially growing the nitride semiconductor layer 20.

The drift region 21 is made of gallium nitride (GaN) containing silicon as an n-type impurity. The drift region 21 is formed by crystal growth from the surface of the nitride semiconductor substrate 10 by using the Metal Organic Chemical Vapor Deposition (MOCVD) method.

The current constriction region 22 is made of gallium nitride (GaN) containing silicon as an n-type impurity. The current constriction region 22 is provided on a part of the surface of the drift region 21, and has a convex shape protruding from the surface of the drift region 21.

The p-type buried region 23 is made of gallium nitride (GaN) containing magnesium as a p-type impurity. The p-type buried region 23 is provided on a part of the surface of the drift region 21, and is arranged with the current constriction region 22 in between. The p-type embedded region 23 is exposed on the surface of the nitride semiconductor layer 20 in a cross section (not shown) and is in ohmic contact with the source electrode 34.

The p-type buried region 23 is formed by growing crystals from the surface of the drift region 21 by using the metalorganic chemical vapor deposition method, and then removing the portion corresponding to the current constriction region 22 by using the dry etching technique. To. The current constriction region 22 is formed by crystal growth from the surface of the drift region 21 exposed to the portion where a part of the p-type buried region 23 is removed by using the metalorganic chemical vapor deposition method.

The heterojunction region 27 is provided on the surfaces of the current constriction region 22 and the p-type buried region 23. The lower hetero region 25 is made of gallium nitride (GaN) containing silicon as an n-type impurity. The upper hetero region 26 is made of undoped aluminum gallium nitride (AlGaN). The lower hetero region 25 is formed at the same time as the current constriction region 22 is crystal-grown. The upper hetero region 26 is formed by crystal growth from the surface of the lower heterojunction region using the metalorganic chemical vapor deposition method.

The bandgap of the upper heteroregion 26 is wider than the bandgap of the lower heteroregion 25. Therefore, a two-dimensional electron gas is generated on the lower hetero region 25 side of the heterojunction surfaces of the lower hetero region 25 and the upper hetero region 26. In the semiconductor device 1, the thickness of the upper hetero region 26 and / or the aluminum composition of the upper hetero region 26 is adjusted so that the lower hetero region when the insulating gate portion 36 and the p-type gate portion 38 are grounded. 25 is configured so that two-dimensional electron gas is not generated. As a result, the semiconductor device 1 can operate with normalization off.

The source region 24 is a region containing a high concentration of silicon as an n-type impurity. The source region 24 is provided on the surface of the p-type buried region 23, is exposed on the surface of the nitride semiconductor layer 20, and is separated from the current constriction region 22 by the heterojunction region 27. The source region 24 is formed by irradiating a part of the heterojunction region 27 with silicon using an ion implantation technique. The source region 24 is in ohmic contact with the source electrode 34. The source electrode 34 is a laminated electrode of titanium and aluminum.

The insulating gate portion 36 is provided on a part of the surface of the nitride semiconductor layer 20, and has a silicon oxide gate insulating film 36a and a polysilicon gate electrode 36b. Specifically, the insulated gate portion 36 is provided so as to cover a part of the surface of the heterojunction region 27, is arranged on the source region 24 side of the p-type gate portion 38, and one end thereof is the source region. It is in contact with 24. Further, the insulating gate portion 36 is arranged so as to be within the range of the p-type buried region 23 when observed from a direction orthogonal to the surface of the nitride semiconductor layer 20, and is a source region of the p-type buried region 23. It is arranged so as to overlap the portion adjacent to the 24. The gate electrode 36b of the insulated gate portion 36 is connected to a driving portion (not shown). When the semiconductor device 1 turns on, the first drive voltage G1 is applied to the gate electrode 36b of the insulated gate portion 36.

The p-type gate portion 38 is provided on a part of the surface of the nitride semiconductor layer 20, and has a p-type gate region 38a containing p-type impurities and a Ni-Au p-type gate electrode 38b. Specifically, the p-type gate portion 38 is provided so as to cover a part of the surface of the heterojunction region 27, and is arranged on the current constriction region 22 side of the insulating gate portion 36. Further, the p-type gate portion 38 is arranged so as to overlap the entire current constriction region 22 when observed from a direction orthogonal to the surface of the nitride semiconductor layer 20, and also overlaps with the current constriction region 22. It extends from the position to the position overlapping with the p-type buried area 23. The p-type gate electrode 38b of the p-type gate portion 38 is connected to a drive portion (not shown). When the semiconductor device 1 turns on, the second drive voltage G2 is applied to the p-type gate electrode 38b of the p-type gate portion 38. The second drive voltage G2 is smaller than the first drive voltage G1.

Next, the operation of the semiconductor device 1 will be described. At the time of use, a positive voltage is applied to the drain electrode 32, and the source electrode 34 is grounded. When a positive first drive voltage G1 is applied to the gate electrode 36b of the insulated gate 36 and a positive second drive voltage G2 is applied to the p-type gate electrode 38b of the p-type gate 38, the heterojunction region Two-dimensional electron gas is generated in the lower hetero region 25 of 27, and the semiconductor device 1 turns on. At this time, electrons flow from the source region 24 into the current constriction region 22 via the two-dimensional electron gas. The electrons that have flowed into the current constriction region 22 flow vertically through the current constriction region 22 and head toward the drain electrode 32. As a result, the drain electrode 32 and the source electrode 34 become conductive.

When the gate electrode 36b of the insulated gate portion 36 and the p-type gate electrode 38b of the p-type gate portion 38 are grounded, the two-dimensional electron gas disappears and the semiconductor device 1 turns off. At this time, the depletion layer extends from the p-type gate region 38a of the p-type buried region 23 and the p-type gate portion 38. The p-type gate region 38a of the p-type gate portion 38 has a portion arranged at a position overlapping the p-type buried region 23 when observed from a direction orthogonal to the main surface of the nitride semiconductor layer 20. Therefore, a part of the heterojunction region 27 is sandwiched between the p-type buried region 23 and the p-type gate region 38a of the p-type gate portion 38, and when the semiconductor device 1 is off, the sandwiched portion is sandwiched. It is well depleted. Since the insulated gate portion 36 is arranged on the source region 24 side of the portion sandwiched between the p-type buried region 23 and the p-type gate portion 38, the insulated gate portion 36 is provided when the semiconductor device 1 is off. The application of a high electric field is suppressed. That is, in the semiconductor device 1, even if the current constriction region 22 is manufactured in a state where the impurity concentration is higher than the design value and the current constriction region 22 is not pinched off satisfactorily, it is possible to suppress the application of a high electric field to the insulating gate portion 36. , Dielectric breakdown of the insulating gate portion 36 is suppressed. As described above, the semiconductor device 1 can have high reliability with respect to the variation in the impurity concentration in the current constriction region 22.

Further, in the semiconductor device 1, the p-type gate region 38a of the p-type gate portion 38 is arranged so as to overlap the entire range of the current constriction region 22 when observed from a direction orthogonal to the surface of the nitride semiconductor layer 20. Has been done. Therefore, when the semiconductor device 1 is off, the depletion layer can spread over a wide range from the p-type gate region 38a of the p-type gate portion 38 toward the inside of the current constriction region 22, and the dielectric breakdown of the insulating gate portion 36 is further increased. It can be suppressed.

Further, the semiconductor device 1 is characterized by having two types of gate portions, an insulated gate portion 36 and a p-type gate portion 38. For example, it is assumed that only the p-type gate portion 38 is provided on the surface of the heterojunction region 27. In this case, since the gate insulating film does not exist in the p-type gate portion 38 in the first place, the problem of dielectric breakdown does not occur. However, in the p-type gate portion 38, when a voltage (about 3.5 V or more) higher than the diffusion potential of the diode structure of the p-type gate region 38a and the upper hetero region 26 is applied to the p-type gate electrode 38b, a leak current is generated. There is a problem that flows. Therefore, when only the p-type gate portion 38 is provided, it is necessary to set the threshold voltage lower than the diffusion potential of the diode structure. Such a low threshold voltage has a problem that malfunction due to noise is likely to occur. Further, when only the insulating gate portion 36 is provided on the surface of the heterojunction region 27, the threshold voltage can be set high and malfunction due to noise can be suppressed, but this will be described in the background art of the present specification. As described above, there is a concern about dielectric breakdown of the gate insulating film. As described above, when it is composed of only one of the insulating gate portion 36 and the p-type gate portion 38, it is difficult to suppress the dielectric breakdown of the gate insulating film and the malfunction due to noise at the same time.

On the other hand, the semiconductor device 1 has two types of gate portions, an insulated gate portion 36 and a p-type gate portion 38. Since the semiconductor device 1 is provided with the insulated gate portion 36, the threshold voltage can be set high, and malfunction due to noise can be suppressed. Further, since the p-type gate portion 38 is provided, the dielectric breakdown of the gate insulating film 36a of the insulating gate portion 36 is suppressed. As described above, the semiconductor device 1 can both suppress the dielectric breakdown of the gate insulating film and suppress the malfunction due to noise. Further, in the semiconductor device 1, since the p-type gate portion 38 is provided in a wide range on the heterojunction region 27, the density of the two-dimensional electron gas becomes high and the on-resistance of the heterojunction region 27 decreases. As described above, the semiconductor device 1 can have both low dielectric breakdown of the gate insulating film and suppression of malfunction due to noise, and can have a low on-resistance because different drive voltages can be applied.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. In addition, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in the present specification or drawings can achieve a plurality of purposes at the same time, and achieving one of the purposes itself has technical usefulness.

1: Semiconductor device, 10: Nitride semiconductor substrate, 20: Nitride semiconductor layer, 21: Drift region, 22: Current constriction region, 23: p-type region, 24: Source region, 25: Lower hetero region, 26: Upper hetero region, 27: Heterojunction region, 32: Drain electrode, 34: Source electrode, 36: Insulated gate, 36a: Gate insulating film, 36b: Gate electrode, 38: p-type gate, 38a: p-type gate region , 38b: p-type gate electrode

Claims (3)

Nitride semiconductor layer and
An insulating gate portion provided on one main surface of the nitride semiconductor layer and
It is provided with a p-type gate portion provided on the main surface of the nitride semiconductor layer.
The nitride semiconductor layer is
n-type drift region and
An n-type current constriction region provided on the drift region and
A p-type p-type buried region provided on the drift region and arranged with the current constriction region in between, and a p-type buried region.
A heterojunction region provided on the current constriction region and the p-type buried region and having a heterojunction, and a heterojunction region.
It has an n-type source region that is provided on the p-type buried region and is separated from the current constriction region by the heterojunction region.
The insulating gate portion is provided on the heterojunction region, and is arranged on the source region side of the p-type gate portion.
The p-type gate portion has a p-type p-type gate region in contact with the heterojunction region.
A semiconductor device having a portion of the p-type gate region arranged at least at a position overlapping the p-type embedded region when observed from a direction orthogonal to the main surface of the nitride semiconductor layer. The p-type gate region of the p-type gate portion overlaps with the p-type buried region from a position overlapping the current constriction region when observed from a direction orthogonal to the main surface of the nitride semiconductor layer. The semiconductor device according to claim 1, which is provided so as to extend to. Further, it is further provided with a drive unit configured to apply a first drive voltage to the insulated gate portion and a second drive voltage to the p-type gate portion when in the ON state.
The semiconductor device according to claim 1 or 2, wherein the first drive voltage is larger than the second drive voltage.

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