JP6859178B2 - Oscillator circuit device and switching regulator - Google Patents

Description

The present invention relates to an oscillation circuit device and a switching regulator, and in particular, an oscillation circuit device capable of selecting an oscillation frequency adjustment function extremely easily, a pulse width modulation (PWM) method controlled by the oscillation circuit device, or a pulse frequency modulation (PFM). It relates to a switching regulator controlled by a method.

A switching regulator using a PWM signal is usually a method in which a frequency is fixed at a predetermined value and a pulse duty ratio is controlled to drive a switching element on / off. However, when the pulse duty ratio is, for example, 10% or less, the switching element cannot be sufficiently turned on, and it becomes difficult to generate a predetermined output voltage. In particular, if the frequency is set high, the switching regulator can be operated at high speed, but the driving ability of the switching element is reduced, and the above tendency is remarkable. Various ideas have been proposed to overcome these problems.

For example, Patent Document 1 proposes a switching power supply that changes the frequency according to an increase or decrease in an input voltage and performs stable switching operation. In Patent Document 1, when the input voltage becomes high, the oscillation frequency is lowered by controlling the on-time by lowering the oscillation frequency. That is, even if the input voltage fluctuates, the switching operation is stabilized by controlling the switching means.

If the switching frequency is unnecessarily increased, the switching loss is increased, and if the switching frequency is decreased, the peak value of the current is increased, and the copper loss generated in the choke coil is increased when the input voltage is low. In order to solve such a problem, Patent Document 2 proposes a switching power supply capable of increasing switching efficiency by fluctuating the frequency according to an input voltage. More specifically, a frequency correction circuit that outputs a correction signal according to the input voltage and an oscillation circuit device that outputs a reference signal whose oscillation frequency is changed according to the correction signal are provided. Such an oscillation circuit device is configured to lower the oscillation frequency of the reference signal when the input voltage is relatively high and increase the oscillation frequency of the reference signal when the input voltage is relatively low, depending on the correction signal. Has been done.

Japanese Patent No. 4999362 Japanese Unexamined Patent Publication No. 2001-197730

However, in Patent Document 1, when the switching element is turned on / off according to the fluctuation of the input voltage or the like, there is a problem that a switching loss occurs.

According to Patent Document 2, when the input voltage is in a low voltage state of a predetermined voltage or less, if the frequency of the reference signal of the oscillation circuit device is increased, the period of the reference signal of the oscillation circuit device becomes smaller and the pulse is lost. There is a problem that it affects the circuit operation.

The present invention has been made to overcome the above-mentioned problems, and an object of the present invention is to fall into a low voltage state below a predetermined voltage range even when the input voltage exceeds a predetermined voltage range and falls into an overvoltage state. Even when the input voltage is within a predetermined range, the frequency of the PWM signal is lowered, the pulse width is widened, and a switching regulator that can sufficiently secure the ON state of the switching element is provided. The purpose.

The oscillation circuit device of one aspect of the present invention includes an input voltage conversion unit that converts an input voltage into a predetermined voltage, and an input voltage conversion unit.
The reference voltage section that generates the reference voltage and
A reference voltage adjusting unit that receives the input voltage and lowers the reference voltage when the input voltage is overvoltage exceeding the voltage in the normal range or when the input voltage is in a low voltage state below the voltage in the predetermined range.
It is provided with a clock signal generation circuit that generates a current corresponding to the reference voltage and generates a clock signal having an oscillation frequency proportional to the magnitude of the current.
The input voltage conversion unit, the reference voltage unit, the reference voltage adjusting unit, and the clock signal generation circuit are built in the first semiconductor integrated circuit device.

In the oscillation circuit device of another aspect of the present invention, the input voltage conversion unit lowers the input voltage by a resistance circuit when the input voltage deviates from the predetermined range.

In the oscillation circuit device of another aspect of the present invention, when the input voltage deviates from the predetermined range, the input voltage conversion unit lowers the input voltage via a constant voltage element.

In the oscillation circuit device of another aspect of the present invention, the input voltage conversion unit has a first voltage-current conversion means for converting the stepped-down voltage into a first current.

In the oscillation circuit device of another aspect of the present invention, the reference voltage unit is generated by the band gap reference circuit that generates the band gap voltage, the voltage dividing circuit that divides the band gap voltage, and the voltage dividing circuit. It has a second voltage-current conversion means that generates a second current proportional to the divided voltage.

In the oscillation circuit device of another aspect of the present invention, the second current is set by a resistor to which the voltage dividing voltage is supplied, prepared in the reference voltage section, and connected to the outside of the first semiconductor integrated circuit device. ..

In the oscillation circuit device of another aspect of the present invention, the second current is set by a resistor to which the divided voltage is supplied, prepared in the reference voltage section, and built in the first semiconductor integrated circuit device.

In another aspect of the oscillator circuit apparatus of the present invention, the voltage divider circuit includes a resistor circuit including a first resistor and a second resistor connected in series via a common connection circuit point, and one end of the first resistor is The other end of the first resistor is connected to the common connection circuit point in the band gap reference circuit, one end of the second resistor is connected to the common connection circuit point, and the other end of the second resistor is connected to the ground potential. To.

In the oscillation circuit device of another aspect of the present invention, the enable state of the reference voltage adjusting unit is controlled based on the first current and the second current.

In another aspect of the oscillation circuit device of the present invention, the reference voltage adjusting unit controls the enable state based on the step-down voltage obtained by stepping down the second current and the input voltage.

In the oscillation circuit device of another aspect of the present invention, when the output of the reference voltage adjusting unit is connected to the common connection circuit point and the reference voltage adjusting unit is controlled from the disable state to the enable state, the reference voltage is the same. It is lower than when it is in the disable state.

In the oscillation circuit device of another aspect of the present invention, the reference voltage adjusting unit includes a latch circuit having a set terminal and a reset terminal, and the set terminal has a set input signal corresponding to the second current and the reset terminal. A reset input signal corresponding to the first current is input to the latch circuit, and the latch circuit is a reset priority type.

In another aspect of the oscillating circuit device of the present invention, the clock signal generation circuit includes a current mirror circuit that generates a third current based on the second current, and a capacitor that is repeatedly charged or discharged by the third current. It has a comparator that sets an upper limit value and a lower limit value of a triangular wavy voltage generated in the capacitor, and outputs a rectangular clock signal from the output of the comparator.

One aspect of the switching regulator, which is another invention of the present invention, is the oscillation circuit device of each of the above-described embodiments.
A switching means that is turned on / off to generate an output voltage from the input voltage, and
An inductor that repeatedly stores and releases energy by the switching operation of the switching means.
A smoothing means that receives the energy released from the inductor and smoothes the output voltage.
An error amplifier circuit that generates an error signal according to the difference between the output voltage or the feedback voltage corresponding thereto and the first reference voltage, and
A slope signal generation circuit that generates a triangular wave-shaped or sawtooth-shaped slope signal generated based on the clock signal generated by the clock signal generation circuit of the oscillation circuit device, and a slope signal generation circuit.
A PWM comparator that compares the slope signal with the error signal and outputs a PWM signal with a modulated pulse width.
It includes a drive control circuit that receives the clock signal and the output signal from the PWM comparator and controls the switching means.

In another aspect of the present invention, the switching regulator, the error amplifier circuit, the slope signal generation circuit, the PWM comparator, and the drive control circuit are the first semiconductor in which the oscillation circuit device is built. It is built in a second semiconductor integrated circuit device separate from the integrated circuit device.

In another aspect of the switching regulator of the present invention, the switching means, the error amplifier circuit, the slope signal generation circuit, the PWM comparator, and the drive control circuit are built in the first semiconductor integrated circuit device.

In another aspect of the switching regulator of the present invention, whether the input voltage is in the overvoltage state or the undervoltage state than in the normal state range, the switching means has a frequency lower than that in the normal state. It is controlled on / off by the switching voltage of.

In another aspect of the switching regulator of the present invention, the frequency of the switching voltage decreases linearly in proportion to the magnitude of the overvoltage and the magnitude of the undervoltage.

According to the configuration of the present invention, it is extremely easy to select whether or not the oscillation circuit device is provided with the frequency adjustment function. Further, it is possible to provide a switching regulator capable of supplying a stable output by driving the switching regulator by such an oscillation circuit device.

It is a circuit block diagram which shows 1st Embodiment of the switching regulator which concerns on this invention. It is a circuit block diagram which shows the 2nd Embodiment of the switching regulator which concerns on this invention. It is a timing chart of each part in an overvoltage state when the frequency adjustment function of an oscillation circuit apparatus is invalidated in the switching regulator which concerns on this invention. It is a timing chart of each part in an overvoltage state when the frequency adjustment function of an oscillation circuit apparatus is enabled in the switching regulator which concerns on this invention. It is a timing chart of each part in a low voltage state when the frequency adjustment function of an oscillation circuit apparatus is disabled in the switching regulator which concerns on this invention. It is a timing chart of each part in a low voltage state when the frequency adjustment function of an oscillation circuit apparatus is enabled in the switching regulator which concerns on this invention. It is a circuit diagram which shows an example of the oscillation circuit apparatus suitable for detecting an overvoltage state in the switching regulator which concerns on this invention. FIG. 7 is a timing chart of each part when the frequency adjustment function of the oscillation circuit device is disabled. FIG. 7 is a timing chart of each part when the frequency adjustment function of the oscillation circuit device is enabled. It is a circuit diagram which shows another example of the oscillation circuit apparatus suitable for detecting an overvoltage state in the switching regulator which concerns on this invention. It is a circuit diagram which shows still another example of the oscillation circuit apparatus suitable for detecting an overvoltage state in the switching regulator which concerns on this invention. FIG. 11 is a timing chart of each part when the frequency adjustment function of the oscillation circuit device is enabled. It is a circuit diagram which shows an example of the oscillation circuit apparatus suitable for detecting a low voltage state in the switching regulator which concerns on this invention. FIG. 13 is a timing chart of each part when the frequency adjustment function of the oscillation circuit device is enabled. It is a circuit block diagram which shows another example of the oscillation circuit apparatus suitable for monitoring and detecting a low voltage state in the switching regulator which concerns on this invention. It is a latch circuit diagram used for the reference voltage adjustment part of this invention.

(First Embodiment)
FIG. 1 is a circuit configuration diagram showing a first embodiment of a switching regulator to which the present invention is applied. Hereinafter, embodiments of the present invention will be described with reference to the drawings. The switching regulator 1 of this configuration example constitutes a well-known step-down switching regulator that steps down the input voltage Vin supplied to the input terminal IN and outputs a desired output voltage Vout to the output terminal OUT. ..

The switching regulator 1 includes a switching transistor 2a, a synchronous rectifier element 3, a soft start control circuit 4, an error amplifier 5, an oscillation circuit device 6, a slope signal generation circuit 11, a totaling means 12, a PWM comparator 13, and a drive control circuit 14. These are built in the semiconductor integrated circuit device 1a. The semiconductor integrated circuit device 1a is provided with a plurality of external terminals.

Further, the input voltage Vin, the inductor L, the capacitors C1 to C3, the resistors R1 to R4, and the ground potential GND are connected via the external terminals provided outside the semiconductor integrated circuit device 1a. The switching regulator 1 performs a step-down operation by the action of a semiconductor integrated circuit device 1a and passive elements such as an inductor, a capacitor, and a resistor connected to an external terminal attached to the semiconductor integrated circuit device 1a. For example, the inductance of the inductor L is selected to be several μH, the capacitance value of the capacitor C1 is several tens of μF to several tens of μF, that of the capacitor C2 is several hundred pF to several thousand pF, and that of the capacitor C3 is several hundred pF to several thousand. Set to pF respectively. However, these values are just one of the design items, and depend on the step-down type, step-up type, buck-boost type, inverting type, etc., the magnitude of each input voltage and output voltage, and the desired frequency characteristics. Those values will be chosen as appropriate.

The input voltage Vin is, for example, a DC voltage selected from 10V to 15V, and is applied to the input terminal IN. The output voltage Vout is set to, for example, around 5V. The source of the switching transistor 2a is connected to the input terminal IN. The drain of the switching transistor 2a is connected to the switching terminal SW and the drain of the synchronous rectifying element 3. The source of the synchronous rectifying element 3 is connected to the ground potential GND via the ground terminal PGND. The ground terminal AGND is connected to the ground potential GND in the same manner as the ground terminal PGND, but is prepared separately from the ground terminal PGND. This is because a relatively small current flows and the circuit operation of the soft start control circuit 4, the operational capacitor 5, the oscillation circuit device 6, the PWM comparator 13, and the drive control circuit 14 connected to the ground terminal AGND has a relatively large current. This is to prevent the influence of the fluctuation of the potential of the flowing ground terminal PGND.

In FIG. 1, the switching transistor 2a is a p-channel type MOS transistor, and the synchronous rectifying element 3 is an n-channel type MOS transistor, but the combination is not limited to these. For example, the switching transistor 2a may be an nMOS transistor, or the synchronous rectifying element 3 may be replaced with a diode.

One end of the inductor L is connected to the switching terminal SW. The other end of the inductor L is connected to the output terminal OUT and one end of the capacitor C1, and the other end of the capacitor C1 is connected to the ground potential GND.

The resistors R1 and R2 connected in series between the output terminal OUT and the ground potential GND operate as a feedback voltage generation circuit. The resistors R1 and R2 output a feedback voltage Vfb to each other's common connection node. The feedback voltage Vfb is input to the inverting input terminal (−) of the error amplifier 5 via the feedback terminal FB.

One end of the capacitor C2 is connected to the soft start control circuit 4 via the soft start terminal SS, and the other end is connected to the ground potential GND. The soft start control circuit 4 is composed of, for example, a resistor, a capacitor, a switching element, or the like (not shown), and generates a soft start voltage Vss. The soft start voltage Vss is input to the first non-inverting input terminal (+) of the error amplifier 5.

The soft start voltage Vss is input to the first non-inverting input terminal (+) of the error amplifier 5, the reference voltage Vref is input to the second non-inverting input terminal (+), and the feedback voltage Vfb is input to the inverting input terminal (-). Will be done. The error amplifier 5 outputs an error signal Verr corresponding to the voltage received by each input terminal to the inverting input terminal (−) of the PWM comparator 13. Further, the output terminal of the error amplifier 5 is connected to the resistor R4 and the capacitor C3 via the phase compensation terminal COMP.

The oscillation circuit device 6 includes an input voltage conversion unit 7, a reference voltage unit 8, a reference voltage adjustment unit 9, and a clock signal generation unit 10. The frequency of the clock signal CLK generated by the oscillation circuit device 6 is controlled and adjusted by the reference voltage adjusting unit 9. The circuit function of the reference voltage adjusting unit 9 is enabled when both the input voltage conversion unit 7 and the reference voltage unit 8 are placed in the enabled (enabled) state, and one of them is placed in the disabled (disabled) state. When it becomes invalid. Therefore, even if an overvoltage exceeding a predetermined range or a low voltage below a predetermined range is applied to the input voltage conversion unit 7 via the input terminal IN, the circuit function of the reference voltage adjusting unit 9 is performed on the reference voltage unit 8 side. It can be disabled. Similarly, even if the reference voltage unit 8 is placed in the enabled state, if the input voltage conversion unit 7 does not output a predetermined voltage, the circuit function of the reference voltage adjusting unit 9 is in a disable state and a clock signal is generated. The frequency adjustment and control of the clock signal CLK generated by the unit 10 is not executed.

More specifically, the oscillator circuit device 6 is placed in an overvoltage state in which the input voltage Vin is a constant voltage or more (for example, 23 V or more) or a low voltage state in which the input voltage Vin is a constant voltage or less (for example, 10 V or less). If so, it works to adjust the frequency of the clock signal CLK. The selection of whether to enable or disable the reference voltage adjustment unit 9 can be determined by the magnitude of the current flowing through the reference voltage section 8, and the magnitude of the current is on the reference voltage section 8 side. It is determined by the resistance value of the resistor R3 connected to. Therefore, one of the major features of the present invention is that the resistor R3 can set whether to enable or disable the circuit function of the reference voltage adjusting unit 9.

To put it the other way around, when the resistance R3 is, for example, several hundred kΩ or more, the reference voltage adjusting unit 9 becomes disable, and when the resistance R3 is, for example, several tens of kΩ or less, it can be set to the enable state. In any case, when the reference voltage adjusting unit 9 is placed in the enabled state, it is assumed that the input voltage Vin fluctuates in either the direction higher than the predetermined range (overvoltage state) or the direction lower than the predetermined range (undervoltage state). The frequency of the clock signal CLK generated by the clock signal generation unit 10 is lowered in proportion to the magnitude of the increase / decrease voltage, and is output to the drive control circuit 14 in the subsequent stage.

The slope signal generation circuit 11 outputs the lamp signal Vramp to the summing means 12 in the subsequent stage. The ramp signal Vramp is, for example, a triangular wave or a sawtooth wave whose period changes following the clock signal CLK.

In the summing means 12, the voltage components corresponding to the lamp signal Vram and the switching current Isw are summed via the signal line CS, a slope signal Vslope is generated, and the voltage components are output to the non-inverting input terminal (+) of the PWM comparator 13. Since the summing means 12 is prepared to configure the switching regulator 1 as a current feedback type, it is unnecessary when it is used in the voltage feedback type.

The PWM comparator 13 receives a slope signal Vslope at the non-inverting input terminal (+) and an error signal Verr at the inverting input terminal (−), and outputs a reset signal Reset to the drive control circuit 14. The drive control circuit 14 is connected to the gate of the switching transistor 2a and the synchronous rectifier element 3.

The operation of the step-down switching regulator 1 having such a configuration will be described below. In the step-down mode, when the switching transistor 2a is on and the synchronous rectifier element 3 is off, the switching current Isw flows from the input terminal IN to the capacitor C1 via the inductor L, and magnetic energy is stored in the switching regulator 1. Conversely, when the switching transistor 2a is in the off state and the synchronous rectifier element 3 is in the on state, a current flows from the synchronous rectifier element 3 side to the capacitor C1 via the inductor L, so that the magnetic energy stored in the inductor L is released. It is released. By such an operation, the input voltage Vin is stepped down, and the output voltage Vout is output from the output terminal OUT. The resistors R1 and R2 divide the output voltage Vout output from the output terminal OUT to generate a feedback voltage Vfb, which is sent to the feedback terminal FB.

The soft start control circuit 4 starts charging of the capacitor C2 connected to the soft start terminal SS at the same time as starting the switching regulator 1. The voltage charged in the capacitor C2 is input to the soft start control circuit 4 via the soft start terminal SS, and is output as the soft start voltage Vss. The capacitance value of the capacitor C2 can be selected, for example, from several hundred pF to several thousand pF. With such a soft start control circuit 4, when the switching regulator 1 is started, the soft start voltage Vss that gradually rises and the output feedback control of the feedback voltage Vfb are performed so as to follow the soft start voltage Vss. And the inrush current to the capacitor C1 can be prevented.

The error amplifier 5 compares the lower soft start input voltage Vss or reference voltage Vref with the feedback voltage Vfb, and outputs an error signal Verr according to the comparison result. The feedback voltage Vfb is, for example, 0.6V to 5V.

The resistor R4 and the capacitor C3 connected in series between the phase compensation terminal COMP and the ground potential GND are configured as a phase compensation circuit. The resistor R4 and the capacitor C3 set the gain and frequency characteristics of the error amplifier 5. The frequency characteristic of the switching regulator 1 is corrected by the phase compensation. The phase compensation circuit is not a series circuit of the resistor R4 and the capacitor C3, but another capacitor may be connected to them in parallel, for example, to give a so-called secondary characteristic. The resistor R4 and the capacitor C3 also set the voltage gain of the error amplifier 5.

The oscillating circuit device 6 oscillates at a frequency corresponding to the current flowing through the resistor R3 connected to the setting terminal RT, which will be further clarified later. The setting terminal RT is prepared as an external terminal of the semiconductor integrated circuit device 1a, and it is preferable that the resistor R3 is externally attached. As a result, the value of the resistor R3 can be freely selected, and the influence of the temperature characteristics of the resistor, the variation in the resistance value, and the like can be eliminated. The resistance value of the resistor R3 is selected according to the terminal voltage of the setting terminal RT and the setting of the frequency magnitude of the clock signal CLK. The set voltage Vrt of the setting terminal RT is set to, for example, 0.3V to 0.5V, and the resistance value of the resistor R3 can be selected, for example, from several tens of kΩ to several hundreds of kΩ. The frequency (period) of the clock signal CLK (set signal Set) output from the oscillation circuit device 6 is set by the resistor R3. The frequency of the clock signal CLK is selected, for example, from 200 kHz to 5 MHz. Normally, the switching transistor 2a and the synchronous rectifying element 3 are on / off controlled at one frequency within these ranges. For example, when the frequency is set to 1 MHz, it is 0.9 μs when the on-duty ratio is 90%, and 0.1 μs when the on-duty ratio is 10%.

The drive control circuit 14 receives the set signal Set output from the oscillation circuit device 6 and the reset signal Set output from the PWM comparator 13, and outputs the gate signal Gp and the gate signal Gn. The switching transistor 2a and the synchronous rectifying element 3 are complementarily turned on / off by the gate signal Gp and the gate signal Gn. An RS flip-flop (not shown), for example, is prepared inside the drive control circuit 14, and a set signal Sset (clock signal CLK) generated by the oscillation circuit device 6 is set as a reset terminal at the set terminal of the RS flip-flop. A reset signal Reset output from the PWM comparator 13 is applied to each of the PWM comparators 13.

Although not shown, the drive control circuit 14 has a gate signal Gp of high level (“H”) and a gate signal Gn of low in order to prevent an excessive through current flowing from the switching transistor 2a toward the synchronous rectifier element 3. A section that becomes a level (“L”), a so-called dead time, is provided. In the dead time section, the switching transistor 2a and the synchronous rectifying element 3 are both placed in the off state to block the current path of the through current.

(Second Embodiment)
FIG. 2 is a circuit configuration diagram showing a second embodiment of a switching regulator to which the present invention is applied. The second embodiment is the same as the first embodiment shown in FIG. 1. First, a bootstrap terminal Bo is prepared in the semiconductor integrated circuit device 100A, and a drive control circuit 14 is connected to the bootstrap terminal Bo. The switching transistor 2a composed of the pMOS transistor was replaced with the switching transistor 2b which is an nMOS transistor. Third, the bootstrap circuit was composed of the diode d1 and the capacitor C4, and these common connection points were used as the bootstrap terminal Bo. It is connected. Other circuit configurations are the same. Here, a difference in such a circuit configuration in which FIG. 2 is different from FIG. 1 will be described.

In the second embodiment shown in FIG. 2, an nMOS transistor is used as the switching transistor 2b and the synchronous rectifying element 3 of the switching regulator 100. In particular, in a switching regulator that uses an nMOS transistor on the high side, a bootstrap circuit that boosts the drive voltage applied to the gate to more than the input voltage Vin applied to the drain in order to turn on the switching transistor 2b sufficiently. Will be adopted.

The diode d1 and the capacitor C4 form a bootstrap circuit. The common connection node of the diode d1 and the capacitor C4 is connected to the drive control circuit 14 via the bootstrap terminal Bo. When the switching transistor 2b is off, that is, during the period when the synchronous rectifying element 3 is on, the capacitor C4 is charged for a predetermined time (for example, 80 ns). While the synchronous rectifying element 3 is on, a current flows from the drive power supply Vdd toward the ground potential GND via the diode d1, the capacitor C4, the switching terminal SW, the synchronous rectifying element 3 and the ground terminal PGND. As a result, the potential Vbo at one end of the capacitor C4, that is, the node Nbo, rises to Vdd-Vd1 (Vd1 is the forward voltage of the diode d1) and is set higher than the potential of the input voltage Vin. By this operation, the switching transistor 2b is lifted until it can be sufficiently driven.

Although a step-down type switching regulator is used in the present invention, the switching regulator is not limited to the step-down type or the step-up type, and is not limited to the synchronous rectification method or the asynchronous rectification method. Further, the bootstrap circuit may be built in the semiconductor integrated circuit device 100a.

FIG. 3 shows a timing chart of the main nodes of the switching regulator 1 shown in FIG. It is a timing chart when the switching regulators 1 and 100 are in an overvoltage state, that is, when the input voltage Vin applied to the input terminal IN exceeds a predetermined range and the resistance R3 is relatively large, such as several hundred kΩ or more.

One of the features of the switching regulators 1 and 100 according to the present invention is that the oscillation frequency of the clock signal CLK originally generated by the oscillation circuit device 6 can be adjusted, but such an oscillation frequency adjustment function is extremely easy. One of the major features is that it can be disabled. Generally, the selection of whether or not a PWM control type switching regulator has a frequency adjustment function differs depending on the user. The switching regulators 1 and 100 according to the present invention are intended to easily meet such demand.

Whether to enable or disable the oscillation frequency adjustment function of the oscillation circuit device 6 can be determined by enabling or disabling the circuit function of the reference voltage adjustment unit 9 as described above. Moreover, the reference voltage adjusting unit 9 can be set by the resistance value of the resistor R3 connected to the reference voltage unit 8. FIG. 3 shows a case where the resistor R3 is selected to be, for example, several hundred kΩ or more, and the function of the reference voltage adjusting unit 9 is invalidated.

In FIG. 3, the input voltage Vin, the clock signal CLK (set signal Set), the lamp signal Vram, the slope signal Vslope, the reset signal Reset, and the switching voltage Vsw are depicted in this order from the top.

The input voltage Vin is applied to the input terminal IN. In the switching regulators 1 and 100 according to the present invention, fluctuations in the input voltage Vin are monitored and detected, and the magnitude of the frequency of the clock signal CLK generated by the oscillation circuit device 6 fluctuates according to the increase / decrease in the input voltage Vin. To do. The input voltage Vin has a predetermined magnitude and is constant in the section from time t1 to t5. The section from time t6 to t9 schematically shows a state in which the time gradually increases for some reason.

The clock signal CLK (set signal Sset) is generated by the clock signal generation circuit 10 and indicates a state in which the clock signal CLK (set signal Sset) is generated at a constant cycle regardless of the times t1 to t9. When the reference voltage adjusting unit 9 is placed in the invalid state, the clock signal CLK (set signal Sset) is generated at a constant frequency (cycle) even after the time t6 when the input voltage Vin fluctuates. become.

The lamp signal Vramp is output from the slope signal generation circuit 11 and becomes a triangular wave-like or sawtooth-like wave signal that follows the clock signal CLK. Similar to the clock signal CLK, the lamp signal Vramp is generated in the interval of time t1 to t9 at a constant cycle.

The slope signal Vslope is output from the summing means 12 and input to the non-inverting input terminal (+) of the PWM comparator 13. The slope signal Vslope is a signal obtained by adding the voltage components corresponding to the switching current Isw to the lamp signal Vram via the signal line CS. The slope signal Vslope starts to gradually increase from the timing of the falling edge of the set signal Sset (clock signal CLK), and suddenly drops to a predetermined potential V1 when the error signal Verr is reached. The error signal Verr is gradually stepped down as the input voltage Vin increases.

The reset signal Reset is output from the PWM comparator 13 and input to the drive control circuit 14. The reset signal Reset is generated at the timing when the slope signal Vslope transitions from the high level to the low level L. The drive control circuit 14 is controlled by the reset signal Reset and the set signal Set.

The switching voltage Vsw is output from the switching terminal SW. The switching voltage Vsw is generated and output by the drive control circuit 14, the switching transistor 2a, and the synchronous rectifying element 3, but the generation timing thereof is synchronized with the set signal Set and the reset signal Reset. Therefore, the section at times t1 to t3 has a high level H, and the section between sections t3 to t5 has a low level L. The pulse width of the high level H of the switching voltage Vsw becomes narrower as the input voltage Vin increases, and becomes the narrowest in the section from time t7 to t8, which is disadvantageous for turning on the switching transistor 2a. Even in the state, the minimum on-time ton required to turn on the switching transistor 2a is controlled so as to be secured.

FIG. 4 shows a timing chart of the main nodes of the switching regulator 1 shown in FIG. In particular, in the switching regulator 1, the timing is in an overvoltage state, that is, when the input voltage Vin applied to the input terminal IN exceeds a predetermined range and the resistance R3 is a relatively small resistance value of several tens of kΩ or more. It is a chart. In FIG. 3 described above, the oscillation frequency adjusting function of the oscillation circuit device 6 is set to the disable state, but FIG. 4 is different from each other in that it is set to the enable state.

Whether to enable or disable the oscillation frequency adjustment function of the oscillation circuit device 6 can be determined by enabling or disabling the function of the reference voltage adjustment unit 9. Moreover, as described above, the reference voltage adjusting unit 9 can be set by the resistance value of the resistor R3 connected to the reference voltage unit 8. FIG. 4 shows a case where the resistor R3 is selected to be, for example, about several tens of kΩ and the circuit function of the reference voltage adjusting unit 9 is enabled.

In FIG. 4, similarly to FIG. 3, the input voltage Vin, the clock signal CLK (set signal Sset), the lamp signal Vram, the slope signal Vslope, the reset signal Sset, and the switching voltage Vsw are depicted in this order from the top.

The input voltage Vin is applied to the input terminal IN. In the switching regulators 1 and 100 according to the present invention, fluctuations in the input voltage Vin are monitored and detected, and the magnitude of the frequency of the clock signal CLK generated by the oscillation circuit device 6 is controlled according to the increase or decrease in the input voltage Vin. , Adjusted. The input voltage Vin schematically shows a state in which the input voltage Vin gradually increases from the time t1 to the time t8. It is assumed that the input voltage Vin is higher than the magnitude of the predetermined voltage at time t2 by a predetermined voltage Δv1.

The clock signal CLK (set signal Sset) is generated by the clock signal generation circuit 10 built in the oscillation circuit device 6, but the period after the time t2 when the input voltage Vin is higher than the voltage in the normal state by a predetermined voltage Δv1 Indicates a state in which the spread frequency is adjusted to be low. That is, it indicates that the oscillation frequency adjustment function is set to the enabled state. The specific circuit configuration of the oscillation frequency adjustment function will be described later.

The lamp signal Vramp is output from the slope signal generation circuit 11 and becomes a triangular wave-like or sawtooth-like wave signal that follows the clock signal CLK. Similar to the clock signal CLK, the lamp signal Vram gradually has a longer cycle and a lower frequency after time t1.

The slope signal Vslope is output from the summing means 12 and input to the non-inverting input terminal (+) of the PWM comparator 13. The slope signal Vslope is a signal obtained by adding the voltage components corresponding to the switching current Isw to the lamp signal Vram via the signal line CS. The slope signal Vslope starts to gradually increase from the timing of the falling edge of the set signal Sset (clock signal CLK), and suddenly drops to a predetermined potential V1 when the error signal Verr is reached. The error signal Verr is gradually stepped down as the input voltage Vin increases.

The reset signal Reset is output from the PWM comparator 13 and input to the drive control circuit 14. The reset signal Reset is generated at the timing when the slope signal Vslope transitions from the high level to the low level. The drive control circuit 14 is controlled by the reset signal Reset and the set signal Set.

The switching voltage Vsw is output from the switching terminal SW. The switching voltage Vsw is generated and output by the drive control circuit 14, the switching transistor 2a, and the synchronous rectifying element 3, but the generation timing thereof is synchronized with each rising edge of the set signal Set and the reset signal Reset. Therefore, the section at time t2 to t3 has a high level H, and the section between sections t3 to t4 has a low level L. The time of the high level H of the switching voltage Vsw becomes narrower in proportion to the increase of the input voltage Vin, and becomes the narrowest in the section from time t7 to t8, which is disadvantageous for turning on the switching transistor 2a. Even in the state, the minimum on-time ton required to turn on the switching transistor 2a is controlled so as to be secured.

FIG. 5 shows a timing chart of the main nodes of the switching regulator 1 shown in FIG. In particular, in the switching regulator 1, the timing is in the low voltage state, that is, when the input voltage Vin applied to the input terminal IN is below a predetermined range and the resistance R3 is a relatively large resistance value of several hundred kΩ. It is a chart.

When the input voltage Vin is in a low voltage state, the resistor R3 is selected to have a relatively high resistance value of, for example, several hundred kΩ or more in order to disable the oscillation frequency adjustment function of the oscillation circuit device 6 as in the overvoltage state. This can be achieved by disabling the circuit function of the reference voltage adjusting unit 9.

In FIG. 5, similarly to FIGS. 3 to 4, the input voltage Vin, the clock signal CLK (set signal Sset), the lamp signal Vram, the slope signal Vslope, the reset signal Sset, and the switching voltage Vsw are depicted in this order from the top. ing.

The input voltage Vin is applied to the input terminal IN. In the switching regulators 1 and 100 according to the present invention, fluctuations in the input voltage Vin are monitored and detected, and the frequency magnitude of the clock signal CLK generated by the oscillation circuit device 6 is low in response to the decrease in the input voltage Vin. It is adjusted to be. The input voltage Vin has a predetermined magnitude and is constant in the section from time t1 to t5. The section from time t6 to t8 schematically shows a state of decrease for some reason.

The clock signal CLK (set signal Sset) is generated by the clock signal generation circuit 10 and indicates a state in which the clock signal CLK (set signal Sset) is generated at a constant cycle regardless of the times t1 to t8. The clock signal CLK (set signal Sset) is generated at a constant frequency (cycle) even after the time t6 when the input voltage Vin fluctuates when the reference voltage adjusting unit 9 is placed in the disable state. ..

The lamp signal Vramp is output from the slope signal generation circuit 11 and becomes a triangular wave-like or sawtooth-like wave signal that follows the clock signal CLK. Like the clock signal CLK, the lamp signal Vramp is generated in the entire section of time t1 to t8 at a constant cycle.

The slope signal Vslope is output from the summing means 12 and input to the non-inverting input terminal (+) of the PWM comparator 13. The slope signal Vslope is a signal obtained by adding the voltage components corresponding to the switching current Isw to the lamp signal Vram via the signal line CS. The slope signal Vslope starts to gradually increase from the timing of the falling edge of the set signal Sset (clock signal CLK), and suddenly drops to a predetermined potential V1 when the error signal Verr is reached. The error signal Verr is gradually boosted as the input voltage Vin increases.

The reset signal Reset is output from the PWM comparator 13 and input to the drive control circuit 14. The reset signal Reset is generated at the timing when the slope signal Vslope transitions from the high level to the low level L. The drive control circuit 14 is controlled by the reset signal Reset and the set signal Set.

The switching voltage Vsw is output from the switching terminal SW. The switching voltage Vsw is generated and output by the drive control circuit 14, the switching transistor 2a, and the synchronous rectifying element 3, but the generation timing thereof is synchronized with each rising edge of the set signal Set and the reset signal Reset. Therefore, the section at times t1 to t3 has a high level H, and the section between sections t3 to t5 has a low level L. The low level L time of the switching voltage Vsw becomes narrower as the input voltage Vin decreases, and becomes the narrowest in the section from time t7 to t8. In particular, when the switching transistor is an nMOS transistor such as the switching regulator 100, it is controlled so that the minimum on-time tmoff required to turn on the nMOS transistor can be secured.

FIG. 6 shows a timing chart of the main nodes of the switching regulator 1 shown in FIG. In particular, in the switching regulator 1, in the timing chart in the low voltage state, that is, when the input voltage Vin applied to the input terminal IN is below a predetermined range and the resistance R3 is a relatively small resistance value of several tens of kΩ. is there. FIG. 5 described above shows that the oscillation frequency adjusting function of the oscillation circuit device 6 is in a disable state, but FIG. 6 is different from each other in that it is set in the enable state.

To enable the oscillation frequency adjustment function of the oscillation circuit device 6, select the resistor R3 provided in the reference voltage unit 8 to a relatively low resistance value of, for example, several tens of kΩ, and enable the circuit function of the reference voltage adjustment unit 9. And.

In FIG. 6, similarly to FIGS. 3 to 5, the input voltage Vin, the clock signal CLK (set signal Sset), the lamp signal Vram, the slope signal Vslope, the reset signal Sset, and the switching voltage Vsw are depicted in this order from the top. There is.

The input voltage Vin is applied to the input terminal IN. In the switching regulators 1,100 according to the present invention, fluctuations in the input voltage Vin are monitored and detected, and the magnitude of the frequency of the clock signal CLK generated by the oscillation circuit device 6 is controlled according to the increase or decrease in the input voltage Vin. , Adjusted. The input voltage Vin schematically shows a state in which the input voltage Vin gradually decreases after the time t1. Then, it is assumed that the input voltage Vin becomes lower than the magnitude of the predetermined voltage by the predetermined voltage Δv2 at the time t2.

The clock signal CLK (set signal Sset) is generated by the clock signal generation circuit 10 built in the oscillation circuit device 6, but is adjusted so that the period becomes wider and the frequency becomes lower after the time t1 when the input voltage Vin starts to decrease. Indicates the state to be performed. That is, it indicates that the oscillation frequency adjustment function is set to the enabled state. The specific circuit configuration of the oscillation frequency adjustment function will be described later.

The lamp signal Vramp is output from the slope signal generation circuit 11 and becomes a triangular wave-like or sawtooth-like wave signal that follows the clock signal CLK. Similar to the clock signal CLK, the lamp signal Vramp has a gradually longer cycle and a lower frequency after time t1.

The slope signal Vslope is output from the summing means 12 and input to the non-inverting input terminal (+) of the PWM comparator 13. The slope signal Vslope is a signal obtained by adding the voltage components corresponding to the switching current Isw to the lamp signal Vram via the signal line CS. The slope signal Vslope starts to gradually increase from the timing of the falling edge of the set signal Sset (clock signal CLK), and suddenly drops to a predetermined potential V1 when the error signal Verr is reached. The error signal Verr is gradually stepped down according to the input voltage Vin.

The reset signal Reset is output from the PWM comparator 13 and input to the drive control circuit 14. The reset signal Reset is generated at the timing when the slope signal Vslope transitions from the high level to the low level L. The drive control circuit 14 is controlled by the reset signal Reset and the set signal Set.

The switching voltage Vsw is output from the switching terminal SW. The switching voltage Vsw is generated and output by the drive control circuit 14, the switching transistor 2a, and the synchronous rectifying element 3, but the generation timing thereof is synchronized with the set signal Set and the reset signal Reset. The pulse width in the low level L section of the switching voltage Vsw becomes narrower as the input voltage Vin decreases. Even in the period from time t3 to t4, when the switching transistor is an nMOS transistor, it is controlled so that the minimum on-time tmoff for turning on the nMOS transistor can be sufficiently secured. The cycles T1, T2 and T3 gradually change after the time t2, T1 <T2 <T3, the cycle of the switching voltage Vsw becomes long, and the frequency gradually decreases.

In the switching regulators 1 and 100 according to the present invention with reference to FIGS. 1 to 6, the oscillation frequency adjusting function of the oscillation circuit device 6 when the input voltage Vin falls into an overvoltage state or an undervoltage state has been described. One of the features of the present invention is that the setting of whether to enable or disable the oscillation frequency adjustment function in any state can be set extremely easily by selecting the resistance value of the resistor R3 connected to the reference voltage unit 8. As mentioned above. Next, a specific circuit configuration of the oscillation circuit device 6 for selecting such a circuit function will be described.

FIG. 7 shows an example of the oscillation circuit device 6 used in the switching regulators 1, 100 according to the present invention. In particular, a circuit configuration suitable for monitoring and detecting the overvoltage when the input voltage Vin falls into an overvoltage state and adjusting the oscillation frequency of the clock signal CLK (set signal Set) is shown.

The oscillation circuit device 6 includes an input voltage conversion unit 7, a reference voltage unit 8, a reference voltage adjustment unit 9, a clock signal generation circuit 10, and a current mirror circuit 15.

The input voltage conversion unit 7 is composed of Zener diodes z1 to z4, resistors r1, pMOS transistors p1 and p2, and nMOS transistors n1 and n2. The cathode of the Zener diode z1 as a constant voltage element is connected to the input terminal IN, and its anode is connected to the cathode of the Zener diode z2. Similarly, the Zener diodes z2 to z4 are connected in series. The input voltage Vin is clamped based on the forward voltage of the Zener diodes z1 to z4 (for example, 5.0 V per one). The resistor r1 determines the detection current Ij flowing through the Zener diodes z1 to z4. The number of Zener diodes z1 to z4 is not limited to these, and various forms can be easily assumed by those skilled in the art for step-down methods such as different numbers of series connection, parallel connection, or a combination of series and parallel connection. .. For example, several general diodes that utilize a general pn junction, which is a constant voltage element, in the forward direction may be connected in series to one Zener diode. The gate voltage Vj2 of the nMOS transistors n1 and n2 when the detection current Ij flows is substantially equal to the threshold voltage between the gate and source of the nMOS transistors n1 and n2. The nMOS transistors n1 and n2 form a current mirror circuit, and the pMOS transistors p1 and p2 also form separate current mirror circuits. Therefore, the detection current Ij generated on the resistor r1 side and flowing through the nMOS transistor n1 generates the same detection current Ij on the pMOS transistor p2. If the constant voltage element is used for the input voltage conversion unit 7, the current does not flow until the constant voltage element conducts, so that the power consumption can be reduced.

The reference voltage unit 8 generates a reference current Irt corresponding to the resistance value of the resistor R3. A resistor R3 can be externally attached to the setting terminal RT. The reference voltage unit 8 includes bipolar transistors b1 and b2, a bandgap reference circuit 16, a constant current source 17, and resistors r2 and r3. The bandgap reference circuit 16 produces a predetermined bandgap voltage Vbgr1 (eg, 1.25V). The bandgap voltage Vbgr1 is divided by the resistors r1 and r2, and the divided voltage Vbgr2 is generated at the common connection node of the resistors r2 and r3.

The emitter of the NPN type bipolar transistor b2 is connected to the setting terminal RT. The constant current source 17 is connected to the emitter of the PNP type bipolar transistor b1 and the base of the bipolar transistor b2. A divided voltage dividing voltage Vbgr2 is applied to the base of the bipolar transistor b1. A circuit for supplying the emitter current of the bipolar transistor b1 and the base current of the bipolar transistor b2 is connected to the emitter of the bipolar transistor b2, but the configuration is not particularly limited and is not shown.

Assuming that the base-emitter voltage Vbe of the bipolar transistor b1 and the bipolar transistor b2 is equal, the set voltage Vrt of the setting terminal RT becomes equal to the voltage dividing voltage Vbgr2. Therefore, the reference current Irt given by the mathematical formula (1) flows through the resistor R3 via the bipolar transistor b2.
Irt = Vbgr2 / R3 ... (1)
The reference voltage unit 8 outputs the current flowing through the bipolar transistor b2 as the reference current Irt.

The current mirror circuit 15 is composed of pMOS transistors p3 to p5. The drain of the pMOS transistor p3 and the gate of the pMOS transistors p3 to p5 are connected to the collector of the bipolar transistor b2, and the reference current Irt is generated at the drain of the pMOS transistors p3 to p5, respectively. The drain of the pMOS transistor p4 is connected to the drain of the capacitor C, the nMOS transistor n3, and the non-inverting input terminal (+) of the hysteresis comparator 18. The drain of the pMOS transistor p5 is connected to one end of the resistor r4 to generate a node voltage Vn1 at the node N1. The node voltage Vn1 is output to the latch circuit 19.

The clock signal generation circuit 10 includes a capacitor C, an nMOS transistor n3, a hysteresis comparator 18, a first comparison voltage V1 and a second comparison voltage V2. The hysteresis comparator 18 compares the voltage between both ends of the capacitor C with the first comparison voltage V1 and the second comparison voltage V2, and outputs a rectangular clock signal CLK and a set signal Sset.

When the nMOS transistor n3 forming a part of the clock signal generation circuit 10 is off, a reference current Irt flows through the capacitor C to charge the capacitor C, and when the nMOS transistor n3 is on, the charge charged to the capacitor C is the nMOS transistor n3. Is discharged via. When the capacitor C is charged, the period from when the capacitor voltage Vc reaches the first comparison voltage V1 to when the capacitor C is charged to the second comparison voltage V2 is set as the off period Toff, and the hysteresis comparator 18 sets a low level. Output the signal set.

After the capacitor voltage Vc reaches the second comparison voltage V2, the electric charge accumulated in the capacitor C is discharged. When the capacitor C is discharged, the hysteresis comparator 18 outputs a high-level set signal Sset, in particular, with the period from the second comparison voltage V2 to the discharge of the first comparison voltage V1 as the on-period Ton. To do. That is, at this time, since the nMOS transistor n3 is on, the capacitor C is discharged via the nMOS transistor n3. After that, by repeating this operation, the hysteresis comparator 18 continues to output the set signal Sset at a constant period T.

As described above, the reference voltage unit 8, the current mirror circuit 15, and the clock generation circuit 10 are configured to generate and output the set signal Set and the clock signal CLK. The reference current Irt shown in the above equation (1) is adjusted according to the resistance R3, and adjusts the frequencies of the clock signal CLK and the set signal Sset. Further, since the reference current Irt is transmitted from the current mirror circuit 15 to the reference voltage adjusting unit 9 in the subsequent stage, the magnitude of the node voltage Vn1 is determined by the set resistor R3.

Next, the circuit operation of the input voltage conversion unit 7 and the reference voltage adjustment unit 9 when the resistor R3 is set to a relatively low resistance of about several tens of kΩ and the reference voltage adjustment unit 9 is enabled will be described. The input voltage conversion unit 7 generates a predetermined second detection voltage Vj2 by stepping down the input voltage Vin applied to the input terminal IN by using the Zener diodes Z1 to Z4 and the resistor r1. The second detection voltage Vj2 is substantially equal to the threshold voltage between the gate and source of the nMOS transistors n1 and n2. The second detection voltage Vj2 operates as the gate voltage of each gate of the nMOS transistors n1 and n2. The nMOS transistors n1 and n2 and the pMOS transistors p1 and p2 form a current mirror circuit, and by transmitting the detection current Ij flowing through the resistor r1 to the resistor r5 provided on the latch circuit 19 side, the node voltage Vn2 is transmitted to the node N2. Generate. The node voltage Vn2 is output to the latch circuit 19.

The reference voltage adjusting unit 9 is composed of resistors r4 and r5, a latch circuit 19, a first detection transistor JT1 and a second detection transistor JT2. The latch circuit 19 turns on / off the first detection transistor JT1 according to the input node voltages Vn1 and Vn2. In the normal state, that is, when the input voltage Vin is within a predetermined range, the first detection transistor JT1 is turned on, and in the overvoltage state, the first detection transistor JT1 is turned off. A comparator (not shown) that converts the node voltages Vn1 and Vn2 into high level H and low level L can be included in the latch circuit 19.

When the input voltage Vin is in the normal state, the latch circuit 19 outputs a high-level first detection voltage Vj1 to the gate of the first detection transistor JT1. At this time, the node voltage Vn1 is at a high level (for example, 0.65V), and the node voltage Vn2 is at a low level (for example, 0V). When the first detection transistor JT1 is in the ON state, the second detection voltage Vj2 is substantially equal to the ground potential GND (low level). When the second detection voltage Vj2 is at a low level, the threshold voltage is not applied to the gates of the nMOS transistors n1 and n2, so that all the nMOS transistors n1 and n2 are in the off state. Therefore, when the input voltage Vin is in the normal state, the reference voltage unit 8, the current mirror circuit 14, and the clock generation circuit 10 generate and output the original clock signal CLK (set signal Sset) whose frequency is not adjusted.

On the other hand, when the input voltage Vin is in the overvoltage state, the latch circuit 19 outputs the first detection voltage Vj1 corresponding to the high level to the gate of the first detection transistor JT1. At this time, the node voltage Vn1 is at a high level (for example, 0.65V), and the node voltage Vn2 is at a low level (for example, 0V). When the first detection transistor JT1 has a low level, the second detection voltage Vj2 has a high level. When the second detection voltage Vj2 is at a high level, a voltage equal to or higher than the threshold voltage is applied to the gates of the nMOS transistors n1 and n2, so that all the nMOS transistors n1 and n2 are turned on.

When the second detection transistor JT2 is on, the detection current Ij is flowing through the second detection transistor JT2. This is because the nMOS transistors n1 and n2 and the second detection transistor JT2 form a current mirror circuit, and it can be considered that the same detection current Ij is flowing through the drain of each nMOS transistor. The detection current Ij changes according to the input voltage Vin that gradually increases. Therefore, the voltage dividing voltage Vbgr2 is gradually lowered.

Since the voltage of the setting terminal RT becomes equal to the voltage dividing voltage Vbgr2, the voltage is gradually lowered. Therefore, the reference current Irt flowing through the resistor R3 also gradually decreases. At this time, the reference current Irt flowing through the capacitor C also gradually decreases, and the charging time inevitably increases. Correspondingly, the off period Toff from reaching the first comparison voltage V1 to being charged to the second comparison voltage V2 becomes longer. The on-period Ton until the capacitor voltage Vc is discharged from the second comparison voltage V2 to the first comparison voltage V1 is invariant. After that, by repeating this operation, a set signal Sset whose period T gradually increases is output. The change of the set signal Sset will be described later.

FIG. 8 shows a timing chart of each part of the oscillation circuit device 6 shown in FIG. 7 when the input voltage Vin is in an overvoltage state. FIG. 8 relates to FIG. 3 previously mentioned. That is, FIG. 3 has described a case where the resistor R3 is selected to be several hundred kΩ or more in order to set the oscillation frequency adjustment function of the oscillation circuit device 6 to the disable state, but FIG. 8 is a diagram. It is a timing chart of the main node of the oscillation circuit apparatus 6 shown in 7.

FIG. 8 shows the voltage at each node until the set signal Sset is output according to the input voltage Vin in order from the top.

The input voltage Vin starts to increase at time t1 and is detected as an overvoltage state when the predetermined voltage exceeds a predetermined voltage by Δv1 at time t2, but the circuit function of the reference voltage adjusting unit 9 is placed in the disable.

The node voltage Vn1 appears at the node N1. The node voltage Vn1 is substantially low level L regardless of the transition of time. The magnitude of the node voltage Vn1 is determined by the product of the reference current Irt and the resistor r4. The reference current Irt is determined by the resistor R3, and when the resistor R3 is selected to have a relatively high resistance value of several hundred kΩ or more, the reference current Irt becomes negligibly small, and the node voltage Vn1 is almost low level L or latch. The potential does not reach the potential at which the circuit 19 is operated.

The node voltage Vn2 appears at the node N2. The node voltage Vn2 changes from low level L to high level H when the detection current Ij starts to flow in the reference voltage unit 7, that is, at the time t2 when the detection current Ij starts to flow in the Zener diodes z1 to z4.

The first detection voltage Vj1 is output from the latch circuit 19 to the gate of the first detection transistor JT1. The first detection voltage Vj1 is set to be low level L only when both the node voltages Vn1 and Vn2 applied to the latch circuit 19 are high level H, and to be high level H in other combinations. Therefore, the first detection voltage Vj1 becomes the high level H regardless of the transition of time.

Since the second detection voltage Vj2 is the inverted version of the first detection voltage Vj1, the second detection voltage Vj2 has a low level L regardless of the transition of time.

The voltage dividing voltage Vbgr2 is applied to the base of the bipolar transistor b1. The voltage dividing voltage Vbgr2 is set by the voltage generated by the bandgap reference circuit 16 and the resistors r2 and r3. Further, it follows the on / off state of the reference voltage adjusting unit 9. The period until time t2, that is, until the overvoltage state is detected, is maintained at the voltage generated by the bandgap reference circuit 16 and the relatively high high level H set by the resistors r2 and r3.

When the base-emitter forward voltage of the bipolar transistors b1 and b2 is equal, the set voltage Vrt follows the change of the voltage dividing voltage Vbgr2, and its magnitude is also substantially equal to the voltage of the setting terminal RT. Therefore, the high level H is obtained regardless of the time transition.

The capacitor voltage Vc becomes a triangular wave-shaped or serrated wave voltage generated in the capacitor C, the capacitor C is charged by the reference current Irt, and the nMOS transistor n3 repeatedly discharges steeply, so that the gradient voltage has high linearity. Become. The period of the capacitor voltage Vc is the same regardless of whether the input voltage Vin is in the normal state at time t1 or after the time t2 when the input voltage Vin enters the overvoltage state. This is because the set voltage Vrt of the setting terminal RT is constant regardless of the transition of time, and the reference current Irt for charging the capacitor C is constant without changing.

The clock signal CLK (set signal Sset) is a clock signal CLK (set signal Sset) output from the hysteresis comparator 10. When the capacitor voltage Vc reaches the first comparison voltage V1 and the second comparison voltage V2, respectively, it becomes a rectangular wave signal that repeats high level and low level. The period (frequency) of the clock signal CLK (set signal Sset) is the same regardless of the time transition, that is, regardless of the normal state or the overvoltage state, like the period of the capacitor voltage Vc.

FIG. 9 is a timing chart of each part of the oscillation circuit device 6 when the input voltage Vin falls into the overvoltage state in FIG. 7. FIG. 9 relates to FIG. 4 previously mentioned. That is, FIG. 4 illustrates the case where the resistor R3 is selected to have a relatively low resistance value of about several tens of kΩ in order to set the oscillation frequency adjustment function of the oscillation circuit device 6 to the enable state. FIG. 9 shows a timing chart of each part when the oscillator circuit device 6 shown in FIG. 7 is set to the enabled state.

FIG. 9 shows the voltage at each node until the clock signal CLK (set signal Set) is output according to the input voltage Vin in order from the top. The input voltage Vin starts to increase from time t1, and when the predetermined voltage exceeds a predetermined voltage by Δv1 at time t2, it is determined to be in an overvoltage state, and the reference voltage adjusting unit 9 adjusts the oscillation frequency in the oscillation circuit device 6.

The node voltage Vn1 appears at the node N1 shown in FIG. The node voltage Vn1 is substantially low level L. The magnitude of the node voltage Vn1 is determined by the product of the reference current Irt and the resistor r4. The reference current Irt is determined by the resistor R3, and when the resistor R3 is selected to be about several tens of kΩ, the reference current Irt becomes relatively large. Therefore, the node voltage Vn1 is the time t1 when the input voltage Vin is in the normal state and the overvoltage state. At the detected time t2, it is placed at the high level H. From time t2 to t3, the second detection transistor JT2 gradually becomes stronger in the ON state, and the set voltage Vrt becomes lower accordingly. At this time, the current flowing from the current mirror circuit 15 side toward the node N1 also gradually decreases, and the transition from the high level H to the low level L occurs at time t3. As a result, the first detection voltage Vj1 output from the latch circuit 19 can be properly output.

The node voltage Vn2 appears at the node N2 shown in FIG. The node voltage Vn2 becomes a high level H when the detection current Ij starts to flow in the reference voltage unit 7, that is, at the time t2 when the detection current Ij starts to flow in the Zener diodes z1 to z4.

The first detection voltage Vj1 is output from the latch circuit 19 to the gate of the first detection transistor JT1. The first detection voltage Vj1 is determined by the node voltage Vn1 and the node voltage Vn2, becomes low level L when both potentials are high level H, and outputs high level H in other combinations. Therefore, the section low level L at times t2 to t3 is obtained.

The second detection voltage Vj2 appears at the gate of the nMOS transistors n1 and n2. The second detection voltage Vj2 follows the timing at which the detection current Ij flows through the Zener diodes z1 to z4, but is determined by the on / off state of the first detection voltage Vj1, that is, the first detection transistor JT1. When the first detection transistor JT1 is turned on, that is, when the first detection voltage Vj1 is high level H and low level L, it becomes low level L and high level H, respectively. Therefore, the polarity of the second detection voltage Vj2 is reversed from that of the first detection voltage Vj1.

The voltage dividing voltage Vbgr2 is applied to the base of the bipolar transistor b1. The voltage dividing voltage Vbgr2 is set by the voltage generated by the bandgap reference circuit 16 and the resistors r2 and r3. Further, it follows the on / off state of the reference voltage adjusting unit 9. The period until time t2, that is, until the overvoltage state is detected, is maintained at the voltage generated by the bandgap reference circuit 16 and the relatively high potential set by the resistors r2 and r3. However, after time t2, a current gradually starts in the second detection transistor JT2, so that the voltage of the voltage dividing voltage Vbgr2 drops linearly.

When the base-emitter forward voltage of the bipolar transistors b1 and b2 is equal, the set voltage Vrt follows the change of the voltage dividing voltage Vbgr2, and its magnitude is also substantially equal to the voltage of the setting terminal RT. Therefore, it gradually decreases after the time t2.

The capacitor voltage Vc becomes a triangular wavy voltage appearing in the capacitor C, the capacitor is charged by the reference current Irt, and the nMOS transistor n3 repeatedly discharges steeply repeatedly, so that the gradient voltage has excellent linearity. Become. The capacitor voltage Vc becomes a triangular wavy voltage that repeats high level and low level when the first comparison voltage V1 and the second comparison voltage V2 are reached, respectively. The capacitor voltage Vc has a predetermined frequency (cycle) up to the time t2 immediately before entering the overvoltage state even at the time t1 when the input voltage Vin is in the normal state. After the time t2 when the overvoltage is detected, the frequency gradually decreases, and the period T2 becomes longer than the period T1.

The clock signal CLK (set signal Sset) is a clock signal CLK (set signal Sset) output from the hysteresis comparator 10. Since the clock signal CLK is a waveform-shaped capacitor voltage Vc, the frequency after the time t2 gradually decreases, and naturally the period T2 becomes longer than the period T1.

FIG. 10 shows an example of each oscillation circuit device according to the present invention. The oscillation circuit device 6a of FIG. 10 is provided in the current mirror circuit 15 in that the resistors R3a and R3b corresponding to the resistors R3 are incorporated in the oscillation circuit 6c as compared with the oscillation circuit device 6 shown in FIG. The difference is that the pMOS transistor p5 is not prepared, and the latch circuit 19 is replaced with the Schmidt inverter circuit St. Other circuit configurations and low frequency operation are the same. Here, FIG. 10 describes the difference in effect due to the different configurations of FIG. 7.

The resistors R3a and R3b in FIG. 10 operate as fixed resistors by being incorporated inside the oscillation circuit device 6a. With this circuit configuration, the node voltage Vn1 is always set to either high level H or low level L, and the frequency adjustment function in the clock signal generation circuit 10 can be used only in the state of the input voltage Vin.

In the oscillation circuit device 6a shown in FIG. 10, resistors corresponding to the resistors R3 provided in the oscillation circuit device 6 of FIG. 7 are built in as resistors R3a and R3b. The resistor R3b is selected to be, for example, an order of magnitude larger than the resistor R3a, for example, several hundred kΩ or more. The resistor R3a is set to, for example, about several tens of kΩ, and by incorporating these resistors in the oscillation circuit device 6c, the setting terminal RT prepared in FIG. 7 becomes unnecessary, and the number of external terminals can be reduced. The third detection transistor JT3 is connected to the common connection point between the resistors R3a and R3b, and when the third detection transistor JT3 is off, the resistors R3a and R3b are located between the emitter of the bipolar transistor b2 and the ground potential GND. Connected in series.

To give the clock signal generation circuit 10 a frequency adjustment function, the third detection transistor JT3 is turned on and R3a having a relatively low resistance is selected. To disable the frequency adjustment function, the third detection transistor JT3 is turned off and the series resistance of the resistor R3a and the resistor R3b is selected.

The control voltage Vjt3 is not fixed to either the high level or the low level, but uses, for example, the first detection voltage Vj1 applied to the gate of the first detection transistor JT1 to use the first detection voltage Vj1 or its inversion. It may be linked to the voltage.

Of course, only the resistor R3a or the resistor R3b may be connected to the emitter of the bipolar transistor b2 without preparing the series resistance circuit of the resistors R3a and R3b or the third detection transistor JT3.

FIG. 11 shows another oscillator circuit device 6b suitable for monitoring and detecting an overvoltage state in the switching regulator according to the present invention. FIG. 11 shows that the internal configurations of the input voltage conversion unit 7 and the reference voltage adjustment unit 9 are different from those of the oscillation circuit device 6 shown in FIG. 7 and the oscillation circuit device 6a shown in FIG. Other circuit configurations and circuit operations are the same. Here, a circuit configuration different from that of FIG. 7 and a difference in effect will be described.

The oscillation circuit device 6b of FIG. 11 includes a resistor circuit in which resistors r6 to r8 are connected in series to the input voltage conversion unit 7. The input voltage Vin is divided by the resistor r6, the resistor r7, and the resistor r8, respectively, and the node voltage Vn3 is generated at the node N3 and the node voltage Vn4 is generated at the node N4.

In FIG. 11, the reference voltage adjusting unit 9 includes a latch circuit 19, a first detection transistor JT1, a second detection transistor JT2, a buffer comparator 22, a resistor r4, and a resistor r9. The latch circuit 19 controls the first detection transistor JT1 on / off according to the inputs of the node voltages Vn1 and Vn3.

In the buffer comparator 22, the node voltage Vn4 is connected to the non-inverting input terminal, and the connection point of the second detection transistor JT2 and the resistor r9 is connected to the inverting input terminal. The buffer comparator 22 outputs the second detection voltage Vj2 to the gate of the second detection transistor JT2. The first detection transistor JT1 and the second detection transistor JT2 operate in a complementary manner. That is, when the first detection transistor JT1 is on, the buffer comparator 22 outputs a low-level second detection voltage Vj2, and turns off the second detection transistor JT2. When the first detection transistor JT1 is off, the buffer comparator 22 outputs the second detection voltage Vj2 and turns on the second detection transistor JT2.

FIG. 12 is a timing chart of each part of the oscillation circuit device 6b when the input voltage Vin falls into the overvoltage state in FIG. In particular, it is a timing chart when the resistor R3 provided in the reference voltage section 8 is selected to have a relatively low resistance value of about several tens of kΩ and the reference voltage adjusting section 9 is enabled. FIG. 12 is the same as most of FIG. 9 described above, except that the timing charts of node N3 and node N4 are depicted.

FIG. 12 shows the voltage at each node until the clock signal CLK (set signal Set) is output according to the input voltage Vin in order from the top. The input voltage Vin starts to increase from time t1, and when the predetermined voltage exceeds a predetermined voltage by Δv1 at time t2, it is determined to be in an overvoltage state, and the reference voltage adjusting unit 9 adjusts the oscillation frequency in the oscillation circuit device 6.

The node voltage Vn1 appears at the node N1 shown in FIG. The magnitude of the node voltage Vn1 is determined by the product of the reference current Irt and the resistor r4. The reference current Irt is determined by the resistor R3, and when the resistor R3 is selected to be about several tens of kΩ, the reference current Irt becomes relatively large. Therefore, the node voltage Vn1 is the time t1 when the input voltage Vin is in the normal state and the overvoltage state. At the detected time t2, it is placed at the high level H. At times t2 to t3, the second detection transistor JT2 gradually becomes stronger in the ON state, and the set voltage Vrt becomes lower accordingly. At this time, the current flowing from the current mirror circuit 15 side toward the node N1 also gradually decreases, and the level transitions from the high level H to the low level L at time t3. The time t3 can be adjusted and controlled by the magnitudes of the reference current Irt and the resistor r4, and is not determined by the voltage or current of another node.

The node voltage Vn3 appears at the node N3 shown in FIG. The node voltage Vn3 gradually rises after the time t1 when the overvoltage state is detected. Based on the node voltage Vn3, the high level H is output by a comparator (not shown) provided on the latch circuit 19 side at time t2.

The first detection voltage Vj1 is output from the latch circuit 19 to the gate of the first detection transistor JT1. The first detection voltage Vj1 is determined by the signals generated according to the levels of the node voltage Vn1 and the node voltage Vn3, becomes low level L when both potentials are high level H, and is high level in other combinations. H is output. Therefore, the section low level L at times t2 to t3 is obtained.

The second detection voltage Vj2 is output to the buffer comparator 22. The second detection voltage Vj2 is the same as the node voltage Vn4 generated in the node N4. The node voltage Vn4 gradually increases after the time t1 like the node voltage Vn3.

The voltage dividing voltage Vbgr2 is applied to the base of the bipolar transistor b1. The voltage dividing voltage Vbgr2 is set by the voltage generated by the bandgap reference circuit 16 and the resistors r2 and r3. Further, it follows the on / off state of the reference voltage adjusting unit 9. The period until time t2, that is, until the overvoltage state is detected, is maintained at the voltage generated by the bandgap reference circuit 16 and the relatively high potential set by the resistors r2 and r3. However, after time t2, a current gradually starts in the second detection transistor JT2, so that the voltage of the voltage dividing voltage Vbgr2 drops linearly.

The set voltage Vrt follows the behavior of the voltage dividing voltage Vbgr2 when the base-emitter forward voltage of the bipolar transistors b1 and b2 is equal, and its magnitude is also substantially equal to the voltage of the setting terminal RT. Therefore, it gradually decreases after the time t2.

The capacitor voltage Vc becomes a triangular wavy or serrated voltage appearing on the capacitor C, the capacitor is charged by the reference current Irt, and the nMOS transistor n3 is generated by repeating a steep discharge, so that the gradient has excellent linearity. Slope) It becomes a voltage. The capacitor voltage Vc becomes a triangular wavy voltage that repeats high level and low level when the first comparison voltage V1 and the second comparison voltage V2 are reached, respectively. The capacitor voltage Vc has a predetermined frequency (cycle) up to the time t2 immediately before entering the overvoltage state even at the time t1 when the input voltage Vin is in the normal state. After the time t2 when the overvoltage is detected, the frequency gradually decreases, and the period T2 becomes longer than the period T1.

The clock signal CLK (set signal Sset) is a clock signal CLK (set signal Sset) output from the hysteresis comparator 18. Since the clock signal CLK is a waveform-shaped capacitor voltage Vc, the frequency after the time t2 gradually decreases, and naturally the period T2 becomes longer than the period T1.

FIG. 13 shows still another example of the oscillation circuit device according to the present invention. The oscillation circuit device 6c of FIG. 13 has a circuit configuration suitable when the input voltage Vin falls into a low voltage state. The circuit configuration of the input voltage conversion unit 7 is different from that for detecting the overvoltage state shown in FIG. 7. Other circuit configurations and circuit operations are almost the same. Here, the circuit configuration in which FIG. 13 is different from that in FIG. 7 and the difference in its effect will be described.

In FIG. 13, the input voltage conversion unit 7 includes resistors r10 to r12, pMOS transistors pL, nMOS transistors n1 and n2, and pMOS transistors p1 and p2. A resistor r10 and a resistor r11 are connected in series between the input terminal IN and the ground potential GND. The input voltage Vin is divided by the resistor r10 and the resistor r11 to generate a node voltage Vn5 at the node N5 and output it to the gate of the pMOS transistor pL.

The source of the pMOS transistor pL is connected to the power supply voltage Vcc via the resistor r12, and its drain is connected to the drain and gate of the nMOS transistor n1 and the gate of the nMOS transistor n2. The detection current Ij generated by the pMOS transistor pL is determined by the node voltage Vn5, the threshold voltage Vgs between the gate and source of the pMOS transistor pL, and the resistor r12. A current substantially the same as or different from the current flowing through the pMOS transistor pL can be passed through the nMOS transistors n1 and n2 and the pMOS transistors p1 and p2 constituting the current mirror circuit.

When the input voltage Vin falls into a low voltage and becomes a potential difference between the voltage during normal operation and the set voltage Δv2 or more, it is determined that the voltage is low and the pMOS transistor pL is turned on. At this time, the gate-source voltage Vgs is, for example, 0.65 V, and a high-level node voltage Vn2 is connected to the node N2 via the nMOS transistors n1 and n2 and the pMOS transistors p1 and p2 forming the current mirror circuit in the subsequent stage. To generate.

Similar to that shown in FIG. 7, the latch circuit 19 turns off the first detection transistor JT1 when both the node voltages Vn1 and Vn2 are at high level H, and when at least one of the node voltages Vn1 and Vn2 is at low level. , Operates to turn on the first detection transistor JT1.

The reference voltage unit 8, the reference voltage adjusting unit 9, the current mirror circuit 15, and the clock signal generation unit 10 in FIG. 13 are the same as those shown in FIG.

FIG. 14 is a timing chart of each part in the low voltage state of the fourth embodiment of the oscillation circuit device according to the present invention. FIG. 13 shows the voltage at each node until the set signal Sset is output according to the input voltage Vin in order from the top. FIG. 14 is a timing chart of each part of the oscillation circuit device 6c when the input voltage Vin falls into the low voltage state in FIG. That is, FIG. 14 is a timing chart when the resistor R3 is selected to have a relatively low resistance value of about several tens of kΩ in order to set the oscillation frequency adjustment function of the oscillation circuit device 6c to the enable state.

FIG. 14 shows the voltage at each node until the clock signal CLK (set signal Set) is output according to the input voltage Vin in order from the top. The input voltage Vin starts stepping down at time t1, and when it falls below a predetermined voltage by Δv2 at time t2, it is determined to be in a low voltage state, and the reference voltage adjusting unit 9 adjusts the oscillation frequency in the oscillation circuit device 6. ..

The magnitude of the node voltage Vn1 is determined by the product of the reference current Irt and the resistor r4. The reference current Irt is determined by the resistor R3. When the resistor R3 is selected to be about several tens of kΩ, the reference current Irt becomes relatively large, so that the node voltage Vn1 becomes high level H at the time t1 when the input voltage Vin is in the normal state and at the time t2 when the low voltage state is detected. Be placed. From time t2 to t3, the second detection transistor JT2 gradually becomes stronger in the ON state, and the set voltage Vrt becomes lower accordingly. At this time, the current flowing from the current mirror circuit 15 side toward the node N1 also gradually decreases, and at time t3, the current flows from the high level H to the level corresponding to the low level L. The timing of time t3 can be adjusted and controlled by the magnitude of the reference current Irt and the resistor r4, and is not determined by the voltage or current of other nodes, but the node voltage Vn2 changes from low level to high level. It is adjusted to be later than the time t2. As a result, the first detection voltage Vj1 output from the latch circuit 19 can be properly output.

The node voltage Vn5 appears at the node N5. The node voltage Vn5 gradually decreases from the time t1 when the low voltage state is entered. At time t2, the node voltage Vn5 decreases by a predetermined voltage ΔV3, and thereafter decreases with the passage of time.

The first detection voltage Vj1 is output from the latch circuit 19 to the gate of the first detection transistor JT1. The first detection voltage Vj1 is set to the high level H until the time t2 when the low voltage is detected, and is set to the low level L after the time t2 in the low voltage state. The first detection voltage Vj1 is set by the latch circuit by the node voltage Vn1 and the node voltage Vn2 (same as Vn2 in FIG. 9) (not shown in FIG. 14).

The second detection voltage Vj2 appears at the gate of the nMOS transistors n1 and n2. The second detection voltage Vj2 has the polarity of the first detection voltage Vj1 reversed.

The voltage dividing voltage Vbgr2 is applied to the base of the bipolar transistor b1. The voltage dividing voltage Vbgr2 is set by the voltage generated by the bandgap reference circuit 16 and the resistors r2 and r3. Further, it follows the on / off state of the reference voltage adjusting unit 9. Until time t2, that is, the section until the low voltage state is detected, the voltage generated by the band gap reference circuit 16 and the relatively high potential set by the resistors r2 and r3 are maintained, but at time t2. After that, since the current gradually starts in the second detection transistor JT2, the voltage of the voltage dividing voltage Vbgr2 drops linearly.

When the base-emitter forward voltage of the bipolar transistors b1 and b2 is equal, the set voltage Vrt follows the change of the voltage dividing voltage Vbgr2, and its magnitude is substantially equal to the voltage of the setting terminal RT.

The capacitor voltage Vc is generated in the capacitor C and becomes a triangular wave-shaped or serrated voltage. The capacitor is charged by the reference current Irt, and the nMOS transistor n3 repeatedly discharges steeply repeatedly, so that the slope has excellent linearity. ) It becomes a voltage. The period of the capacitor voltage Vc expands as the set voltage Vrt decreases, and the frequency decreases.

The clock signal CLK (set signal Sset) is a clock signal CLK (set signal Sset) output from the hysteresis comparator 10. When the capacitor voltage Vc reaches the first comparison voltage V1 and the second comparison voltage V2, respectively, it becomes a rectangular wave signal that repeats high level and low level. The period (frequency) of the clock signal CLK (set signal Sset) increases with the passage of time, and the frequency decreases.

FIG. 15 shows still another example of the oscillation circuit device according to the present invention. The oscillation circuit device 6d has a circuit configuration that can be used when the input voltage Vin is in a low voltage state. The configuration of a part of the input voltage conversion unit 7 and the reference voltage adjustment unit 9 is different from that of FIG. Other circuit configurations and circuit operations are the same. Here, a circuit configuration in which FIG. 15 is different from FIG. 13 will be described.

The oscillation circuit device 6d includes resistors r13 and r14, a first detection transistor JT1 and a second detection transistor JT2 in the reference voltage adjusting unit 9. The resistors r13 and r14 are connected in series between the select terminal SELECT and the ground. A node voltage Vn6 is generated at the common connection node N6 of the resistors r13 and r14, and this is input to the gate of the first detection transistor JT1. The oscillation circuit device 6d must prepare the select terminal SELECT as an external terminal, but it is extremely possible to set whether to enable or disable the frequency adjustment function by that amount without adopting a latch circuit or the like. It is possible to set it easily and surely. Further, if an external terminal is prepared, it is possible to easily set whether or not the clock signal generation circuit 10 has frequency adjustment at the time of low voltage.

FIG. 16 is a detailed configuration example of the latch circuit according to the present invention. The latch circuit 19 is a well-known two-input latch circuit composed of Schmidt inverter circuits 20 and 21, inverter In1 and negative logic products NAND1 and NAND2. The node voltage Vn1 input as a set signal is input or output to the terminal a, the node voltage Vn2 input as a reset signal is input or output to the terminal b, and the first detection voltage Vj1 is input or output via the terminal c. The latch circuit 19 sets the first detection voltage Vj1 to the high level H by using the falling edge of the node voltage Vn1 as a trigger, and resets the first detection voltage Vj1 to the low level L by using the rising edge of the node voltage Vn2 as a trigger. The latch circuit 19 may be configured by combining a NOR circuit and an inverter or the like instead of the sheffer fatigue circuit.

The node voltage Vn1 is the reference current Irt converted into a voltage by the resistor r4, and the node voltage Vn2 is the input current Ij converted into a voltage by the resistor r5. When the frequency dividing operation is performed in the overvoltage state, the detection current Irt decreases and the node voltage Vn1 is also stepped down, and the node voltage Vn1 drops from the high level to the low level, so that the logical operation is reversed. Therefore, it is desirable that the latch circuit 19 is a reset priority type as shown in FIG.

As described above, the oscillation circuit device according to the present invention has extremely high industrial utility value because it can be applied not only to various types of switching regulators but also to other electronic circuit devices. Further, the switching regulator driven by such an oscillation circuit device can obtain a stable output because the same frequency adjustment is executed in both the overvoltage state and the undervoltage state of the input voltage.

1,100 Switching regulator 1a, 100a Semiconductor integrated circuit device 2a, 2b Switching transistor 3 Synchronous rectifying element 4 Soft start control circuit 5 Error amplifier 6 Oscillating circuit device 7 Input voltage conversion unit 8 Reference voltage unit 9 Reference voltage adjustment unit 10 Clock signal Generation circuit 11 Slope signal generation circuit 12 Summing means 13 PWM comparator 14 Drive control circuit 15 Current mirror circuit 16 Band gap reference circuit 17 Constant current source 18 Hysteresis comparator 19 Latch circuits 20, 21 Schmidt trigger circuits 22 Buffer comparators a, b, c Terminals b1, b2 Bipolar transistors C, C1, C2, C3 Capacitor COMP Phase compensation terminal CS signal line FB Feedback terminal Gp, Gn Gate voltage Ij Detection current In1, In2 Inverter IN Input terminal Irt Reference current Isw Switching current JT1 First detection transistor JT2 2nd detection transistor L inductor n1 to n5 nMOS transistor N1 to N4 node NAND1, NAND2 Negative logic product circuit OUT output terminal p1 to p5 pMOS transistor PGND, AGND ground terminal r1 to r8, R1 to R4 resistance RT setting terminal Voltage reset signal Set signal SS soft start terminal SW switching terminal V1 1st comparison voltage V2 2nd comparison voltage Vbgr1 Band gap voltage Vbgr2 Divided voltage Vc Capsule voltage Vcs Current detection signal Verr Error signal Vfb Feedback voltage Vin Input voltage Vj1 1st detection voltage Vj2 Second detection voltage Vn1 to Vn3 Node voltage Vout Output voltage Vref Threshold voltage Vslope Slope signal Vss Soft start voltage Vsw Switching voltage z1 to z4 Zener diode

Claims (15)

It is an oscillation circuit device of a switching regulator that generates an output voltage from an input voltage by driving a switching means in synchronization with a clock signal.
An input voltage converter that converts the input voltage into a predetermined voltage,
The reference voltage section that generates the reference voltage and
The predetermined voltage is received, and the input voltage is in an overvoltage state exceeding the voltage in the predetermined range in the normal state , or the input voltage is in a low voltage state lower than the voltage in the predetermined range . A reference voltage adjusting unit that lowers the reference voltage according to the predetermined voltage when it deviates from the range.
The reference voltage is received a higher larger the reference current, and a clock signal generating circuit for generating the clock signal having an oscillation frequency proportional to the magnitude of the reference current,
The input voltage conversion unit, the reference voltage unit, the reference voltage adjustment unit, and the clock signal generation circuit are built in the semiconductor integrated circuit device .
The input voltage conversion unit includes a detection means for converting the input voltage into the predetermined voltage when the input voltage deviates from the predetermined range, and a first voltage for converting the predetermined voltage into a first current. -Has a current conversion means
The reference voltage section uses a band gap reference circuit that generates a predetermined band gap voltage, a voltage dividing circuit that divides the band gap voltage, and a second current proportional to the voltage dividing voltage generated by the voltage dividing circuit. It has a second voltage-current conversion means to be generated, outputs the divided voltage as the reference voltage, and outputs the second current as the reference current.
The reference voltage adjusting unit is an oscillation circuit device whose enable state and disable state are controlled based on the first current and the second current. The oscillation circuit device according to claim 1, wherein the input voltage conversion unit generates the predetermined voltage by stepping down the input voltage by a resistance circuit when the input voltage is in the overvoltage state. The input voltage conversion unit, when the input voltage becomes the overvoltage condition, the oscillator circuit device according to claim 1 for generating a predetermined voltage by stepping down the input voltage through a constant voltage element. Oscillator circuit, wherein said second current to claim 1 which is set by the resistor connected to an external is provided in the reference voltage unit is supplied the divided voltage of the semiconductor integrated circuit device apparatus. The second current oscillator circuit device according to claim 1 which is set by a resistor built in is provided in the reference voltage unit and the divided voltage is supplied the semiconductor integrated circuit device. The voltage divider circuit includes a resistor circuit including a first resistor and a second resistor connected in series via a common connection circuit point, and one end of the first resistor is connected to a band gap reference circuit and the other end of the first resistor. Is connected to the common connection circuit point, one end of the second resistor is connected to the common connection circuit point, and the other end of the second resistor is connected to the ground potential, according to any one of claims 1 to 5. The oscillator circuit device described. The output of the reference voltage adjusting unit, said common connection being connected to a circuit point, the reference voltage said reference voltage when the adjusting unit is controlled to the enable state from the disk enabled state is lower than when the disc enable state The oscillation circuit device according to claim 6. The reference voltage adjusting unit includes a latch circuit having a set terminal and a reset terminal, a set input signal corresponding to the second current to the set terminal, a reset input to the reset terminal in accordance with the first current signal is input, the latch circuit is reset-priority der is, the output of the latch circuit, the reference voltage adjusting unit according to claim 7 indicating which said enable state or a disk enabled state Oscillation circuit device. The clock signal generation circuit includes a current mirror circuit that generates a third current based on the second current, a capacitor that is repeatedly charged or discharged by the third current, an upper limit value of a triangular wavy voltage generated in the capacitor, and an upper limit value of a triangular wavy voltage generated in the capacitor. It has a comparator to set the lower limit, the oscillator circuit device according to any one of claims 1 to 8 for outputting the clock signal of rectangular shape from the output of the comparator. It is an oscillation circuit device of a switching regulator that generates an output voltage from an input voltage by driving a switching means in synchronization with a clock signal.
An input voltage conversion unit that steps down the input voltage and converts it into a first step-down voltage and a second step-down voltage lower than the first step-down voltage.
The reference voltage section that generates the reference voltage and
When the input voltage receives the second step-down voltage and becomes an overvoltage state exceeding the voltage in the predetermined range in the normal state and deviates from the predetermined range, the reference voltage is lowered according to the second step-down voltage. Reference voltage adjustment unit and
The reference voltage is received a higher larger the reference current, and a clock signal generating circuit for generating the clock signal having an oscillation frequency proportional to the magnitude of the reference current,
The input voltage conversion unit, the reference voltage unit, the reference voltage adjustment unit, and the clock signal generation circuit are built in the semiconductor integrated circuit device .
The reference voltage unit generates a bandgap reference circuit that generates a predetermined bandgap voltage, a voltage dividing circuit that divides the bandgap voltage to generate the reference voltage, and the reference current proportional to the reference voltage. Has a voltage-current conversion means to
The reference voltage adjusting unit is an oscillation circuit device whose enable state and disable state are controlled based on the reference current and the first step-down voltage. The oscillator circuit device according to any one of claims 1 to 10.
And said switching means which is turned on / off to generate the output voltage from the input voltage,
An inductor that repeatedly stores and releases energy by the switching operation of the switching means.
A smoothing means that receives the energy emitted from the inductor and smoothes the output voltage.
An error amplifier circuit that generates an error signal according to the difference between the output voltage or the feedback voltage corresponding thereto and the first reference voltage, and
A slope signal generation circuit for generating the triangular or sawtooth slope signal is generated based on the clock signal generated by the clock signal generation circuit of the oscillator circuit device,
A PWM comparator that compares the slope signal with the error signal and outputs a PWM signal with a modulated pulse width.
A switching regulator including a drive control circuit that receives the clock signal and the PWM signal and controls the switching means. The switching means, the error amplification circuit, the slope signal generation circuit, the PWM comparator, and the drive control circuit are together with the input voltage conversion unit, the reference voltage unit, the reference voltage adjustment unit, and the clock signal generation circuit. the switching regulator of claim 11 which is incorporated in one of said semiconductor integrated circuit device. The switching regulator according to claim 11 or 12 , wherein when the input voltage deviates from the predetermined range , the switching means is on / off controlled at a switching voltage having a frequency lower than that in the normal state. Switching means that are turned on and off to generate an output voltage from the input voltage,
An inductor that repeatedly stores and releases energy by the switching operation of the switching means.
A smoothing means that receives the energy emitted from the inductor and smoothes the output voltage.
An error amplifier circuit that generates an error signal according to the difference between the output voltage or the feedback voltage corresponding thereto and the first reference voltage, and
Oscillator circuit device that generates clock signal and
A slope signal generation circuit that generates a triangular wave-shaped or serrated slope signal generated based on the clock signal, and a slope signal generation circuit.
A PWM comparator that compares the slope signal with the error signal and outputs a PWM signal with a modulated pulse width.
A drive control circuit that receives the clock signal and the PWM signal and controls the switching means is provided.
The oscillation circuit device is
An input voltage converter that converts the input voltage into a predetermined voltage,
The reference voltage section that generates the reference voltage and
The predetermined voltage is received, and even if the input voltage is in an overvoltage state exceeding the voltage in the predetermined range in the normal state or the input voltage is in a low voltage state lower than the voltage in the predetermined range. A reference voltage adjusting unit that lowers the reference voltage when it deviates from the range,
It is provided with a clock signal generation circuit that receives a reference current that increases as the reference voltage increases and generates the clock signal having an oscillation frequency proportional to the magnitude of the reference current.
A switching regulator in which the switching means is on / off controlled at a switching voltage having a frequency lower than that in the normal state, regardless of whether the input voltage is in the overvoltage state or the undervoltage state. The switching regulator according to claim 13 or 14 , wherein the frequency of the switching voltage decreases linearly in proportion to the magnitude of the overvoltage in the overvoltage state and the magnitude of the low voltage in the undervoltage state.

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