JP6860166B2 - Optical calculator - Google Patents

Description

The present invention relates to an optical arithmetic unit composed of a photoelectric fusion type arithmetic circuit.

Current electronic arithmetic circuits have been devised to reduce the chip size and element size to the utmost limit in order to improve the processing speed of arithmetic operations. This is because the resistance (R) and the capacitance (C) in the circuit greatly control the signal propagation, and therefore, the only way to increase the calculation speed is to reduce the chip size and the element size. For this reason, elements have been packed into narrow-area logic blocks and cores, and devised such as multi-core and many-core, but the wiring for connecting these creates a new "delay", and there is a limit to speeding up operations. I'm seeing it.

On the other hand, optical wiring and optical path gates used in optical communication and the like can propagate optical signals independently of C and R in the wiring path. In addition, with the progress of nanophotonics, the energy consumption of optical gates has been dramatically improved, and this energy cost [J / bit] is becoming the same level for CMOS gates and optical path gates. For this reason, various studies have been conducted to make communication within and between chips optical.

Here, a connection form in which a signal is input from the electric control port side of the optical gate is defined as a cascade connection, and a form in which the optical propagation path of the switch is continuously connected is defined as a serial connection. For example, in the case of a photoelectric fusion type circuit in which serial connection and cascade connection are mixed, the cascade connection portion is the boundary between light and electricity. At this boundary, the optical signal propagating in the circuit is once converted into electricity (OE conversion). Since this conversion is rate-determined by an electric circuit, a circuit in which OE conversion is frequently used has little merit of using light. Therefore, the boundary between light and electricity, that is, the location and number of cascade connections, is an important point in the circuit configuration.

Here, an N-input AND circuit will be taken as an example. In the case of a CMOS circuit, an S input element is configured by a path block gate connected serially, and an N input function is constructed by cascading the S input elements in a tree-like manner. In this case, the delay time of the N input function is as follows.

In this case, since the electric signal propagation delay of the serial connection portion is affected by the resistance and the capacitance corresponding to the number of gates, there is a problem that it increases in proportion to the square of the number of stages S of the serial connection. If the operating voltage is increased to solve this problem, the power consumption also increases, so the S of the CMOS circuit is limited to 2 at most. Further, in order to use a small S, it is necessary to increase the number of cascade stages M, and as a result, there is a problem that the delay of the N input function is increased.

In the case of an optical circuit, it is known that an operation with a small delay can be performed only by serial connection (Non-Patent Documents 1 and 2). This is because the optical signal propagation delay of the serial part depends only on the length of the gate, that is, the delay has a characteristic that it is proportional to S, and it is possible to alleviate the problem of the electric signal propagation delay described above. Is.

J. Hardy et al., "Optics inspired logic architecture", Optics Express, vol. 15, no. 1, pp. 150-165, 2007. Tetsuya Asai et al., "Photonic Crystal Integrated Device Based on Binary Determining Graph", Proceedings of the 2000 IEICE General Conference, pp. 386-387, 2000. Q. Xu et al., "Reconfigurable optical directed-logic circuits using microresonator-based optical switches", Optics Express, vol. 19, no. 6, pp. 5244-5259, 2011. Toru Ishihara et al., "Proposal of parallel adder circuit based on optical passgate logic and operation verification by photoelectric mixed circuit simulator", Shingaku Giho, vol. 116, no. 94, pp. 109-114, 2016.

However, since the light intensity loss is also proportional to S, it is possible to handle S larger than electricity, but when handling too large S, it is necessary to take measures against signal deterioration.

The present invention has been made to solve the above problems, and an object of the present invention is to enable faster optical calculation.

The optical arithmetic unit according to the present invention is configured by serially connecting S arithmetic elements (S is a natural number of 2 or more ) that output one optical signal with respect to the input signal, and 1 by the S input signals. A plurality of arithmetic units for calculating and outputting one optical signal are provided, and the plurality of arithmetic units are cascade-connected, and signals output from the S arithmetic units in the previous stage are input to one arithmetic unit in the subsequent stage.

In the above optical arithmetic unit, the input signal is an electric signal, and each of the plurality of arithmetic units includes a conversion element that photoelectrically converts an optical signal output from a serially connected final stage arithmetic element.

In the above optical arithmetic unit, the input signal is an optical signal, and each of the plurality of arithmetic units outputs a value 1 when an optical signal is output from the S arithmetic elements, and light is emitted from the S arithmetic elements. A conversion element that outputs a value 0 except when a signal is output is provided.

In the optical computing element, the number S of stages M and computing devices of the cascade connection from the number N of the input signal, and operation time tau _Gate in the calculation device, and the processing time tau _OEO in the conversion element, S number of processing elements The calculation delay time according to (A) is determined by S having the minimum value, with the M root of N as S.

In the above optical arithmetic unit, the arithmetic elements of the plurality of arithmetic units in the first stage are composed of Mach-Zehnder interferometers, and the arithmetic elements in the plurality of arithmetic units in the second and subsequent stages are one input signal which is an electric signal. On the other hand, one optical signal may be output.

From the above description, according to the present invention, it is possible to obtain an excellent effect that optical calculation can be performed at a higher speed.

FIG. 1 is a configuration diagram showing a configuration of an optical arithmetic unit according to the first embodiment of the present invention. FIG. 2 is a configuration diagram showing a configuration of a calculation unit 101 of an optical calculator according to the first embodiment of the present invention. FIG. 3 is an explanatory diagram for explaining a calculation delay of a calculation unit (calculation circuit) that performs an AND operation. FIG. 4 is a configuration diagram showing a partial configuration of the optical arithmetic unit according to the first embodiment of the present invention. FIG. 5 is a configuration diagram showing the configuration of the arithmetic unit 101 of the optical arithmetic unit according to the second embodiment of the present invention. FIG. 6 is a configuration diagram showing a configuration of an optical arithmetic unit according to the third embodiment of the present invention. FIG. 7 is a configuration diagram showing a configuration of an optical arithmetic unit according to a fourth embodiment of the present invention. FIG. 8 is a configuration diagram showing a configuration of a 2-input 2-output XOR and XNOR calculation element in the present invention and an XNOR-AND and XOR-OR calculation unit by the combination thereof.

Hereinafter, embodiments of the present invention will be described.

[Embodiment 1]
First, the optical arithmetic unit according to the first embodiment of the present invention will be described with reference to FIG. This optical arithmetic unit includes a plurality of arithmetic units 101 connected in cascade. The arithmetic unit 101 is configured by serially connecting S arithmetic elements 102 (S is a natural number of 2 or more ) that outputs one optical signal with respect to the input signal. The calculation unit 101 calculates and outputs one optical signal from the S input signals. Further, the signals output from the S arithmetic units 101 in the previous stage are input to one arithmetic unit 101 in the subsequent stage. Note that FIG. 1 illustrates the case of S = 2. Further, FIG. 1 illustrates a case where the number of stages M of the cascade connection is 3.

Here, in the first embodiment, the input signal is an electric signal, and the arithmetic unit 101 includes a conversion element 103 that photoelectrically converts an optical signal output from the serially connected final-stage arithmetic element 102. For example, as shown in FIG. 2, the calculation unit 101 may be composed of a light source 111, a 1 × 1 optical pass gate 102a, and a conversion element 103. The two 1 × 1 optical pass gates 102a are serially connected. In this configuration, the electric control input to _{the 1 × 1 optical pass gate 102a in the first stage is x i,} and the electric control input to the 1 × 1 optical pass gate 102a in the second stage is y _i . If the signal is set to be transmitted only when the electric control input is 1, the combination of electric signals in which both the front 1 × 1 optical pass gate 102a and the rear 1 × 1 optical pass gate 102a are transmitted, that is, x It is an AND operation in which light is output only when _i y _{j = 1.}

In the present invention, as described above, the optical calculation is further speeded up by the cascade connection of the optical serial connection circuit. In the first embodiment, the conversion element 103 is used in order to input the optical output from the serial connection circuit by the 1 × 1 optical pass gate 102a to the electric control side of the 1 × 1 optical pass gate 102a. The calculation delay time in this configuration is as follows.

Here, in order to simplify the calculation, all the serial stages are uniform, and in all the 1 × 1 optical path gates 102a (calculation element 102), the propagation time of the light propagating in the arithmetic element 102 is uniform at _{τ gate.} , It is assumed that the OE conversion time in all the conversion elements 103 is also _{uniform in τ OEO} , and the calculation delay characteristic is dealt with. The calculation delay under this condition is expressed by the following equation (3).

In the electric circuit, since the conversion element 103 is not required for the cascade connection portion, τ _OEO = 0, and the response becomes slow when the number of serial stages is large, so the value of S is up to about 2. On the other hand, the optical arithmetic unit according to the first embodiment needs to pass the output of the arithmetic element 102 serially connected to the conversion element 103, and can handle S larger than 2. In these respects, the configurations of the electric circuit and the optical arithmetic unit in the first embodiment are significantly different.

As shown in FIG. 3, the delay amount of the M-stage cascade and the M + 1-stage cascade is reversed at a certain input number N, and the delay of the M + 1-stage cascade is smaller than that of the M-stage cascade at a larger number of inputs. Become.

That is, _{if N = N 0 satisfying F (N 0} , M) = F (N ₀ , M + 1) is set as the break-even point, the number of cascade stages of M + 1 for the number of inputs exceeding this and the number of cascade stages of M for the number of inputs not exceeding this. By adopting, it is possible to keep the delay small. Further, when N = N ₀ , a smaller S can be adopted by adopting the number of cascade stages of M + 1 stages, and the problem of loss of the optical serial circuit can be solved.

Next, we focus on the delay characteristics when N is fixed to a specific value and S, M = log _S (N) is used as a parameter. In the optical arithmetic unit according to the first embodiment, it is necessary to treat M and S as natural numbers, but here, it is extended to the real number range and the arithmetic delay is expressed by the equation (4).

The delays of the electric circuit and the optical circuit are represented by the equations (6) and (7), respectively. _{Here, in the electric circuit, τ OEO} = 0 is set because an OE conversion element is not required for the cascade connection portion, _{and τ gate} = τ _CMOS is set to distinguish it from the optical arithmetic unit in the embodiment.

By the way, the maximum value of the right side of the equation (8) is expressed by the following equation, and under the condition that it is smaller than 1, the delay of the optical arithmetic unit in the first embodiment becomes smaller than that of the electric circuit.

That is, using the light pass gate having a smaller propagation delay than e ^1-p times the CMOS switching time (arithmetic element 102), constitute a serial connection of S ₀ = e ^p stage, the light output from the serial connection circuit An electric circuit is obtained by cascading a signal through a photoelectric conversion element (conversion element 103) whose response speed is smaller than e (p-1) times the CMOS switching time _{and cascading M 0} = log _{S0 (N) stages.} An optical circuit with a smaller delay can be constructed.

In other words, the number of stages M of the cascade connection and the number S of the arithmetic elements 102 are calculated by the equation (4) from _{the number N of the input signals, the arithmetic time τ gate in the arithmetic element 102, and the processing time τ OEO} in the conversion element 103. Can be decided.

Here, the response speed of the conversion element 103 is sufficient to be about that of an electric circuit, but the propagation delay of the arithmetic element 102 must be smaller than the response speed of CMOS. Regarding this, considering that the propagation speed of light is about 100 μm / ps in a semiconductor, this condition is achieved by realizing an optical path gate (calculation element 102) having an element length of 1000 μm or less by nanophotonics. ..

By the way, the above-mentioned S ₀ and M ₀ are real values, but in an actual circuit, it is necessary to treat them as natural numbers. Therefore, the following natural numbers S and M are adopted as these values.

First, the number of cascade stages M is a candidate for adopting a value obtained by rounding up or rounding down the decimal point _{of the real value M 0} = log _{S0 (N).} It is clear from Eq. (3) that the lowest value appears in the calculation delay between two natural numbers sandwiching the real value M _0. The number of serial connection stages S is obtained by substituting the candidate M to be adopted into the equation (3). The minimum calculation delay can be obtained by substituting the two candidates of S and M into the equation (3) and adopting S and M having a smaller F (N, M).

If the values of F (N, M) are the same, the value obtained by rounding up the decimal point of _{M 0 may be adopted as M for the reason described above.} The method of setting M is the same as the method when the _{break-even point N 0 is taken into consideration.}

By the way, the existence of the break-even point N _{0 and the characteristic that the delay takes the minimum value at S 0} are that the serial connection part whose calculation delay increases in proportion to S and the cascade connection part which decreases as S increases coexist. _Therefore , the same tendency appears even in the case where S, τ _gate , and τ OEO are not uniform in the circuit.

In such a case, when the natural number S that minimizes the equation (2) is S (N, M) and the value of the natural number M is gradually increased from 1, F (N, M) <F (N). , M + 1), and M and S (N, M) are adopted. However, if the value of S becomes larger than the _{maximum allowable value S max} (natural number), the value of M shall be increased until _{S ≦ S max.} This allows the minimum delay to be obtained.

As described above, according to the first embodiment, the arithmetic element 102 (for example, an optical pass gate) having a propagation delay smaller than the switching time of CMOS causes the arithmetic unit 101 to be formed by a multi-stage serial connection circuit which is impossible in an electric circuit. The optical signal output from the serial connection circuit of the arithmetic element 102 is photoelectrically converted by the conversion element 103 and connected (input) to the arithmetic element 102 in the subsequent stage to form an optical circuit having a smaller delay than the electric circuit. can do.

FIG. 3 shows a comparison of calculation delays between the CMOS circuit and the optical calculator according to the first embodiment in the above-mentioned multi-input AND operation. The delay of the optical circuit is _{calculated using Eq. (3) with τ gate} = 0.2 _{ps and τ OEO} = 25 ps, and is shown by a curve of M = 1-3. Further, in this case, S ₀ = 44.7, and the characteristic curve represented by the equation (4) is a straight line tangent _{to the curve represented by the equation (3) at N = S 0} ^M. The delay of the CMOS circuit is _{calculated using Eq. (4) with τ gate} = 10 ps, τ _OEO = 0 ps, and S = 2.

This result shows that it is possible to realize a calculation with a significantly lower delay than a CMOS circuit only by adopting a cascade connection of at most one or two stages. _{For example, when N = 1000, M 0} = 1.82 from equations (3) and (5), and _{F (1000, 1) S = 1000} > F ( _{1000, 2) S = 32} from equation (3). Therefore, M = 2 and S = 32 are adopted. In this case, as shown in FIG. 4, it is a square circuit with 32 steps × 32 steps of 1 × 1 optical pass gate 102a, and the 1 × 1 optical pass gate 102a serially connected after the light is input (calculation). The time to pass through the element 102) is all equal. However, since the 32 ² = 1024> 1000, unnecessary gate exists.

[Embodiment 2]
Next, the optical arithmetic unit according to the second embodiment of the present invention will be described with reference to FIG. Also in the second embodiment, as described with reference to FIG. 1, a plurality of arithmetic units 101 connected in cascade are provided. As shown in FIG. 5, the arithmetic unit 101 is configured by serially connecting S arithmetic elements 102b (S is a natural number) that output one optical signal with respect to the input optical signal.

In the second embodiment, for example, the first arithmetic element 102b serially connected optically couples the optical _{signal λ 1 to the waveguide connected to the conversion element 103b.} The next arithmetic element 102b serially connected combines the light number λ ₂ with the light output from the first arithmetic element 102b. The arithmetic element 102b is, for example, a combiner composed of a ring resonator.

Further, in the second embodiment, the arithmetic unit 101 outputs an optical signal having a value of 1 when an optical signal is output from the S arithmetic elements 102b, and outputs an optical signal from the S arithmetic elements 102b. A conversion element 103b that outputs an optical signal having a value of 0 is provided except for the case. In this configuration, it becomes a multi-input OR arithmetic circuit.

In the second embodiment, when the power coupling efficiency of the combined wave in each arithmetic element 102b is α and the number of inputs N, M = 1, that is, S = N (case where only one input is combined) / ( The intensity ratio of (case where all inputs do not combine) is {α + (1-α) × (N-1)} / {(1-α) × N}. This value is the contrast ratio when the difference between "0" and "1" in the OR calculation output is the smallest.

The contrast ratios when α = 0.9 are 0.33 dB and 2.6 dB when N = 100 and 10, respectively, and the larger N is, the more the contrast deteriorates.

Here, S _max = 10 is set to the maximum value of the number of serial connection stages in which contrast can be detected on the optical receiving side of the conversion element 103b, and N = 100 when the circuit characteristics of the optical arithmetic unit are the same as those in the first embodiment. Consider the OR operation of.

In this case, from equations (3) and (5), S ₀ = 44.7, M ₀ = 1.2, and from F (100, 1) _{S = 100} <F ( _{100, 2) S = 10} , M = It becomes 1. However, since S = 100 and S _max = 10 is exceeded, M = 2 and S = 10 are adopted. As a result, the minimum delay can be realized while ensuring the suppression of the contrast decrease.

[Embodiment 3]
Next, the optical arithmetic unit according to the third embodiment of the present invention will be described with reference to FIG. In the third embodiment, a plurality of arithmetic units 101a of k = 1st stage connected in multiple stages are composed of an arithmetic element 102c composed of a Mach-Zehnder interferometer of 1 input and 1 output and a conversion element 103c. .. The input signal X and the input signal Y are input to the electric control units provided on the two arms of the Mach-Zehnder interferometer. The calculation unit 101 of the second and subsequent stages of k = is composed of the same calculation element 102 and conversion element 103 as in the first embodiment described above. In the third embodiment, the operation of the composite function XNOR-AND is performed.

Here, the conversion element 103c is the same as the conversion element 103 of the first embodiment. The electric signals output from the conversion element 103c are the input signals x ( _{N-digit binary signals of x 1 to x N} ) and the input signals y (y ₁ to) of the N arithmetic elements 102c serially connected. In _{the N-digit binary signal of y N} ), it is the result of ANDing in each digit, and it becomes 1 when all digits match, and 0 when it does not match. That is, the operation of the composite function XNOR-AND can be performed only in the first stage (M = 1).

However, k = 1 stage only (M = 1) In the decision output of the matching of each _{digit, AND M (A 1, ···} , A N), A j = XNOR (X j, Y j), A _j = XNOR (X _j , Y _{j ) is an electronic signal (X j} , Y _j ) at the two input terminals of the arithmetic element 102c, which is a Mach-Zehnder interferometer type intensity modulator. Is executed by inputting, and AND _M (A ₁ , ..., _AN ) is executed by serially connecting the arithmetic element 102c that executes the above arithmetic. Since the AND _M generally has a larger structure than the AND by the arithmetic element 102a in the first embodiment, the delay in the AND operation becomes large.

In order to solve this problem, we consider adopting a cascade connection for the AND operation part. That is, in the equation (2), the first stage of k = _{is composed of AND M having a large τ gate} , and the second stage of k ≧ is composed of the AND by the arithmetic unit 101 in the first embodiment having a small _{τ gate.} In this case, equation (3) is rewritten to equation (12). Here, S ₁ , τ _gate 1 is k = the number of serial connection stages of the first stage and one arithmetic element 102c propagation delay, and S ₂ , τ _gate 2 is k = the number of serial connection stages of the second and subsequent stages and propagation of one arithmetic element 102. Delay, L is k = total number of inputs to the second stage, and M is k = number of cascade stages after the second stage. However, in equation (12), it holds only when M is a natural number, and when M = 0, F (N, M) = βS1τ _gate2 .

For example, in the case of N = 10000, α = 125, β = 100, M = 3, S ₁ = 1, S ₂ = 22 is adopted from the following.

When M = 0, F (10000,0) = (10 6) τ gate2,
When _{M = 1, S 1 = 10} 1, S 2 = 10 3, F (10000,1) = (2125) τ gate2,
When _{M = 2, S 1 = 10} 0, S 2 = 10 2, F (10000,2) = (550) τ gate2,
When _{M = 3, S 1 = 10} 0, S 2 = 22, F (10000,3) = (541) τ gate2,
When _{M = 4, S 1 = 10} 0, S 2 = 10 1, F (10000,4) = (640) τ gate2,

For example, in the case of N = 100, α = 125, β = 100, M = 1, S ₁ = 1, S ₂ = 100 is adopted from the following.

When M = 0, F (10000,0) = (10 4) τ gate2,
When _{M = 1, S 1 = 10} 0, S 2 = 10 2, F (10000,1) = (325) τ gate2,
When _{M = 2, S 1 = 10} 0, S 2 = 10 1, F (10000,2) = (370) τ gate2.

[Embodiment 4]
Next, the optical arithmetic unit according to the fourth embodiment of the present invention will be described with reference to FIG. 7. In the fourth embodiment, a plurality of arithmetic units 101a of k = 1st stage, which are cascade-connected in multiple stages, are composed of arithmetic elements 102d in which a 2-input 2-output Mach-Zehnder interferometer is serially connected in two stages. In this configuration, the electrical control input to the Mach-Zehnder interferometer in the front stage of the arithmetic element 102d is X _i, and the electrical control input to the Mach-Zehnder interferometer in the rear stage is Y _i . The calculation unit 101 of the second and subsequent stages of k = is composed of the same calculation element 102b and conversion element 103b as in the second embodiment described above. In the fourth embodiment, the operation of the composite function XOR-OR is performed.

In the first stage of k = 1 of this configuration, the element corresponding to the conversion element 103c in the third embodiment is unnecessary, and the optical signal output from the arithmetic unit 101a is generated by the serially connected N arithmetic elements 102d. For each input signal x (N-digit binary signal of _{x 1 to x N ) and input signal y (N-digit binary signal of y 1 to y N} ), the calculation result of XOR in each digit is calculated in all digits. As a result of taking OR in, it becomes 0 when all digits match, and 1 when it does not. That is, the operation of the composite function XOR-OR can be performed only in the first stage of k = (M = 1).

However, the output of only the first stage of k = (M = 1) is expressed as OR _M (A ₁ , ..., _AN ), A _j = XOR (X _j , Y _j ). _{An electronic signal (X j} , Y _j ) is input to the 2 input terminals of the arithmetic element 102d in which two Mach-Zehnder interferometers are serially connected, and the signal from the port on the cross side with the light source connected to 102d is output. By executing A _j = XOR (X _j , Y _j ) and connecting the output signal from 102d in the previous stage to an input port different from the port to which the light source is connected, OR _M (A ₁ , ..., A) _{Execute N} ). Since this OR _M is realized by using a Mach-Zehnder interferometer, the structure is generally larger than that of the OR by the arithmetic element 102b in the second embodiment, and the delay in the OR arithmetic is large.

In order to solve this problem, we consider adopting a cascade connection for the OR operation part. That is, in the equation (2), the first stage of k = is composed of the OR _{M having a large τ gate} , and the second stage of k ≧ is composed of the OR by the arithmetic unit 101 in the second embodiment having a small _{τ gate.} In this case, equation (3) is rewritten to equation (14). Here, S ₁ , τ _gate 1 is k = the number of serial connection stages of the first stage and one arithmetic element 102d propagation delay, and S ₂ , τ _gate 2 is k = the number of serial connection stages of the second and subsequent stages and propagation of one arithmetic element 102. Delay, L is k = total number of inputs to the second stage, and M is k = number of cascade stages after the second stage. However, in equation (14), it holds only when M is a natural number, and when M = 0, F (N, M) = βS ₁ τ _{gate 2} .

The other configurations are the same as those in the third embodiment described above, and the description thereof will be omitted.

The result of inverting 0 and 1 of the output of XNOR-AND of the third embodiment is the same as the output result of the XOR-OR of the fourth embodiment. Further, there are cases where a circuit having a higher speed can be mounted by the multi-input OR in the second embodiment than by the multi-input AND in the first embodiment. For example, in the second embodiment, the serially connected arithmetic element 102b is connected to the conversion element 103b, but the parallel connected arithmetic element 102b can be connected to the conversion element 103b to obtain the same effect as that of the second embodiment. ..

In this case, since the outputs from the plurality of conversion elements 102b are collectively connected to the conversion element 103b, the configuration of the calculation unit 101 becomes large, but since the operations of the operator 102b are processed in parallel, they are connected serially. The delay may be smaller than. That is, the calculation using the XOR-OR of the fourth embodiment instead of the XNOR-AND of the third embodiment may be faster. Since multi-bit pattern matching can be implemented by using XNOR-AND or XOR-OR, it is possible to select a circuit configuration that meets the needs.

By the way, in the calculation unit of the first stage of k = in the present embodiment, (a) of FIG. 8 is serially connected to the configuration of (c) of FIG. Here, (a) of FIG. 8 shows the configuration of a two-input, two-output arithmetic element, and the output port is switched when X _i and Y _{i match and when they do not match the electric control signals X i} and Y _i. Any arithmetic element may be used. In the configuration of FIG. 8C, a light source is connected to one of the input ports of the arithmetic element in the first stage, _{and the output port when X i} and Y _i do not match (XOR) is the input port of the arithmetic element in the next stage. And connect the light source to the input port on the opposite side of the port used for this connection [Explanation 1]. As a result, the XOR-OR operation can be realized only in the first stage of k = (M = 1). Further, it is clear that the XOR-OR operation with a smaller delay can be obtained by configuring the second and subsequent stages of k = in the fourth embodiment.

Further, if the calculation unit in the first stage of k = in this embodiment is changed to a configuration in which FIG. 8A is serially connected to the configuration shown in FIG. 8D, the XNOR-AND calculation becomes possible. Here, in FIG. 8D, a light source is connected to one of the input ports of the first-stage arithmetic element, _{and the output port when X i} and Y _i match (XNOR) is connected to the input port of the next-stage arithmetic element. [Explanation 2]. As a result, the XNOR-AND operation can be realized only in the first stage of k = (M = 1). Further, it is clear that the XNOR-AND operation with a smaller delay can be obtained by configuring the second and subsequent stages of k = in the third embodiment.

Here, FIG. 8A is composed of a combination of two 2-input 2-output Mach-Zehnder interferometers, and the electric control signals X _i and Y _{i are attached to one arm of each Mach-Zehnder interferometer.} give. The arm on the side to which the electric control signal is given is set to shift the phase of the light propagating there by π, and in the case of this configuration in which one of the two arms is electrically controlled, Mach with 2 inputs and 2 outputs. -The Zehnder interferometer outputs an optical signal from the bar side / cross side output port to the input port to which the light source is connected when there is / does not have an electric control input. As a result, the arithmetic element of FIG. 8A outputs XOR (X _i , Y _{i ) from the output port on the cross side of the light source, and outputs X NOR (X i} , Y _i ) from the bar port opposite to the light source.

_{Therefore, the function of the arithmetic element shown in FIG. 8 (a) is that the electric control signals X i} and Y _i are attached to both arms of the one 2-input 2-output Mach-Zehnder interferometer 102e shown in FIG. 8 (b). It can also be realized by giving. That is, the phase difference becomes π when an electric control signal is given to one arm, and the phase difference becomes zero when an electric signal is given to both arms or not given to both arms. To do. At this time, the positional relationship between XNOR and XOR in the output port is opposite to that in FIG. 8 (a), but according to the above-mentioned [Explanation 1] and [Explanation 2], the XOR output port is set to the next during the XOR-OR operation. It may be connected to the stage, and the output port of XNOR may be connected to the next stage at the time of XNOR-AND operation. Since the element length (element length) shown in FIG. 8 (b) is half the element length shown in FIG. 8 (a), the configuration shown in FIG. 8 (a) is shown in FIG. 8 (b). A smaller calculation delay can be obtained by substituting with the configuration shown in.

Further, the 2-input 2-output Mach-Zehnder interferometer used in FIG. 8A can be replaced with a 2-input 2-output directional coupler. That is, the coupling state of the directional coupler with 2 inputs and 2 outputs is controlled by the electric control signal, and the optical signal is output from the output port on the cross side with respect to the port to which the optical signal is input. Switches the state in which an optical signal is output from the output port on the bar side to the port where is input. Since the directional coupler can be smaller in size than the Mach-Zehnder interferometer, this alternative can result in a smaller computational delay.

Further, the 2-input 2-output Mach-Zehnder interferometer used in FIG. 8A can be replaced with a 2-input 2-output XOR and XNOR arithmetic element (Non-Patent Document 3) using a ring resonator or the like. .. That is, in a 2-input 2-output arithmetic element in which two waveguides are coupled via a ring resonator, the resonance state of the resonator is controlled by an electric control signal, and the optical signal is input to the port. The resonance state in which the optical signal is output from the output port on the cross side and the non-resonant state in which the optical signal is output from the output port on the bar side with respect to the port to which the optical signal is input are switched. Since ring resonators can be smaller in size than Mach-Zehnder interferometers, this alternative allows for smaller computational delays.

As described above, a plurality of S (S is a natural number) arithmetic elements that output one optical signal with respect to the input signal are serially connected, and one optical signal is arithmetically output by the S input signals. Since the arithmetic units of are connected in cascade, optical arithmetic can be performed at higher speed.

The present invention is not limited to the embodiments described above, and many modifications and combinations can be carried out by a person having ordinary knowledge in the art within the technical idea of the present invention. That is clear.

101 ... arithmetic unit, 102 ... arithmetic element, 103 ... conversion element.

Claims (5)

A plurality of S (S is a natural number of 2 or more ) arithmetic elements that output one optical signal with respect to the input signal are serially connected to each other, and one optical signal is arithmetically output by the S input signals. Equipped with a calculation unit of
The plurality of arithmetic units are cascade-connected and
An optical arithmetic unit characterized in that signals output from S arithmetic units in the previous stage are input to one arithmetic unit in the latter stage. In the optical arithmetic unit according to claim 1,
The input signal is an electric signal and
An optical arithmetic unit characterized in that each of the plurality of arithmetic units includes a conversion element that photoelectrically converts an optical signal output from the arithmetic element in the final stage connected serially. In the optical arithmetic unit according to claim 1,
The input signal is an optical signal and
Each of the plurality of arithmetic units outputs a value 1 when an optical signal is output from the S arithmetic elements, and outputs a value 0 except when an optical signal is output from the S arithmetic elements. An optical arithmetic unit characterized by being provided with a conversion element. In the optical arithmetic unit according to claim 2 or 3,
The number S of stages M and the operation elements of the cascade connection, the number N of the input signal, and operation time tau _Gate in the calculation device, and a processing time tau _OEO in the conversion element, S number of the processing elements Find the real values S and M when the formula (A) showing the calculation delay time is the minimum value, convert the obtained real values S and M into natural numbers, and substitute the naturalized values into F (S) again. An optical calculator characterized in that it is determined as S and M when indicating a smaller calculation delay time.

In the optical arithmetic unit according to claim 1,
In the plurality of arithmetic units in the first stage, the arithmetic element is composed of a Mach-Zehnder interferometer.
The arithmetic device in the plurality of operation portions of the second and subsequent stages, optical arithmetic unit and outputting one optical signal to one of said input signal is an electrical signal.

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