JP6860722B2 - Memory system control method - Google Patents

Description

The present embodiment relates to a method of controlling a memory system.

Conventionally, a memory system using a NAND flash memory as a storage medium is known. The capacity of the storage medium mounted on the memory system tends to increase.

Japanese Unexamined Patent Publication No. 2009-21216

One embodiment provides a highly convenient memory system.

According to one embodiment, the control method of the memory system is to manage the translation information indicating the correspondence between the logical position information and the physical position information, and the first memory transfers the first translation information and the second translation information. The present invention includes storing the first translation information and the second translation information in the same page, which is to store the plurality of pages in the first area. Logical position information is logical position information associated with data. The physical position information is physical position information indicating a position in the first memory in which data is stored. The translation information is hierarchized into a plurality of layers, and includes a first translation information belonging to the first layer and a second translation information belonging to the second layer. The size of the first translation information and the size of the second translation information are equal. Each page is a writing unit to the first memory.

FIG. 1 is a diagram showing an example of a configuration of a memory system according to the first embodiment. FIG. 2 is a diagram schematically showing a data processing unit and a minimum position management unit in the NAND memory according to the first embodiment. FIG. 3 is a diagram showing various information held in the memory system. FIG. 4 is a diagram illustrating an example of the configuration of various tables. FIG. 5 is a diagram illustrating an effective bitmap. FIG. 6 is a diagram for explaining block management information. FIG. 7 is a diagram showing an example of the storage mode of the second table, the third table, and the effective bitmap. FIG. 8 is a diagram showing a structure of cache management information. FIG. 9 is a diagram showing a configuration of a control unit according to the second embodiment. FIG. 10 is a diagram showing the configuration of the RAM of the second embodiment. FIG. 11 is a diagram showing the configuration of the RAM of the third embodiment. FIG. 12 is a diagram showing the configuration of the RAM of the fourth embodiment. FIG. 13 is a diagram illustrating changes in the storage mode of each first table. FIG. 14 is a diagram illustrating changes in the storage mode of each first table. FIG. 15 is a diagram illustrating changes in the storage mode of each first table. FIG. 16 is a diagram illustrating changes in the storage mode of each first table. FIG. 17 is a diagram illustrating changes in the storage mode of each first table. FIG. 18 is a diagram illustrating changes in the storage mode of each first table. FIG. 19 is a diagram illustrating changes in the storage mode of each first table. FIG. 20 is a diagram showing a log storage area of the fifth embodiment. FIG. 21 is a diagram showing an implementation example of a memory system.

The memory system according to the embodiment will be described in detail with reference to the accompanying drawings. The present invention is not limited to these embodiments.

(First Embodiment)
FIG. 1 is a diagram showing an example of a configuration of a memory system according to the first embodiment. The memory system 1 is, for example, an SSD (Solid State Drive). In the following, a case where a NAND type flash memory (hereinafter referred to as NAND memory) is used as the non-volatile memory will be described as an example.

The memory system 1 is configured to be connectable to the host 2. For example, a CPU (Central Processing Unit), a personal computer, a portable information device, a server, etc. correspond to the host 2. Any interface standard can be adopted as the interface standard for communication between the memory system 1 and the host 2. Two or more hosts 2 may be connected to the memory system 1 at the same time. The host 2 and the memory system 1 may be connected via a network.

The memory system 1 transmits / receives data to / from the host 2 in response to an access command from the host 2. Access commands include write commands and read commands. The access command includes location information that logically indicates the access location. For example, LBA (Logical Block Address) can be adopted as the logical position information. Further, for example, when NVMe is adopted as an interface standard for communication between the memory system 1 and the host 2, the logical position information logically indicates the identification information of the namespace and the position in the namespace. The address (eg, LBA) may be included. The namespace is a logical address space specified by the identification information of the namespace. That is, when NVMe is adopted, the memory system 1 can manage a plurality of logical address spaces. Hereinafter, the logical position information included in the access command is referred to as a logical address.

The memory system 1 includes a host interface unit 11, a NAND memory 12, a NAND controller 13, a RAM (Random Access Memory) 14, and a control unit 15.

The control unit 15 includes, for example, one or more processors. The control unit 15 executes control of the memory system 1 by executing a program stored in a predetermined position in the memory system 1 in advance. The storage position of the program is arbitrarily designed. For example, the program is stored in the NAND memory 12 in advance and loaded into the RAM 14 at startup. The control unit 15 executes the program loaded in the RAM 14. The control of the memory system 1 is composed of a plurality of processes. A part or all of the plurality of processes executed by the control unit 15 may be realized by a hardware circuit. Further, the control unit 15 may be configured by a control circuit which is a hardware circuit. Each process executed by the control unit 15 will be described later.

The host interface unit 11 is an interface device for the memory system 1 to communicate with the host 2. For example, the host interface unit 11 transfers user data between the host 2 and the RAM 14 under the control of the control unit 15.

The NAND controller 13 is an interface device for accessing the NAND memory 12. The NAND controller 13 executes the transfer of user data or management information between the RAM 14 and the NAND memory 12 under the control of the control unit 15. Although details are omitted, the NAND controller 13 can perform error correction processing.

The NAND memory 12 is a non-volatile storage medium that functions as storage. The NAND memory 12 is composed of one or more chips.

FIG. 2 is a diagram schematically showing a data processing unit and a minimum position management unit in the NAND memory 12 in the first embodiment. Inside the chip that constitutes the NAND memory 12, the data storage area is composed of a plurality of blocks. Each block is composed of a plurality of pages. A page is a unit that can be accessed by write and read. A block is the smallest unit in which data can be erased all at once. In the example of FIG. 2, one block is composed of n (n is a natural number) pages.

Physical location information (physical address) is assigned to units smaller than one page. Here, the unit to which the physical address is assigned is referred to as a cluster. The size of one cluster may be equal to or different from the minimum unit of access from host 2.

The RAM 14 is a storage medium for temporarily storing data. As the RAM 14, for example, a storage medium of a type faster than the NAND memory 12 can be adopted. As the RAM 14, for example, a volatile or non-volatile storage medium can be adopted. As the RAM 14, for example, DRAM (Dynamic RAM), SRAM (Static RAM), FeRAM (Ferroelectric RAM), MRAM (Magnetoresistive RAM), PRAM (Phase change RAM) and the like can be adopted.

FIG. 3 is a diagram showing various information held in the memory system 1. An emergency evacuation area 121, a management information area 122, and a user data area 123 are secured in the NAND memory 12. A log storage area 124 is secured in the management information area 122.

One or more user data 301s are stored in the user data area 123. Each user data 301 is data requested to be written by the host 2. It is assumed that each user data 301 has the same size as the size of one cluster.

A write buffer 141, a read buffer 142, and a cache area 143 are reserved in the RAM 14.

The write buffer 141 and the read buffer 142 are buffers for data transfer between the host 2 and the NAND memory 12. Specifically, the write buffer 141 stores user data received from the host 2 by the host interface unit 11. The user data stored in the write buffer 141 is written to the user data area 123 by the NAND controller 13. The read buffer 142 stores the user data 301 read from the user data area 123 by the NAND controller 13. The user data 301 stored in the read buffer 142 is transferred to the host 2 by the host interface unit 11.

The management information area 122 is an area for storing information (management information) for management of the memory system 1 in a non-volatile state. Management information includes translation information, valid information, and statistical information 225.

The translation information is information for associating a logical address with a physical address. Since the logical address is associated with the physical address by the translation information, the host 2 can read the user data 301 stored at the position indicated by the physical address corresponding to the logical address by using the logical address. The storage positions of the plurality of user data 301 stored in the user data area 123 are indicated by any physical address associated with the logical address by the translation information, or are associated with the logical address by the translation information. Not indicated by any physical address. The user data 301 stored at the position indicated by the former physical address can be read by the host 2. The user data 301 stored at the position indicated by the latter physical address cannot be read by the host 2.

The control unit 15 stores the first user data 301 at the first position in the user data area 123. After that, when the user data 301 requested to be written together with the designation of the same logical address as the logical address specified at the time of writing the first user data 301 is requested to be written by the host 2, the control unit 15 performs the write request. The write-requested user data 301 is stored in the user data area 123 at a position different from the first position. The control unit 15 is a second user who is the latest user data 301 of the user data 301 requested to be written together with the designation of the same logical address as the logical address specified at the time of writing the first user data 301. The state of the data 301 is managed as a valid state. Further, the control unit 15 is among the user data 301 for which writing is requested together with the designation of the same logical address as the logical address specified at the time of writing the first user data 301 and the first user data 301. , The state of the user data 301 other than the second user data 301 is managed as an invalid state. Note that the latest means that the message was received from the host 2 by the last write request (excluding the atomic write write request described later) among the write requests for which the same logical address is specified. The control unit 15 associates the logical address with the physical address indicating the storage position of the second user data 301 instead of the first user data 301. In other words, the physical address indicating the storage position of the valid user data 301 is associated with a certain logical address by the translation information. Further, the physical address indicating the storage position of the invalid user data 301 is not associated with any logical address by the translation information.

In recent years, the size of translation information tends to increase as the notation capacity of the memory system 1 increases. The notation capacity refers to the total size of the logical address space provided to the outside by the memory system 1. In order to manage a huge size of translation information, the translation information is hierarchized into a plurality of layers. Each of the translation information of the plurality of layers has a different size of the range of logical addresses covered by the recorded correspondence. The size of the range of logical addresses covered by the correspondence recorded in the translation information belonging to the upper hierarchy is larger than the size of the range of logical addresses covered by the correspondence recorded in the translation information belonging to the lower hierarchy. In other words, the granularity of the recorded correspondence is finer in the translation information belonging to the lower hierarchy than in the translation information belonging to the upper hierarchy. Since the number of records in the translation information belonging to the lower hierarchy is larger than that in the translation information belonging to the upper hierarchy, the translation information belonging to the lower hierarchy is divided into smaller pieces than the translation information belonging to the higher hierarchy. Multiple translation information belonging to the same hierarchy have the same size of the range of logical addresses covered by the recorded correspondence.

The storage position of the translation information belonging to one hierarchy is indicated by the translation information belonging to one hierarchy higher than the translation information belonging to the one hierarchy. To be shown means that they are linked by, for example, a pointer. For example, the translation information belonging to the highest layer is read into the RAM 14 and used on the RAM 14. Use is a reference or modification. The translation information belonging to the hierarchy other than the highest hierarchy is appropriately read from the NAND memory 12 into the RAM 14 and used on the RAM 14. In order to improve the efficiency of writing to the NAND memory 12, there is a demand for reducing the size of the unit to be read into the RAM 14. Further, there is a request to reduce the size of the area in the RAM 14 that stores the translation information belonging to the highest layer. In order to meet these demands, the translation information is layered into three or more layers. In the first embodiment, as an example, the translation information is hierarchized into three layers.

The management information area 122 stores the first table 201a, which is translation information belonging to the highest hierarchy. In the log storage area 124 in the management information area 122, the second table 202a, which is the translation information belonging to the second layer, and the third table 203a, which is the translation information belonging to the third layer, are stored.

FIG. 4 is a diagram illustrating an example of the configuration of various tables. The logical address space of the memory system 1 is divided into a plurality of subspaces (first space). Further, each first space is divided into a plurality of subspaces (second spaces). Each second space is divided into a plurality of third spaces. The size of each third space is equal to the size of one cluster.

One third table 203a includes a record for each third space included in one second space. Each record constituting one second table 202a associates a logical address with an address information (data address) indicating a position in which the user data 301 indicated by the logical address is stored. The data address is represented by, for example, a physical address. When the user data 301 corresponding to a certain third space is not stored in the memory system 1, for example, a null value is recorded in the record corresponding to the third space.

The first table 201a includes a record for each first space. Each record in the first table 201a indicates a position where the second table 202a is stored. In each record of the first table 201a, the position where the second table 202a is stored is indicated, for example, in the form of a physical address.

The second table 202a includes a record for each second space. Each record in the second table 202a indicates a position where the third table 203a is stored. In each record of the second table 202a, the position where the third table 203a is stored is indicated, for example, in the form of a physical address.

The valid information is information that records whether each user data 301 is valid or invalid. Here, as an example, the valid information is hierarchized into two layers, the block management information 211a which is the effective information belonging to the first layer and the effective bitmap 212a which is the effective information belonging to the second layer.

FIG. 5 is a diagram illustrating an effective bitmap 212a. The valid bitmap 212a is bitmap information that collects flags that describe whether the user data 301 is valid or invalid. The range corresponding to one flag is arbitrarily designed. According to the example of FIG. 5, in each valid bitmap 212a, a 1-bit flag indicating whether it is valid or invalid is recorded for each page. Each valid bitmap 212a records flags for a plurality of pages having consecutive physical addresses. The valid bitmap 212a is stored in the log storage area 124.

FIG. 6 is a diagram for explaining the block management information 211a. Each flag recorded in each valid bitmap 212a is associated with a physical address. Specifically, the block management information 211a indicates a position where the corresponding block management information 211a is stored for each physical address space composed of pages of the number of flags recorded in one valid bitmap 212a. .. The block management information 211a is stored in the management information area 122.

FIG. 7 is a diagram showing an example of the storage mode of the second table 202a, the third table 203a, and the effective bitmap 212a. In the first embodiment, the size of the first space and the size of the second space are determined so that the size of one second table 202a and the size of one third table 203a are equal to each other. .. Further, in the first embodiment, one effective bit so that the size of one second table 202a, the size of one third table 203a, and the size of one effective bitmap 212a are equal to each other. The number of flags recorded on the map 212a is fixed. The size of one second table 202a means the size of the one second table 202a itself as data. The size of one third table 203a means the size of the one third table 203a itself as data. The size of one effective bitmap 212a means the size of the one effective bitmap 212a itself as data. As a result, the log storage area 124 can store the second table 202a, the third table 203a, and the effective bitmap 212a in a mixed manner.

Specifically, it is possible to store a plurality of different unit information on one page. The unit information is the second table 202a, the third table 203a, or the effective bitmap 212a. In addition, the number of unit information recorded per page can always be constant. Moreover, since the size of each unit information is the same, it is easy to manage the position of the boundary between the unit information. The size information of the unit information can be unnecessary for specifying the unit information. In the example of FIG. 7, six unit information is stored on one page.

Each unit information is read into the cache area 143 when it is used. In other words, each unit information is cached in the cache area 143. Use is a reference or modification. The second table 202a existing in the cache area 143 is referred to as the second table 202b. The third table 203a existing in the cache area 143 is referred to as the third table 203b. The effective bitmap 212a existing in the cache area 143 is referred to as an effective bitmap 212b.

The unit information cached in the cache area 143 changes to a state different from the unit information stored in the log storage area 124 due to the change by the control unit 15. The state of the unit information cached in the cache area 143, which is different from the unit information stored in the log storage area 124, is referred to as dirty. The dirty unit information is written back to the log storage area 124 at a predetermined timing. Dirty unit information is written to the log storage area 124 to transition to a non-dirty state.

The first table 201a is read into the RAM 14 and used on the RAM 14. The first table 201a read into the RAM 14 is referred to as the first table 201b. The block management information 211a is read into the RAM 14 and used on the RAM 14. The block management information 211a read into the RAM 14 is referred to as block management information 211b. The first table 201b and the block management information 211b stored in the RAM 14 are used by the control unit 15, respectively, and are copied to the management information area 122 at a predetermined timing of the memory system 1.

Each record of the first table 201b stored in the RAM 14 further indicates the position where the corresponding second table 202b is cached when the corresponding second table 202b is cached in the cache area 143. .. Further, in each record of the second table 202b cached in the cache area 143, when the corresponding third table 203b is cached in the cache area 143, the corresponding third table 203b is cached. The position is further indicated. Further, in each record of the third table 203b cached in the cache area 143, when the corresponding user data is stored in the write buffer 141, the corresponding user data is stored in the write buffer 141. Indicates the position.

Each record of the block management information 211b stored in the RAM 14 further indicates the position where the corresponding valid bitmap 212b is cached when the corresponding valid bitmap 212b is cached in the cache area 143. ..

Dirty unit information is managed by cache management information 221.

FIG. 8 is a diagram showing the configuration of cache management information 221. The cache management information 221 is information for managing the cache area 143. The cache management information 221 is stored in, for example, RAM 14, and is used on RAM 14. The cache management information 221 includes user dirty information 222, GC dirty information 223, and free information 224. The user dirty information 222 is information indicating the second table 202b and the third table 203b that have become dirty in response to the writing of the user data 301 from the write buffer 141 to the user data area 123. The user dirty information 222 may be configured to further indicate a valid bitmap 212b that has become dirty in response to the writing of the user data 301 from the write buffer 141 to the user data area 123. The GC dirty information 223 is information indicating the second table 202b and the third table 203b that have become dirty due to garbage collection. The GC dirty information 223 may be configured to further indicate the valid bitmap 212b that has been made dirty by garbage collection. Free information 224 is information indicating an unused cache line. For example, one unit information is cached in one cache line. The user dirty information 222 and the GC dirty information 223 indicate dirty unit information in a state in which the order in which they become dirty can be recognized. For example, user dirty information 222 and GC dirty information 223 include a linked list data structure. The free information 224 indicates the order in which the unused cache lines are not used in a recognizable state. For example, free information 224 comprises a linked list data structure.

Dirty / non-dirty management is also executed for the first table 201b and the block management information 211b. For example, the first table 201b is treated as dirty when different from the first table 201a. For example, among the plurality of records constituting the first table 201b, records different from the corresponding records among the plurality of records constituting the first table 201a may be managed as dirty. Further, for example, the block management information 211b may be managed as dirty when different from the block management information 211a. Further, for example, only the records different from the corresponding records among the plurality of records constituting the block management information 211a among the plurality of records constituting the block management information 211b may be managed as dirty. In the first table 201b, for example, when the number of dirty records exceeds a predetermined number, the first table 201b at that time is written in the management information area 122 as the first table 201a. As for the block management information 211b, for example, when the number of dirty records exceeds a predetermined number, the block management information 211b at that time is written in the management information area 122 as the block management information 211a. The state of each record of the first table 201b and the block management information 211b transitions to non-dirty in response to writing to the management information area 122.

Statistical information 225 is various information indicating an operating state. For example, the statistical information 225 includes the usage status of the NAND memory 12, the usage status of the memory system 1, the power-on time, the number of times dirty information is lost due to the power failure, the number of operations of the power loss protection (PLP), and the normal power failure. The number of occurrences of, etc. are included. A normal power outage here means a power outage in which no dirty information loss has occurred. The PLP is a process in which the control unit 15 stores at least dirty translation information in the RAM 14 in the emergency evacuation area 121 when the power supply from the outside is suddenly stopped. In PLP, the user data in the write buffer 141 is also the target of storage. In the PLP, the control unit 15 may dump the memory image in the RAM 14 to the emergency evacuation area 121 as it is. The PLP is executed using the electric power stored in the battery (not shown) built in the memory system 1. The control unit 15 generates statistical information 225 in RAM 14, and periodically dumps the generated statistical information 225 to the management information area 122.

In the user data area 123, one or more log information 231 is stored in addition to the user data 301 by the control unit 15. The log information 231 is information recorded in association with the user data 301 when the user data 301 is written to the user data area 123. The log information 231 corresponds to a logical address indicating the position of the corresponding user data 301 and a physical address (former physical address) associated with the logical address before writing the corresponding user data 301. At least a physical address (new physical address) indicating the position of the writing destination of the user data 301 is recorded.

Next, each process executed by the control unit 15 will be described.

(1) Basic operation The processing executed by the control unit 15 is roughly classified into a startup processing, a command waiting processing, a command execution processing, and a restart waiting processing.

(1-1) Process at startup The control unit 15 executes an initialization operation as a scheduler at startup. After that, the control unit 15 registers any of the following processes (first to third startup processes) in the scheduler. The control unit 15 executes the registered startup process according to the instruction of the scheduler.

(1-1-1) First Startup Process When dirty unit information is lost due to a power failure, the first startup process is executed. The first startup process is a process of reconstructing translation information. Reconstruction involves recovering lost dirty unit information. Reconstruction can be performed by referencing the log information 231 in the write order or in the reverse order of the write order.

(1-1-2) Second Startup Process When various information is stored in the emergency evacuation area 121 by PLP or the like at the power failure immediately before, the second startup process is executed. The second startup process is a process of restoring the memory image of the RAM 14 by using various information stored in the emergency evacuation area 121.

(1-1-3) Third startup process When all the dirty unit information is normally written to the management information area 122 and the state transitions to the non-dirty state when the power is turned off, the third startup process is performed. The process is executed. The third startup process is a process of reading the first table 201a into the RAM 14 as the first table 201b.

(1-2) Command standby processing The control unit 15 executes processing as an interrupt handler. In response to the command from host 2, the interrupt handler registers the corresponding process in the scheduler. The command is transmitted when the scheduler executes the corresponding process. The command execution is also started when the interrupt handler inside the memory system 1 registers the corresponding process in the scheduler. If there is no executable command, the control unit 15 may shift the state of the memory system 1 to the sleep state. Even when the memory system 1 is in the sleep state, the control unit 15 may execute the timer interrupt. The control unit 15 shifts the state of the memory system 1 from the sleep state to the normal state by a timer interrupt.

(1-3) Command execution processing (1-3-1) Host command queue processing The host command queue processing is implemented in the control unit 15 as an interrupt handler, for example. The command from host 2 is notified by an interrupt. The host command queue process includes a process of analyzing a command from host 2 and a process of registering the command in a command queue (not shown) waiting for issuance. The issue-waiting command queue is, for example, a ring-type queue. In the host command queue processing, the control unit 15 can only register the command queue waiting to be issued. The number of commands waiting to be issued in the command queue waiting to be issued can be calculated by comparing the position information on the registration side with the position information on the issuing side. In the host command queue processing, when the number of commands waiting to be issued exceeds a predetermined threshold value, the control unit 15 stops accepting commands from the host 2. In the host command queue processing, if the host 2 requests the registration of a command while the acceptance of the command from the host 2 is stopped, the control unit 15 notifies the host 2 of the acceptance refusal. When the host 2 receives the notification of acceptance refusal, the host 2 re-requests the registration of the command after a predetermined time has elapsed. If the command reception is not stopped at the time of re-request, the control unit 15 receives the command in the host command queue processing. The difference between the number of commands waiting to be issued in the command queue waiting to be issued and the predetermined threshold value indicates the number of commands that can be accepted. The control unit 15 may send the number of commands that can be accepted in the host command queue processing to the host 2 as status information. Whether to use the notification of acceptance refusal or the notification of the number of commands that can be accepted is set by the agreement with the host 2. In the host command queue processing, the control unit 15 registers the host command issuing process in the execution waiting queue (not shown) of the scheduler, and ends the host command queue processing. Each of the registered commands is managed together with information indicating the execution status (unexecuted status, running status, end waiting status).

(1-3-2) Host command issuance process After receiving a command from host 2, an execution request for host command issuance process is registered in the scheduler at the end of the command or by a timer interrupt or the like. In the host command issuance process, the control unit 15 transitions the state of the command whose execution request is registered in the scheduler to the executing state. Further, when the execution of the command is completed, for example, when the data transfer is completed, the control unit 15 shifts the state of the command to the end waiting state. After that, upon receiving the execution end confirmation from the host 2, the control unit 15 deletes the command from the command queue waiting to be issued. The control unit 15 starts executing a command in the unexecuted state.

(1-3-3) Read processing The read processing is a process of analyzing a command, a process of accessing translation information, a process of reading user data 301 from the NAND memory 12, and a process of reading the user data 301 read from the NAND memory 12. It includes a process of storing in the buffer 142, a process of transmitting the user data 301 stored in the read buffer 142 to the host 2, and a process of notifying the host 2 of the end of command execution. In the read process, the control unit 15 notifies the host command issuance process of the end of the command after the host 2 confirms the end of the command execution.

(1-3-4) Write processing The write processing is a process of analyzing a command, a process of notifying the host 2 of command execution, a process of storing user data from the host 2 in the write buffer 141, and a user in the write buffer 141. It includes a process of updating translation information according to data storage and a process of notifying host 2 of the end of command execution. When the write command includes the designation of the FUA mode, in the write process, the control unit 15 performs a process of storing the user data stored in the write buffer 141 in the NAND memory 12 and a user in the NAND memory 12. Further, the process of updating the translation information according to the storage of the data is executed. In the write process, the control unit 15 notifies the host command issuance process of the end of the command after the host 2 confirms the end of the command execution.

(1-3-5) Cache Flush Process The cache flush process is a process of executing the flush of the write buffer 141 and the flush of the dirty part of the translation information. When the cache flush is notified, in the cache flush process, the control unit 15 stops issuing the next write command until the write execution flag to the write buffer 141 is set. The write execution flag is flag information indicating whether or not the user data stored in the write buffer 141 has been written to the NAND memory 12. The state in which the write execution flag is set indicates that the corresponding user data has been written to the NAND memory 12. When NVMe is adopted, the control unit 15 may execute the cache flush process independently for each namespace.

(1-3-6) Trim processing The trim processing is a processing for canceling the correspondence between the logical address and the physical address of the specified logical address. In the trim processing, the control unit 15 stops issuing a new write command and a new read command, and invalidates the corresponding record included in the translation information. If NVMe is adopted, the trim command may be configured to allow, for example, a namespace to be specified. The control unit 15 stops issuing write commands and read commands to the designated namespace in the trim processing.

(1-3-7) Emergency evacuation processing The emergency evacuation processing includes processing for discarding commands waiting to be issued and all running access commands, and all of the user data and translation information in the write buffer 141. Includes a process of storing the dirty portion of the above in the emergency evacuation area 121. If the storage of the above information is successful in the emergency evacuation process, the control unit 15 lowers the Unexpected Shutdown flag. If the storage of the above information fails in the emergency evacuation process, the control unit 15 does not lower the Unexpected Shutdown flag. The Unexpected Shutdown flag is recorded in the management information area 122 of the NAND memory 12, for example. At the next startup, whether or not to execute the first startup process is determined based on the Unexpected Shutdown flag. When the emergency evacuation is notified, new acceptance of all commands except restart is stopped. Emergency evacuation is notified from the power supply.

(1-3-8) Sleep processing In sleep processing, all dirty parts of the user data and translation information in the write buffer 141 are urgently required after the execution of all the commands waiting to be issued and the access command being executed is completed. This is a process of storing in the save area 121. If the storage of the above information is successful in the sleep process, the control unit 15 lowers the Unexpected Shutdown flag. If the storage of the above information fails in the sleep process, the control unit 15 does not lower the Unexpected Shutdown flag. When the sleep is notified, new acceptance of all commands other than the wakeup command is stopped. The sleep is notified from the host 2.

(1-3-9) Shutdown process The shutdown process is a process of executing a cache flush process after the execution of all commands waiting to be issued is completed. When the shutdown is notified, all new commands except the restart will be stopped. Host 2 notifies the shutdown. If the flush is successful, the control unit 15 lowers the Unexpected Shutdown flag. If the flush fails, the control unit 15 does not lower the Unexpected Shutdown flag.

(1-4) Restart wait process The restart wait process is the state after the emergency evacuation process or shutdown process is completed. In the restart standby process, the control unit 15 accepts only the restart command.

(2) Restoration process of translation information The restoration process of translation information is a process of restoring the first table 201b. While the translation information restoration process is being executed, the control unit 15 does not accept the access command. Signature and Identify responses are allowed. In the process of restoring translation information, the "time" is substituted by the total number of rewrites of the system. The number of rewrites is the number of writes and erases for each block. In the process of restoring the translation information, the control unit 15 restores the latest record among the records in the first table 201b. The control unit 15 restores the unit information recorded in the log storage area 124 whose time is newer than the corresponding record in the first table 201a. When the translation information restoration process is executed in the first startup process, the following process is executed.

That is, the control unit 15 restores the corresponding record of the translation information for the block in which the user data 301 is stored and whose time is newer than the restored translation information. The control unit 15 restores the corresponding record of the translation information based on the log information 231. For a block whose time is older than the restored translation information, the control unit 15 does not restore the corresponding record of the translation information. The restored records are managed as dirty.

After the translation information is restored, the dirty part of the translation information may or may not be flushed. Whether or not the dirty part of the translation information is flushed after the translation information is restored may be set externally.

(3) Power cutoff processing There are two types of power cutoff processing: normal processing and PLP.

(3-1) Normal processing The normal processing includes a flash of user data in the write buffer 141, a flash of various dirty information, and a flash of statistical information 225. The control unit 15 lowers the Unexpected Shutdown flag after the normal processing is completed.

(3-2) PLP
The PLP includes a process of storing the user data in the write buffer 141 and various dirty information in the emergency evacuation area 121. After the end of PLP, the control unit 15 lowers the Unexpected Shutdown flag and sets the PLP flag. The PLP flag is a flag indicating that the memory system 1 has been terminated by PLP, and is recorded in, for example, the management information area 122. The statistical information 225 is stored in the emergency evacuation area 121 after the storage of the above information is completed. In PLP, retention of statistical information 225 may not be guaranteed.

(4) Operation of write processing The write processing means writing in response to a command from the host 2. There are four types of write processing: write using cache, FUA light, atomic light, and trim processing. The write using the cache finishes the processing earliest among the four types of write processing. The write using the cache is a write process that ends when the user data is stored in the write buffer 141. The FUA write is a write process that ends when the writing of user data to the NAND memory 12 is completed. While the FUA write is being executed, the user data 301 written in the NAND memory 12 cannot be read until the update of the translation information is completed. If it is necessary to read the corresponding user data 301 while the FUA write is being executed until the update of the translation information is completed, the control unit 15 reads the user data from the write buffer 141. Atomic write is a write that updates the translation information after the writing of all the user data requested to be written by a plurality of write commands is completed. According to Atomic Write, each user data cannot be read until all the user data requested to be written by a plurality of write commands has been written. The trim processing is treated as one of the light processing.

There is a cache flush command as a command incidental to the write process. The cache flush command is a command for executing the cache flush process. In the cache flush process, the control unit 15 writes the user data in the write buffer 141 to the NAND memory 12 and updates the translation information. The cache flush process can be executed for the entire memory system 1. Further, the memory system 1 may be configured so that the cache flush process is executed in a limited namespace or stream. In the memory system 1 in which the PLP can be executed, the memory system 1 may be configured so as to be able to ignore the cache flush command.

(4-1) Write Buffer Processing The write buffer 141 is a buffer having a double buffer configuration in which data is input / output according to FIFO rules. The write buffer 141 includes a write execution flag for each area of a predetermined size.

In the case of a write using a cache or an atomic write, the control unit 15 copies the user data in the write buffer 141 to the NAND memory 12 on a page-by-page basis as a predetermined amount is accumulated in the write buffer 141. In the case of FUA write, the control unit 15 copies the user data to the NAND memory 12 in page units immediately after the user data is written to the write buffer 141. In the case of the trim processing, the control unit 15 writes the trim notification itself to the write buffer 141, and copies the trim notification from the write buffer 141 to the NAND memory 12 (user data area 123 of the NAND memory 12). After copying, the control unit 15 sets a write execution flag in the copy source area. The control unit 15 can treat the area in which the write execution flag is set as a free area.

During copying to the NAND memory 12, the write buffer process does not have control of the copy source area. That is, in the write buffer process, the control unit 15 cannot write to the copy source area. For areas other than the copy source area, when another user data is sent by specifying the same logical address as the user data already stored in the write buffer 141 (rewrite), control is performed in the write buffer processing. The unit 15 overwrites the other user data with the user data already stored in the write buffer 141.

In the write buffer process, the control unit 15 can store the user data sent from the host 2 in the write buffer 141 at an arbitrary timing as long as the write buffer 141 has a free area. Except for the case of rewriting, the control unit 15 updates the translation information according to the storage of the user data in the write buffer 141. Specifically, the physical address of the storage position in the write buffer 141 is associated with the logical address indicating the position of the user data. The control unit 15 updates the translation information on the RAM 14. If the corresponding unit information does not exist in the cache area 143, the control unit 15 reads the corresponding unit information from the log storage area 124 to the cache area 143, and then updates the unit information. After updating the unit information, the control unit 15 sets the updated unit information and the unit information of the upper layer indicating the updated unit information dirty.

Detects when a cache flush command is received, when a FUA write is executed, when the target translation information is not written in the FUA read and data exists in the write buffer 141, and an idle time of a time longer than a preset time is detected. When this is done, the control unit 15 executes a copy from the write buffer 141 to the NAND memory 12. In the case of FUA write, for example, the control unit 15 copies only the user data written by the write command of FUA write from the write buffer 141 to the NAND memory 12. When copying the user data to be written to the NAND memory 12 to the NAND memory 12, the control unit 15 sends the user data to the NAND memory 12 together with the user data to be written if there is a free area on the write destination page. User data that has not yet been set for writing may be copied.

(4-2) Processing for selecting a write-destination block The control unit 15 selects a free block having as few rewrites as possible from one or more free blocks as a write-destination block. The free block means a block in which valid user data 301 is not stored. Free blocks are generated by garbage collection. The control unit 15 may randomly select a predetermined number of free blocks as candidates from two or more free blocks, and select the free block having the least number of rewrites among the selected candidates as the write destination block. Free blocks are managed in a list format (free block list) so that the order in which they are generated can be known, for example. The control unit 15 may select the oldest generated predetermined number of free blocks or the latest generated predetermined number of free blocks as candidates. The free block selected as the write destination block is set as the write destination after being erased. At the time of erasing, the control unit 15 assigns a unique sequence number in the memory system 1 to the block. The sequence number is a number indicating the order in which the erasures are executed. When writing information on the last page of one block, the control unit 15 records the sequence number of that block.

(4-3) Writing to NAND Memory 12 When writing user data from the write buffer 141 to the NAND memory 12, the control unit 15 locks the copy source area. When there is free space on the copy destination page, the control unit 15 reads data from the NAND memory 12 and combines the read data with the user data to be written, for example, in the manner of read-modify-write. And write to the copy destination page. After the writing of the user data to the NAND memory 12 is completed, if the writing is a process associated with a write using a cache or a FUA write, the control unit 15 requests an update of the translation information (hereinafter, simply an update request). Is issued. The update request includes a logical address, an address indicating a copy source in the write buffer 141, an old physical address, a new physical address, and a size of data. Regarding the trim processing, the control unit 15 issues an update request including the logical address range to be invalidated based on the trim command.

(4-4) Atomic Light In the atomic light, the control unit 15 writes the start and end of the atomic light in the user data area 123. There are two possible operations for the atomic light.

(4-4-1) The first atomic light control unit 15 queues the update request until the last write of the atomic write is confirmed. After confirming the last write of the atomic write, the control unit 15 issues the queued update request. During the update of the translation information in response to the atomic write, the control unit 15 stops reading the logical address range targeted by the atomic write. The size of the area corresponding to the atomic write is determined by the spare capacity of the memory system 1 and the amount that can queue the update request. According to the first atomic light, nesting is possible.

(4-4-2) The second atomic light control unit 15 issues an update request. The control unit 15 duplicates the unit information for which the update request has been made in the cache area 143. The control unit 15 updates the copy of the unit information during the execution of the atomic write. After confirming the last writing of the atomic write, the control unit 15 reflects the duplication of the unit information in the unit information of the duplication source. In the read operation or the write operation other than the atomic write, the control unit 15 uses the unit information of the copy source. The reflection is executed as follows. That is, the control unit 15 overwrites the non-dirty portion of the copy of the unit information from the unit information of the copy source to the copy of the unit information. Then, the control unit 15 updates the table address recorded in the higher-level translation information so as to indicate the duplication of the unit information. The size of the area corresponding to the second atomic write is determined by the amount that can store a copy of the unit information in the cache area 143 and the spare capacity of the memory system 1. According to the second atomic light, the update of the translation information can be completed earlier than that of the first atomic light, which needs to execute a plurality of update requests sequentially. That is, the period for stopping reading can be shortened. When a plurality of atomic lights are executed, the control unit 15 generates a copy of the unit information for each atomic light.

(4-5) Translation Information Update Processing When the control unit 15 receives the update request, the control unit 15 checks the update timing of the translation information. The control unit 15 queues the update request until the timing at which the translation information can be updated. The control unit 15 may queue the update request for each stream, for example. After updating the translation information, the control unit 15 releases the write buffer 141.

(4-6) Trimming process In the trim processing, the control unit 15 records the received trim command in the user data area 123. The smallest unit written to the user data area 123 can accommodate a plurality of trim commands. After recording the trim command, the control unit 15 updates the translation information and updates the corresponding valid information. When all the records of the unit information are invalidated, the control unit 15 invalidates the record of the higher translation information indicating the unit information in which all the records are invalidated.

(5) Garbage collection Garbage collection refers to a process of copying valid user data 301 included in one block to another block and then invalidating all user data 301 stored in the one block. A block in which all the user data 301 stored internally is invalidated by garbage collection is managed as a free block.

(5-1) Selection of Garbage Collection Target Block The control unit 15 selects a garbage collection target block from one or more blocks that store valid user data 301. The block targeted for garbage collection is referred to as a GC block. The method of selecting the GC block affects the delay time and the write amplification. The control unit 15 selects the GC block by, for example, the following method.

For example, the control unit 15 selects the block having the largest number of stored invalid user data 301 as the GC block. According to this selection method, the writing magnification can be reduced. The control unit 15 may be configured to select the GC block by this selection method when the free block is almost exhausted.

For example, the control unit 15 selects a GC block from the blocks in which the number of invalid user data 301 stored exceeds a predetermined threshold value. The control unit 15 may be configured to select the GC block by this selection method when the free block is almost exhausted. The control unit 15 may change the threshold value according to the number of free blocks.

For example, the control unit 15 classifies a block having a long elapsed time after being rewritten and a block having a short elapsed time from being rewritten, and among the blocks having a long elapsed time since being rewritten, invalid user data. The block in which 301 is stored is selected as the GC block. The control unit 15 may be configured to select the GC block by this selection method during the idle time.

(5-2) Determination of GC ratio The control unit 15 updates the GC ratio after selecting the GC block. The GC ratio is a set value of the ratio of the copy amount by garbage collection to the write amount of user data to the NAND memory 12. The control unit 15 sets the GC ratio as a numerical value obtained by dividing the number of valid user data 301 in the block by the number of invalid user data 301 in the block. After that, the control unit 15 updates the GC ratio at any time according to the progress of writing the user data to the NAND memory 12 and copying by garbage collection.

(5-3) Securing a copy destination block The control unit 15 selects a block having as few rewrites as possible among free blocks as a copy destination block. For example, the control unit 15 may randomly select a predetermined number of free blocks as candidates from two or more free blocks, and select the free block having the least number of rewrites among the selected candidates as the copy destination block. Good. Free blocks are managed in a list format so that the order in which they are generated can be known, for example. The control unit 15 may select the oldest generated predetermined number of free blocks or the latest generated predetermined number of free blocks as candidates. The control unit 15 assigns a sequence number to the selected copy destination block.

(5-4) Copy of Valid User Data 301 The control unit 15 identifies valid user data 301 based on the valid information. The control unit 15 generates a copy command for copying the specified valid user data 301 to the copy destination block. The copy command includes a logical address and a physical address indicating the location of the copy source user data 301. The control unit 15 calculates a physical address indicating the position of the copy destination before executing the copy command. The control unit 15 calculates a physical address indicating the position of the copy destination so that the user data is stored by copying in order from the beginning of the copy destination block. The control unit 15 adjusts the execution timing of the copy command based on the GC ratio. The control unit 15 executes the copy command with priority over the generation of the copy command. The control unit 15 updates the GC ratio after copying. The control unit 15 subtracts the value obtained by subtracting the number of copied user data 301 from the number of initially valid user data 301, and subtracts the number of user data writes from the number of initially invalid user data 301. Calculate the new GC ratio by dividing by the value obtained.

(5-5) Update of translation information and valid information After copying, the control unit 15 updates the translation information and valid information. The control unit 15 starts updating the translation information and the valid information after the copying of all the valid user data 301 stored in the GC block is completed, for example. The execution priority of the translation information and the valid information associated with the garbage collection is set lower than the execution priority of the process of accessing the NAND memory 12.

For example, after copying, the control unit 15 first updates the valid information related to the copy destination block. Specifically, the control unit 15 updates the valid information assuming that all the user data 301 copied to the copy destination block are valid. Subsequently, the control unit 15 confirms that the translation information indicates the position of the copy source of the user data 301. This is because the translation information may be updated by writing the user data by the write command until the copy is completed. When the translation information indicates the position of the copy source of the user data 301, the control unit 15 updates the translation information so that the position of the copy source of the user data 301 indicates the position of the copy destination. The control unit 15 updates the GC dirty information 223 when the state of the unit information changes from non-dirty to dirty due to the update of the translation information. When the translation information does not indicate the position of the copy source of the user data 301, the control unit 15 does not update the translation information, invalidates the corresponding user data 301, and updates the valid information related to the copy destination block. After updating the translation information and the valid information for all the copied user data 301, the control unit 15 updates the valid information of the copy source block assuming that all the user data 301 are invalid.

The control unit 15 monitors the valid information. If there is a block in which all user data 301 is recorded as invalid, the control unit 15 manages the block as a free block. Specifically, the control unit 15 adds a block in which all user data 301 are recorded as invalid to the free block list. The position where the block is added does not have to be at the end of the free block list. For example, the control unit 15 compares the number of rewrites between the block recorded at the end of the free block list and the block to be added. When the number of rewrites of the block recorded at the end of the free block list is larger than the number of rewrites of the block to be added, the control unit 15 sets the block to be added one before the block recorded at the end of the free block list. Add to the position of. When the number of rewrites of the block recorded at the end of the free block list is less than the number of rewrites of the block to be added, the control unit 15 positions the block to be added after the block recorded at the end of the free block list. Add to. The reason why the complete sort based on the number of rewrites is not performed is to extend the life of the NAND memory 12 by extending the erasing execution interval.

(6) Reed processing There are two types of reed processing: a read using a cache and a FUA read. The read type can be specified by a read command. The FUA read flushes if the range of logical addresses specified by the read command remains in the cache, then issues a request to invalidate the page buffer cache of the NAND memory 12, and then reads using the cache. Is a read that executes. If data exists in the write buffer 141 at the time of flashing, the control unit 15 flushes the write buffer 141. The read using the cache translates the logical address in the range specified by the write command, sends a read request to the NAND controller 13, and stores the user data 301 sent from the NAND controller 13 in the read buffer 142. And transmission of the user data 301 stored in the read buffer 142 to the host.

(6-1) Read cache There are two types of read cache, a page buffer cache and a read buffer 142. The page buffer cache is provided inside the chip that constitutes the NAND memory 12. When the NAND controller 13 continuously reads the user data 301 from the same physical address, the NAND controller 13 does not send a read command to the NAND memory 12 but reads the user data 301 stored in the page buffer cache. Data is input / output to / from the read buffer 142 according to the FIFO rules.

(7) Replacement of cache line in cache area 143 (7-1) First replacement When a cache line is vacated during write processing or read processing, the first replacement control unit 15 selects a cache line that has become dirty due to garbage collection. Priority is given to emptying. Specifically, the control unit 15 first refers to the GC dirty information 223. Then, the control unit 15 writes back the oldest unit information among the unit information indicated by the GC dirty information 223 to the log storage area 124 and deletes it from the cache area 143. When there is no unit information that has become dirty due to garbage collection, the control unit 15 randomly selects the unit information cached in the cache area 143. The control unit 15 generates a random number and selects unit information by using the generated random number. The control unit 15 determines whether or not the selected unit information is dirty by referring to the user dirty information 222. If the selected unit information is not dirty, the control unit 15 deletes the selected unit information from the cache area 143. When the selected unit information is dirty, the control unit 15 writes back the oldest unit information among the unit information indicated by the user dirty information 222 to the log storage area 124 and deletes it from the cache area 143.

(7-2) Second Replacement When a cache line is vacated for garbage collection, the control unit 15 replaces the cache line as follows. That is, the control unit 15 sets an upper limit value for the number of unit information indicated by the GC dirty information 223. When the number of unit information indicated by the GC dirty information 223 has reached the upper limit, the control unit 15 writes back the oldest unit information among the unit information indicated by the GC dirty information 223 to the log storage area 124. , Delete from the cache area 143. When the number of unit information indicated by the GC dirty information 223 has not reached the upper limit value, the control unit 15 randomly selects the unit information cached in the cache area 143. If the selected unit information is not dirty, the control unit 15 deletes the selected unit information from the cache area 143. When the selected unit information is dirty, the control unit 15 writes back the oldest unit information among the unit information indicated by the user dirty information 222 to the log storage area 124 and deletes it from the cache area 143.

As described above, in the first embodiment, the translation information is managed in a plurality of layers. Then, the size of the second table 202a, which is the translation information belonging to the second layer, is equal to the size of the third table 203a, which is the translation information belonging to the second layer. This makes it easy to manage the sizes of the tables 202a and 203a. Further, the second table 202a and the third table 203a can be mixed and stored in the log storage area 124. That is, it is not necessary to manage the area for storing the second table 202a and the area for storing the third table 203a separately. Further, the second table 202a and the third table 203a can be mixed and stored in one page. In addition, it is possible to keep the number of tables that can be stored in each page constant. As described above, according to the first embodiment, since the translation information is easily managed, the translation information management cost is low and the convenience is high.

In the above description, it has been described that the size of the second table 202a, which is the translation information belonging to the second layer, and the size of the third table 203a, which is the translation information belonging to the third layer, are equal. The translation information may be layered into four or more layers, and the size of the translation information belonging to each of the two arbitrary layers may be equal to each other. For example, when the size of the translation information belonging to the i-th layer and the size of the translation information belonging to the j-th layer are configured to be equal to each other, the translation information belonging to the i-th layer and the translation information belonging to the j-th layer are combined. It is possible to mix and store in the same area.

Further, the size of each effective bitmap 212a is equal to the size of the second table 202a and the third table 203a. As a result, the effective bitmap 212a, the second table 202a, and the third table 203a can be mixed and stored in the log storage area 124. Further, the effective bitmap 212a, the second table 202a, and the third table 203a can be mixed and stored in one page. It is possible to keep the number of unit information that can be stored on each page constant.

(Second Embodiment)
The second embodiment can be applied to the memory system 1 of the first embodiment. According to the second embodiment, the control unit 15 includes two or more processors.

FIG. 9 is a diagram showing the configuration of the control unit 15 of the second embodiment. According to the example in this figure, the control unit 15 includes a plurality of (three in this case) processors 151. One of the three processors 151 functions as a dynamic task scheduler that dynamically distributes tasks to the other two processors 151. The processor 151 as a dynamic task scheduler is referred to as a master processor 151a. The two processors 151 whose tasks are distributed from the master processor 151a are referred to as slave processors 151b. The task constitutes the control of the memory system 1. The control of the memory system 1 is composed of a plurality of tasks. One process may be composed of one task. One process may be composed of a plurality of tasks. The plurality of processes may be composed of one task.

FIG. 10 is a diagram showing the configuration of the RAM 14 of the second embodiment. The configuration described with reference to FIG. 3 will be omitted here. According to the second embodiment, the RAM 14 includes a program load area 144 and a work area 145. One or more task programs 241 are loaded in the program load area 144. The task program 241 is a set of program codes for realizing one task.

One task program 241 may be executed simultaneously by a plurality of processors 151. The work area 145 includes a data area 242 that is reserved and released for each execution. Each data area 242 stores a value used to execute the task.

For example, the task of updating translation information is realized by one task program 241. A different data area 242 is secured for each update request for one task program 241 for updating translation information. In each data area 242, the logical address, the old physical address, the new physical address, and the like included in the update request are stored as values used for executing the task. The one task program 241 for the task of updating the translation information is executed simultaneously by the plurality of processors 151, and the plurality of processors 151 simultaneously executing the one task program 241 for the task of updating the translation information. It is configured to use different data areas 242. As a result, the control unit 15 can process a plurality of update requests different from each other in parallel.

For example, the task of analyzing commands is realized by one task program 241. A different data area 242 is secured for each command for one task program 241 for analyzing the command. In each data area 242, the identification information of the command, the parameters included in the command, and the like are stored as values used for executing the task. One task program 241 for a task that parses a command is executed simultaneously by a plurality of processors 151, and a plurality of processors 151 that simultaneously execute one task program 241 for a task that parses the command are different from each other. Data area 242 is used. As a result, the control unit 15 can analyze a plurality of commands different from each other in parallel.

Since the memory system 1 is configured so that a plurality of data areas 242 different for each execution can be allocated to one task program 241, it is not necessary to load the task program 241 into the program load area 144 for each execution. The control unit 15 loads all the task programs 241 into the program load area 144 in the startup process. The control unit 15 can transfer data between a plurality of tasks using the data area 242.

The master processor 151a includes a master queue 152a. Each slave processor 151b includes a slave queue 152b. A task waiting to be executed is registered in the master queue 152a. Specifically, the identification information indicating the task program 241 that realizes the task waiting to be executed is registered in the master queue 152a in association with the information that specifies the data area 242 used for executing the task. Will be done. The master processor 151a distributes one or more tasks registered in the master queue 152a to two slave processors 151b. The master processor 151a registers the task registered in the master queue 152a in the slave queue 152b provided in any of the slave processors 151b. Each slave processor 151b executes a task registered in the slave queue 152b provided therein. In other words, each slave processor 151b uses the data area 242 designated by the information associated with the identification information for the task program 241 indicated by the identification information registered in the slave queue 152b provided in the slave processor 151b. Execute while.

The method of distributing tasks is arbitrarily designed. For example, an upper limit is set for the number of tasks that can be registered in each slave queue 152b. The master processor 151a registers tasks in each slave queue 152b until the upper limit is reached. Each slave processor 151b transmits a completion notification to the master processor 151a each time the task registered in the slave queue 152b provided in the slave processor 151b is executed. The master processor 151a that has received the completion notification registers a new task in the slave queue 152b provided in the slave processor 151b that has transmitted the completion notification.

Note that one task may generate another task. The other task is registered in the master queue 152a and then distributed to any of the slave queues 152b. One task may be configured to allow the slave processor 151b to execute another task. In that case, the other task may be directly registered in the slave queue 152b provided in the designated slave processor 151b without going through the master queue 152a. When a slave processor 151b for executing another task is specified, whether or not the number of tasks registered in the slave queue 152b provided in the specified slave processor 151b has reached the upper limit. Regardless, the other task may be registered in the slave queue 152b provided in the designated slave processor 151b.

In this way, the master processor 151a can dynamically distribute tasks to a plurality of slave processors 151b.

Each of the plurality of slave processors 151b may be configured to be able to individually supply power or stop supplying power. For example, the memory system 1 is configured to be able to operate in two modes, a normal mode and a low power consumption mode in which power consumption is lower than that of the normal mode. The power control unit supplies power to the two slave processors 151b in the normal mode. The power control unit supplies power to only one of the two slave processors 151b. The power control unit is composed of hardware, software, or a combination of both. For example, the master processor 151a functions as a power supply control unit. The master processor 151a distributes the task to the two slave processors 151b in the normal mode. In the low power consumption mode, the master processor 151a supplies a task only to the slave processor 151b to which the power is supplied out of the two slave processors 151b. In this way, since the master processor 151a dynamically determines the task registration destination, the control unit 15 continues to control the memory system 1 even if the number of slave processors 151b to which power is supplied changes. be able to.

The master processor 151a may include a slave queue 152b in addition to the master queue 152a. The master processor 151a may distribute tasks to its own slave queue 152b.

In the second embodiment, in order to maintain the consistency of the translated information and the valid information, the task of updating the translated information and the task of updating the valid information are executed by the predetermined slave processor 151b.

For example, in the case of translation information, the logical address space of the memory system 1 is divided into two logical address ranges. The task of registering the task of updating the translation information is executed in any of the processors 151. The task of registering the task of updating the translation information makes an update request for a logical address included in the first logical address range of the two logical address ranges, which is a predetermined one of the two slave processors 151b. Is executed by the slave processor 151b of. Further, the task of registering the task of updating the translation information makes an update request for the logical address included in the second logical address range of the two logical address ranges, and the other slave of the two slave processors 151b. Let the processor 151b execute it. When a plurality of tasks for updating translation information are registered in one slave queue 152b, the slave processor 151b including the slave queue 152b registers each task for updating translation information in the slave queue 152b. It will be executed in order. In this way, regarding the update of the translation information, the consistency of the translation information is maintained by presetting the logical address range in charge for each slave processor 151b.

For example, in the case of valid information, the physical address space of the memory system 1 is divided into two subspaces. The task of registering the task of updating the valid information is executed in any of the processors 151. The task of registering the task for updating valid information makes an update request for a logical address included in the first physical address range of the two physical address ranges, which is a predetermined one of the two slave processors 151b. Is executed by the slave processor 151b of. Further, the task of registering the task of updating the valid information makes an update request for the logical address included in the second physical address range of the two physical address ranges, and the other slave of the two slave processors 151b. Let the processor 151b execute it. When a plurality of tasks for updating valid information are registered in one slave queue 152b, the slave processor 151b including the slave queue 152b registers each task for updating valid information in the slave queue 152b. It shall be executed in the order of. In this way, regarding the update of the valid information, the consistency of the valid information is maintained by presetting the physical address range in charge for each slave processor 151b.

For example, in garbage collection, a task to register a task to generate a copy command is executed. The task of registering the task of generating the copy command divides the physical address range of the GC block into two physical address ranges. The task of registering the task of generating the copy command sets the effective bitmap 212b of the first physical address range of the two physical address ranges to the predetermined slave processor 151b of the two slave processors 151b. And register the task to generate the copy command in the one slave processor 151b. When the one slave processor 151b generates a copy command based on the registered task, the one slave processor 151b identifies valid user data 301 to be copied based on the valid bitmap 212b of the first physical address range. Further, the task of registering the task of generating the copy command passes the effective bitmap 212b of the second physical address range of the two physical address ranges to the other slave processor 151b of the two slave processors 151b. , Register a task to generate a copy command in the other slave processor 151b. When the other slave processor 151b generates a copy command based on the registered task, the other slave processor 151b identifies valid user data 301 to be copied based on the valid bitmap 212b of the second physical address range.

Thus, in the second embodiment, the memory system 1 includes a plurality of processors 151. Each processor 151 is set with a range of logical addresses. Each processor 151 executes the update of the record related to the logical address included in the range of the logical address set to itself in the translation information. As a result, the translation information can be updated in parallel on a plurality of processors 151. Therefore, the translation information can be updated at a higher speed than when the translation information is updated on only one processor 151. Can be done. In addition, the translated information can be updated at high speed without impairing the consistency of the translated information.

Further, each processor 151 is set with a range of physical addresses. Each processor 151 updates a record of valid information in the range of physical addresses set to itself. As a result, the valid information can be updated in parallel on a plurality of processors 151. Therefore, the valid information can be updated at a higher speed than when the valid information is updated by only one processor 151. Can be done. In addition, the valid information can be updated at high speed without impairing the consistency of the valid information.

Further, one processor 151 causes a plurality of processors 151 to share the process of generating a copy command at the time of garbage collection. Specifically, one processor 151 divides the GC block into a plurality of areas. Each processor 151 identifies valid user data 301 stored in one of the divided areas and generates a copy command for copying the identified valid user data 301. As a result, even if there is a large amount of valid user data 301 stored in the GC block, a copy command can be created at high speed.

(Third Embodiment)
The third embodiment can be applied to any of the memory systems 1 of the first embodiment and the second embodiment. According to a third embodiment, the memory system 1 includes a Software Defined platform. The software-defined platform, for example, separates the function of the memory system 1 from the control of the hardware and executes the control by the software.

In the third embodiment, as in the second embodiment, the control unit 15 includes a plurality of (three in this case) processors 151. The three processors 151 include one master processor 151a and two slave processors 151b.

In the configuration of the memory system 1, the host interface unit 11, the NAND controller 13, the RAM 14, and the three processors 151 are included in the hardware.

FIG. 11 is a diagram showing the configuration of the RAM 14 of the third embodiment. The configuration described with reference to FIG. 3 will be omitted here. According to the third embodiment, the RAM 14 includes a program load area 144 and a work area 145. Two or more application programs 251 and a control program 252 are loaded in the program load area 144. Each application program 251 is composed of one or more task programs 241. The work area 145 includes a data area 242 that is reserved and released for each execution.

The software-defined platform of the third embodiment includes a control program 252, hardware, and NAND memory 12. By using the software-defined SSD platform, it is possible to control the software by separating the SSD function from the hardware control. In the third embodiment, the platform means a whole of hardware, an operating system (OS), middleware, a combination thereof, a setting, an environment, etc., which are the foundations necessary for operating hardware or software.

Each processor 151 executes the control program 252. The master processor 151a includes a master queue 152a. The slave processor 151b includes a slave queue 152b.

The control program 252 is a common module that absorbs differences in hardware. Specifically, the control program 252 realizes a basic operation between each application program 251 and the hardware so that each application program 251 becomes hardware-independent. Independent means, at least, the property that remains available even if the other software or hardware with which it collaborates is replaced. Therefore, the control program 252 conforms to the API (Application Program Interface).

For example, the control program 252 receives a command issued by the application program 251 according to a specific interface, and executes control over the hardware and the NAND memory 12 based on the command. The control program 252 schedules the task. The master processor 151a monitors the status of the two slave queues 152b and distributes the tasks registered in the master queue 152a to the two slave queues 152b. Each slave processor 151b executes a task registered in each slave queue 152b.

The storage position of the control program 252 and the storage position of each application program 251 in the RAM 14 are determined when the memory system 1 is started, and are not rearranged during the subsequent startup.

Each application program 251 is various software such as firmware. Each application program 251 may be configured to include software other than firmware.

In the third embodiment, each application program 251 can independently realize the SSD function. Each of the two or more application programs 251 includes a task program 241 that realizes a task that analyzes a command, a task program 241 that realizes a task that updates translation information, a task program 241 that realizes a task that updates valid information, and the like. Since it is provided, the SSD function can be realized by using any of two or more application programs 251.

The task program 241 that realizes the same type of task may be different for each application program 251. For example, the task program 241 that realizes the read processing included in the first application program 251 can correspond to the position designation using the LBA, and realizes the read processing included in the second application program 251. The task program 241 can support position designation using KVS (Key-Value Store). Further, for example, the task program 241 that realizes the management of the translation information included in the first application program 251 and the task program 241 that realizes the management of the translation information included in the second application program 251 may be used. The management unit of translation information is different. Also, for example, access from processor 151 to RAM 14 is encrypted. For example, an encryption key when the processor 151 accesses RAM 14 under the control of the first application program 251 and an encryption key when the processor 151 accesses RAM 14 under the control of the second application program 251. And are different. The encryption key is different for each application program 251. The encryption key may be different for each task program 241.

For example, the control program 252 is created by the manufacturer of the memory system 1 and initially stored in the memory system 1. Each application program 251 does not have to be initially stored in the memory system 1. Part or all of the two or more application programs 251 may be created or stored by a person other than the manufacturer, such as a customer, a purchaser of the memory system 1, or a software developer.

The host 2 can select the application program 251 to be used from the two or more application programs 251.

For example, when NVMe is adopted as an interface standard for communication between the memory system 1 and the host 2, when the host 2 creates a namespace in the memory system 1, the host 2 uses two or more application programs. Of the 251 applications, the application program 251 to be used is specified. The control unit 15 stores the correspondence between the host 2 and the namespace, and when the command is received from the host 2, the control unit 15 executes the corresponding application program 251 according to the namespace of the host 2 from which the command is sent or the namespace of the access destination. Identify.

As described above, according to the third embodiment, the memory system 1 loads a plurality of application programs 251 into the RAM 14. The memory system 1 is configured so that the application program 251 to be used can be selected from the plurality of application programs 251. As a result, for example, when a plurality of hosts 2 are connected to the memory system 1, the memory system 1 can perform different operations for each host 2.

Further, the memory system 1 is configured so that the application program 251 can be selected when the namespace is created. As a result, the memory system 1 can perform different operations for each namespace.

(Fourth Embodiment)
The fourth embodiment can be applied to any of the memory systems 1 of the first to third embodiments. According to the fourth embodiment, the memory system 1 is configured so that a plurality of logical address spaces independent of each other can be constructed. Each of the plurality of logical address spaces that are independent of each other is, for example, a namespace.

The control unit 15 adds a new namespace in response to the generation request from the host 2. Further, the control unit 15 deletes the existing namespace in response to the deletion request from the host 2. The control unit 15 can add new namespaces until the total size of all namespaces reaches the notation capacity of the memory system 1.

FIG. 12 is a diagram showing the configuration of the RAM 14 of the fourth embodiment. In the fourth embodiment, the first table storage area 146 is secured in the RAM 14. The control unit 15 manages the first table 201b for each namespace. The first table storage area 146 stores the first table 201b for each namespace.

The control unit 15 generates a new first table 201b in response to a generation request from the host 2. Further, the control unit 15 deletes the first table 201b corresponding to the namespace specified by the deletion request in response to the deletion request from the host 2. Removing the namespace involves updating the valid information, as in the case of trimming. The control unit 15 stores each first table 201b in a continuous area. The control unit 15 manages the storage position of each first table 201b in association with the namespace.

The management unit of each first table 201b may be the same between the namespaces, or may be different for each namespace. Here, as an example, it is assumed that the management unit of each first table 201b is the same between the namespaces. The size of the first table storage area 146 is at least twice the size of the total size of all the first tables 201b when the total size of all namespaces reaches the upper limit.

13 to 19 are views for explaining changes in the storage mode of each first table 201b. When the memory system 1 has three namespaces (NS # 0, NS # 1, and NS # 2), for example, as shown in FIG. 13, each first table 201b starts from the beginning of the first table storage area 146. Arranged in order. Each first table 201b is arranged without a space between each first table 201b.

When the control unit 15 receives the deletion request of NS # 1 in the state of FIG. 13, the control unit 15 deletes the first table 201b of NS # 1 as shown in FIG. The control unit 15 updates the valid information before deleting the first table 201b of NS # 1. Specifically, the control unit 15 invalidates all the user data 301 written by designating NS # 1. Further, the control unit 15 invalidates all the translation information belonging to the lower hierarchy of the translation information of NS # 1 before deleting the first table 201b of NS # 1.

Subsequently, the control unit 15 performs an operation of filling the space created by the deletion of the first table 201b. For example, in the state of FIG. 14, the control unit 15 rearranges the first table 201b of NS # 2. The relocation is performed as follows. As shown in FIG. 15, the control unit 15 duplicates the first table 201b of NS # 2, which is the first table 201b to be rearranged, in the free area of the first table storage area 146. The duplicated first table 201b is referred to as the first table 201c. Since the first table storage area 146 has a size that is at least twice the maximum value of the total size of each first table 201b, the size of the first table storage area 146 is irrespective of the size of the first table 201b. It is possible to duplicate the first table 201b. Further, since each first table 201b is arranged from the beginning of the first table storage area 146, the area from the center to the end of the first table storage area 146 is an area in which a duplicate of the first table 201b is stored. Can be used as.

Subsequently, as shown in FIG. 16, the control unit 15 deletes the first table 201b of NS # 2 from the first table storage area 146. Then, as shown in FIG. 17, the control unit 15 duplicates the first table 201c of NS # 2 as the first table 201b of NS # 2 at a position continuous with the end of the first table 201b of NS # 0. To do. Then, as shown in FIG. 18, the control unit 15 deletes the first table 201c of NS # 2 from the first table storage area 146, and completes the rearrangement of the first table 201b of NS # 2.

When there are a plurality of first tables 201b to be rearranged in order to fill the space created by the deletion of the first table 201b, the control unit 15 sequentially rearranges each of the plurality of first tables 201b. To do. The control unit 15 rearranges the plurality of first tables 201b to be rearranged in order from the first table 201b closest to the space.

When the control unit 15 receives the additional request of NS # 3 in the state of FIG. 18, the control unit 15 continuously attaches the first table 201b of NS # 3 to the end of the first table 201b of NS # 2, as shown in FIG. Generate at the position where you want to.

The control unit 15 prohibits the addition of a new namespace until the work of filling the space is completed. Further, the first table 201b to be relocated is duplicated until the relocation is completed. The control unit 15 updates both the first table 201b and the first table 201c when updating the translation information in the case of executing the access to the namespace related to the duplicated first table 201b.

As described above, according to the fourth embodiment, the memory system 1 provides a plurality of logical address spaces to the outside. In the RAM 14, the first table storage area 146 is secured. The control unit 15 stores the first table 201b for each logical address in the first table storage area 146. The control unit 15 deletes the first table 201b in response to the deletion request from the host 2. The control unit 15 fills the free area created between the two first tables 201b due to the deletion. When there is a first free area between the first table 201b for the first logical address space and the first table 201b for the second logical address space, the control unit 15 uses the first free area. The first table 201b for the second logical address space is rearranged to eliminate free space. Specifically, the control unit 15 replicates the first table 201b for the second logical address space in the second free area. Then, the control unit 15 deletes the copy source first table 201b. Then, the control unit 15 further duplicates the first table 201c for the second logical address space at a position continuous with the first table 201b for the first logical address space in the first free area. .. Then, the control unit 15 deletes the first table 201c for the second logical address space. As a result, the control unit 15 can store the first table 201b for each logical address in the first table storage area 146 without generating an empty area between them. Therefore, the first table storage area 146 can be used efficiently.

Further, the first table storage area 146 has a size at least twice the maximum value of the total size of the first table 201b. This enables the above-mentioned rearrangement.

Further, when the control unit 15 updates the first table 201b during the rearrangement of the first table 201b, the control unit 15 updates both the first table 201b and the first table 201c. This maintains the consistency of the translated information.

(Fifth Embodiment)
The fifth embodiment can be applied to any of the memory systems 1 of the first to fourth embodiments.

FIG. 20 is a diagram showing a log storage area 124 of the fifth embodiment. As shown in the figure, hot storage 124a and cold storage 124b are secured in the log storage area 124.

Unit information is input / output to / from the hot storage 124a according to the FIFO rules. The control unit 15 writes dirty unit information to the hot storage 124a. The control unit 15 extracts the unit information from the hot storage 124a according to the rules of the FIFO, and writes the valid unit information of the extracted unit information to the cold storage 124b. The valid unit information is the unit information directly indicated by the first table 201b or the block management information 211b, or the unit information indicated by the second table 202a indicated by the first table 201b. ..

The sizes of the hot storage 124a and the cold storage 124b may be variably configured. For example, the control unit 15 reduces the size of the hot storage 124a and increases the size of the cold storage 124b when the locality is high. Then, when the locality is low, the control unit 15 reduces the size of the cold storage 124b and increases the size of the hot storage 124a. For example, the control unit 15 measures the ratio of valid unit information to the output unit information. The control unit 15 can use the measured ratio as a measured value of locality.

As described above, according to the fifth embodiment, the log storage area 124 includes the hot storage 124a and the cold storage 124b, and the control unit 15 hot stores the unit information according to the elapsed time from the update. It is stored in either 124a or cold storage 124b. The log storage area 124 includes three or more areas, and the control unit 15 may store unit information in any of the three or more areas according to the elapsed time since the update.

(Sixth Embodiment)
FIG. 21 is a diagram showing an implementation example of the memory system 1. The memory system 1 is implemented in, for example, the server system 1000. The server system 1000 is configured by connecting the disk array 2000 and the rack mount server 3000 by a communication interface 4000. Any standard can be adopted as the standard of the communication interface 4000. The rack mount server 3000 is configured by mounting one or more hosts 2 on the server rack. The plurality of hosts 2 can access the disk array 2000 via the communication interface 4000.

Further, the disk array 2000 is configured by mounting one or more memory systems 1 on a server rack. In the disk array 2000, one or more hard disk units may be mounted in addition to the memory system 1. Each memory system 1 can execute a command from each host 2. Further, each memory system 1 has a configuration in which the first or second embodiment is adopted. As a result, each memory system 1 can easily execute atomic write.

In the disk array 2000, for example, each memory system 1 may be used as a cache for one or more hard disk units. The disk array 2000 may be mounted with a storage controller unit for constructing a RAID using one or more memory systems 1.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and the equivalent scope thereof.

1 memory system, 2 hosts, 11 host interface, 12 NAND memory, 13 NAND controller, 14 RAM, 15 control, 121 emergency save area, 122 management information area, 123 user data area, 124 log storage area, 124a hot storage , 124b cold storage, 141 write buffer, 142 read buffer, 143 cache area, 144 program load area, 145 work area, 146 first table storage area, 151 processor, 151a master processor, 151b slave processor, 152a master queue, 152b slave. Queue, 201a, 201b, 201c 1st table, 202a, 202b 2nd table, 203a, 203b 3rd table, 211a, 211b Block management information, 212a, 212b Effective bitmap, 221 cache management information, 225 statistics, 231 logs Information, 241 task programs, 242 data areas, 251 application programs, 252 control programs, 301 user data, 1000 server systems, 2000 disk arrays, 3000 rack mount servers.

Claims (16)

Management of translation information indicating the correspondence between logical position information and physical position information, the logical position information is logical position information associated with data, and the physical position information is non-volatile in which the data is stored. It is physical position information indicating a position in the first memory of the sex, and the translation information is hierarchized into a plurality of layers, and the first translation information belonging to the first layer and the second translation information belonging to the second layer. The size of the first translation information and the size of the second translation information are equal to each other, including the translation information.
The first translation information and the second translation information are stored in the first area included in the first memory. The first area includes a plurality of pages, and each page is written to the first memory. It is a unit, and the first translation information and the second translation information are stored on the same page.
How to control the memory system, including. Reading the first translation information and the second translation information from the first area to the second memory,
Using the first translation information and the second translation information stored in the second memory, and
To store the first translation information and the second translation information after use in the first area, and
The method for controlling a memory system according to claim 1, further comprising. Writing the data to the second area included in the first memory and
Managing state management information that records whether the data in the second region is in the first state or the second state, the size of the first translation information, the size of the second translation information, and the state. Equal to the size of management information,
The method for controlling a memory system according to claim 1, further comprising. To store the first translation information, the second translation information, and the state management information in the first area.
The memory system control method according to claim 3, further comprising. To store the first translation information, the second translation information, and the state management information on the same page.
4. The method for controlling a memory system according to claim 4. Reading the first translation information, the second translation information, and the state management information from the first area to the second memory,
Using the first translation information, the second translation information, and the state management information stored in the second memory, and
To store the first translation information, the second translation information, and the state management information after use in the first area.
The memory system control method according to claim 5, further comprising. To store the first data in the first position in the second area, and
The second data, which is the latest data among the data to which the same logical position information as the first data is specified, is stored in the second position.
Managing the state of the first data as the first state and
Managing the state of the second data as the second state and
The memory system control method according to claim 3, further comprising. Management of translation information indicating the correspondence between logical position information and physical position information, the logical position information is logical position information associated with data, and the physical position information is non-volatile in which the data is stored. It is the physical position information indicating the position in the first memory of the sex, and the translation information includes the first translation information.
Writing the data to the first area included in the first memory and
The state management information that records whether the data in the first region is the first state or the second state is managed, and the state management information includes the first state management information and is the first translation. The size of the information is equal to the size of the first state management information,
Writing the first translation information and the first state management information to a second area included in the first memory, the second area includes a plurality of pages, and each page is written to the first memory. It is a unit, and the first translation information and the first state management information are stored on the same page.
How to control the memory system, including. Reading the first translation information and the first state management information from the second area to the second memory,
Using the first translation information and the first state management information stored in the second memory, and
To store the first translation information and the first state management information after use in the second area, and
The memory system control method according to claim 8, further comprising. To store the first data in the first position in the first area, and
The second data, which is the latest data among the data to which the same logical position information as the first data is specified, is stored in the second position in the first area.
Managing the state of the first data as the first state and
Managing the state of the second data as the second state and
The memory system control method according to claim 8, further comprising. The translation information is layered into a plurality of layers, and the first translation information includes a second translation information belonging to the first layer and a third translation information belonging to the second layer.
The method for controlling a memory system according to claim 8. Management of translation information indicating the correspondence between logical position information and physical position information, the logical position information is logical position information associated with data, and the physical position information is non-volatile in which the data is stored. It is the physical position information indicating the position in the first memory of the sex, and the translation information includes the first translation information.
Writing the data to the first area included in the first memory and
The state management information that records whether the data in the first region is the first state or the second state is managed, the state management information includes the first state management information, and the translated information includes the first state management information. , The first translation information is layered into a plurality of layers, and the first translation information includes a second translation information belonging to the first layer and a third translation information belonging to the second layer, and the size of the second translation information and the above. The size of the third translation information is equal to the size of the first state management information,
How to control the memory system, including. To store the first translation information and the first state management information in the second area included in the first memory.
The memory system control method according to claim 12, further comprising. The second area includes a plurality of pages, and each page is a writing unit to the first memory.
To store the first translation information and the first state management information on the same page,
13. The method for controlling a memory system according to claim 13. Reading the first translation information and the first state management information from the second area to the second memory,
Using the first translation information and the first state management information stored in the second memory, and
To store the first translation information and the first state management information after use in the second area, and
14. The method for controlling a memory system according to claim 14. To store the first data in the first position in the first area, and
The second data, which is the latest data among the data to which the same logical position information as the first data is specified, is stored in the second position in the first area.
Managing the state of the first data as the first state and
Managing the state of the second data as the second state and
The memory system control method according to claim 12, further comprising.

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