JP6863700B2 - Non-volatile semiconductor storage device and its measurement method - Google Patents

Description

The present invention relates to a non-volatile semiconductor storage device and a measuring method thereof, and in particular, the measuring method relates to measuring the threshold voltage of a memory cell constituting the semiconductor storage device.

In recent years, the capacity of semiconductor storage devices, especially non-volatile semiconductor storage devices, has become widespread. As the capacity of the non-volatile semiconductor storage device increases, the time for measuring the threshold voltage of each memory cell in a test mode different from the normal mode also increases.

Patent Document 1 provides a simultaneous measurement control circuit for a semiconductor test apparatus suitable for testing a DUT (Device Under Test: device under test) that cannot be written / read more than a predetermined number of times, such as a flash memory.

Patent Document 1 describes a signal obtained by ORing a match flag output from a plurality of DUTs at good times in a DUT test mode, and at least one DUT between a predetermined number of match indexes. By taking the logical sum with the signal obtained by the logical sum when the match is obtained, the extracted signal is logically compared with the expected value to measure whether or not they match.

Patent Document 2 provides a non-volatile multi-level memory using a proper setting of a reference voltage for program verification and reading. A process for measuring a change in the threshold voltage distribution of a non-volatile semiconductor storage device is disclosed.

JP-A-11-64454 Japanese Patent Application Laid-Open No. 2011-511110

In Patent Document 1, the read time can be shortened as a result by obtaining the logical product or the logical sum from the data of a plurality of DUTs and minimizing the number of reads. However, for example, in a large-capacity memory cell array inside a DUT, a logical product or a logical sum is obtained from the data of a plurality of memory cells, and is a non-volatile semiconductor storage device such as EEPROM (Electronically-Erasable and Programmable Read Only Memory). It cannot be expected to reduce the read time inside the DUT.

In Patent Document 2, the data change in the memory cell can be measured in detail by applying the predetermined step size voltage in a plurality of times. However, due to the recent increase in the capacity of non-volatile semiconductor storage devices, it is expected that the throughput for measuring a large amount of data in a non-volatile semiconductor storage device such as EEPROM and outputting the amount of data change will be improved. Can not.

An object of the present invention is to provide a non-volatile semiconductor storage device capable of shortening the measurement time of the threshold voltage in the test mode and a method for measuring the non-volatile semiconductor storage device.

One aspect of the non-volatile semiconductor storage device according to the present invention includes a non-volatile memory transistor for storing data and a bit select transistor connected in series with the memory transistor, and the bit select transistor has a word line and a sense. It is coupled to a bit line connected to an amplifier, and a memory cell sequence is formed by the memory transistor and the bit select transistor. A plurality of the memory cell sequences are arranged to form a memory cell array, and the memory cell array is a control / logic circuit. The memory cell array is further divided into a plurality of columns according to a predetermined number of columns of the memory cell row, and the bit line coupled to the memory cell row and the sense amplifier are separated from each other. A column selection transistor that turns on and off on a column-by-column basis is interposed.

In another aspect of the present invention, the common connection point between the column selection transistor and the sense amplifier is connected to a bit correspondence line, and the same address of the column selected along the arithmetic progression is connected to the bit correspondence line. The bit lines given with are connected in common.

In another aspect of the present invention, the inputs of the AND circuit and the OR circuit controlled by the control / logic circuit are coupled to the output of the sense amplifier.

In another aspect of the present invention, the logical circuit and the OR circuit performs a logical AND operation and OR operation respectively by the column unit.

Further, in another aspect of the present invention, each output of the AND circuit and the OR circuit is separately coupled to the input of the first selector circuit, and the first selector circuit is the result of the logical operation in the AND circuit and the result of the logical operation. At least one of the OR operation results in the OR circuit is output.

In another aspect of the present invention, the column selection transistor is connected in series between the sense amplifier and the memory cell sequence, and the common connection point between the column selection transistor and the sense amplifier is a bit correspondence line. the coupled, the bit line of the column to the bit corresponding line selected along the arithmetic sequence is coupled.

In another aspect of the present invention, the gate of the memory transistor is connected to a bite select transistor, the bite select transistor is coupled to a DC voltage applying means for applying a DC voltage, and the DC voltage applying means connects the memory transistor. The DC voltage is set high enough to turn it off or on.

In another aspect of the present invention, the DC voltage is set to a stepped voltage sufficient to turn the memory transistor off or on.

In another aspect of the present invention, when a DC voltage sufficient to turn off the memory transistor is applied, the AND operation result in the AND circuit is selected from the first selector circuit and output.

In another aspect of the present invention, when a DC voltage sufficient to turn on the memory transistor is applied from the DC voltage applying means, the OR calculation result in the OR circuit is selected from the first selector circuit. Is output.

In the arithmetic and measurement method of the non-volatile semiconductor storage device, which is another invention of the present invention, when measuring the threshold voltage of the memory transistor, first, a start bit signal indicating the start of communication is input in a start condition, and then an operation code is used. At the input, a stepped DC voltage is applied to the gate of the memory transistor via the byte select transistor, and then data of the transition state of the memory transistor to off or on is transmitted from the bit line to the sense amplifier via the sense amplifier. , The logical product circuit and the logical sum (OR) circuit perform each logical operation.

In another embodiment of the calculation method of measuring the non-volatile semiconductor memory device of the present invention is also a part of the memory cell array before performing the logical operation in the logical product (AND) circuit and the logical sum (OR) circuit The information read from the provided trimming data area is the information of the equal difference number sequence having the target information in each logical operation once.

It is a circuit block diagram which shows the structure of the non-volatile semiconductor storage device which concerns on embodiment of this invention. It is a circuit block diagram which shows the detailed circuit structure of the periphery of column 0 of FIG. 1 and the sense amplifier connected to it. It is a figure which shows the measurement input voltage used when measuring the threshold voltage of the memory cell transistor of this invention. It is a figure which shows the measurement input voltage used when measuring the threshold voltage of the memory cell transistor of this invention. It is a figure which shows an example of the logical product (AND) operation output of columns 0-3 when the measurement input voltage shown in FIG. 3 is applied to a memory transistor. It is a figure which shows an example of the OR operation output of columns 0 to 3 when the threshold voltage measurement input voltage shown in FIG. 4 is applied to a memory transistor. This is an operation flow when a measurement input voltage is applied to a memory cell transistor of the non-volatile semiconductor storage device shown in FIG. 1 and a threshold voltage is measured.

(Embodiment of the present invention)
FIG. 1 is a circuit block diagram showing a configuration of a non-volatile semiconductor storage device according to the implementation of the present invention.

The non-volatile semiconductor storage device 1 includes a control / logic circuit 2, a memory cell array 3, a sense amplifier 4a, 4b, 4c, 4d, a logical product (AND) circuit 5, a logical sum (OR) circuit 6, a first selector circuit 7, and a third. It includes two selector circuits 8, a third selector circuit 9, a logic circuit input unit 10, and a data output unit 11.

The control / logic circuit 2 forms the central part of the non-volatile semiconductor storage device 1, and controls signals and switching signals are sent to the first selector circuit 7, the second selector circuit 8, and the third selector circuit 9 in the memory cell array 3. A write signal, a read signal, and an erase signal of information are supplied to each of the above. The control / logic circuit 2 may be provided with a measurement input voltage (DC voltage) generator at the gate of the memory transistor when measuring the threshold voltage of the memory transistor according to the present invention. The application path of the measurement input voltage is omitted from the viewpoint of the explanation of this document and the simplification of the drawings, and the signal line Sd is used as a substitute for the supply of these various signals and voltages. The control / logic circuit 2 is connected to the logic circuit input unit 10. The logic circuit input unit 10 and the data output unit 11 are connected to other CPUs, IC testers, etc. (not shown).

The memory cell array 3 is an array of a plurality of memory cells. A memory cell can hold 1-bit data consisting of "0" or "1", which is the smallest unit of information. In addition to "memory cell", there is a phrase "memory cell sequence". Generally, it should be understood that the "memory cell sequence" includes a "memory cell" in which other transistors or memory transistors are connected in the column direction, but in this document, the "memory cell" and the "memory cell sequence" are used. Is treated as a synonym, and these are collectively referred to as "memory cell string" thereafter. The memory cell array 3 is arranged in a matrix in which a plurality of memory cell columns are connected to word lines WL and bit lines bits 0 to 7, which are respectively arranged in the horizontal direction (row direction) and the vertical direction (column direction). The memory transistor adopted in the present invention is non-volatile so that data can be stored by itself.

In the memory cell array 3, for example, one memory cell sequence is composed of the memory transistor M0 and the bit select transistor BS0 connected to the word line WL. Such a memory cell sequence is connected to the byte select transistor BST. Further, the memory cell column is divided into a plurality of columns in units of eight, for example. FIG. 1 shows columns 0 to 127 divided into 128 columns. Further, although the terminal (for example, source) which is the memory transistor M0 and is not connected to the bit select transistor BS0 is shown as an open state, it is actually connected to one terminal (for example, drain) of another memory transistor and one memory cell. It constitutes a column. In NAND flash memory, a large number of memory transistors are connected in series to form a "memory cell sequence".

The column selection transistors KS0, ... KS8 ... KS16 ... KS24 ... KS32 ... KS1016 ... KS1023 are distinguished from the memory cell array 3. The column selection transistor KS0 arranged on the column 0 is connected in series between the bit select transistor BS0 and the sense amplifier 4a. With such a circuit configuration, the bit line bit0, which is the output of the bit select transistor BS0, is coupled to the sense amplifier 4a via the column selection transistor KS0.

The column selection transistor KS8 is arranged on the column 1 and is connected in series with the bit select transistor BS8. The output (for example, drain) of the column selection transistor KS8 is connected to the input side of the sense amplifier 4b. With such a circuit configuration, the bit line bit0, which is the output of the bit select transistor BS8, is coupled to the sense amplifier 4b via the column selection transistor KS8.

The column selection transistor KS16 is arranged on the column 2 and connected in series with the bit select transistor BS16. The output (for example, drain) of the column selection transistor KS16 is connected to the input side of the sense amplifier 4c. With such a circuit configuration, the bit line bit0, which is the output of the bit select transistor BS16, is coupled to the sense amplifier 4c via the column selection transistor KS16.

The column selection transistor KS24 is arranged on the column 3 and connected in series with the bit select transistor BS24. The output (for example, drain) of the column selection transistor KS24 is connected to the input side of the sense amplifier 4d. With such a circuit configuration, the bit line bit0, which is the output of the bit select transistor BS24, is coupled to the sense amplifier 4d via the column selection transistor KS24.

The column selection transistor KS32 is arranged on the column 4 and connected in series with the bit select transistor BS32. The output (for example, drain) of the column selection transistor KS32 is connected to the input side of a predetermined sense amplifier (not shown). With such a circuit configuration, the bit line bit0, which is the output of the bit select transistor BS32, is coupled to a predetermined sense amplifier via the column selection transistor KS32.

The column selection transistor KS1016 is arranged on the column 127 and is connected in series with the bit select transistor BS1016. The output (for example, drain) of the column selection transistor KS1016 is connected to the input side of a predetermined sense amplifier (not shown). With such a circuit configuration, the bit line bit0, which is the bit select transistor BS1016, is coupled to a predetermined sense amplifier via the column selection transistor KS1016.

The column selection transistor KS1023 is connected in series with the final stage bit select transistor BS1023 of the final stage column 127. The output (for example, drain) of the column selection transistor KS1023 is connected to the input side of a predetermined sense amplifier (not shown). With such a circuit configuration, the bit line bit7, which is the output of the bit select transistor BS1023, is coupled to a predetermined sense amplifier via the column selection transistor KS1023.

For convenience of drawing, only six column selection transistors shown in FIG. 1 are shown: KS0, KS8, KS16, KS24, KS32 and KS1016. However, in the actual circuit configuration, a total of 1024 transistors are prepared for each memory cell row, including column selection transistors KS0, KS1, KS2, KS3 ... KS1020, KS1021, KS1022, KS1023. ..

In order to measure the threshold voltage, a measurement input voltage (DC voltage) is applied to each gate of the memory transistors M0 to M1023 via the byte select transistor BST. At this time, the column selection transistors KS0 to KS31 are in the ON state, and all the column selection transistors constituting the columns 4 to 127 are turned off. On / off control of such a column selection transistor is performed by the control / logic circuit 2. Further, when measuring the threshold voltage of the memory transistors M1016 to M1023 constituting the columns 124 to 127, all of the column selection transistors KS1016 to KS1023 are turned on at the same time. At this time, all the column selection transistors coupled to the columns 0 to 123 are turned off. With such a circuit configuration and condition setting, the logical product operation in the logical product (AND) circuit 5 and the logical sum operation in the logical sum (OR) circuit 6 can be performed quickly and surely.

The sense amplifiers 4a, 4b, 4c and 4d are prepared to amplify the minute signal extracted from each of the bit lines bit0 to bit7. Although there are four sense amplifiers shown in FIG. 1, 32 sense amplifiers are actually prepared, and each sense amplifier 4a, 4b, 4c, and 4d is composed of eight sense amplifiers, respectively. The bus lines BUS1 to BUS4 display the sense amplifier outputs A0 to A7, B0 to B7, C0 to C7, and D0 to D7 in a bundle. The bus lines BUS1 to BUS4 are connected to the OR circuit 6, the AND circuit 5, and the second switch 8. Further, in addition to the 32 sense amplifiers for micro signal amplification described above, 6 sense amplifiers are prepared to realize the ECC function, and a total of 38 sense amplifiers are built in the non-volatile semiconductor storage device 1. ..

The AND circuit 5 is used in the test mode of the present invention, but the circuit operation in the normal mode is stopped. In the test mode, for example, the threshold voltage of the memory transistors M0 to M1023 is measured. At this time, a voltage of, for example, 2V to 4V is applied to the gates of the memory transistors M0 to M1023 via the byte select transistor BST.

The logical product (AND) circuit 5 first performs a logical product operation of data extracted from each bit line bit0 to bit7 of columns 0 to 3. After that, the logical product operation of the data extracted from each bit line bit0 to bit7 of columns 124 to 127 is finally performed in the order of columns 4 to 7, columns 8 to 11, and so on. Each minute information signal extracted from the bit lines bit0 to bit is input to the sense amplifiers 4a to 4d via the column selection transistors KS0 to KS24, and is amplified by these sense amplifiers and then to the logical product (AND) circuit 5. Entered. The logical product (AND) circuit 5 outputs a logical value "1" or "0" by a logical product operation.

In one embodiment of the present invention, the logical product output output from the logical product (AND) circuit 5 is set to be, for example, "1". Such condition setting is defined in the present invention as the expected value "1". When the logical value "1" is output, for example, it means that all the threshold voltages of the four columns (32 memory transistors) for which the logical operation is performed satisfy the expected value "1". That is, when the logical value "1" is output, for example, all the threshold voltages for the four columns for which the logical operation has been performed are in a predetermined range. On the contrary, when the logical value "0" is output, it means that the threshold voltage of at least one memory transistor among the four columns for which the logical operation is performed does not satisfy the expected value "1". That is, when the logical value "0" is output, for example, the threshold voltage of at least one memory transistor is present outside the predetermined range among the four columns for which the logical operation is performed.

FIG. 1 shows a device in which information from each bit line bit0 of the sense amplifiers 4a to 4c is amplified by the sense amplifiers 4a to 4d and the data is ANDed by the logical product (AND) circuit 5 for convenience of drawing. There is. One of the features of the present invention is that the logical product operation performed by the logical product (AND) circuit 5 is performed in units of a plurality of columns. FIG. 1 shows that a logical product operation is performed on the data of bit lines bit0 of four columns from column 0 to column 3. That is, one embodiment of the present invention is not one column unit but four columns. An example is an example of performing a logical product operation in units. The logical product calculation time can be shortened by not only four columns but at least two or more columns to be ORed.

The logical product operation performed by the logical product (AND) circuit 5 is, for example, column 0 to column 3, column 4 to column 7, column 8 to column 11, ..., Column 120 to column 123, column 124 to 127. For example, it is performed in units of four columns, that is, in units of columns with tolerances of arithmetic progressions. As a result, the time required for the logical product operation is shortened. That is, one embodiment of the present invention performs a logical operation in a memory cell array in which columns 0 to 127 are arranged in numerical order. Considering the column to be the target of the logical operation using an arithmetic progression, the column of the first term is (0, 4, 8, 12, ... 120, 124), and the tolerance is 4 columns. Therefore, the columns that are the target of one logical product operation are 4 columns including the first term (0 to 3, 4 to 7, 8 to 11, 12 to 15 ... 117 to 120, 121 to 124). )It turns out that.

The OR circuit 6 is used in the test mode of the present invention in the same manner as the AND circuit 5. The OR circuit 6 first performs an OR operation on the data extracted from each bit line bit0 to bit7 of columns 0 to 3. After that, all the columns up to column 127 are ORed according to the arithmetic progression in the same manner as the previous logical operation. The minute information signal extracted from the bit lines bit0 to bit7 is amplified by the sense amplifiers 4a to 4d via the column selection transistors KS0 to KS24 and input to the OR circuit 6. The OR circuit 6 outputs the OR output 6o by the OR operation. The OR output 6o is "0" or "1". In one embodiment of the present invention, when the logical value "1" is output, it is determined that at least one threshold voltage of the memory transistors M0 to M1023 of columns 0 to 127 deviates from a predetermined range. .. When the logical value "0" is output, the threshold voltage is in a predetermined range, and it is determined that the expected value "0" is satisfied. FIG. 1 shows a device in which information from each bit line bit0 of the sense amplifiers 4a to 4c is taken out by the sense amplifiers 4a to 4d and the data values are ORed for convenience of drawing.

FIG. 1 shows that the data of the bit lines bit0 of the four columns from column 0 to column 3 is subjected to the OR operation. The number of columns to be ORed is not limited to four, and if it is at least two, the logical operation time can be shortened.

The OR operation performed by the OR circuit 6 is performed in the same manner as the AND operation. That is, when the column to be ORed is considered using an arithmetic progression, the column of the first term is (0, 4, 8, 12, ... 120, 124), and the tolerance is 4 columns. Therefore, the columns subject to one OR operation are 4 columns including the first term (0 to 3, 4 to 7, 8 to 11, 12 to 15 ... 117 to 120, 121-124). It means that there are 4 columns, which is the same as the tolerance column.

The first selector circuit 7 separately receives the logical values output from the logical product (AND) circuit 5 and the OR circuit 6. The first selector circuit 7 transmits the logical value of either the logical product (AND) circuit 5 or the OR circuit 6 to the third selector circuit 9 in the subsequent stage in the test mode of the present invention. The first selector circuit 7 is controlled by the control / logic circuit 2. That is, when the output of the logical product operation is selected by the control / logic circuit 2, the result of the logical product operation in the logical product (AND) circuit 5 is passed through the first selector circuit 7 and the third selector circuit 9. Is derived to the data output unit 11. On the other hand, when the output of the OR operation is selected by the control / logic circuit 2, the result of the OR operation in the OR circuit 6 is data via the first selector circuit 7 and the third selector circuit 9. It is derived to the output unit 11. For example, an IC tester (not shown) is connected to the data output 11, and the OR operation is stored in the IC tester.

The second selector circuit 8 is prepared for a purpose different from that of the first selector circuit 7. The second selector circuit 8 is used in the normal mode instead of the test mode. In the normal mode, the circuit operation as the original non-volatile semiconductor storage device is performed without measuring the threshold voltage of the memory transistors M0 to M1023. The second selector circuit 8 and the first selector circuit 7 are alternately selected by the control / logic circuit 2.

The third selector circuit 9 is prepared for switching the non-volatile semiconductor storage device 1 of the present invention to either a test mode or a normal mode. Switching to either one is performed by a switching (control) signal (not shown) applied from the control / logic circuit 2. A data output unit 11 is connected to the third selector circuit 9. In the test mode, the data output unit 11 outputs the threshold voltage of the non-volatile semiconductor storage device 1 and its measurement result. In the normal mode, which is different from the test mode, a signal for communicating with the outside is output.

FIG. 2 is a circuit block diagram showing column 0 and its peripheral portion in FIG. The memory cell column MS0 constituting the column 0 is composed of a series connection of the memory transistor M0 and the bit select transistor BS0. The memory cell sequence MS1 is composed of a series connection of a memory transistor M1 and a bit select transistor BS1. The memory cell sequence MS2 is composed of a series connection of a memory transistor M2 and a bit select transistor BS2. The memory cell sequence MS3 is composed of a series connection of a memory transistor M3 and a bit select transistor BS3. The memory cell sequence MS4 is composed of a series connection of a memory transistor M4 and a bit select transistor BS4. The memory cell sequence MS5 is composed of a series connection of a memory transistor M5 and a bit select transistor BS5. The memory cell row MS6 is composed of a series connection of a memory transistor M6 and a bit select transistor BS6. Similarly, the memory cell sequence MS7 is composed of a series connection of the memory transistor M7 and the bit select transistor BS7. The terminals (for example, source) of the memory transistors M0 to M7 that are not connected to the bit select transistors BS0 to BS7 are shown as open, but are actually connected to one terminal (for example, drain) of another memory transistor and are connected to the memory cell. It constitutes a column. In the present invention, a circuit configuration including such a memory cell transition (not shown) is defined as a memory cell sequence. Taking the sense amplifier 4a constituting the column 0 as an example, the sense amplifier 4a shown in FIG. 1 is composed of eight sense amplifiers 4a0, 4a1, 4a2, 4a3, 4a4, 4a5, 4a6 and 4a7.

The sense amplifiers 4a to 4a7 shown in FIG. 2 correspond to the sense amplifiers 4a of FIG. The sense amplifiers 4a to 4a7 all have the same circuit configuration, and are configured by, for example, a CMOS inverter type. Generally, a CMOS inverter type, a differential type, a latch type, etc. are used as the type of the sense amplifier, but the CMOS inverter type is adopted in the present invention. The sense amplifier 4a0 is a signal amplifier circuit composed of a depletion transistor DE, a resistor RE, pMOS transistors P1, P2, P3, nMOS transistors N1, N2, and an inverter INV. The sense amplifiers 4a1 to 4a7 have the same circuit configuration as the sense amplifiers 4a0. Sense amplifier outputs A0 to A7 are taken out from each sense amplifier. The sense amplifier outputs A to A7 are separately supplied to the logical product (AND) circuit 5 and the logical sum (OR) circuit 6 shown in FIG.

The bit correspondence lines BT0 to BT7 are connected to the output side of the column selection transistors KS0 to KS7, that is, the input side of the sense amplifiers 4a1 to 4a7. Although the output side of the column selection transistors KS0 to KS7 is different from the conventional bitline, substantially the same information as the data of the bitlines bit0 to bit7 is taken out.

In addition to the bit line bit0 of column 0, the bit line bit0 of columns 4, 8, 12 ... 116,120,124 is connected to the bit correspondence line BT0.

In addition to the bit line bit1 of column 0, the bit line bit1 of columns 4, 8, 12 ... 116,120,124 is connected to the bit correspondence line BT1.

In addition to the bit line bit2 of column 0, the bit line bit2 of columns 4, 8, 12 ... 116,120,124 is connected to the bit correspondence line BT2.

In addition to the bit line bit 3 of column 0, the bit line bit 3 of columns 4, 8, 12 ... 116, 120, 124 is connected to the bit correspondence line BT3.

In addition to the bit line bit 4 of column 0, the bit line bit 4 of columns 4, 8, 12 ... 116, 120, 124 is connected to the bit correspondence line BT4.

In addition to the bit line bit 5 of column 0, the bit line bit 5 of columns 4, 8, 12 ... 116,120, 124 is connected to the bit correspondence line BT5.

In addition to the bit line bit 6 of column 0, the bit line bit 6 of columns 4, 8, 12 ... 116, 120, 124 is connected to the bit correspondence line BT6.

In addition to the bit line bit7 of column 0, the bit line bit7 of columns 4, 8, 12 ... 116,120,124 is connected to the bit correspondence line BT7.

FIG. 2 shows column 0, and shows a state in which bit lines bit0 to bit7 of columns 4, 8, ... 120, 124 are coupled to bit correspondence lines BT0 to BT7. The bit lines BT0 to BT7 of the column 1 are coupled to the bit lines bits 0 to bit7 of the columns 5, 9, ... 121, 125. Further, the bit lines BT0 to BT7 of the column 2 are coupled to the bit lines bits 0 to bit7 of the columns 6, 10, ... 122, 126. Similarly, the bit lines BT0 to BT7 of the column 3 are coupled to the bit lines bits 0 to bit7 of the columns 7, 11, ... 123, 127. That is, the columns grouped in an arithmetic progression are connected to the bit correspondence lines BT0 to BT7.

FIG. 3 shows a schematic measurement input voltage VM1 used when measuring the threshold voltage of the memory transistors M0 to M1027 shown in FIG. The step-shaped measurement input voltage VM1 is applied to each gate of the memory transistors M0 to M1027 via the byte select transistor BST in the test mode. The measurement input voltage VM1 is generated by the control / circuit logic circuit 2 shown in FIG. 1 or by an IC tester (not shown). The IC tester not only generates the measurement input voltage VM1, but also holds the measurement result of the threshold voltage and the result of the pass / fail judgment in the present invention.

The measurement input voltage VM1 is set in a range of, for example, 2.1 V to 4.0 V, in steps of, for example, in steps of 0.1 V. The range of such a measurement input voltage VM1 is determined based on the standard value and distribution characteristics of the threshold voltage required for the memory transistors M0 to M1027, for example, when writing, reading, or erasing data. At a voltage in such a range, it is expected that all of the memory transistors M0 to M1027 are turned off, for example, and the data value output to the bit lines bit0 to bit7 is "1".

The initial value of the measurement input voltage VM1 is set to, for example, a voltage of 2.1V. The voltage 2.1V is the lower limit of the allowable threshold voltage range. The voltage 2.1V is applied to each gate of the memory transistors M0 to M1027, for example, at a time of 75 ms. When the application of the voltage 2.1V is completed, a voltage 2.2V higher than that by 0.1V is applied, and then a voltage in increments of 0.1V is sequentially applied up to 4.0V for a time of 75ms. Although FIG. 3 shows that the voltage 2.2V is applied immediately after the application of the voltage 2.1V is completed, the logical product calculation is actually performed by the logical product (AND) circuit 5 after the voltage 2.1V is applied. Is performed, and after the logical product calculation is completed, the next voltage of 2.2 V is applied. After that, the same processing is performed up to 4.0V.

For example, the measurement time required to raise the voltage to 4.0 V is 1500 ms (1.5 sec). The range of the measurement input voltage VM1 and the setting of the measurement time are so-called design matters that are sequentially determined on the design side or the manufacturing side of the non-volatile semiconductor storage device.

In one embodiment of the present invention, the step voltage is set in increments of 0.1 V, but if the measurement accuracy of the threshold voltage is not so required, it may be expanded to, for example, 0.2 V or more. The measurement time can be shortened by widening the step voltage step.

FIG. 4 shows another measurement input voltage VM2 used when measuring the threshold voltage of the memory transistors M0 to M1027 shown in FIG. The step-shaped measurement input voltage VM2 is applied to each gate of the memory transistors M0 to M1027 via the byte select transistor BST in the test mode as in FIG.

Unlike the one in FIG. 3, the measurement input voltage VM2 is set in a range of 0 V or less, for example, −0.1 V to −2.0 V, in steps of, for example, in steps of 0.1 V. The range of such measurement input voltage is determined based on the standard value of the threshold voltage required for the memory transistors M0 to M1027. When a voltage in this range is applied to the gates of the memory transistors M0 to M1027, it is expected that all of the memory transistors M0 to M1027 will be turned on and the data value output to the bit lines bit0 to bit7 will be "0". Has been done.

The initial value of the measurement input voltage VM2 is set to, for example, −0.1 V. The voltage −0.1 V is applied to each gate of the memory transistors M0 to M1027, for example, at a time of 75 ms. When the application of the voltage −0.1 V is completed, the voltage −0.2 V is applied, and then the voltage in increments of 0.1 V is sequentially applied to the minimum −2.0 V in a time of 75 ms. Although FIG. 4 shows that the voltage -0.2V is applied as soon as the application of the voltage -0.1V is completed, in reality, the OR circuit 6 is used after the voltage -0.1V is applied. The OR operation is performed, and after the OR operation is completed, the voltage is lowered to -0.2V, and the same processing is performed thereafter up to -2.0V.

The measurement time required to reduce the voltage from −0.1 V to −2.0 V is, for example, 1500 ms (1.5 sec). The range of the measurement input voltage and the setting of the measurement time are so-called design matters that are sequentially determined on the design side or the manufacturing side of the non-volatile semiconductor storage device.

In one embodiment of the present invention, the step voltage is set in increments of −0.1 V, but may be expanded to −0.2 V or less, for example. The measurement time can be shortened by widening the step voltage step.

The time during which the measurement input voltage shown in FIGS. 4 and 3 is supplied is, for example, 1.5 sec, for a total of 3 sec (seconds). Therefore, the total time required to measure the threshold voltage of the non-volatile semiconductor storage device 1 of the present invention is 3 seconds. As shown in FIG. 1, such a time can be obtained by measuring the threshold voltage in units of 4 columns, for example, and in the conventional method of measuring the threshold voltage in units of 1 column, it is 4 times that of the present invention, that is, 12 Since the measurement time of seconds is required, the measurement time of the threshold voltage cannot be shortened.

FIG. 5 is an example showing the logical product output 5o output to the logical product (AND) circuit 5 when a voltage in the range of 2.1 V to 4.0 V shown in FIG. 3 is applied to the memory transistors M0 to M1023. is there. The voltage range of 2.1V to 4.0V does not necessarily represent a standard value determined as a non-defective product, but is a voltage range prepared for measuring the threshold voltage of the memory transistors M0 to M1023. FIG. 5 shows a case where the expected value is “1”. Here, the expected value "1" indicates a state in which data "1" is predicted to be output to the bit lines of many columns. Here, looking at the data in column 0, the data in bitlines bit0, bit1, bit2, bit3, bit4, bit5, bit6 and bit7 are "0", "1", "1", "1", respectively. It can be seen that the bit line bit0 is output as "1", "1", "1", and "1", and the expected value "1" is not output unlike the bitlines bit1 to bit7. Similarly, looking at the data of each column, column 1 and column 3 output the expected value "1", but the bit line bit7 of column 2 outputs the data "0" instead of the expected value "1". You can see that it is outputting. In the logical product output 5o of the logical product (AND) circuit 5, the bit lines bit0 and bit7 are "0", and the bitlines bit1 to bit7 are "1". The range of the measurement input voltage VM1 of the threshold voltage and the standard value for determining the quality of the product are set separately. When the logical product output 5o shown in FIG. 5 is output at, for example, the start voltage of 2.1 V shown in FIG. 3, the application of the next voltage of 2.2 V and the logical product calculation are stopped.

FIG. 6 shows the OR output 6o output to the OR circuit 6 when a voltage in the range of −0.1 V to −2.0 V shown in FIG. 4 is applied to the memory transistors M0 to M1023. This is an example. The voltage range of -0.1V to -2.0V does not necessarily represent the standard value judged as a non-defective product, but is within the voltage range prepared for measuring the threshold voltage of the memory transistors M0 to M1023. is there. FIG. 6 shows a case where the expected value is “0”. Here, the expected value "0" indicates a state in which data "0" is expected to be output to the bit lines of many columns. Here, looking at the data in column 0, the data in bitlines bit0, bit1, bit2, bit3, bit4, bit5, bit6 and bit7 are "0", "0", "0", "0", respectively. It can be seen that the bit line bit6 is output as "0", "0", "1", and "0", and the expected value "0" is not output unlike the bitlines bit1 to bit5 and bit7. Similarly, looking at the data of each column, column 1 and column 3 output the expected value "0", but the bit line bit6 of column 2 outputs the data "1" instead of the expected value "0". You can see that it is outputting. The OR output 6o of the OR circuit 6 has a bit line bit 6 of "1" and other bit lines of "0". Measurement of threshold voltage The range of input voltage VM2 and the standard value for product quality judgment are set separately. When the logical product output 5o shown in FIG. 6 is output at, for example, −0.1 V of the start voltage shown in FIG. 4, the application of the next voltage −0.2 V and the logical product calculation are stopped. ..

FIG. 7 shows the processing and drive flow when the non-volatile semiconductor storage device 1 shown in FIG. 1 is applied with the measurement input voltage in the test mode and the logical operation is performed. In the test mode, the control / logic circuit 2, the memory cell array 3, the column select transistors KS0 to KS1023, the sense amplifiers 4a to 4b, the logical product (AND) circuit 5, the logical sum (OR) circuit 6, the first selector circuit 7, and the first 3 The selector circuit 9 is the target of operation. In the test mode, an IC tester (not shown) is coupled to the data output unit 11, and the measurement result of the threshold voltage measured by the AND circuit 5 and the OR circuit 6 is recorded in this IC tester. To. Further, the stepped DC voltage shown in FIGS. 3 and 4 may be supplied from this IC tester or may be supplied from the control / logic circuit 2. Hereinafter, FIG. 7 will be described with reference to FIGS. 1 to 6.

In FIG. 7, step S100 is a start condition. In the start condition, a so-called start bit indicating the start of communication is input to the control / logic circuit 2. In step S100, for example, the start bit "1" is input.

Step S200 executes the operation code input. In the operation code input, in order to measure the threshold voltage of each memory transistor, for example, the stepped DC voltage shown in FIGS. 3 and 4 is applied to the memory transistor via the byte select transistor BST.

Data for 4 columns of columns 0 to 3 is read from the memory cell area provided in a part of the memory cell 3. Then, a voltage is applied to the memory transistors M0 to M31 for four columns of the read columns 0 to 3, a logical operation is performed, and the result is held in the control / logic circuit 2. The data read at this time is information on the memory transistor and the ECC function. For example, information on 4 columns of columns 0 to 3 in FIG. 1, that is, information on 32 bits of the memory transistors M0 to M31 and 6 bits of the ECC function. It is 38 bits including the minute information.

Step S300 is a data output. In each step of outputting the data of 4 columns, the data of 4 columns held by the control / logic circuit 2 is output, the data of 4 columns of the next step is read, and the data of the read 4 columns is read. A voltage is applied to the memory transistor to perform a logical operation, and the result is held in the control / logic circuit 2. After that, this series of operations is also performed in step S301, step S302, ... Step S331. Step S332 only outputs data. In the data output, for example, when the range is 2.1V to 4.0V and the steps are set in steps of 0.1V, for example, the logical product (AND) operation or logic of 4 columns from columns 0 to 127 is performed. The measurement is performed at the next step voltage only when all the output data of the sum (OR) operation satisfy the expected value. For example, if all the data are "1" as a result of performing the logical product (AND) operation at 2.1 V for columns 0 to 127, the logical product (AND) operation is performed at the next voltage of 2.2 V. If at least one data has "0", the logical product (AND) operation is not performed at the next voltage of 2.2 V, and the operation is stopped.

Step S301 is one of steps S400, and shows the data output of the logical product (AND) operation and the logical sum (OR) operation of four columns from column 0 to column 3. That is, the data of columns 4 to 7 is read at the same time as the data output of 4 columns from columns 0 to 3 is completed, and the logical product (AND) operation and the logical sum (OR) operation for these 4 columns are performed to control and logic. Data is held in the circuit 2.

Step S302 is one of steps S300, and is the data of the logical product (AND) operation and the logical sum (OR) operation of the four columns from column 4 to column 7 held in the control / logic circuit 2 in the previous step S301. Shows the output. That is, the data of columns 8 to 11 is read at the same time as the data output of 4 columns from columns 4 to 7 is completed, and the logical product (AND) operation and the logical sum (OR) operation for these 4 columns are performed to control and logic. Data is held in the circuit 2. Hereinafter, the same operation is performed for steps S303 to S331 (not shown), but they are omitted for convenience of explanation.

Step S332 is one of steps S300, and is a logical product (AND) operation of four columns from the final columns 124 to 127 held in the control / logic circuit 2 in the previous step S331 (not shown). The data of the logical sum (OR) operation is output.

Step S400 is a stop condition. The stop condition indicates that a series of instructions from step S100 to step S332 has been completed. That is, it is also a flag indicating that the measurement of the threshold voltage of the memory cell transistors M0 to M1023 according to the present invention has been completed and that the next step can be performed. After the completion of step S400, a predetermined process is executed by an IC tester (not shown) in which the measurement result of the threshold voltage is stored. This completes the measurement of the threshold voltage of the non-volatile semiconductor storage device according to the present invention.

As described above, the non-volatile semiconductor storage device of the present invention has high industrial applicability because it can realize cost reduction and productivity improvement by shortening the measurement time of the threshold voltage in the test mode.

1 Non-volatile semiconductor storage device 2 Control / logic circuit 3 Memory cell array 4a0, 4a, 4b, 4c, 4d Sense amplifier 5 Logic product (AND) circuit 5o Logic product output 6 Logic sum (OR) circuit 6o Logic sum output 7 1st Selector circuit 8 2nd selector circuit 9 3rd selector circuit 10 Logic circuit input unit 11 Data output unit BUS1 to BUS4 Bus wiring A0 to A7, B0 to B7, C0 to C7, D0 to D7 Sense amplifier output BT0 to BT7 Bit compatible line bit0 to bit7 Bitline BS0 to BS1023 Bit select transistor KS0 to KS1023 Column selection transistor M0 to M1023 Memory transistor MS1 to MS7 Memory cell Sd Signal line WL Wordline BST Byte select transistor

Claims (8)

A non-volatile memory transistor for storing data and a bit select transistor connected in series with the memory transistor are provided, and the bit select transistor is coupled to a word line and a bit line connected to a sense amplifier, and the memory transistor is connected. And the bit select transistor form a memory cell sequence, a plurality of the memory cell sequences are arranged to form a memory cell array, the memory cell array is controlled by a control / logic circuit, and the memory cell array is predetermined. It is divided into a plurality of columns according to the number of columns in the memory cell row, and a column selection transistor for turning on and off in the column unit is interposed between the bit line coupled to the memory cell row and the sense amplifier. and has a non-volatile semiconductor memory device,
A logical product circuit and a logical sum circuit that perform a logical product operation and a logical sum operation on the output signals of the plurality of sense amplifiers provided for each column, respectively.
A first selector circuit that is controlled by the control / logic circuit and selectively outputs either the logical operation result in the AND circuit or the OR operation result in the OR circuit.
A second selector circuit that is controlled by the control / logic circuit and selectively outputs any of the output signals of the plurality of sense amplifiers.
A third selector circuit that is controlled by the control / logic circuit and selectively outputs the output signal of the first selector circuit in the test mode and selectively outputs the output signal of the second selector circuit in the normal mode.
Non-volatile semiconductor storage device. The common connection point between the column selection transistor and the sense amplifier is connected to a bit-corresponding line, and the bit-corresponding line is common to bit lines given the same address of the column selected along the arithmetic progression. The non-volatile semiconductor storage device according to claim 1, which is connected to the above. The column selection transistor is connected in series between the sense amplifier and the memory cell row, and a common connection point between the column selection transistor and the sense amplifier is coupled to a bit correspondence line and becomes the bit correspondence line. the nonvolatile semiconductor memory device according to claim 1, wherein the bit lines of the selected column along the arithmetic sequence is attached is. The gate of the memory transistor is connected to a byte select transistor, the byte select transistor is coupled to a DC voltage applying means for applying a DC voltage, and the DC voltage applying means has a DC voltage sufficient to turn the memory transistor off or on. The non-volatile semiconductor storage device according to any one of claims 1 to 3 , which is set in 1. The non-volatile semiconductor storage device according to claim 4 , wherein the DC voltage is a stepped voltage sufficient to turn off or on the memory transistor. The fifth aspect of claim 5 is that when a DC voltage sufficient to turn off the memory transistor is applied from the DC voltage applying means , the AND operation result in the AND circuit is selected from the first selector circuit and output. The non-volatile semiconductor storage device described. According to claim 5 , when a DC voltage sufficient to turn on the memory transistor is applied from the DC voltage applying means, the OR calculation result in the OR circuit is selected from the first selector circuit and output. The non-volatile semiconductor storage device described. In the non-volatile semiconductor storage device according to any one of claims 1 to 7 , when measuring the threshold voltage of the memory transistor in the test mode, first, in the start condition, a start bit signal indicating the start of communication is transmitted. After inputting, a stepped DC voltage is applied to the gate of the memory transistor by the operation code input, and then the data of the transition state of the memory transistor to off or on is transmitted from the bit line to the sense amplifier via the sense amplifier. A method for calculating and measuring a non-volatile semiconductor storage device that performs each logic operation in a logic product circuit and the logic sum circuit.

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