JP6866809B2 - Silicon Carbide Semiconductor Wafers and Silicon Carbide Semiconductor Devices - Google Patents

Description

The present disclosure relates to silicon carbide semiconductor wafers and silicon carbide semiconductor devices.

Japanese Unexamined Patent Publication No. 2015-185751 (Patent Document 1) describes a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a gate trench.

Japanese Unexamined Patent Publication No. 2015-185751

An object of the present disclosure is to provide a silicon carbide semiconductor wafer and a silicon carbide semiconductor device capable of performing quality control of electrodes while suppressing an increase in contact resistance of the electrodes.

The silicon carbide semiconductor wafer according to the present disclosure includes a silicon carbide substrate, a first electrode, an insulating film, and a second electrode. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The first electrode and the insulating film are provided on the first main surface. The second electrode is provided on the second main surface. A groove is provided on the second main surface. The second main surface includes a first region and a second region separated by a groove. The groove is defined by a first side surface connected to the first region, a second side surface connected to the second region, and a bottom surface connected to each of the first side surface and the second side surface. The second electrode includes a first portion in contact with the first region, a second portion in contact with the second region, and a third portion in contact with the bottom surface. The third part is separated from each of the first and second parts.

The silicon carbide semiconductor device according to the present disclosure includes a silicon carbide substrate, a first electrode, an insulating film, a second electrode, and a bonding material. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The first electrode and the insulating film are provided on the first main surface. The second electrode is provided on the second main surface. A groove is provided on the second main surface. The second main surface includes a first region and a second region separated by a groove. The groove is defined by a first side surface connected to the first region, a second side surface connected to the second region, and a bottom surface connected to each of the first side surface and the second side surface. The second electrode includes a first portion in contact with the first region, a second portion in contact with the second region, and a third portion in contact with the bottom surface. The third part is separated from each of the first and second parts. The joining material electrically connects the first portion, the second portion, and the third portion.

According to the present disclosure, it is possible to provide a silicon carbide semiconductor wafer and a silicon carbide semiconductor device capable of performing quality control of electrodes while suppressing an increase in contact resistance of the electrodes.

It is a plan schematic diagram which shows the structure of the silicon carbide semiconductor wafer which concerns on 1st Embodiment. It is an enlarged view of the region II of FIG. It is sectional drawing which follows the line III-III of FIG. It is sectional drawing which shows the structure of the 1st modification of the silicon carbide semiconductor wafer which concerns on 1st Embodiment. It is a schematic cross-sectional view which shows the structure of the 2nd modification of the silicon carbide semiconductor wafer which concerns on 1st Embodiment, and is taken along the line VV of FIG. It is a plan schematic diagram which shows the structure of the 2nd modification of the silicon carbide semiconductor wafer which concerns on 1st Embodiment. It is sectional drawing which shows the 1st step of the manufacturing method of the silicon carbide semiconductor wafer which concerns on 1st Embodiment. It is sectional drawing which shows the 2nd step of the manufacturing method of the silicon carbide semiconductor wafer which concerns on 1st Embodiment. It is sectional drawing which shows the 3rd process of the manufacturing method of the silicon carbide semiconductor wafer which concerns on 1st Embodiment. It is sectional drawing which shows the 4th process of the manufacturing method of the silicon carbide semiconductor wafer which concerns on 1st Embodiment. It is sectional drawing which shows the 5th process of the manufacturing method of the silicon carbide semiconductor wafer which concerns on 1st Embodiment. It is sectional drawing which shows the process of measuring the electric resistance of a lower electrode. It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the structure of the modification of the silicon carbide semiconductor device which concerns on 2nd Embodiment. It is a plan schematic diagram which shows the structure of the 3rd modification of the silicon carbide semiconductor wafer which concerns on 1st Embodiment.

[Summary of Embodiments of the present disclosure]
First, the outline of the embodiment of the present disclosure will be described. In the crystallographic description in the present specification, the individual orientation is indicated by [], the aggregation orientation is indicated by <>, the individual plane is indicated by (), and the aggregation plane is indicated by {}. Also, a negative crystallographic exponent is usually expressed by adding a "-" (bar) above the number, but in the present specification, a negative sign is added before the number. There is.

(1) The silicon carbide semiconductor wafer 100 according to the present disclosure includes a silicon carbide substrate 1, a first electrode 17, an insulating film 15, and a second electrode 30. The silicon carbide substrate 1 has a first main surface 10 and a second main surface 20 on the opposite side of the first main surface 10. The first electrode 17 and the insulating film 15 are provided on the first main surface 10. The second electrode 30 is provided on the second main surface 20. A groove 26 is provided on the second main surface 20. The second main surface 20 includes a first region 21 and a second region 22 separated by a groove 26. The groove 26 is defined by a first side surface 23 connected to the first region 21, a second side surface 25 connected to the second region 22, and a bottom surface 24 connected to each of the first side surface 23 and the second side surface 25. The second electrode 30 includes a first portion 31 in contact with the first region 21, a second portion 32 in contact with the second region 22, and a third portion 33 in contact with the bottom surface 24. The third portion 33 is separated from each of the first portion 31 and the second portion 32.

In the silicon carbide semiconductor wafer 100 according to (1) above, the first portion 31 is separated from the second portion 32. Therefore, the contact resistance between each of the first portion 31 and the second portion 32 and the silicon carbide substrate 1 can be measured. That is, quality control of each of the first portion 31 and the second portion 32 can be performed. Further, in the silicon carbide semiconductor wafer 100 according to the above (1), the second electrode 30 includes a first portion 31 in contact with the first region 21 and a third portion 33 in contact with the bottom surface 24. As a result, a wider contact area between the second electrode 30 and the silicon carbide substrate 1 can be secured as compared with the case where the second electrode 30 is patterned by etching a part of the second electrode 30. .. Therefore, it is possible to suppress an increase in the contact resistance of the second electrode 30.

(2) In the silicon carbide semiconductor wafer 100 according to (1) above, the first side surface 23, the second side surface 25, and the bottom surface 24 may have a planar shape. The first angle θ1 formed by the first side surface 23 and the bottom surface 24 and the second angle θ2 formed by the second side surface 25 and the bottom surface 24 may be 90 ° or less.

(3) In the silicon carbide semiconductor wafer 100 according to (2) above, the first angle θ1 and the second angle θ2 may be 45 ° or more and 65 ° or less. As a result, the width of the groove 26 becomes narrower toward the second main surface 20. Therefore, when the bonding material is provided inside the groove 26, it is possible to prevent the bonding material from peeling off from the silicon carbide substrate 1.

(4) In the silicon carbide semiconductor wafer 100 according to any one of (1) to (3) above, the total area of the second electrode 30 is the second main surface 20 when viewed from the direction perpendicular to the first region 21. It may be 90% or more of the total area of.

(5) In the silicon carbide semiconductor wafer 100 according to any one of (1) to (4) above, the first region 21 and the second region 22 are less than 8 ° with respect to the (0001) plane or the (0001) plane. It may be an inclined surface at an off angle.

(6) In the silicon carbide semiconductor wafer 100 according to any one of (1) to (5) above, the first main surface 10 is less than 8 ° with respect to the (000-1) surface or the (000-1) surface. It may be an inclined surface at an off angle.

(7) In the silicon carbide semiconductor wafer 100 according to any one of (1) to (6) above, the groove 26 may have a hexagonal shape when viewed from a direction perpendicular to the first region 21.

(8) In the silicon carbide semiconductor wafer 100 according to any one of (1) to (6) above, the grooves 26 may have a lattice shape when viewed from a direction perpendicular to the first region 21.

(9) The silicon carbide semiconductor device 200 according to the present disclosure includes a silicon carbide substrate 1, a first electrode 17, an insulating film 15, a second electrode 30, and a bonding material 7. The silicon carbide substrate 1 has a first main surface 10 and a second main surface 20 on the opposite side of the first main surface 10. The first electrode 17 and the insulating film 15 are provided on the first main surface 10. The second electrode 30 is provided on the second main surface 20. A groove 26 is provided on the second main surface 20. The second main surface 20 includes a first region 21 and a second region 22 separated by a groove 26. The groove 26 is defined by a first side surface 23 connected to the first region 21, a second side surface 25 connected to the second region 22, and a bottom surface 24 connected to each of the first side surface 23 and the second side surface 25. The second electrode 30 includes a first portion 31 in contact with the first region 21, a second portion 32 in contact with the second region 22, and a third portion 33 in contact with the bottom surface 24. The third portion 33 is separated from each of the first portion 31 and the second portion 32. The joining material 7 electrically connects the first portion 31, the second portion 32, and the third portion 33.

In the silicon carbide semiconductor device 200 according to (9) above, the first portion 31 is separated from the second portion 32. Therefore, the contact resistance between each of the first portion 31 and the second portion 32 and the silicon carbide substrate 1 can be measured. That is, quality control of each of the first portion 31 and the second portion 32 can be performed. Further, in the silicon carbide semiconductor device 200 according to the above (7), the second electrode 30 includes a first portion 31 in contact with the first region 21 and a third portion 33 in contact with the bottom surface 24. As a result, a wider contact area between the second electrode 30 and the silicon carbide substrate 1 can be secured as compared with the case where the second electrode 30 is patterned by etching a part of the second electrode 30. .. Therefore, it is possible to suppress an increase in the contact resistance of the second electrode 30.

(10) In the silicon carbide semiconductor device 200 according to (9) above, the first side surface 23, the second side surface 25, and the bottom surface 24 may have a planar shape. The first angle θ1 formed by the first side surface 23 and the bottom surface 24 and the second angle θ2 formed by the second side surface 25 and the bottom surface 24 may be 90 ° or less.

(11) In the silicon carbide semiconductor device 200 according to the above (10), the first angle θ1 and the second angle θ2 may be 45 ° or more and 65 ° or less. As a result, the width of the groove 26 becomes narrower toward the second main surface 20. Therefore, it is possible to prevent the bonding material 7 from peeling off from the silicon carbide substrate 1.

(12) In the silicon carbide semiconductor device 200 according to any one of (9) to (11) above, the total area of the second electrode 30 is the second main surface 20 when viewed from the direction perpendicular to the first region 21. It may be 90% or more of the total area of.

(13) In the silicon carbide semiconductor device 200 according to any one of (9) to (12) above, the first region 21 and the second region 22 are less than 8 ° with respect to the (0001) plane or the (0001) plane. It may be an inclined surface at an off angle.

(14) In the silicon carbide semiconductor device 200 according to any one of (9) to (13) above, the first main surface 10 is less than 8 ° with respect to the (000-1) plane or the (000-1) plane. It may be an inclined surface at an off angle.

(15) In the silicon carbide semiconductor device 200 according to any one of (9) to (14) above, the groove 26 may have a hexagonal shape when viewed from a direction perpendicular to the first region 21.

(16) In the silicon carbide semiconductor device 200 according to any one of (9) to (14) above, the grooves 26 may have a lattice shape when viewed from a direction perpendicular to the first region 21.

[Details of Embodiments of the present disclosure]
Hereinafter, details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are given the same reference number, and the description thereof will not be repeated.

(First Embodiment)
First, the configuration of the silicon carbide semiconductor wafer 100 according to the first embodiment of the present disclosure will be described.

As shown in FIGS. 1, 2 and 3, the silicon carbide semiconductor wafer 100 according to the first embodiment includes a silicon carbide substrate 1, a first electrode 17, a second electrode 30, and a gate insulating film 15. , A gate electrode 47 and an interlayer insulating film 45 are mainly provided. The silicon carbide substrate 1 includes a silicon carbide single crystal substrate 11 and a silicon carbide epitaxial layer 2. The silicon carbide epitaxial layer 2 is provided on the silicon carbide single crystal substrate 11. The silicon carbide substrate 1 has a first main surface 10 and a second main surface 20. The second main surface 20 is on the opposite side of the first main surface 10. The silicon carbide epitaxial layer 2 constitutes the first main surface 10. The silicon carbide single crystal substrate 11 constitutes the second main surface 20.

The first main surface 10 is, for example, a surface inclined at an off angle of less than 8 ° with respect to the (000-1) surface or the (000-1) surface. The off angle may be 6 ° or less, or 4 ° or less. The off angle may be 2 ° or more. The silicon carbide single crystal substrate 11 and the silicon carbide epitaxial layer 2 are, for example, polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 11 has an n-type conductive type containing n-type impurities such as nitrogen.

The second electrode 30 is provided on the second main surface 20. The second electrode 30 is, for example, a drain electrode. The second electrode 30 is made of a material containing, for example, nickel silicide (NiSi) in the case of n-type and titanium aluminum (TiAl) in the case of p-type, depending on the conductive type of SiC. The second electrode 30 may be made of a material containing, for example, titanium aluminum silicon (TiAlSi) regardless of whether it is n-type or p-type. The contact resistance with SiC is 10 ^-1 Ωcm ² units or less, preferably ^10-3 Ωcm ² units or less, and more preferably ^10-5 Ωcm ² units or less. It is desirable that the contact resistance is ohmic contact that does not depend on the current value. If there is a problem in the contact between the SiC and the electrodes, the resistance may increase or decrease depending on the current value, resulting in Schottky contact, which may adversely affect the device operation.

As shown in FIG. 3, the second main surface 20 is provided with a groove 26. The second main surface 20 includes a first region 21 and a second region 22 separated by a groove 26. The groove 26 is defined by a first side surface 23, a second side surface 25, and a bottom surface 24. The first side surface 23 is connected to the first region 21. The second side surface 25 is connected to the second region 22. The bottom surface 24 is connected to each of the first side surface 23 and the second side surface 25. The bottom surface 24 is located on the first main surface 10 side of each of the first region 21 and the second region 22.

As shown in FIG. 3, the width 111 of the opening of the groove 26 is, for example, 2 μm or more and 10 μm or less. The groove spacing is, for example, 50 μm or more and 1000 μm or less. The grooves may or may not be evenly spaced. The second electrode 30 includes a first portion 31, a second portion 32, and a third portion 33. The first portion 31 touches the first region 21. The second portion 32 is in contact with the second region 22. The third portion 33 is in contact with the bottom surface 24. The third portion 33 is separated from each of the first portion 31 and the second portion 32.

The third portion 33 may be separated from the first boundary 28 between the bottom surface 24 and the first side surface 23. Similarly, the third portion 33 may be separated from the second boundary 27 between the bottom surface 24 and the second side surface 25. The third portion 33 may cover a part of the bottom surface 24. A part of the bottom surface 24 may be exposed from the third portion 33. The first portion 31 and the second portion 32 are in contact with the silicon carbide single crystal substrate 11 in the first region 21 and the second region 22, respectively. Similarly, the third portion 33 is in contact with the silicon carbide single crystal substrate 11 on the bottom surface 24.

As shown in FIGS. 1 and 2, the grooves 26 are provided on the second main surface 20 in a grid pattern, for example. When viewed from a direction perpendicular to the first region 21, the grooves 26 are, for example, in a grid pattern. From another point of view, the groove 26 extends along a straight line parallel to, for example, the first straight line 201, and extends along a straight line parallel to the second straight line 202. The first straight line 201 extends, for example, along the <11-20> direction. The second straight line 202 extends, for example, along the <1-100> direction.

As shown in FIGS. 1 and 2, the third portion 33 is provided, for example, in a grid pattern. The third portion 33 extends, for example, along the first straight line and extends along the second straight line. As shown in FIG. 1, when viewed from a direction perpendicular to the first region 21 (in a plan view), the third portion 33 may surround each of the first portion 31 and the second portion 32. .. Each of the first portion 31 and the second portion 32 is physically separated from each other. In a plan view, the shapes of the first portion 31 and the second portion 32 are not particularly limited, but are, for example, square. In plan view, the length 110 of each of the first portion 31 and the second portion 32 is, for example, less than or equal to the chip size. The length 110 of each of the first portion 31 and the second portion 32 is, for example, 200 μm or more and 500 μm or less. The shape of each of the first portion 31 and the second portion 32 may be, for example, a rectangle.

As shown in FIG. 3, the first side surface 23, the second side surface 25, and the bottom surface 24 have, for example, a planar shape. The first angle θ1 formed by the first side surface 23 and the bottom surface 24 and the second angle θ2 formed by the second side surface 25 and the bottom surface 24 are, for example, 90 ° or less. The first angle θ1 and the second angle θ2 may be 45 ° or more and 65 ° or less. The first angle θ1 and the second angle θ2 may be, for example, 50 ° or more. The first angle θ1 and the second angle θ2 may be, for example, 60 ° or less. The first region 21 and the second region 22 are, for example, a (0001) plane or a plane inclined at an off angle of less than 8 ° with respect to the (0001) plane. The off angle may be 6 ° or less, or 4 ° or less. The off angle may be 2 ° or more. The angle formed by each of the first side surface 23 and the second side surface 25 and the bottom surface 24 is, for example, less than 90 °. In cross-sectional view, the width of the groove 26 may decrease from the bottom surface 24 toward the first region 21 and the second region 22.

Regarding the first straight line 201 and the second straight line 202, the angles formed by the bottom surface 24 and each of the first side surface 23 and the second side surface 25 may be the same or different (even if they are mixed). Good). From another point of view, the angle formed by the bottom surface 24 and each of the first side surface 23 and the second side surface 25 in the direction along the first straight line 201 is the bottom surface 24 in the direction along the second straight line 202. The angle formed by each of the first side surface 23 and the second side surface 25 may be the same as or different from each other.

As shown in FIG. 3, the silicon carbide substrate 1 mainly includes a drift region 12, a body region 13, a source region 14, and a contact region 18. The drift region 12 contains an n-type impurity such as nitrogen and has an n-type conductive type (first conductive type). The concentration of n-type impurities in the drift region 12 is, for example, about ^{7 × 10 15} cm ^-3. The concentration of n-type impurities in the silicon carbide single crystal substrate 11 may be higher than the concentration of n-type impurities in the drift region 12.

The body region 13 is on the drift region 12. The body region 13 is in contact with the drift region 12. The body region 13 contains a p-type impurity such as aluminum and has a p-type conductive type (second conductive type). A channel can be formed in the region of the body region 13 facing the gate insulating film 15.

The source region 14 is on the body region 13. The source region 14 is in contact with the body region 13. The source region 14 is separated from the drift region 12 by the body region 13. The source region 14 contains n-type impurities such as nitrogen or phosphorus and has an n-type conductive type. The source region 14 constitutes a part of the first main surface 10. The concentration of the n-type impurity in the source region 14 may be higher than the concentration of the n-type impurity in the drift region 12.

The contact region 18 is in contact with, for example, the body region 13 and the source region 14. The contact region 18 contains a p-type impurity such as aluminum and has a p-type conductive type. The concentration of the p-type impurity contained in the contact region 18 may be higher than the concentration of the p-type impurity contained in the body region 13. The contact region 18 connects the body region 13 and the first main surface 10. The contact region 18 may form a part of the first main surface 10. The concentration of the n-type impurity or the p-type impurity in each of the impurity regions can be measured by, for example, SIMS (Secondary Ion Mass Spectrometry).

As shown in FIG. 3, a gate trench 6 may be provided on the first main surface 10. The first main surface 10 has, for example, a flat portion 5, a side surface 3, and a bottom surface 4. The gate trench 6 is defined by a side surface 3 and a bottom surface 4. The side surface 3 is connected to the flat portion 5. The side surface 3 penetrates the body region 13 and the source region 14 to reach the drift region 12. The bottom surface 4 is connected to the side surface 3. The bottom surface 4 is located in the drift region 12.

In cross-sectional view, the side surface 3 may be inclined so that the width of the gate trench 6 tapers toward the bottom surface 4. The side surface 3 is inclined at 52 ° or more and 72 ° or less with respect to the (000-1) plane, for example. The side surface 3 may be substantially perpendicular to the flat portion 5. The bottom surface 4 may be substantially parallel to the flat portion 5. In cross-sectional view, the gate trench 6 may have a U-shape or a V-shape. The source region 14, the body region 13, and the drift region 12 form a side surface 3 of the gate trench 6. The drift region 12 constitutes the bottom surface 4 of the gate trench 6.

The gate insulating film 15 is provided on the first main surface 10. The gate insulating film 15 is, for example, a thermal oxide film. The gate insulating film 15 is made of a material containing, for example, silicon dioxide. The thickness of the gate insulating film 15 is, for example, about 45 nm. The gate insulating film 15 is in contact with the source region 14, the body region 13, and the drift region 12 on the side surface 3. The gate insulating film 15 is in contact with the drift region 12 on the bottom surface 4. The gate insulating film 15 may be in contact with the source region 14 on the first main surface 10.

The gate electrode 47 is provided on the gate insulating film 15 inside the gate trench 6. The gate electrode 47 is made of polysilicon containing impurities, for example. The gate electrode 47 is provided so as to face the source region 14, the body region 13, and the drift region 12. The gate insulating film 15 is provided between the body region 13 and the gate electrode 47. The interlayer insulating film 45 is provided in contact with the gate electrode 47 and the gate insulating film 15. The interlayer insulating film 45 is made of, for example, a material containing silicon dioxide. The interlayer insulating film 45 may be provided on the gate electrode 47 inside the gate trench 6. The interlayer insulating film 45 electrically insulates the gate electrode 47 and the source electrode 16.

The first electrode 17 is provided on the first main surface 10. The first electrode 17 has, for example, a source electrode 16 and a source wiring 19. The source electrode 16 is in contact with the first main surface 10. Specifically, the source electrode 16 is in contact with the source region 14 on the first main surface 10. The source electrode 16 may be in contact with the contact region 18. The source electrode 16 is made of a material containing, for example, titanium (Ti), aluminum (Al), and silicon (Si). The source electrode 16 is ohmic-bonded to, for example, the source region 14. The source wiring 19 is in contact with the source electrode 16. The source wiring 19 is made of a material containing, for example, aluminum.

Next, a first modification of the silicon carbide semiconductor wafer 100 according to the first embodiment will be described.

As shown in FIG. 4, the angle θ1 formed by the first region 21 and the first side surface 23 and the angle θ2 formed by the second region 22 and the second side surface 25 may be approximately 90 °. Similarly, each of the first side surface 23 and the second side surface 25 extends substantially perpendicular to the bottom surface 24. The third portion 33 may be in contact with the entire surface of the bottom surface 24. The third portion 33 may be in contact with the first boundary 28 between the bottom surface 24 and the first side surface 23 and the second boundary 27 between the bottom surface 24 and the second side surface 25. The third portion 33 may be in contact with a part of each of the first side surface 23 and the second side surface 25. In other words, the third portion 33 may cover the entire surface of the bottom surface 24 and a part of each of the first side surface 23 and the second side surface 25.

Next, a second modification of the silicon carbide semiconductor wafer 100 according to the first embodiment will be described.

As shown in FIG. 5, the angle θ1 formed by the first region 21 and the first side surface 23 and the angle θ2 formed by the second region 22 and the second side surface 25 are larger than 90 ° and larger than 180 °. It may be small. The width of the groove 26 may increase from the bottom surface 24 toward each of the first region 21 and the second region 22. The third portion 33 may be in contact with the entire surface of the bottom surface 24. The third portion 33 may be in contact with the first boundary 28 between the bottom surface 24 and the first side surface 23 and the second boundary 27 between the bottom surface 24 and the second side surface 25. The third portion 33 may be in contact with a part of each of the first side surface 23 and the second side surface 25. In other words, the third portion 33 may cover the entire surface of the bottom surface 24 and a part of each of the first side surface 23 and the second side surface 25. In cross-sectional view, the width of the upper surface of the third portion 33 (the boundary surface between the third portion 33 and the bottom surface 24) may be smaller than the width of the lower surface of the third portion 33.

As shown in FIG. 6, a part of the silicon carbide single crystal substrate may be exposed from the second electrode 30 when viewed from the direction perpendicular to the first region 21. Specifically, a part of each of the first side surface 23 and the second side surface 25 may be exposed from the second electrode 30. When viewed from the direction perpendicular to the first region 21, the total area of the second electrode 30 is, for example, 90% or more of the total area of the second main surface 20. From another point of view, the portion where the silicon carbide single crystal substrate is exposed from the second electrode 30 when viewed from the direction perpendicular to the first region 21 is less than 10% of the total area of the second main surface 20. Is.

The total area of the second electrode 30 may be 95% or more or 98% or more of the total area of the second main surface 20 when viewed from the direction perpendicular to the first region 21. .. The total area of the second electrode 30 is the total area of the first portion 31, the second portion 32, and the third portion 33. The total area of the second main surface 20 viewed from the direction perpendicular to the first region 21 is the same as the total area of the second main surface 20 in which the groove 26 is not formed. When the second electrode 30 covers the entire second main surface 20 when viewed from the direction perpendicular to the first region 21, the total area of the second electrode 30 is the entire area of the second main surface 20. Equal to the area.

Next, a third modification of the silicon carbide semiconductor wafer 100 according to the first embodiment will be described.

As shown in FIG. 15, the groove 26 may have a honeycomb structure extending along each side of, for example, a hexagon on the second main surface 20. The groove 26 may have a hexagonal shape, for example, when viewed from a direction perpendicular to the first region 21. From another point of view, the groove 26 extends along a straight line parallel to, for example, the first straight line 201, extends along a straight line parallel to the third straight line 203, and is parallel to the fourth straight line 204. It extends along a straight line. The first straight line 201 extends, for example, along the <11-20> direction. Each of the third straight line 203 and the fourth straight line 204 extends along a direction equivalent to <11-20>. The fourth straight line 204 extends, for example, along the <-2110> direction. The third straight line 203 extends along the <1-210> direction, for example. The angle formed by any two straight lines in the first straight line 201, the third straight line 203, and the fourth straight line 204 is 120 °. In this case, since the groove directions are crystallographically equivalent, there is an advantage that the angle formed by the bottom surface 24 and each of the first side surface 23 and the second side surface 25 does not depend on the groove direction.

Next, a method for manufacturing the silicon carbide semiconductor wafer 100 according to the first embodiment will be described.
First, a step of preparing the silicon carbide substrate 1 is carried out. For example, the silicon carbide single crystal substrate 11 is prepared by using a sublimation method. The maximum diameter of the silicon carbide single crystal substrate 11 is, for example, 100 mm or more, preferably 150 mm or more. Next, an epitaxial layer is formed on the silicon carbide single crystal substrate. For example, CVD using a _{mixed gas of silane (SiH 4} ) and propane (C ₃ H ₈ ) as a raw material gas, hydrogen gas (H ₂ ) as a carrier gas, and ammonia (NH _{3) as a dopant gas.} A drift region is formed by epitaxial growth on the silicon carbide single crystal substrate 11 by the Chemical Vapor Deposition) method. The thickness of the drift region is, for example, 9 μm. The concentration of nitrogen atoms contained in the drift region is, for example, about ^{7 × 10 15} cm ^-3.

Next, an ion implantation step is performed. P-type impurities such as aluminum are ion-implanted into the surface of the drift region 12. As a result, the body region 13 in contact with the drift region 12 is formed. The thickness of the body region 13 is, for example, 0.9 μm. Next, n-type impurities such as phosphorus are ion-implanted into the body region 13. As a result, the source region 14 having an n-type conductive type is formed. The thickness of the source region 14 is, for example, 0.4 μm. The source region 14 constitutes the first main surface 10. The concentration of n-type impurities contained in the source region 14 is higher than the concentration of p-type impurities contained in the body region 13. Next, the contact region 18 is formed by ion-implanting a p-type impurity such as aluminum into the source region 14 (see FIG. 7).

Next, activation annealing is performed to activate the impurities ion-implanted into the silicon carbide substrate 1. The temperature of activation annealing is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C. The activation annealing time is, for example, about 30 minutes. The atmosphere of the activated annealing is preferably an inert gas atmosphere, for example, an Ar atmosphere.

Next, a step of forming a gate trench is carried out. For example, a mask 40 having an opening at a position where the gate trench 6 (FIG. 3) is formed is formed on the first main surface 10 composed of the source region 14 and the contact region 18. Using the mask 40, a part of the source region 14, a part of the body region 13, and a part of the drift region are removed by etching. As the etching method, for example, reactive ion etching, particularly inductively coupled plasma reactive ion etching can be used. Specifically, for example _{, inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF 6} ) or _{a mixed gas of SF 6} and oxygen (O ₂ ) as the reaction gas can be used. A side portion substantially perpendicular to the first main surface 10 and a bottom portion provided continuously with the side portion and substantially parallel to the first main surface 10 in the region where the gate trench 6 should be formed by etching. A recess is formed.

Next, thermal etching is performed in the recess. Thermal etching can be performed by heating with the mask 41 formed on the first main surface 10, for example, in an atmosphere containing a reactive gas having at least one kind of halogen atom. At least one or more halogen atoms contain at least one of a chlorine (Cl) atom and a fluorine (F) atom. The atmosphere contains, for example, chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), SF ₆ or carbon tetrafluoride (CF ₄ ). For example, heat etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas and setting the heat treatment temperature to, for example, 800 ° C. or higher and 900 ° C. or lower. The reaction gas may contain a carrier gas in addition to the chlorine gas and oxygen gas described above. As the carrier gas, for example, nitrogen gas, argon gas, helium gas, or the like can be used.

By the thermal etching, a gate trench 6 is formed on the first main surface 10 of the silicon carbide substrate 1 (see FIG. 8). The gate trench 6 is defined by a side surface 3 and a bottom surface 4. The side surface 3 is composed of a source region 14, a body region 13, and a drift region 12. The bottom surface 4 is composed of a drift region 12. The angle between the side surface 3 and the surface along the bottom surface 4 is, for example, 54.7 °. Next, the mask 40 is removed from the first main surface 10.

Next, a step of forming the gate insulating film 15 is carried out. For example, the silicon carbide substrate 1 is heated in an atmosphere containing oxygen, for example, at a temperature of 1300 ° C. or higher and 1400 ° C. or lower. As a result, a gate insulating film 15 is formed which is in contact with the drift region on the bottom surface 4, is in contact with the drift region, the body region 13 and the source region 14 on the side surface 3, and is in contact with the source region 14 on the first main surface 10. To.

After forming the gate insulating film 15 by thermally oxidizing the silicon carbide substrate 1, heat treatment (NO annealing) may be performed on the silicon carbide substrate 1 in a nitric oxide (NO) gas atmosphere. In NO annealing, the silicon carbide substrate 1 is held for about 1 hour under the conditions of, for example, 1100 ° C. or higher and 1300 ° C. or lower. As a result, nitrogen atoms are introduced into the interface region between the gate insulating film 15 and the body region 13. As a result, the formation of the interface state in the interface region is suppressed, so that the channel mobility can be improved. If a nitrogen atom can be introduced, a gas other than NO gas (for example, N ₂ O) may be used as the atmospheric gas. After NO annealing, Ar annealing using argon (Ar) as an atmospheric gas may be further performed. The heating temperature of Ar annealing is, for example, higher than the heating temperature of NO annealing. The Ar annealing time is, for example, about 1 hour. As a result, the formation of an interface state in the interface region between the gate insulating film 15 and the body region 13 is further suppressed.

Next, a step of forming the gate electrode 47 is carried out. For example, a gate electrode 47 in contact with the gate insulating film 15 is formed inside the gate trench 6. The gate electrode 47 is arranged inside the gate trench 6 and is formed on the gate insulating film 15 so as to face each of the side surface 3 and the bottom surface 4 of the gate trench 6. The gate electrode 47 is formed by, for example, an LPCVD (Low Pressure Chemical Vapor Deposition) method.

Next, a step of forming the interlayer insulating film 45 is formed. For example, the interlayer insulating film 45 is formed so as to cover the gate electrode 47 and contact the gate insulating film 15. Preferably, the interlayer insulating film 45 is formed by, for example, a chemical vapor deposition method. The interlayer insulating film 45 is made of, for example, a material containing silicon dioxide. Next, a part of the interlayer insulating film 45 and the gate insulating film 15 is etched so that an opening is formed on the source region 14 and the contact region 18. As a result, the contact region 18 and the source region 14 are exposed from the gate insulating film 15.

Next, a step of forming the first electrode 17 is carried out. Specifically, the source electrode 16 in contact with the source region 14 and the contact region 18 is formed on the first main surface 10. The source electrode 16 is formed by, for example, a sputtering method. The source electrode 16 is made of a material containing, for example, Ti, Al and Si. Next, alloying annealing is performed. Specifically, the source electrode 16 in contact with the source region 14 and the contact region 18 is held at a temperature of, for example, 900 ° C. or higher and 1100 ° C. or lower for about 5 minutes. As a result, at least a part of the source electrode 16 reacts with the silicon contained in the silicon carbide substrate 1 to silicide. As a result, the source electrode 16 that is ohmic-bonded to the source region 14 is formed. Next, the source wiring 19 that is electrically connected to the source electrode 16 is formed. The source wiring 19 is formed on the source electrode 16 and the interlayer insulating film 45. As a result, the first electrode 17 including the source electrode 16 and the source wiring 19 is formed (see FIG. 9).

Next, the back surface polishing step is carried out. Specifically, the silicon carbide substrate 1 is polished on the second main surface 20. Specifically, a part of the silicon carbide single crystal substrate 11 is removed by polishing. As a result, the silicon carbide single crystal substrate 11 is thinned (see FIG. 10). If the silicon carbide single crystal substrate 11 is sufficiently thin, this step is omitted.

Next, the step of forming the groove 26 is carried out. For example, a mask 41 having an opening is formed at a position where a groove 26 (see FIG. 3) is formed on the second main surface 20. A part of the silicon carbide single crystal substrate is removed by etching using the mask 41. As the etching method, for example, reactive ion etching, particularly inductively coupled plasma reactive ion etching can be used. Specifically, for example, inductively coupled plasma reactive ion etching using _{SF 6} or _{a mixed gas of SF 6} and O _{2 can be used as the reaction gas.} The region where the groove 26 should be formed by etching has a side portion substantially perpendicular to the second main surface 20 and a bottom portion provided continuously with the side portion and substantially parallel to the second main surface 20. A recess is formed.

Next, thermal etching is performed in the recess. Thermal etching can be performed by heating with the mask 41 formed on the second main surface 20, for example, in an atmosphere containing a reactive gas having at least one kind of halogen atom. At least one or more halogen atoms contain at least one of a chlorine atom and a fluorine atom. The atmosphere comprises, for example, Cl ₂ , BCl ₃ , SF ₆ or CF ₄ . For example, heat etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas and setting the heat treatment temperature to, for example, 800 ° C. or higher and 900 ° C. or lower. The reaction gas may contain a carrier gas in addition to the chlorine gas and oxygen gas described above. As the carrier gas, for example, nitrogen gas, argon gas, helium gas, or the like can be used.

Grooves 26 are formed on the second main surface 20 of the silicon carbide substrate 1 by the thermal etching (see FIG. 11). The grooves 26 are provided on the second main surface 20 in a grid pattern, for example. In a cross-sectional view, the first angle θ1 formed by the first region 21 and the first side surface 23 and the second angle θ2 formed by the second region 22 and the second side surface 25 are, for example, 90 ° or less. The first angle θ1 and the second angle θ2 may be, for example, 45 ° or more and 65 ° or less. The second main surface 20 is composed of, for example, a first region 21, a second region 22, a first side surface 23, a bottom surface 24, and a second side surface 25. The groove 26 is defined by a bottom surface 24, a first side surface 23, and a second side surface 25. Next, the mask 41 is removed from the second main surface 20.

The groove formation by the thermal etching may be carried out after the step of forming the first electrode 17, and may be carried out at the same time as the step of forming the gate trench 6 or before and after the step of forming the gate trench 6. When the back surface polishing process is not performed, the degree of freedom in the process of forming the groove 26 is increased.

Next, the step of forming the second electrode 30 is carried out. Specifically, the second electrode 30 is formed on the second main surface 20. The second electrode 30 includes, for example, a drain electrode. The drain electrode is made of, for example, a material containing NiSi. The material constituting the drain electrode is formed by, for example, sputtering. Next, laser annealing is performed on the material formed by sputtering. As a result, the material constituting the drain electrode is alloyed. Instead of alloying by laser annealing, alloying by heat treatment, for example, treatment by RTA (Rapid Thermal Annealing) may be performed.

The spot diameter of the laser annealing is smaller than the length of each side of the first portion 31 and the second portion 32. When the drain electrode is divided without forming the groove 26, a part of the drain electrode is etched to expose a part of the silicon carbide single crystal substrate. When the edge portion of the drain electrode is alloyed by laser annealing, the laser spot contains a material constituting the drain electrode and silicon carbide. The material constituting the drain electrode and silicon carbide have different reflectances with respect to the wavelength of the laser. Therefore, alloying is not uniform at the edge portion of the drain electrode. In the present embodiment, in a plan view, the drain electrode covers the entire surface of the second main surface 20, and the silicon carbide single crystal substrate is not exposed from the drain electrode. Therefore, in a plan view, the reflectance becomes uniform, and the drain electrode is uniformly alloyed.

The second electrode 30 includes a first portion 31 in contact with the first region 21, a second portion 32 in contact with the second region 22, and a third portion 33 in contact with the bottom surface 24. The third portion 33 is separated from each of the first portion 31 and the second portion 32. As described above, the silicon carbide semiconductor wafer 100 (see FIGS. 1 to 3) according to the first embodiment is manufactured. Although the case where the groove 26 and the gate trench 6 are formed in different steps has been described above, the groove 26 and the gate trench 6 may be formed at the same time.

Next, a method of measuring the electrical resistance (contact resistance) of the drain electrode will be described.
As shown in FIG. 12, the first portion 31 is physically separated from the second portion 32. The first terminal 51 is connected to the first portion 31. The second terminal 52 is connected to the second portion 32. The electrical resistance between the first portion 31 and the second portion 32 is measured, for example, using the two-terminal method. For example, the voltage between the first portion 31 and the second portion 32 is measured while passing a current from the first portion 31 to the second portion 32. The third portion 33 is separated from each of the first portion 31 and the second portion 32. Therefore, the current flows from the first portion 31 through the silicon carbide single crystal substrate to the second portion 32, but does not flow to the third portion 33. The electrical resistance of the first portion 31 and the second portion 32 may be measured by using the TLM (Transfer Length Method) method.

Next, the action and effect of the silicon carbide semiconductor wafer 100 according to the first embodiment will be described.
In the silicon carbide semiconductor wafer 100 according to the first embodiment, the first portion 31 is separated from the second portion 32. Therefore, the contact resistance between each of the first portion 31 and the second portion 32 and the silicon carbide substrate 1 can be measured. That is, quality control of each of the first portion 31 and the second portion 32 can be performed.

Further, in the silicon carbide semiconductor wafer 100 according to the first embodiment, the second electrode 30 includes a first portion 31 in contact with the first region 21 and a third portion 33 in contact with the bottom surface 24. As a result, a wider contact area between the second electrode 30 and the silicon carbide substrate 1 can be secured as compared with the case where the second electrode 30 is patterned by etching a part of the second electrode 30. .. Therefore, it is possible to suppress an increase in the contact resistance of the second electrode 30.

Further, in the silicon carbide semiconductor wafer 100 according to the first embodiment, the first angle θ1 and the second angle θ2 may be 45 ° or more and 65 ° or less. As a result, the width of the groove 26 becomes narrower toward the second main surface 20. Therefore, when the bonding material 7 is provided inside the groove 26, it is possible to prevent the bonding material 7 from peeling off from the silicon carbide substrate 1.

(Second Embodiment)
Next, the configuration of the silicon carbide semiconductor device 200 according to the second embodiment of the present disclosure will be described. The silicon carbide semiconductor device 200 according to the second embodiment is mainly different from the silicon carbide semiconductor wafer 100 according to the first embodiment in a configuration in which the silicon carbide semiconductor device 200 is divided into semiconductor chips and has a bonding material 7. Other configurations are substantially the same as those of the silicon carbide semiconductor wafer 100 according to the first embodiment. Hereinafter, a configuration different from that of the silicon carbide semiconductor wafer 100 according to the first embodiment will be mainly described.

As shown in FIG. 13, the silicon carbide semiconductor device 200 according to the second embodiment is, for example, a vertical MOSFET, and includes a silicon carbide substrate 1, a first electrode 17, a second electrode 30, and a bonding material 7. , A gate insulating film 15, a gate electrode 47, and an interlayer insulating film 45 are mainly provided. The second electrode 30 has, for example, a first portion 31, a second portion 32, a third portion 33, a fourth portion 34, a fifth portion 35, and a sixth portion 36. Each of the first portion 31, the second portion 32 and the third portion 33 is an ohmic electrode. Each of the fourth portion 34, the fifth portion 35 and the sixth portion 36 is a cover layer. The joining material 7 fills the groove 26. The joining material 7 may be in contact with the side surface of the first portion 31, the side surface of the second portion 32, and the side surface of the third portion 33. The joining material 7 connects the first portion 31, the second portion 32, and the third portion 33. The joining material 7 may be in contact with the first side surface 23 and the second side surface 25. The joining material 7 may be in contact with a portion of the bottom surface 24 of the groove 26 that is exposed from the third portion 33. The joining material 7 may be in contact with a part of the bottom surface 24, the first boundary 28, and the second boundary 27. The joining material 7 may be provided so as to cover the fourth portion 34, the fifth portion 35, and the sixth portion 36. The joining material 7 may be provided so as to face the drift region 12.

The joining material 7 electrically connects the first portion 31, the second portion 32, and the third portion 33. The bonding material 7 is a material having conductivity. The material of the bonding material 7 is not particularly limited, but is, for example, a solder material such as PbSn, SnAgCu, SnSb, SnCuNi, or a sintered material containing silver (Ag) and copper (Cu). The thickness 104 of the bonding material 7 on the fifth portion 35 may be larger than the thickness 101 of the third portion 33. The thickness 104 of the bonding material 7 on the fifth portion 35 may be larger than the total thickness 102 of the third portion 33 and the fifth portion 35. The thickness 104 of the bonding material 7 on the fifth portion 35 may be, for example, the depth 103 or more of the groove 26. The depth 103 of the groove 26 is, for example, 0.1 μm or more and 10 μm or less, and more preferably 0.2 μm or more and 5 μm or less. It is desirable that the depth 103 of the groove 26 is larger than the thickness of the third portion 33. The thickness 104 of the bonding material 7 on the fifth portion 35 is, for example, 100 μm or more and 1 mm or less.

Each of the fourth portion 34, the fifth portion 35 and the sixth portion 36 has, for example, a three-layer structure. Each of the fourth portion 34, the fifth portion 35, and the sixth portion 36 has, for example, a layer containing titanium (Ti), a layer containing nickel (Ni), and a layer containing gold (Au). .. A layer containing Ag may be used instead of the layer containing Au. Each material of the 4th part 34, the 5th part 35 and the 6th part 36 has adhesion to the bonding material, wettability of the solder material, reactivity with the solder material, temperature cycle, reliability of the power cycle test, etc. It is selected based on the creep characteristics that represent the deterioration of the solder material during evaluation. The thickness of the layer containing Ti is, for example, 250 nm. The thickness of the layer containing Ni is, for example, 200 nm. The thickness of the layer containing Au is, for example, 50 nm. The layer containing Ti may be in contact with each of the first portion 31, the second portion 32 and the third portion 33. The layer containing Au may be in contact with the bonding material 7.

Next, the configuration of a modified example of the silicon carbide semiconductor device 200 according to the second embodiment will be described.

As shown in FIG. 14, the second electrode 30 may be composed of a first portion 31, a second portion 32, a third portion 33, and a seventh portion 37. Each of the first portion 31, the second portion 32 and the third portion 33 is an ohmic electrode. The seventh portion 37 is a cover layer. The seventh portion 37 may be integrally configured. The seventh portion 37 is in contact with the first portion 31, the second portion 32, and the third portion 33. The seventh portion 37 may be in contact with the first side surface 23, the second side surface 25, and a part of the bottom surface 24.

The measurement of the electrical resistance of the ohmic electrode is performed after the ohmic electrode is formed and before the cover layer is formed. Therefore, the ohmic electrodes may be separated from each other, and the cover layer may be formed integrally. When the cover layers are integrally formed, the contact area between the cover layer and the bonding material is larger than when the cover layers are separated from each other. Therefore, the bonding material can be brought into good contact with the cover layer.

Next, a method for manufacturing the silicon carbide semiconductor device 200 according to the second embodiment will be described.
First, for example, the silicon carbide semiconductor wafer 100 (see FIGS. 1 to 3) is prepared by using the method for manufacturing the silicon carbide semiconductor wafer 100 according to the first embodiment.

Next, the step of forming the cover layer is carried out. Specifically, for example, by sputtering, a Ti layer is formed on the drain electrode. The thickness of the Ti layer is, for example, 250 nm. Next, for example, by sputtering, a Ni layer is formed on the Ti layer. The thickness of the Ni layer is, for example, 200 nm. Next, for example, by sputtering, an Au layer is formed. The thickness of the Au layer is, for example, 50 nm. As a result, the fourth portion 34 is formed on the first portion 31. A sixth portion 36 is formed on the second portion 32. A fifth portion 35 is formed on the third portion 33.

The shape of FIG. 13 can be formed under conditions of high parallelism of sputter atoms (conditions in which the mean free path in plasma becomes long), for example, under low gas pressure conditions. The ion beam sputtering method can also be applied to the formation of the shape shown in FIG. The shape of FIG. 14 can be formed under conditions where diffusion of sputtered atoms on the surface is promoted (high plasma energy, short mean free path), for example, high gas pressure, high grasshopper power, and high temperature. Is. Good coverage of the bottom surface 24 of the groove 26 can also be formed by CVD of the metal film.

Next, a step of forming the bonding material 7 is carried out. The joining material 7 is formed so as to fill the groove 26. As shown in FIG. 13, the joining material 7 is formed in contact with each of the fourth portion 34, the fifth portion 35, and the sixth portion 36, and in contact with the first side surface 23 and the second side surface 25. Alternatively, as shown in FIG. 14, it may be formed so as to cover the seventh portion 37. The material of the bonding material 7 is, for example, solder. Next, a dicing step is carried out. Specifically, the silicon carbide semiconductor wafer 100 is divided into a plurality of semiconductor chips. As a result, the silicon carbide semiconductor device 200 according to the second embodiment is manufactured.

Next, the operation and effect of the silicon carbide semiconductor device 200 according to the second embodiment will be described.
In the silicon carbide semiconductor device 200 according to the second embodiment, the first portion 31 is separated from the second portion 32. Therefore, the contact resistance between each of the first portion 31 and the second portion 32 and the silicon carbide substrate 1 can be measured. That is, quality control of each of the first portion 31 and the second portion 32 can be performed.

Further, in the silicon carbide semiconductor device 200 according to the second embodiment, the second electrode 30 includes a first portion 31 in contact with the first region 21 and a third portion 33 in contact with the bottom surface 24. As a result, a wider contact area between the second electrode 30 and the silicon carbide substrate 1 can be secured as compared with the case where the second electrode 30 is patterned by etching a part of the second electrode 30. .. Therefore, it is possible to suppress an increase in the contact resistance of the second electrode 30.

Further, in the silicon carbide semiconductor device 200 according to the second embodiment, the first angle θ1 and the second angle θ2 may be 45 ° or more and 65 ° or less. As a result, the width of the groove 26 becomes narrower toward the second main surface 20. Therefore, it is possible to prevent the bonding material 7 from peeling off from the silicon carbide substrate 1.

Further, in the silicon carbide semiconductor device 200 according to the second embodiment, the groove 26 is provided on the second main surface 20. Therefore, the contact area between the bonding material 7 and the second electrode 30 is larger than that in the case where the second electrode 30 is patterned without the groove 26 being provided on the second main surface 20. Therefore, when the chip is mounted, the adhesion between the bonding material 7 and the second electrode 30 is improved. As a result, it is possible to prevent the bonding material 7 from peeling from the second electrode 30. Further, the heat dissipation of the silicon carbide semiconductor device 200 can be improved.

In each of the above embodiments, the case where the silicon carbide semiconductor wafer 100 and the silicon carbide semiconductor device 200 have a MOSFET having a gate trench 6 has been described, but the silicon carbide semiconductor wafer 100 and the silicon carbide semiconductor device 200 have a gate trench. It is not limited to the case of having a MOSFET having. The silicon carbide semiconductor wafer 100 and the silicon carbide semiconductor device 200 may have, for example, a planar MOSFET. The silicon carbide semiconductor wafer 100 and the silicon carbide semiconductor device 200 may have, for example, an SBD (Schottky barrier diode), an IGBT (Insulated Gate Bipolar Transistor), or an SJ (Superjunction) structure. You may have a power semiconductor device having the above.

It should be considered that the embodiments disclosed this time are exemplary in all respects and not restrictive. The scope of the present invention is shown by the scope of claims rather than the above description, and it is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

1 Silicon Carbide Substrate 2 Silicon Carbide epitaxial layer 3 Sides 4, 24 Bottom surface 5 Flat part 6 Gate trench 7 Joint material 10 First main surface 11 Silicon carbide single crystal substrate 12 Drift region 13 Body region 14 Source region 15 Gate insulating film (insulation) film)
16 Source electrode 17 First electrode 18 Contact region 19 Source wiring 20 Second main surface 21 First region 22 Second region 23 First side surface 25 Second side surface 26 Groove 27 Second boundary 28 First boundary 30 Second electrode 31 First 1 part 32 2nd part 33 3rd part 34 4th part 35 5th part 36 6th part 37 7th part 40, 41 Mask 45 Interlayer insulating film 47 Gate electrode 51 1st terminal 52 2nd terminal 100 Silicon carbide semiconductor wafer 200 Silicon Carbide Semiconductor Device 201 1st Straight 202 2nd Straight 203 3rd Straight 204 4th Straight

Claims (12)

A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface,
The first electrode and the insulating film provided on the first main surface,
A second electrode provided on the second main surface is provided.
A groove is provided on the second main surface.
The second main surface includes a first region and a second region separated by the groove.
The groove is defined by a first side surface connected to the first region, a second side surface connected to the second region, and a bottom surface connected to each of the first side surface and the second side surface.
The second electrode includes a first portion in contact with the first region, a second portion in contact with the second region, and a third portion in contact with the bottom surface.
The third part is separated from each of the first part and the second part .
The first side surface, the second side surface, and the bottom surface have a planar shape.
A silicon carbide semiconductor wafer in which the first angle formed by the first side surface and the bottom surface and the second angle formed by the second side surface and the bottom surface are 45 ° or more and 65 ° or less. The silicon carbide semiconductor wafer according to claim 1, wherein the total area of the second electrode is 90% or more of the total area of the second main surface when viewed from a direction perpendicular to the first region. The silicon carbide semiconductor wafer according to claim 1 or 2 , wherein the first region and the second region are planes inclined at an off angle of less than 8 ° with respect to the (0001) plane or the (0001) plane. .. The first main surface is a surface inclined at an off angle of less than 8 ° with respect to the (000-1) surface or the (000-1) surface, according to any one of claims 1 to 3. Silicon Carbide Semiconductor Wafer. The silicon carbide semiconductor wafer according to any one of claims 1 to 4 , wherein the groove is hexagonal when viewed from a direction perpendicular to the first region. The silicon carbide semiconductor wafer according to any one of claims 1 to 4 , wherein the grooves are in a grid pattern when viewed from a direction perpendicular to the first region. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface,
The first electrode and the insulating film provided on the first main surface,
A second electrode provided on the second main surface is provided.
A groove is provided on the second main surface.
The second main surface includes a first region and a second region separated by the groove.
The groove is defined by a first side surface connected to the first region, a second side surface connected to the second region, and a bottom surface connected to each of the first side surface and the second side surface.
The second electrode includes a first portion in contact with the first region, a second portion in contact with the second region, and a third portion in contact with the bottom surface.
The third part is separated from each of the first part and the second part, and further
E Bei a bonding material for electrically connecting said first portion and said second portion and said third portion,
The first side surface, the second side surface, and the bottom surface have a planar shape.
A silicon carbide semiconductor device in which the first angle formed by the first side surface and the bottom surface and the second angle formed by the second side surface and the bottom surface are 45 ° or more and 65 ° or less. The silicon carbide semiconductor device according to claim 7 , wherein the total area of the second electrode is 90% or more of the total area of the second main surface when viewed from a direction perpendicular to the first region. The silicon carbide semiconductor device according to claim 7 , wherein the first region and the second region are planes inclined at an off angle of less than 8 ° with respect to the (0001) plane or the (0001) plane. .. The first main surface is a surface inclined at an off angle of less than 8 ° with respect to the (000-1) surface or the (000-1) surface, according to any one of claims 7 to 9. Silicon carbide semiconductor device. The silicon carbide semiconductor device according to any one of claims 7 to 10 , wherein the groove is hexagonal when viewed from a direction perpendicular to the first region. The silicon carbide semiconductor device according to any one of claims 7 to 10 , wherein the grooves are in a grid pattern when viewed from a direction perpendicular to the first region.

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