JP6867080B2 - Substrate for mounting semiconductor elements and its manufacturing method - Google Patents

Description

The present invention relates to a substrate for mounting a semiconductor element and a method for manufacturing the same.

In recent years, as represented by mobile phones, electronic devices have been rapidly reduced in size and weight, and semiconductor devices used in these electronic devices are also required to be smaller, lighter, and more sophisticated.
In particular, the thickness of the semiconductor device is required to be reduced, and the semiconductor in a mode in which the conductive substrate is finally removed from the semiconductor device using a lead frame processed with a metal material such as QFN (Quad Flat No-Lead). Devices have been developed.

For example, a resist mask with a predetermined pattern is formed on one side surface of the conductive substrate, a metal is plated on the conductive substrate exposed from the resist mask, and a die pad portion for mounting a semiconductor element and a semiconductor element. After forming an internal terminal to be connected to and a lead portion to function as an external terminal for connecting to an external device, a semiconductor element mounting substrate is formed by removing the resist mask, and the formed semiconductor element mounting substrate is formed. A semiconductor element is mounted on the device, and after wire bonding or flip chip connection, resin sealing is performed, the conductive substrate is removed from the resin-sealed resin encapsulation body, and the die pad portion and lead portion are exposed on the back surface of the encapsulating resin. To complete a thin semiconductor device.
According to this type of semiconductor device, the thickness of the semiconductor device can be reduced because the lead portion and the like are formed of the plating layer and the conductive substrate is removed.

By the way, in this type of semiconductor device, the degree of adhesion to the sealing resin such as the lead portion formed by the plating layer is low, so that the lead portion or the like falls off or separates from the sealing resin, and the semiconductor device is reliable. There is a problem that the sex is reduced.
Conventionally, techniques for thinning a semiconductor device while improving adhesion to a sealing resin are described in, for example, the following Patent Documents 1 and 2.

In the technique described in Patent Document 1, a substrate for mounting a semiconductor element is obtained by plating a metal so as to exceed the upper surface of a resist mask and forming an overhanging portion on the periphery of the upper end portion of a plating layer forming a die pad portion or a lead portion. When the resin is sealed, the overhanging portion is made to bite into the sealing resin so that the plating layer remains on the sealing resin side when the conductive substrate is peeled off from the resin encapsulant.
Further, in the technique described in Patent Document 2, by forming the cross-sectional shape of the opening of the resist layer into a trapezoidal shape by using scattered ultraviolet light, the cross-sectional shape of the plating layer forming the die pad portion and the lead portion becomes an inverted trapezoidal shape. The substrate for mounting the semiconductor element formed as described above is obtained so as to improve the adhesion with the sealing resin.

Japanese Patent No. 3626075 Japanese Patent No. 4508604

In recent semiconductor devices, there is an increasing demand for high-speed and high-integration of communication lines and communication devices required for IoT (Internet of Things) construction, and there are many for processing a large number of signals in one semiconductor device. Minimizing the package size is an indispensable requirement for the development of semiconductor devices in the future in order to diversify compatible devices by pinning and reducing and minimizing the weight and minimization of communication devices in which semiconductor devices are incorporated.

However, there is described in Patent Document 2 and a technique of plating a metal so as to exceed the upper surface of the resist mask described in Patent Document 1 to form an overhanging portion on the peripheral edge of the upper end portion of the plating layer forming the die pad portion and the lead portion. In addition, in the technology of forming the plating layer forming the die pad portion and lead portion of a thin semiconductor device so that the cross section has an inverted trapezoidal shape, the lead portions and the like are adjacent to each other in order to increase the number of pins. In order to narrow the distance between the lead portions and the like and to minimize the package size, it becomes difficult to make the boundary position for cutting into each semiconductor device after resin encapsulation as close as possible to the lead portions and the like.

The present invention has been made in view of the above-mentioned conventional problems. In a semiconductor device completed by mounting a semiconductor element and then sealing with a resin to remove a conductive substrate, the conductive substrate is removed after being sealed with a resin. In order to prevent the lead parts from falling off and peeling off from the sealing resin at times, etc., and to increase the number of pins, the distance between adjacent lead parts, etc. should be narrowed, and individual semiconductors after resin sealing should be used. An object of the present invention is to provide a semiconductor device mounting substrate and a method for manufacturing the same, which can minimize the package size by making the boundary position for cutting into an apparatus as close as possible to a lead portion or the like.

In order to achieve the above object, the semiconductor element mounting substrate according to the present invention is a semiconductor element mounting substrate having a plurality of substantially quadrangular prisms composed of plating layers forming at least a lead portion on the upper surface of the conductive substrate. , the entire side surface of the substantially square pillar each have, substantially perpendicular to the vertical plane relative to the upper surface of the conductive substrate has a length over the entire length in the height direction of the substantially square pillar, the It is characterized in that it has a length over the entire length in the height direction of the substantially quadrangular prism and is composed of an inclined surface inclined in a direction in which the upper surface of the substantially quadrangular prism is larger than the lower surface.

Further, in the substrate for mounting a semiconductor element of the present invention, at least one side surface of each of the four side surfaces of the substantially quadrangular prism is formed of the vertical surface, and the remaining side surface is formed of the inclined surface. It is preferable that it is.

Further, in the substrate for mounting a semiconductor element of the present invention, at least one side surface of each of the four side surfaces of the substantially quadrangular prism is formed of the vertical surface, and the remaining side surfaces are the vertical surface and the vertical surface. It is preferably composed of a surface having an inclined surface.

Further, in the substrate for mounting a semiconductor element of the present invention, it is preferable that each of the four side surfaces of each of the substantially quadrangular prisms is composed of a surface having the vertical surface and the inclined surface.

Further, in the substrate for mounting a semiconductor element of the present invention, it is preferable that each of the four side surfaces of the substantially quadrangular prism has the inclined surface at the corner portion.

Further, in the substrate for mounting a semiconductor element of the present invention, it is preferable that adjacent inclined surfaces formed at the corners of the four side surfaces of each of the substantially square pillars are formed flush with each other. ..

Further, in the semiconductor device mounting substrate of the present invention, at least one side surface having the vertical plane of the substantially quadrangular prism arranged in the vicinity of the boundary of one semiconductor device region is one. It is preferably oriented toward the boundary of the semiconductor device region.

Further, in the semiconductor element mounting substrate of the present invention, on the opposite side surfaces of the substantially square prisms adjacent to each other, one side surface of the substantially square pillars is formed by the vertical surface, and the other substantially fours. It is preferable that the side surface of the prism is composed of the inclined surface or the surface having the vertical surface and the inclined surface.

Further, the method for manufacturing a substrate for mounting a semiconductor element according to the present invention is a method for manufacturing a substrate for mounting a semiconductor element having a plurality of substantially square pillars composed of a plating layer forming at least a lead portion on the upper surface of the conductive substrate. A first resist layer that is exposed to light at the first wavelength on the upper surface of the conductive substrate, and a second wavelength that the first resist layer is not exposed to light on the first resist layer. A step of sequentially forming a second resist layer that is photosensitive at a predetermined wavelength containing at least the above, and forming a third resist layer that is photosensitive at the first wavelength on the lower surface of the conductive substrate. The first exposure is performed at a predetermined wavelength including at least the first wavelength to cure a region other than the predetermined region corresponding to the upper surface region of the substantially square pillar in the first and second resist layers, and the above. The entire region of the third resist layer is cured, then the second exposure is performed at the second wavelength, and at least a part of the uncured portion in the second resist layer is the substantially square column. Harden a region other than the predetermined region corresponding to the lower surface region of the substantially square pillar body, which is in the same position as the edge of the upper surface of the body and the other part is located inside the edge of the upper surface of the substantially square pillar body. Next, the uncured portion of the first and second resist layers is developed, and the unexposed portion of the first resist layer located immediately below the cured portion of the second resist layer by the second exposure. The uncured portion of the first and second resist layers is removed so that the portion is scraped and the lower surface of the first resist layer has an inclined surface inclined in a direction larger than the upper surface and remains. In addition, a third exposure is performed at a predetermined wavelength including at least the first wavelength, and the unexposed portion of the first resist layer remaining in the inclined shape is cured to form a resist mask for plating. , The plating process is performed using the resist mask for plating, and the entire side surface is a vertical surface substantially perpendicular to the upper surface of the conductive substrate and an inclined surface whose upper surface is inclined in a direction larger than the lower surface. It is characterized by having a step of forming a substantially square pillar body made of a plating layer composed of the above, and a step of removing the resist mask for plating.

According to the present invention, it is possible to prevent the lead portions from falling off and peeling off when the conductive substrate is removed, and to narrow the distance between adjacent lead portions and the like in order to increase the number of pins, and also to use a resin. A semiconductor device mounting substrate and a method for manufacturing the same can be obtained, which can minimize the package size by making the boundary position for cutting into each semiconductor device after sealing as close as possible to the lead portion or the like.

It is explanatory drawing which shows an example of the schematic structure of the substrate for mounting a semiconductor element which concerns on one Embodiment of this invention, (a) is a sectional view, (b) shows the state which sealed with the sealing resin after mounting a semiconductor element. FIG. 6C is a diagram showing a positional relationship between a boundary position for cutting into individual semiconductor devices and a lead portion or the like, and FIG. 3D is a diagram showing a state of being cut into individual semiconductor devices. FIG. 1 is an explanatory view showing an example of a substantially quadrangular prism forming a lead portion and the like in the substrate for mounting a semiconductor element according to the embodiment of FIG. 1, where FIG. 1A is a top view and FIG. 1B is a sectional view taken along the line CC of FIG. (c) is a cross-sectional view taken along the line DD of (a). FIG. 1 is an explanatory view showing another example of a substantially quadrangular prism forming a lead portion or the like in the substrate for mounting a semiconductor element according to the embodiment of FIG. 1, where (a) is a top view and (b) is an EE cross section of (a). The figure, (c) is the FF sectional view of (a). FIG. 1 is an explanatory view showing still another example of a substantially quadrangular prism forming a lead portion or the like in the substrate for mounting a semiconductor element according to the embodiment of FIG. 1, where (a) is a top view and (b) is GG of (a). The cross-sectional view, (c) is the HH cross-sectional view of (a). FIG. 1 is an explanatory view showing still another example of a substantially quadrangular prism forming a lead portion or the like in the substrate for mounting a semiconductor element according to the embodiment of FIG. 1, where (a) is a top view and (b) is I-I of (a). The cross-sectional view, (c) is the JJ cross-sectional view of (a). FIG. 1 is an explanatory view showing still another example of a substantially quadrangular prism forming a lead portion or the like in the substrate for mounting a semiconductor element according to the embodiment of FIG. 1, where (a) is a top view and (b) is KK of (a). The cross-sectional view, (c) is the LL cross-sectional view of (a). FIG. 1 is an explanatory view showing still another example of a substantially quadrangular prism forming a lead portion or the like in the substrate for mounting a semiconductor element according to the embodiment of FIG. 1, where (a) is a top view and (b) is MM of (a). The cross-sectional view, (c) is the NN cross-sectional view of (a). FIG. 1 is an explanatory view showing still another example of a substantially quadrangular prism forming a lead portion or the like in the substrate for mounting a semiconductor element according to the embodiment of FIG. 1, where (a) is a top view and (b) is OO of (a). The cross-sectional view, (c) is the PP cross-sectional view of (a). FIG. 1 is an explanatory view showing still another example of a substantially quadrangular prism forming a lead portion or the like in the substrate for mounting a semiconductor element according to the embodiment of FIG. 1, where (a) is a top view and (b) is QQ of (a). The cross-sectional view, (c) is the RR side view of (a). It is explanatory drawing which shows the semiconductor element mounting substrate applicable to the semiconductor element mounting substrate of embodiment of this invention, (a) is the top view of the semiconductor element mounting substrate of the type which mounts a semiconductor element by flip chip mounting. , (B) is a cross-sectional view of a semiconductor device manufactured by mounting a semiconductor element on the substrate for mounting a semiconductor element in (a), and (c) is a substrate for mounting a semiconductor element of a type in which the semiconductor element is mounted by wire bonding. (D) is a cross-sectional view of a semiconductor device manufactured by mounting a semiconductor device on a substrate for mounting a semiconductor device in (c), and (e) is a type of light in which an optical semiconductor device is mounted by wire bonding. The top view of the substrate for mounting a semiconductor element, (f) is a cross-sectional view of a lighting device manufactured by mounting the optical semiconductor element on the substrate for mounting the optical semiconductor element of (e). It is explanatory drawing which shows an example of the manufacturing process of the substrate for mounting a semiconductor element which concerns on embodiment of this invention. It is explanatory drawing which shows an example of the manufacturing process of the semiconductor device using the substrate for mounting a semiconductor element which concerns on embodiment of this invention. It is an explanatory view which shows the composition of the main part of the substrate for mounting a semiconductor element which concerns on a conventional example, and (a) is a figure which shows the positional relationship in the height direction of a resist mask and a plating layer at the time of forming a lead part and the like. b) is a diagram showing the shape of the lead portion, etc., (c) is a diagram showing the shape of the lead portion, etc., (c) is a semiconductor element mounting substrate shown in (b), and the semiconductor element is mounted on a sealing resin. The figure which shows the sealed state, (d) is the figure which shows the state which the conductive substrate was peeled off from the resin sealing body of (c). It is explanatory drawing which shows the main part structure of the substrate for mounting a semiconductor element which concerns on a conventional example, (a) is the figure which shows the state which formed the resist mask, (b) is the figure which shows the shape of the formed resist mask, ( c) is a diagram showing a state in which the substrate is etched, (d) is a diagram showing a state in which a plating layer is formed, (e) is a diagram showing the shape of a lead portion composed of the plating layer, and (e). (D) is a diagram showing a state in which the conductive substrate is peeled off and removed after the substrate for mounting the semiconductor element of (d) is sealed with a sealing resin. FIG. 14 is an explanatory view showing an example of a substantially quadrangular prism forming a lead portion or the like in a substrate for mounting a semiconductor element, in which (a) is a top view, (b) is a sectional view taken along the line AA of (a), and (c). Is a sectional view taken along line BB in (a). FIG. 14 is an explanatory view showing an example of a schematic configuration of a semiconductor element mounting substrate, (a) is a cross-sectional view, (b) is a view showing a state in which the semiconductor element is mounted and then sealed with a sealing resin, (c). Is a diagram showing a positional relationship between a boundary position for cutting into an individual semiconductor device and a lead portion or the like, and FIG. 3D is a diagram showing a state of being cut by each semiconductor device.

Prior to the description of the embodiment, the background leading to the derivation of the present invention and the action and effect of the present invention will be described.

FIG. 13 is an explanatory diagram showing a configuration of a main part of a substrate for mounting a semiconductor element using the technique described in Patent Document 1, and FIG. 13A is a height direction of a resist mask and a plating layer when forming a lead portion or the like. (B) is a diagram showing the shape of the lead portion, etc., (c) is a state in which the semiconductor element is mounted on the semiconductor element mounting substrate shown in (b) and sealed with a sealing resin. The figure shown in FIG. 6D is a diagram showing a state in which the conductive substrate is peeled off from the resin encapsulant of (c).

As shown in FIG. 13 (a), the substrate for mounting a semiconductor element using the technique described in Patent Document 1 is shown in FIG. 13 (b) by plating a metal so as to exceed the upper surface of the resist mask 51. As described above, the overhanging portion 52a is formed on the peripheral edge of the upper end portion of the plating layer 52 forming the die pad portion and the lead portion. Then, as shown in FIG. 13 (c), the semiconductor element 53 is mounted, the semiconductor element 53 and the plating layer 52 are connected by the bonding wire 54, and when the resin is sealed, the overhanging portion 52a is formed on the sealing resin 55. The plating layer 52 remains on the sealing resin 55 side when the conductive substrate 50 is peeled off from the resin sealing body by biting into the resin sealing body.
However, in the technique described in Patent Document 1, it is difficult to control the amount of metal plating so as to exceed the upper surface of the resist mask 51, all of the plating layers 52 to be formed do not have the same overhang length, and the overhang does not occur. The portion 52a becomes large and tends to be connected to the adjacent plating layer 52.
Moreover, in a semiconductor device using the technique described in Patent Document 1, in order to narrow the distance between adjacent lead portions and the like, and to cut into individual semiconductor devices after resin encapsulation in order to minimize the package size. In order to make the boundary position of the lead portion as close as possible to the lead portion or the like, it is necessary to form the plating layer 52 constituting the lead portion or the like thinner. However, when the plating layer 52 is made thinner, the width and thickness of the overhanging portion 52a become smaller. Therefore, the adhesion with the sealing resin 55 tends to decrease.
Further, when the overhanging portion 52a is formed by plating a metal so as to exceed the upper surface of the resist mask 51 as in the technique described in Patent Document 1, the resist mask 51 is removed when the overhanging portion 52a is formed large. At the time of plating, the resist tends to remain at the root of the overhanging portion 52, which tends to cause deterioration in quality.

14A and 14B are explanatory views showing a main configuration of a substrate for mounting a semiconductor element using the technique described in Patent Document 2, in which FIG. 14A is a diagram showing a state in which a resist mask is formed, and FIG. 14B is a formed resist. A diagram showing the shape of the mask, (c) a diagram showing a state in which the substrate is etched, (d) a diagram showing a state in which a plating layer is formed, and (e) a diagram showing a lead portion composed of a plating layer, etc. The figure which shows the shape, (f) is the figure which shows the state which the conductive substrate was peeled off after sealing the substrate for mounting a semiconductor element of (e) with a sealing resin. 15A and 15B are explanatory views showing an example of a substantially quadrangular prism forming a lead portion and the like in the substrate for mounting a semiconductor element of FIG. 14, where FIG. 15A is a top view and FIG. 15B is a sectional view taken along the line AA of FIG. (c) is a cross-sectional view taken along the line BB of (a). 16A and 16B are explanatory views showing an example of a schematic configuration of the semiconductor element mounting substrate of FIG. 14, where FIG. 16A is a cross-sectional view and FIG. 16B is a diagram showing a state in which the semiconductor element is mounted and then sealed with a sealing resin. (c) is a diagram showing the positional relationship between the boundary position for cutting into each semiconductor device and the lead portion and the like, and (d) is a diagram showing the state of being cut by each semiconductor device. In FIG. 16, 10 is a conductive substrate, 15 is a solder ball, 20 is a semiconductor element, and 30 is a sealing resin.

As shown in FIGS. 14 (a) to 14 (c), the substrate for mounting a semiconductor element using the technique described in Patent Document 2 uses scattered light to make the cross-sectional shape of the opening of the resist layer 61 trapezoidal. By forming the plating layer 62 forming the die pad portion and the lead portion, the plating layer 62 is formed in an inverted trapezoidal shape. The plating layer 62 formed in an inverted trapezoidal shape improves the adhesion to the sealing resin 63.
However, as shown in FIGS. 15 (a) to 15 (c), the metal layer 62 forming the die pad portion and the lead portion formed by the technique described in Patent Document 2 has four side surfaces more than the lower surface 62d. The upper surface 62c becomes an inclined surface 62b inclined in the increasing direction.
However, in the inclined surface 62b whose four side surfaces are inclined so that the upper surface 62c is larger than the lower surface 62d, for example, in the semiconductor element mounting substrate as shown in FIG. In the manufacture of semiconductor devices such as those shown in FIGS. 16 (b) to 16 (d), the boundary position for cutting into individual semiconductor devices after resin encapsulation is set as much as possible in the lead portion or the like. It becomes difficult to bring them closer.

That is, for example, in an attempt to reduce the size with reference to the surface (upper surface 62c) of the metal layer 62 forming the inverted trapezoidal die pad portion and lead portion as shown in FIGS. 15 (a) to 15 (c) on the semiconductor element mounting side. Then, as a result of the surface (lower surface 62d) on the side opposite to the semiconductor element mounting side narrowing from all sides to the entire side, the lower surface 62d becomes too small and it tends to be difficult to form itself.
On the other hand, even if an attempt is made to reduce the size with reference to the upper surface 62c of the metal layer 62 forming the inverted trapezoidal die pad portion or lead portion as shown in FIGS. 15 (a) to 15 (c), the upper surface is due to the inverted trapezoidal shape. As a result of 62c spreading from all sides to the entire side, the upper surface 62c cannot be reduced.
Therefore, in the semiconductor device mounting substrate described in Patent Document 2, which is composed of an inclined surface 62b whose four side surfaces are inclined so that the upper surface 62c is larger than the lower surface 62d, the upper surface 62c of the metal layer 62 is larger than the lower surface 62d. However, it is difficult to narrow the distance between adjacent lead portions, etc. due to the protrusion in the horizontal direction, and to make the boundary position for cutting into each semiconductor device after resin sealing as close as possible to the lead portions, etc. ..
Further, as described in Patent Document 2, individual semiconductor devices are cut into the vicinity of the lower surface 62c of the lead portion composed of the inclined surface 62b whose four side surfaces are inclined so that the upper surface 62c is larger than the lower surface 62d. When the boundary position for the lead portion is brought as close as possible, a part of the upper surface 62d of the lead portion is cut, and the plating layer constituting the lead portion is exposed from the cut surface of the semiconductor device. Moisture may infiltrate from the interface, which may greatly hinder the durability of the semiconductor device.

Further, in the technique described in Patent Document 2, scattered light is used to form the four side surfaces on an inclined surface inclined so that the upper surface 62c is larger than the lower surface 62d, but scattered light is used. In the technique of forming an inclined shape in the resist layer, the dimensional accuracy of the lower surface varies greatly and the accuracy becomes worse than in the case of forming a predetermined shape in the resist layer using parallel light. In particular, as the lead shape tends to become smaller due to the miniaturization and thinning of the semiconductor device, it is important to improve the dimensional accuracy of the lower surface, but the scattered light described in Patent Document 2 is used for the resist layer. It is difficult to fully meet this demand with the technique of forming an inclined shape.

However, the present inventors have examined these problems, and after trial and error, have improved the adhesion of the metal layer forming the lead portion or the like to the sealing resin, and at the same time, the distance between the adjacent lead portions or the like. For mounting semiconductor devices of the present invention, which can be narrowed and the package size can be minimized by making the boundary position for cutting into each semiconductor device after resin encapsulation as close as possible to the lead portion or the like. We have come to derive the substrate.

The semiconductor element mounting substrate of the present invention is a semiconductor element mounting substrate having a plurality of substantially quadrangular prisms made of a plating layer forming at least a lead portion on the upper surface of the conductive substrate. The entire side surface in the above has a length extending over the entire length in the height direction of the quadrangular prism, and extends over a vertical plane substantially perpendicular to the upper surface of the conductive substrate and a total length in the height direction of the quadrangular prism. It is composed of an inclined surface having a length and inclined in a direction in which the upper surface of a substantially quadrangular prism is larger than the lower surface.

Like the substrate for mounting a semiconductor element of the present invention, the entire side surface of each substantially quadrangular prism has a length over the entire length in the height direction of the substantially quadrangular prism with respect to the upper surface of the conductive substrate. If it is composed of a substantially vertical vertical surface and an inclined surface that has a length over the entire length in the height direction of the substantially quadrangular prism and is inclined in a direction in which the upper surface of the substantially quadrangular prism is larger than the lower surface, it is approximately four. The vertical plane, which has a length over the entire length in the height direction of the prism and is substantially perpendicular to the upper surface of the conductive substrate , narrows the distance between adjacent lead portions, etc., or is individually sealed with resin. The boundary position for cutting into the semiconductor device can be made as close as possible to the lead portion, etc., and at the same time, the upper surface has a length over the entire length in the height direction of the substantially quadrangular prism, and the upper surface is larger than the lower surface. Due to the inclined surface inclined in the above direction, the encapsulating resin can be bitten or caught by having a length over the entire length in the height direction of the substantially quadrangular prism , and the conductive substrate can be peeled off from the encapsulating resin. At that time, it is possible to prevent the lead portion from falling off from the sealing resin, and it is possible to improve the adhesion with the sealing resin.

Specifically, as in the present invention, the entire side surface of each substantially quadrangular prism has a length over the entire length in the height direction of the substantially quadrangular prism and is substantially perpendicular to the upper surface of the conductive substrate. If it is composed of a vertical surface and an inclined surface having a length over the entire length in the height direction of the substantially quadrangular prism and inclined in a direction in which the upper surface of the substantially quadrangular prism is larger than the lower surface, Patent Documents Unlike the technique described in 1, the shape can be controlled by arbitrarily setting the length of the side of the vertical surface, the angle of the inclined surface, etc. of the substantially quadrangular prism forming the lead portion or the like by the resist layer, and the overhanging surface can be controlled. There is no residue left at the base of the part. Then, by arranging the vertical surface on the side to be cut by each semiconductor device, the boundary position for cutting by each semiconductor device can be closer to the lead portion than the inclined surface. As a result, the package size of the semiconductor device can be reduced accordingly.

Further, unlike the technique described in Patent Document 2, in the side surface portion having a vertical surface, the distance between adjacent lead portions and the like is narrowed, and the boundary position for cutting into individual semiconductor devices after resin sealing is set. It is possible to bring it as close to the lead part as possible.

That is, for example, when trying to make the size smaller with respect to the upper surface of the substantially quadrangular prism, the lower surface of the substantially quadrangular prism does not narrow from all sides to the entire side, and the side of the lower surface of the substantially quadrangular prism that is in contact with the vertical surface is It doesn't narrow. Therefore, the lower surface does not become too small, and it is difficult to form it.
On the other hand, when trying to reduce the size based on the lower surface of the substantially quadrangular prism, the upper surface of the substantially quadrangular prism does not spread from all sides to the entire side, and the side of the upper surface of the substantially quadrangular prism that is in contact with the vertical surface does not spread. ..
Therefore, if the substrate for mounting a semiconductor element of the present invention is used, the distance between adjacent lead portions and the like can be narrowed by the length that the vertical surface of the quadrangular prism does not protrude in the horizontal direction, or after resin sealing. The boundary position for cutting into each of the semiconductor devices can be made as close as possible to the lead portion or the like.
Then, unlike the technique described in Patent Document 2, the lead portion or the like is formed by bringing the boundary position for cutting into each semiconductor device closer to the vicinity of the side surface having the vertical surface of the plating layer forming the lead portion or the like. , The substantially quadrangular prism composed of the plating layer is not exposed from the cut surface of the semiconductor device.

Further, unlike the technique described in Patent Document 2, the present invention has a length over the entire length in the height direction of a substantially quadrangular prism, and has a vertical surface substantially perpendicular to the upper surface of the conductive substrate. Therefore, a resist mask for plating for plating and forming a substantially quadrangular prism is formed by using parallel light and does not use scattered light. Therefore, when the scattered light as in the technique described in Patent Document 2 is used, the dimensional accuracy of the lower surface does not vary greatly and the accuracy does not deteriorate.

Then, in such a substrate for mounting a semiconductor element of the present invention, a first resist is formed on a first resist layer and a first resist layer which are exposed to light at a first wavelength on the upper surface of the conductive substrate. A second resist layer that is exposed to a predetermined wavelength including at least a second wavelength that is not exposed to light is sequentially formed, and a third resist layer that is exposed to light at a first wavelength on the lower surface of the conductive substrate. And the first exposure at a predetermined wavelength including at least the first wavelength to cure a region other than the predetermined region corresponding to the upper surface region of the substantially square pillar in the first and second resist layers. At the same time, the entire region of the third resist layer is cured, and then the second exposure is performed at the second wavelength, and at least a part of the uncured portion in the second resist layer is a substantially square pillar. The region other than the predetermined region corresponding to the lower surface region of the substantially square pillar body, which is in the same position as the upper surface edge of the above surface and the other part is located inside the upper surface edge of the substantially square pillar body, is cured, and then First, the uncured portion of the first and second resist layers was developed, and the uncured portion of the first resist layer located immediately below the cured portion of the second resist layer by the second exposure was scraped off to form the first resist layer. The uncured portion of the first and second resist layers is removed so that the lower surface of the resist layer of the resist layer has an inclined surface inclined in a direction larger than the upper surface and remains, and then at least the first wavelength is set. A step of forming a resist mask for plating by performing a third exposure at a predetermined wavelength including, and curing an unexposed portion of the first resist layer remaining in an inclined shape, and a plating process using the resist mask for plating. A substantially square pillar composed of a plating layer, the entire side surface of which is composed of a vertical surface substantially perpendicular to the upper surface of the conductive substrate and an inclined surface in which the upper surface is inclined in a direction larger than the lower surface. It can be manufactured by having a step of forming a body and a step of removing a resist mask for plating.

Therefore, according to the present invention, in a semiconductor device that is completed by sealing with a resin and removing a conductive substrate after mounting a semiconductor element, leads from the sealing resin at the time of resin sealing and removal of the conductive substrate, etc. In order to prevent the parts and the like from falling off and peeling off, and to increase the number of pins, the distance between adjacent lead parts and the like can be narrowed, and for cutting into individual semiconductor devices after resin sealing. A semiconductor device mounting substrate and a method for manufacturing the same can be obtained, which can minimize the package size by making the boundary position as close as possible to the lead portion or the like.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

FIG. 1 is an explanatory view showing an example of a schematic configuration of a semiconductor device mounting substrate according to an embodiment of the present invention, (a) is a cross-sectional view, and (b) is a semiconductor device mounted and then sealed with a sealing resin. A diagram showing a state, (c) is a diagram showing a positional relationship between a boundary position for cutting into an individual semiconductor device and a lead portion, etc., and (d) is a diagram showing a state of being cut into each semiconductor device. .. 2A and 2B are explanatory views showing an example of a substantially quadrangular prism forming a lead portion and the like in the substrate for mounting a semiconductor element according to the embodiment of FIG. 1, where FIG. 2A is a top view and FIG. 2B is CC of FIG. The cross-sectional view, (c) is the DD cross-sectional view of (a).

As shown in FIG. 1A, the semiconductor element mounting substrate of the present embodiment is a lead portion for connecting the conductive substrate 10 and the semiconductor element mounting and external devices arranged on the upper surface thereof. It has a plurality of substantially square pillars 11 made of a plating layer and the like. In the substrate for mounting a semiconductor element of the present embodiment, the lead portion and the like include a die pad portion in addition to the lead portion, but as will be described later, the die pad portion is included in the type in which the semiconductor element is mounted by flip chip mounting. There is no. Therefore, in the substrate for mounting the semiconductor element of the present embodiment, the substantially quadrangular prism 11 made of the plating layer forms at least a lead portion.
The conductive substrate 10 is a substrate on which a substantially quadrangular prism 11 made of a plating layer is formed on the upper surface, and is made of a conductive material so that the plating layer can be formed by electroplating. Has been done.
As shown in FIGS. 2 (a) to 2 (c), each substantially quadrangular prism 11 has an entire side surface having a length over the entire length of the substantially quadrangular prism 11 in the height direction, and is a conductive substrate. A direction in which the upper surface 11c of the substantially quadrangular prism 11 has a length over the entire length in the height direction of the substantially quadrangular prism 11 and a vertical surface 11a substantially perpendicular to the upper surface of the quadrangular prism 11 becomes larger than the lower surface 11d. It is composed of an inclined surface 11b inclined to the surface. More specifically, in the example shown in FIG. 2, one of the four sides of each substantially quadrangular prism 11 (the left side in FIG. 2A) is composed of the vertical surface 11a, and the rest. The three side surfaces (the upper and lower side surfaces and the right side surface in FIG. 2A) are formed by the inclined surface 11b.

In the substrate for mounting the semiconductor element of the present embodiment, the entire side surface of each substantially quadrangular prism 11 has a length over the entire length in the height direction of the substantially quadrangular prism 11, and is above the conductive substrate 10. It has a vertical surface 11a substantially perpendicular to the surface and a length over the entire length in the height direction of the substantially quadrangular prism 11, and is inclined in a direction in which the upper surface 11c of the substantially quadrangular prism 11 is larger than the lower surface 11d. As long as it is composed of the surface 11b, it is not limited to the configuration of the example shown in FIG.
For example, as shown in FIGS. 3 (a) to 3 (c), three side surfaces (upper and lower side surfaces and left side side surface in FIG. 3 (a)) are among the four side surfaces of each substantially quadrangular prism 11. , The vertical surface 11a, and the remaining one side surface (the right side surface in FIG. 3A) may be composed of the inclined surface 11b.
Further, for example, as shown in FIGS. 4 (a) to 4 (c), of the four side surfaces of each substantially quadrangular prism 11, two adjacent side surfaces (lower and left sides in FIG. 4 (a)). Side surface) may be composed of a vertical surface 11a, and the remaining two adjacent side surfaces (upper and right side surfaces in FIG. 4A) may be composed of an inclined surface 11b.
Further, for example, as shown in FIGS. 5 (a) to 5 (c), of the four side surfaces of each substantially quadrangular prism 11, two opposite side surfaces (upper and lower side surfaces in FIG. 5 (a)). ) May be composed of the vertical surface 11a, and the remaining two adjacent side surfaces (the left and right side surfaces in FIG. 5A) may be composed of the inclined surface 11b.

Further, in the substrate for mounting a semiconductor element of the present embodiment, each of the four side surfaces of each substantially quadrangular prism 11 may have a portion of a vertical surface 11a and a portion of an inclined surface 11b.
For example, as shown in FIGS. 6 (a) to 6 (c), all the corners of the four side surfaces of the substantially square pillars 11 of each substantially square pillar 11 are composed of inclined surfaces 11b, and other than the corners. Part may be composed of the vertical surface 11b.
Further, for example, as shown in FIGS. 7 (a) to 7 (c), on the diagonal line of one of the upper surface 11c and the lower surface 11d of the four side surfaces of the substantially quadrangular prism 11 of each substantially quadrangular prism 11. The located corners (upper right and lower left corners in FIG. 7A) may be formed by the inclined surface 11b. Further, as shown in FIG. 7A, adjacent inclined surfaces 11b formed at the corners may be formed flush with each other.
Further, for example, as shown in FIGS. 8 (a) to 8 (c), two side surfaces (the left and right side surfaces in FIG. 8 (a)) facing each other in the lateral direction are formed by the vertical surface 11a and are longitudinal. Two side surfaces facing in the direction (upper and lower side surfaces in FIG. 8A) may be composed of vertical surfaces 11a at both ends and inclined surfaces 11b between both ends.
Further, for example, as shown in FIGS. 9 (a) to 9 (c), two side surfaces (the left and right side surfaces in FIG. 9 (a)) facing each other in the lateral direction have both ends having vertical surfaces 11a and both ends. An inclined surface 11b may be formed between the portions, and two side surfaces (upper and lower side surfaces in FIG. 9A) facing each other in the longitudinal direction may be formed by the inclined surface 11b.

Next, an example of a semiconductor device using the semiconductor element mounting substrate according to the embodiment of the present invention will be described with reference to FIGS. 1 (c) to 1 (d). 1 (c) to 1 (d) are cross-sectional views showing an example of a schematic configuration of a semiconductor device using the semiconductor device mounting substrate shown in FIG. 1 (a).

In the semiconductor device shown in FIG. 1 (d), the semiconductor element 20 is mounted on the upper surface 11c of a substantially square column 11 forming a die pad portion or a lead portion of the semiconductor element mounting substrate shown in FIG. 1 (a). The electrode and the upper surface 11c of the substantially square pillar 11 forming the lead portion are connected, the semiconductor element mounting space is resin-sealed with the sealing resin 30, and then the conductive substrate 10 is removed (see FIG. 1 (b)). ), Cut into individual semiconductor devices (see FIG. 1 (c)). The lower surface 11d of the substantially quadrangular prism 11 forming the lead portion and the like exposed by removing the conductive substrate 10 serves as an external terminal for solder bonding with an external device.

The semiconductor element mounting substrate to which the substantially square column forming the lead portion of the present embodiment can be applied includes, for example, the electrodes of the semiconductor element 20 as shown in FIGS. 10 (a) and 10 (b). , A flip-tip mounting type that is directly bonded to the upper surface 11c of the substantially square pillar 11 forming the lead portion, or a substantially square pillar 11 that functions as a die pad portion as shown in FIGS. 10 (c) and 10 (d). A type in which a substantially square pillar 11 forming a lead portion is arranged around the', and a semiconductor element 20'is mounted by wire bonding, or as shown in FIGS. 10 (e) and 10 (f), wire bonding. It can be applied to any type equipped with an optical semiconductor element 20''.
In FIG. 10, 15 is a solder ball, 15'is a bonding wire, 16 is a die attach material, 30 is a sealing resin, and 31 is a reflector resin.

The semiconductor device mounting substrate of the present embodiment configured as described above is manufactured, for example, as follows. FIG. 11 is an explanatory diagram showing an example of a manufacturing process of a substrate for mounting a semiconductor element according to an embodiment of the present invention. For convenience, FIG. 11 shows a manufacturing process of a substrate for mounting a semiconductor element having a substantially quadrangular prism 11 forming a lead portion and the like shown in FIG. Further, for convenience, description of pretreatment and posttreatment including chemical washing and washing with water, which are carried out in each step of manufacturing, will be omitted.

First, the conductive substrate 10 is prepared (see FIG. 11A). The material of the conductive substrate 10 to be used is not particularly limited as long as conductivity can be obtained, but in general, a metal material such as Cu or a Cu alloy is used. When the conductive substrate is peeled off and removed, a SUS material may be used.
Next, on the upper surface of the conductive substrate 10, the first resist layer R1 exposed to the first wavelength, and on the first resist layer R1, the first resist layer R1 is not exposed to the second wavelength. A second resist layer R2 that is sensitive to a predetermined wavelength containing at least the above is sequentially formed, and a third resist layer R3 that is sensitive to the first wavelength is formed on the lower surface of the conductive substrate 10 (FIG. 11 (b)).
Next, the first exposure is performed at a predetermined wavelength including at least the first wavelength using a glass mask of a predetermined pattern, and corresponds to the upper surface region of the substantially quadrangular prism in the first and second resist layers R1 and R2. A region other than the predetermined region is cured, and the entire region of the third resist layer R3 is cured (see FIG. 11 (c)).
Next, the second exposure is performed at the second wavelength, and at least a part of the uncured portion in the second resist layer R2 coincides with the edge of the upper surface of the substantially quadrangular prism, and the other portion. Hardens a region other than the predetermined region corresponding to the lower surface region of the substantially quadrangular prism, which is located inside the edge of the upper surface of the substantially quadrangular prism (see FIG. 11 (d)).
Next, the uncured portions of the first and second resist layers R1 and R2 are developed, and the unexposed portion of the first resist layer R1 located immediately below the cured portion of the second resist layer R2 due to the second exposure is developed. The uncured portions of the first and second resist layers R1 and R2 are removed so that the portions are scraped and the lower surface of the first resist layer has an inclined surface inclined in a direction larger than the upper surface and remains. (See FIG. 11 (e)).
Next, a third exposure is performed at a predetermined wavelength including at least the first wavelength, and the unexposed portion of the first resist layer R1 remaining in the inclined shape is cured to form the resist mask 41 for plating (. (See FIG. 11 (f)).

Next, plating is performed using the resist mask 41 for plating, and the entire side surface has a length over the entire length in the height direction and becomes a vertical surface 11a substantially perpendicular to the upper surface of the conductive substrate 10. , A substantially square pillar 11 made of a plating layer is formed, which has a length over the entire length in the height direction and is composed of an inclined surface 11b in which the upper surface 11c is inclined in a direction larger than the lower surface 11d (FIG. 11). See (g)).
The type of plating is not particularly limited. For example, four-layer plating in which an Au plating layer, a first Pd plating layer, a Ni plating layer, and a second Pd plating layer are stacked in order on the upper surface of the conductive substrate 10, or further Au plating or Ag. Performs 5-layer or 6-layer plating in which plating or Ag plating and Au plating are laminated in this order. The plating thickness of the substantially quadrangular prism 11 forming the lead portion and the like is also not particularly limited, but considering the adhesion with the sealing resin, Ni plating, which is relatively hard and inexpensive, is applied from the lower side to the upper side. It is preferable to set the thickness so as to straddle. Further, on the outermost surface, a plating layer such as Pd, Ag, Au, which is a metal material having good bondability, is formed at the minimum necessary.

Next, the resist mask 41 for plating is removed (see FIG. 11 (h)).
As a result, the entire side surface of each substantially quadrangular prism 11 has a length over the entire length in the height direction of the substantially quadrangular prism 11, and is a vertical surface 11a substantially perpendicular to the upper surface of the conductive substrate 10. The present implementation is composed of an inclined surface 11b having a length over the entire length in the height direction of the substantially quadrangular prism 11 and inclined in a direction in which the upper surface 11c of the substantially quadrangular prism 11 is larger than the lower surface 11d. A substrate for mounting a semiconductor element in the form can be obtained.

The thickness of the substantially quadrangular prism 11 is set so that the upper surface 11c of the substantially quadrangular prism 11 is located at a position lower than the lower surface of the second resist layer R2. Preferably, the plating thickness is set so that the upper surface 11c of the substantially quadrangular prism 11 is located at a position of 1/2 to 4/5 of the thickness of the first resist layer R1.

Further, the inclination angle of the inclined surface in which the lower surface of the first resist layer R1 is inclined in the direction of becoming larger than the upper surface depends on the thickness of the first resist layer R1, the developing time in the developing process, the discharge pressure of the developing solution, and the like. Can be adjusted. Further, this inclination angle can be arbitrarily set with reference to the horizontal direction, but in consideration of the adhesion with the sealing resin, it is preferably set to 30 ° to 80 °, preferably 30 ° to 60 °. It is more preferable to set.

Next, the manufacture of a semiconductor device using the semiconductor device mounting substrate manufactured through the above-mentioned manufacturing process will be described. FIG. 12 is an explanatory diagram showing an example of a manufacturing process of a semiconductor device using the semiconductor device mounting substrate according to the embodiment of the present invention.

First, the semiconductor element 20 is mounted on a substantially square prism 11 forming a lead portion or the like on a substrate for mounting a semiconductor element. At that time, the semiconductor element 20 is adhesively fixed on the substantially quadrangular prism 11 forming the lead portion or the like by using, for example, a solder ball 15 (see FIG. 12A). Although it is possible to electrically bond the semiconductor element and the lead portion by the wire bonding method, in the example of FIG. 12, only an example in which the semiconductor element is mounted by flip-chip mounting will be described for convenience.
Next, the space region on which the semiconductor element 20 of the semiconductor element mounting substrate is mounted is sealed with the sealing resin 30 (see FIG. 12B).
Next, the conductive substrate 10 is removed from the resin encapsulant sealed with the resin encapsulation 30. The method for removing the conductive substrate 10 is to dissolve and remove the conductive substrate using a dissolution liquid. Alternatively, when the conductive substrate 10 is made of Al, a method of peeling and removing it is used (see FIG. 12 (c)).
Finally, the semiconductor device is cut into individual semiconductor devices (see FIG. 12 (d)) to complete the semiconductor device (see FIG. 12 (e)).

According to the substrate for mounting the semiconductor element of the present embodiment, the entire side surface of each substantially quadrangular prism 11 has a length over the entire length in the height direction of the substantially quadrangular prism 11 and is above the conductive substrate 10. A vertical surface 11a substantially perpendicular to the surface and an inclination in a direction in which the upper surface 11c of the substantially quadrangular prism 11 has a length over the entire length in the height direction of the substantially quadrangular prism 11 and is larger than the lower surface 11d. Since it is composed of the surfaces 11b, the lead portions and the like adjacent to each other are formed by the vertical surfaces 11a having a length over the entire length in the height direction of the substantially quadrangular prism 11 and substantially perpendicular to the upper surface of the conductive substrate 10. It is possible to narrow the distance between them and to make the boundary position for cutting into each semiconductor device after resin sealing as close as possible to the lead portion and the like, and at the same time, substantially in the height direction of the quadrangular prism 11. the inclined surfaces 11b of the upper surface 11c is inclined in the direction of increasing than the lower surface 11d has a length over the length, bite and caught a length over the entire length in the height direction of the substantially rectangular prism body 11 to the sealing resin 30 It is possible to prevent the lead portion from falling off from the sealing resin 30 when the conductive substrate 10 is peeled from the sealing resin 30, and the adhesion to the sealing resin 30 can be prevented. Can be improved.

Specifically, the entire side surface of each substantially quadrangular prism 11 is a vertical plane having a length over the entire length of the substantially quadrangular prism 11 in the height direction and substantially perpendicular to the upper surface of the conductive substrate 10. , The substantially quadrangular prism 11 has a length over the entire length in the height direction, and is composed of an inclined surface that is inclined in a direction in which the upper surface of the substantially quadrangular prism is larger than the lower surface. Unlike the described technique, the shape can be controlled by arbitrarily setting the length of the side of the vertical surface, the angle of the inclined surface, etc. of the substantially quadrangular prism forming the lead portion, etc. by the resist layer, and the overhanging portion can be controlled. There is no residue left on the root. Then, it is possible to approach by placing the side cutting the vertical plane 11a into individual semiconductor device, the boundary position for cutting into individual semiconductor devices than the inclined surface to the lead portion. As a result, the package size of the semiconductor device can be reduced accordingly.

Further, unlike the technique described in Patent Document 2, the boundary position on the side surface portion having the vertical surface 11a for narrowing the distance between adjacent lead portions and the like or for cutting into individual semiconductor devices after resin sealing. Can be brought as close as possible to the lead portion or the like.

That is, for example, when trying to reduce the size with reference to the upper surface 11c of the substantially quadrangular prism 11, the lower surface 11d of the substantially quadrangular prism 11 does not narrow from all sides to the entire side, and the lower surface 11d of the substantially quadrangular prism 11 The side in contact with the vertical surface 11a is not narrowed. Therefore, the lower surface 11d does not become too small, and it is difficult to form the lower surface 11d.
On the other hand, when the lower surface 11d of the substantially quadrangular prism 11 is tried to be reduced as a reference, the upper surface 11c does not spread from all sides over each side, and the side of the upper surface 11c in contact with the vertical surface 11a does not spread.
Therefore, if the substrate for mounting a semiconductor element of the present invention is used, the distance between adjacent lead portions and the like can be narrowed by the length that the vertical surface 11a of the substantially quadrangular prism 11 does not protrude in the horizontal direction, or the resin can be sealed. The boundary position for cutting into each semiconductor device after stopping can be made as close as possible to the lead portion or the like.
Then, unlike the technique described in Patent Document 2, the lead portion or the like is brought closer to the side surface of the plating layer 11 forming the lead portion or the like having the vertical surface 11a, so that the boundary position for cutting into each semiconductor device is brought closer to the side surface of the plating layer 11 forming the lead portion or the like. The substantially quadrangular prism 11 made of the plating layer is not exposed from the cut surface of the semiconductor device.

Further, according to the substrate for mounting a semiconductor element of the present embodiment, unlike the technique described in Patent Document 2, it has a length over the entire length of the substantially quadrangular prism 11 in the height direction and is above the conductive substrate 10. Since it has a vertical surface 11a that is substantially perpendicular to the surface of the above surface, a resist mask for plating for plating and forming a substantially quadrangular prism 11 is formed by using parallel light and does not use scattered light. Therefore, when the scattered light as in the technique described in Patent Document 2 is used, the dimensional accuracy of the lower surface does not vary greatly and the accuracy does not deteriorate.

Therefore, according to the present embodiment, in a semiconductor device that is completed by sealing with a resin and removing a conductive substrate after mounting a semiconductor element, it is possible to remove the conductive substrate from the sealing resin after sealing with the resin. In order to prevent the lead parts from falling off and peeling off, and to reduce the distance between adjacent lead parts in order to increase the number of pins, and to cut into individual semiconductor devices after resin sealing. It is possible to obtain a semiconductor device mounting substrate and a method for manufacturing the same, which can minimize the package size by making the boundary position of the semiconductor element as close as possible to the lead portion or the like.

Hereinafter, examples of the semiconductor device mounting substrate of the present invention will be described. For ease of understanding, the components corresponding to the components of the above-described embodiment are designated by the same reference numerals as those of the embodiment. Further, in the following examples, for convenience, a substrate for mounting a semiconductor element having a substantially quadrangular prism 11 shown in FIG. 2 was manufactured. The semiconductor element mounting substrate having the substantially quadrangular prisms 11 shown in FIGS. 3 to 9 can also be manufactured in the same manner.

Example 1
As the conductive base material 10, a SUS plate (SUS430) having a plate thickness of 0.2 mm was processed into a long plate having a width of 140 mm (see FIG. 11A). Next, a photosensitive dry film resist having a thickness of 0.040 mm, which is photosensitive at the first wavelength (365 nm), is attached as the first resist layer R1 on the upper surface of the conductive substrate 10 using a laminate roll. Attached. Next, on the first resist layer R1, as the second resist layer R2, the thickness is not exposed at the first wavelength and the first resist layer R1 is not exposed at the second wavelength (405 nm). A 0.025 mm photosensitive dry film resist was attached. Further, a photosensitive dry film resist having a thickness of 0.040 mm, which is photosensitive at the first wavelength (365 nm), was attached as a third resist layer R3 on the lower surface of the conductive substrate 10 with a laminate roll (). See FIG. 11 (b)).

Next, on the upper surface side of the conductive substrate 10, a predetermined region corresponding to a region of the upper surface 11c of a substantially square column 11 made of a plating layer, which forms a lead portion in the first and second resist layers R1 and R2, and the like. A glass mask having a pattern formed by opening a region other than the region and covering the other region, and a glass mask having a pattern forming a pattern of opening the entire region of the third resist layer R3 on the lower surface side are used as dry films. The resist is covered with ultraviolet light containing the first wavelength and the second wavelength, and the first exposure is performed on the region of the upper surface 11c of the substantially square pillar 11 in the first and second resist layers R1 and R2. A region other than the corresponding predetermined region was cured, and the entire region of the third resist layer R3 was cured (see FIG. 11 (c)). Next, a glass mask having a pattern formed to open a region other than a predetermined region corresponding to the lower surface region of the substantially quadrangular prism 11 is placed on the dry film resist, and a second ultraviolet light containing only the second wavelength is used. After exposure, at least a part of the uncured portion of the second resist layer R2 coincides with the edge of the upper surface 11c of the substantially quadrangular prism 11, and the other portion is substantially the same as the upper surface 11c of the quadrangular prism 11. A region other than the predetermined region corresponding to the region of the lower surface 11d of the substantially quadrangular prism 11 located inside the edge of the square pillar 11 was cured (see FIG. 11 (d)). At this time, the dry film in a part of the photosensitive area of the first resist layer R1 was exposed to only the first wavelength, so that it was in an unexposed state.

Then, using a sodium carbonate solution, a development process was performed to dissolve the uncured dry film resist that was not exposed to ultraviolet light by blocking the irradiation (see FIG. 11 (e)). By appropriately adjusting the development time, the discharge pressure of the developer, and the like, the inclination angle of the inclined surface formed in the uncured portion of the first resist layer R1 was set to be about 45 °. Then, a third exposure was performed with ultraviolet light containing the first wavelength and the second wavelength, and the unexposed portion remaining from the development of the first resist layer R1 was cured (see FIG. 11 (f)).

Next, the exposed surface of the conductive base material 10 from which the resist layer was removed and the openings were formed was electroplated (see FIG. 11 (g)). In order to form a substantially quadrangular prism composed of a plating layer forming a lead portion, Au plating was performed at about 0.02 μm , P d plating at 0.02 μm, Ni plating at 27 μm, and P d plating at 0.05 μm in that order. The thickness of the plating layer was set with approximately 2/3 of the first resist layer R1 as a guide.

Finally, the dry film resist was peeled off with a sodium hydroxide solution to obtain a substrate for mounting a semiconductor element according to Example 1 of the present invention (see FIG. 11 (h)).

Next, the semiconductor element 20 is mounted on the manufactured substrate for mounting the semiconductor element by flip-chip mounting, and a substantially square pillar 11 composed of a plating layer forming a lead portion with the semiconductor element 20 is connected by a solder ball 15 (FIG. 12). (See (a)), the space in which the semiconductor element 20 is mounted is sealed with the sealing resin 30 (see FIG. 12 (b)), and then the conductive base material 10 is peeled off and removed from the resin sealing body (see FIG. 12 (b)). See FIG. 12 (c)). Finally, the semiconductor device according to the first embodiment was completed by cutting to the size of a predetermined semiconductor device (see FIG. 12 (e)).

Comparative Example 1
In Comparative Example 1, in the resist coating step, a photosensitive dry film resist having a thickness of 0.025 mm was attached to both sides of the conductive substrate 10 using a laminate roll, and exposure development was performed. In the plating step, a plating layer was formed with a thickness (40 μm) exceeding that of the resist layer. As for other conditions, the substrate for mounting the semiconductor element and the semiconductor device were completed in the same manner as in Example 1.

Comparative Example 2
In Comparative Example 2, in the resist coating step, a photosensitive dry film resist having a thickness of 0.05 mm was applied to the upper surface of the conductive substrate 10 and a photosensitive dry film resist having a thickness of 0.025 mm was applied to the lower surface using a laminate roll. In the pasting and exposure steps, exposure was performed using scattered ultraviolet light, and then development was performed. By exposing with scattered ultraviolet light, the resist layer was in a semi-exposed state, and a trapezoidal resist mask was formed. In the plating step, the opening of the formed trapezoidal resist mask was plated to produce an inverted trapezoidal lead portion. Other conditions were the same as in Example 1, and the semiconductor element mounting substrate and the semiconductor device were completed.

Evaluation The semiconductor element mounting substrates of Example 1, Comparative Example 1 and Comparative Example 2 were evaluated using the following methods.

In the semiconductor element mounting substrate, the lead frame size of one unit is set to 70 mm x 250 mm, the inside is divided into 5 blocks, and the required size rail portion is set between the lead frame periphery and the blocks. The number of semiconductor element mounting parts that can be designed was compared. The comparison results are shown in Table 1.

As shown in Table 1, in the semiconductor element mounting substrate of Example 1, 1600 semiconductor devices could be arranged per block and 8000 semiconductor devices could be arranged per lead frame, but the semiconductors of Comparative Example 1 and Comparative Example 2 were arranged. In the element mounting substrate, the number of semiconductor devices that can be arranged was 1444 per block and 7220 per lead frame. The number of semiconductor devices that can be arranged on the semiconductor element mounting substrate of Example 1 is improved by 10.8% as compared with the number of semiconductor devices that can be arranged on the semiconductor element mounting substrates of Comparative Examples 1 and 2. It became. Further, in the size comparison per semiconductor device, the semiconductor device size of the semiconductor device mounting substrate of Example 1 is 4.8% as compared with the semiconductor device size of the semiconductor device mounting substrate of Comparative Examples 1 and 2. It can be reduced.

Further, in the resist peeling step of the manufacturing process of the substrate for mounting the semiconductor element, the presence or absence of the resist remaining defect was observed with a microscope 100 sheets at a time. As a result, no resist residue was generated on the semiconductor element mounting substrates of Example 1 and Comparative Example 2, but resist residue was observed on some lead portions of the semiconductor element mounting substrate of Comparative Example 1. Was done.

Further, in the step of mounting the semiconductor element using the semiconductor element mounting substrates of Example 1, Comparative Example 1 and Comparative Example 2 and sealing the resin, the conductive substrate is peeled off and removed, and the lead portion becomes the conductive substrate. The presence or absence of remaining defects was confirmed by microscopic observation.
As a result, the semiconductor element mounting substrates of Example 1, Comparative Example 1, and Comparative Example 2 are all good without any problem that the lead portion remains on the conductive substrate between the sealing resin and the conductive substrate. In Example 1, it was confirmed that sufficient adhesion with the sealing resin was ensured.

Although the preferred embodiments and examples of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments and examples, and does not deviate from the scope of the present invention. Various modifications and substitutions can be added to the examples.
For example, in the production of the semiconductor device mounting substrate of the first embodiment described above, a second resist layer that is not exposed to light at the first wavelength but is exposed to light at the second wavelength is used, but the second resist is used. As the layer, a layer that is sensitive to the first wavelength in addition to the second wavelength may be used.
Further, for example, in the production of the semiconductor device mounting substrate of the first embodiment described above, as the second resist layer, a layer that is sensitive to the first wavelength in addition to the second wavelength is used, and the first exposure is performed. As the wavelength, only the first wavelength may be used.
Further, for example, in the production of the semiconductor device mounting substrate of the first embodiment described above, only the first wavelength may be used as the third exposure wavelength.
That is, in the method for manufacturing a substrate for mounting a semiconductor element of the present invention, for example, as shown in Table 2 below, the photosensitive wavelengths of the first to third resist layers and the first to third exposure wavelengths are combined. Can be done.

The substrate for mounting a semiconductor element of the present invention and the manufacturing method thereof have a variety of compatible devices by increasing the number of pins for processing a large number of signals in one semiconductor device and reducing and minimizing the weight of the communication device in which the semiconductor device is incorporated. It is useful in fields where the minimum package size is required in order to achieve this.

10 Conductive substrate 11, 11'Approximately square pillar made of plated layer 11a Vertical surface 11b Inclined surface 11c Upper surface 11d Lower surface 15 Solder ball 15' Bonding wire 16 Resist material 20, 20' Semiconductor element 20'Optical semiconductor element 30 Stop resin 31 Reflector resin R1 First resist layer R2 Second resist layer R3 Third resist layer 41 Plating resist mask 51 Resist mask 52 Plating layer forming a die pad part and lead part 52a Overhanging part 53 Semiconductor element 54 Bonding wire 55 Encapsulation resin 61 Resist layer 62 Metal layer forming the die pad part and lead part 62b Inclined surface 62c Upper surface 62d Lower surface 63 Encapsulating resin

Claims (9)

In a substrate for mounting a semiconductor element, which has a plurality of substantially square prisms made of a plating layer, which form at least a lead portion, on the upper surface of the conductive substrate.
Entire side surface of the substantially square pillar each have, substantially perpendicular to the vertical plane relative to the upper surface of the conductive substrate has a length over the entire length in the height direction of the substantially square pillar, the generally For mounting a semiconductor element, which has a length over the entire length in the height direction of the quadrangular prism and is composed of an inclined surface in which the upper surface of the substantially quadrangular prism is inclined in a direction larger than the lower surface. substrate. The first aspect of claim 1, wherein at least one side surface of each of the four sides of the substantially quadrangular prism is formed of the vertical surface, and the remaining side surface is formed of the inclined surface. Substrate for mounting semiconductor elements. Of the four sides of each of the substantially quadrangular prisms, at least one side surface is composed of the vertical surface, and the remaining side surface is composed of a surface having the vertical surface and the inclined surface. The substrate for mounting a semiconductor element according to claim 1. The substrate for mounting a semiconductor element according to claim 1, wherein each of the four side surfaces of the substantially quadrangular prism is composed of a surface having the vertical surface and the inclined surface. The substrate for mounting a semiconductor element according to claim 4, wherein each of the four side surfaces of the substantially quadrangular prism has the inclined surface at a corner portion. The semiconductor device mounting substrate according to claim 5, wherein adjacent inclined surfaces formed at the corners of each of the four side surfaces of the substantially quadrangular prism are formed flush with each other. .. It is characterized in that at least one side surface of the substantially quadrangular prism having the vertical plane arranged near the boundary of one semiconductor device region faces the boundary direction of one semiconductor device region. The semiconductor device mounting substrate according to any one of claims 1 to 6. On opposite side surfaces of adjacent substantially square pillars, one side surface of the substantially square pillar is formed of the vertical surface, and the side surface of the other substantially square pillar is the inclined surface or the vertical surface. The substrate for mounting a semiconductor element according to any one of claims 1 to 3, wherein the substrate is composed of a surface having the inclined surface and the inclined surface. A method for manufacturing a substrate for mounting a semiconductor element, which has a plurality of substantially square prisms composed of plating layers, which form at least a lead portion on the upper surface of the conductive substrate.
A predetermined resist layer containing at least a first resist layer exposed to a first wavelength on the upper surface of the conductive substrate, and at least a second wavelength not exposed to the first resist layer on the first resist layer. A step of sequentially forming a second resist layer that is sensitive to a wavelength and forming a third resist layer that is sensitive to the first wavelength on the lower surface of the conductive substrate.
The first exposure is performed at a predetermined wavelength including at least the first wavelength to cure a region other than the predetermined region corresponding to the upper surface region of the substantially square pillar in the first and second resist layers, and the above. The entire region of the third resist layer is cured, then the second exposure is performed at the second wavelength, and at least a part of the uncured portion in the second resist layer is the substantially square column. Hardens a region other than the predetermined region corresponding to the lower surface region of the substantially square pillar body, which is in the same position as the edge of the upper surface of the body and the other part is located inside the edge of the upper surface of the substantially square pillar body. Next, the uncured portion of the first and second resist layers is developed, and the uncured portion of the first resist layer located immediately below the cured portion of the second resist layer due to the second exposure. The uncured portion of the first and second resist layers is removed so that the exposed portion is scraped and the lower surface of the first resist layer has an inclined surface inclined in a direction larger than the upper surface and remains. Next, a third exposure is performed at a predetermined wavelength including at least the first wavelength, and the unexposed portion of the first resist layer remaining in the inclined shape is cured to form a resist mask for plating. When,
Plating is performed using the resist mask for plating, and the entire side surface is a vertical surface substantially perpendicular to the upper surface of the conductive substrate and an inclined surface whose upper surface is inclined in a direction larger than the lower surface. The process of forming a substantially quadrangular prism composed of a plated layer,
The step of removing the resist mask for plating and
A method for manufacturing a substrate for mounting a semiconductor element.

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