JP6870962B2 - Semiconductor devices, communication devices and reset methods - Google Patents

Description

The present invention relates to semiconductor devices, communication devices and reset methods.

In wireless communication, for example, NFC (Near Field Communication), which is a non-contact wireless communication method, a transmission device that generates electromagnetic waves modulated by data and transmits data and a mutual induction phenomenon by an antenna coil are used. It is equipped with a receiving device that operates by receiving the electromagnetic waves generated by the transmitting device. The receiving device in such a communication method usually does not have a dedicated power source, and generates a power source from the received electromagnetic wave and supplies it to each circuit portion of the receiving device. Further, in such a communication type receiving device, a clock signal extracted from an electromagnetic wave received through an antenna may be used without providing a clock source for generating a clock signal used in each circuit portion.

In non-contact wireless communication as described above, when data is transmitted and received, reception is insufficient due to the mutual induction phenomenon of the antenna coils, for example, due to a large physical distance between the transmitting device and the receiving device. Exists. If the receiving device is operated in such a state, a communication abnormality such as an error in the received data may occur. Therefore, the receiving device is reset to a reset state until the receiving state becomes good, and the operation of the receiving device is stopped. It may be set aside.

The above reset operation will be described in more detail with reference to FIGS. 4 to 6. FIG. 4 shows a communication device 100 and a receiving device 110 according to a comparative example. As shown in FIG. 4, the receiving device 110 includes an antenna coil ACR, a voltage generating unit 116, a regulator 120, a clock extraction unit 124, a clock monitoring unit 126, an internal circuit 112, and a non-volatile memory 114. The internal circuit 112 is a circuit in which the receiving function of the receiving device 110 is mainly integrated. The non-volatile memory 114 is provided so that parameters and the like required for operating the receiving device 110 can be held even in a state where the power supply voltage is not supplied.

In the receiving device 110, the electromagnetic wave generated from the antenna coil ACT of the transmitting device 140 by the current i1 is received by the antenna coil ACR to generate the current i2. The voltage generation unit 116 generates a reception voltage using the current i2, and the reception voltage is converted by the regulator 120 into the internal circuit voltage used in the internal circuit 112. The clock extraction unit 124 extracts the clock from the current i2. The clock monitoring unit 126 monitors the clock extracted by the clock extraction unit 124, and generates a control signal for controlling the reset state of the internal circuit 112 according to the clock extraction state. That is, a signal for shifting the internal circuit 112 from the reset release state to the reset release state or a signal for shifting from the reset release state to the reset state is generated according to a predetermined condition.

The operation of the receiving device 110 will be described in more detail with reference to the timing chart shown in FIG. As shown in FIG. 5B, in this example, reception of the electromagnetic wave by the antenna coil ACR is started at time t1, generation of the received voltage is started in the voltage generation unit 116, and the reception voltage is rising. At the same time, as shown in FIG. 5A, clock extraction by the clock extraction unit 124 is started at time t1, and the amplitude of the clock signal is increasing.
In this example, a reset signal is issued at time t1, and the internal circuit 112 is in the reset state.

In the clock monitoring unit 126 of the receiving device 110 according to the comparative example, when the amplitude of the clock extracted by the clock extraction unit 124 becomes the threshold value Vtc3 or more as shown in FIG. 5A, that is, the clock pulse Cp3 is obtained. At the time t2, it is determined that the reception state by the antenna coil ACR has improved, and the reset state is released as shown in FIG. 5 (d). Then, as shown in FIG. 5E, the state of the internal circuit 112 transitions from the reset state to the operating state.

In the receiving device 110 according to the comparative example having the above configuration, the reception state by the antenna coil ACR is monitored by the clock monitoring unit 126, and the clock extraction state is set in advance in the clock monitoring unit 126 while the reception state is not sufficient. The internal circuit 112 is reset while the specified conditions are not satisfied. On the other hand, the reset is released when the reception state becomes good, that is, when the clock extraction state of the clock monitoring unit 126 satisfies a certain condition. In this way, the receiving device according to the comparative example suppresses malfunction until the receiving state becomes good.

On the other hand, as a prior art of a non-contact communication device, for example, a non-contact information system disclosed in Patent Document 1 is known. In the non-contact information system disclosed in Patent Document 1, when data is returned from a non-contact IC card to a reader / writer, the data should be returned to a logic circuit unit that can operate at a lower voltage than a non-volatile memory circuit unit. During the period when the data is returned, the lower limit voltage for reset detection used in the reset generation circuit is lowered as compared with the other periods. In the non-contact information system according to Patent Document 1, the communicable distance between the non-contact IC card and the reader / writer is extended by such a configuration, and the data from the non-contact IC card becomes the reader / writer. When replying, it is said that data can be sent and received stably even if the power supply voltage drops.

International Publication No. 2005/1010304

However, in the reset method of the receiving device 110 according to the comparative example, although the reception state is judged to be good by the clock monitoring unit 126 depending on the distance between the transmitting device 140 and the receiving device 110, the internal circuit It is assumed that the internal circuit voltage for operating the 112 has not risen sufficiently. That is, in the example shown in FIG. 5, the clock monitoring unit 126 determines that the reception state is good at time t2, but as shown in FIG. 5C, the internal circuit voltage is the threshold value of the internal circuit voltage (internal circuit). The minimum voltage required for normal operation) Vtv5 has not been reached. The internal circuit voltage reaches the threshold value Vtv5 at time t3.

The reset operation in the receiving device 110 will be described in more detail with reference to FIG.
In FIG. 6, the time Tr range shows the operation waveforms of each part before and after the transmitting device 140 and the receiving device 110 approach each other and the reception device 110 starts receiving. The range of the time Tr is basically the same operation as in FIG. On the other hand, the time Tf range shows the operation waveforms of each part before and after the transmission device 140 and the reception device 110 are separated from each other and the reception in the reception device 110 is stopped.

As described above, in the range of time Tr, the reset is released at time t2, and the internal circuit voltage reaches the threshold value Vtv5 at time t3. In other words, a sufficient internal circuit voltage is not obtained between the time t2 and the time t3, and as a result, as shown in FIG. 6 (e), the state of the internal circuit 112 is a state in which a malfunction can occur, that is, It is in an unstable state.

On the other hand, in the time Tf, it is important at what point the reception state is determined to be insufficient and the reset release state is set to the reset state. In this example, as shown in FIG. 6A, when the clock amplitude drops to the threshold value Vtc4 at time t5 (when the clock pulse Cp4 is generated), the internal circuit is shown in FIG. 6D. The reset signal is transitioning from the reset release state to the reset state. However, the internal circuit voltage is already smaller than the threshold value Vtv6 at time t4. Therefore, it is in an unstable state between the time t4 and the time t5.

As described above, in the receiving device 110 according to the comparative example in which the amplitude of the clock signal is monitored and the reset release state and the reset state are switched, there is a problem that there is an unstable state in which the internal circuit 112 may malfunction. There is. In the receiving device 110 equipped with the non-volatile memory 114, in addition to the problem of unstable operation, there is a concern that erroneous writing is performed to the non-volatile memory 114. That is, since the internal circuit voltage is insufficient during the unstable state shown in FIG. 6E, the control operation of the non-volatile memory 114 also becomes unstable, and erroneous data is written to the non-volatile memory 114. There is a possibility of destroying the data necessary for the operation of the receiving device 110. Recovery when the data in the non-volatile memory 114 is destroyed is generally very difficult.

In this respect, the non-contact information system according to Patent Document 1 also has a problem of the relationship between the decrease in the power supply voltage and the reset, but complicated operations such as data retention and change of the reset detection lower limit voltage are required. Further, in the non-contact type communication device, the transmitting device and the receiving device may reciprocate between a communicable distance and an impossible distance. In such a case, the voltage (received voltage) generated by the current i2 received by the antenna coil goes back and forth between a voltage sufficient and a voltage insufficient for the operation of the internal circuit, and is received. It is not reliable enough to directly monitor only the voltage and control the reset state. Further, in the non-contact information system according to Patent Document 1, the relationship between the generation of the clock signal and the reset is not considered.

The present invention has been made to solve the above-mentioned problems, a semiconductor device that receives a power supply and a clock supply for operating an internal circuit by an electromagnetic wave supplied by a transmission unit, and communication using the semiconductor device. In the device and the reset method, when the supply state of the power supply and the clock signal is monitored and the state of the internal circuit is controlled by the reset signal, the purpose is to suppress the malfunction of the internal circuit due to the control.

The semiconductor device according to the present invention is a semiconductor device that receives a power supply and a clock for operating an internal circuit by an electromagnetic wave supplied by a transmission unit, and resets the internal circuit or resets the internal circuit according to the power supply state. A power supply monitoring unit having a first threshold value of the voltage of the power supply for generating the first control signal to be in the reset release state and generating the first control signal, and the power supply monitoring unit according to the supply state of the clock. A clock monitoring unit having a second threshold value of the amplitude of the clock for generating the second control signal that puts the internal circuit in the reset state or the reset release state and generating the second control signal, and the first control signal. When both the control signal of the above and the second control signal are signals to be in the reset release state, the transition from the reset state of the internal circuit to the reset release state is executed, and the first control signal and the second control signal are described. When any of the second control signals is a signal to be in the reset state, it is a logical product circuit that executes a transition from the reset release state of the internal circuit to the reset state, and is the first threshold value and the second. It includes an execution unit that adjusts at least one of the threshold values of the above and changes the issuing order of the first control signal and the second control signal.

The communication device according to the present invention includes an antenna coil that receives electromagnetic waves supplied by the transmitting unit and the above-mentioned semiconductor device connected to the antenna coil.

In the reset method according to the present invention, the power supply and the clock for operating the internal circuit are supplied by the electromagnetic wave supplied by the transmission unit, and the internal circuit is set to the reset state or the reset release state according to the power supply state. A semiconductor including a power supply monitoring unit that generates a first control signal, and a clock monitoring unit that generates a second control signal that sets the internal circuit to a reset state or a reset release state according to the clock supply state. In a reset method by an apparatus, the power supply monitoring unit has a first threshold value of the voltage of the power supply for generating the first control signal, and the clock monitoring unit has the second control signal. A signal that has a second threshold value of the amplitude of the clock for generating the above clock, and causes both the first control signal and the second control signal to be in the reset release state by the execution unit that is a logical product circuit. In this case, the transition from the reset state of the internal circuit to the reset release state is executed, and when either the first control signal or the second control signal is a signal to be in the reset state, the above-mentioned The transition from the reset release state of the internal circuit to the reset state is executed, and at least one of the first threshold value and the second threshold value is adjusted to output the first control signal and the second control signal. It changes the order.

According to the present invention, a power supply and a clock signal are supplied in a semiconductor device that receives a power supply and a clock for operating an internal circuit by an electromagnetic wave supplied by a transmitter, and a communication device and a reset method using the semiconductor device. When the state is monitored and the state of the internal circuit is controlled by the reset signal, it is possible to suppress the malfunction of the internal circuit due to the control.

It is a block diagram which shows an example of the structure of the receiving apparatus which concerns on 1st Embodiment. It is a timing chart which shows the operation of the receiving apparatus which concerns on 1st Embodiment. It is a block diagram which shows an example of the structure of the receiving apparatus which concerns on 2nd Embodiment. It is a block diagram which shows the structure of the receiving apparatus which concerns on a comparative example. It is a timing chart which shows the operation of the receiving device which concerns on a comparative example. It is a timing chart explaining the problem of the receiving apparatus which concerns on a comparative example.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[First Embodiment]
The semiconductor device, the communication device, and the reset method according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a block diagram showing a receiving device 10 and a communication device 1 as semiconductor devices according to the present embodiment.

As shown in FIG. 1, the communication device 1 is composed of a receiving device 10 and a transmitting device 40. The receiving device 10 includes an antenna coil ACR, a voltage generating unit 16, a receiving voltage monitoring unit 18, a regulator 20, an internal circuit voltage monitoring unit 22, a clock extraction unit 24, a clock monitoring unit 26, an AND circuit 28, an internal circuit 12, and a non-volatile unit. It is configured to include the sex memory 14.
The internal circuit 12 is a circuit in which the receiving functions of the receiving device 10 are mainly integrated. The non-volatile memory 14 is provided so that parameters and the like required for operating the receiving device 10 are retained even when the power supply voltage is not supplied.

The transmitting device 40 is a device that transmits data to the receiving device 10, and includes an antenna coil ACT. In the transmission device 40, an electromagnetic wave is generated by passing a current i1 modulated by the transmission data through the antenna coil. In the receiving device 10, the antenna coil ACR receives this electromagnetic wave and generates a current i2.

The voltage generation unit 16 inputs the current i2 to generate a reception voltage that is a source of power for the reception device 10. The regulator 20 inputs a received voltage, converts it into an internal circuit voltage which is a voltage required for the operation of the internal circuit 12, and outputs the voltage. Further, the clock extraction unit 24 extracts a clock signal from the current i2 and supplies it to the internal circuit 12.

The receiving device 10 uses three reset signals, a reset signal A, a reset signal B, and a reset signal C, as reset signals (control signals for the reset operation) for controlling the reset operation of the internal circuit 12. The details of each reset signal will be described below. In the present embodiment, the "reset signal" is a signal that controls whether the connection destination of the reset signal is in the reset release state or the reset state. As an example, the low level (hereinafter, "L") is used. ) Indicates the reset state, and the high level (hereinafter, “H”) indicates the reset release state. Of course, this logic may be reversed, that is, L may be in the reset release state and H may be in the reset state.

The reception voltage monitoring unit 18 inputs the reception voltage generated by the voltage generation unit 16 to monitor the state, and generates a reset signal B according to a predetermined condition. In the present embodiment, as an example of predetermined conditions, when the potential of the reception voltage becomes the predetermined threshold Vtv1 or more, a signal for transitioning from the reset state to the reset release state is generated, and the potential of the reception voltage is generated. Is less than the predetermined threshold value Vtv2, a signal for transitioning from the reset release state to the reset state is generated. The thresholds Vtv1 and Vtv2 may be the same or different.

The internal circuit voltage monitoring unit 22 inputs the internal circuit voltage generated by the regulator 20 to monitor the state, and generates a reset signal A according to a predetermined condition. In the present embodiment, as an example of predetermined conditions, when the potential of the internal circuit voltage becomes the predetermined threshold value Vtv3 or more, a signal for transitioning from the reset state to the reset release state is generated, and the received voltage is measured. When the potential becomes less than the predetermined threshold value Vtv4, a signal for transitioning from the reset release state to the reset state is generated. The thresholds Vtv3 and Vtv4 may be the same or different.

The clock monitoring unit 26 inputs a clock signal extracted by the clock extraction unit 24 to monitor its state, and generates a reset signal C according to a predetermined condition. In the present embodiment, as an example of predetermined conditions, when the amplitude of the clock signal becomes the predetermined threshold value Vtc1 or more, a signal for transitioning from the reset state to the reset release state is generated, and the amplitude of the clock signal is generated. Is less than the predetermined threshold value Vtc2, a signal for transitioning from the reset release state to the reset state is generated. The thresholds Vtc1 and Vtc2 may be the same or different.

The AND circuit 28 takes the reset signal A, the reset signal B, and the reset signal C as inputs, and takes the logical product of them to generate the internal circuit reset signal. That is, when the receiving device 10 starts up (when the receiving device 10 and the transmitting device 40 are close to each other), all of the reset signal A, the reset signal B, and the reset signal C are in the reset release state (the present embodiment). Then, when it becomes H), an internal circuit reset signal (H in the present embodiment) instructing the reset release state is generated. The internal circuit reset signal is input to the internal circuit 12, and the internal circuit 12 is set to the reset release state by the internal circuit reset signal.

On the other hand, when the device of the receiving device 10 is shut down (when the receiving device 10 and the transmitting device 40 are separated from each other), any one of the reset signal A, the reset signal B, and the reset signal C is in the reset state (the present embodiment). Then, when it becomes L), an internal circuit reset signal (L in the present embodiment) indicating the reset state is generated. The internal circuit reset signal is input to the internal circuit 12, and the internal circuit 12 is set to the reset state by the internal circuit reset signal.

Next, the operation of the receiving device 10 will be described in more detail with reference to FIG. FIG. 2 shows the operation waveform of each part in a timing chart.

First, the operation of the receiving device 10 when the device starts up will be described. Due to the proximity of the receiving device 10 and the transmitting device 40, at time t1, the voltage generating unit 16 starts generating the received voltage (FIG. 2B), and the clock extracting unit 24 starts generating the clock. (Fig. 2 (a)). Since the reception voltage has risen, the regulator 20 has started to generate the internal circuit voltage (FIG. 2 (c)). At time t1, the receiving device 10 is reset.

After that, since the amplitude of the clock signal reached the threshold value Vtc1 at time t3 (the position of the clock pulse Cp1 in FIG. 2A), the clock monitoring unit 26 outputs a reset signal C instructing the reset release state (FIG. 2). 2 (f)). However, since the reset signal A and the reset signal B are in the reset state at this point (FIGS. 2 (d) and 2 (e)), the internal circuit reset signal output from the AND circuit 28 maintains the reset state (). FIG. 2 (g)).

After that, since the potential of the reception voltage reaches the threshold value Vtv1 at time t4, the reception voltage monitoring unit 18 outputs a reset signal B instructing the reset release state (FIG. 2 (e)). However, since the reset signal A is in the reset state at this point (FIG. 2 (d)), the internal circuit reset signal output from the AND circuit 28 maintains the reset state (FIG. 2 (g)).

After that, since the potential of the internal circuit voltage reached the threshold value Vtv3 at time t5, the reset signal A instructing the reset release state is output from the internal circuit voltage monitoring unit 22 (FIG. 2D). At this time, since the reset signal B and the reset signal C are signals instructing the reset release state (FIGS. 2 (e) and 2 (f)), the AND circuit 28 outputs a signal instructing the reset release state (FIGS. 2 (e) and 2 (f)). FIG. 2 (g)). In response to this, the state of the internal circuit 12 transitions from the reset state to the operating state (FIG. 2 (h)). The above is the operation of the receiving device 10 according to the present embodiment when the device starts up.

Subsequently, with reference to FIG. 2, the operation of the receiving device 10 when the device is shut down will be described. In the example shown in FIG. 2, since the receiving device 10 and the transmitting device 40 are separated from each other, the receiving voltage becomes less than the threshold value Vtv2 at time t6, so that the reset signal B instructing the reset state by the receiving voltage monitoring unit 18 Is output (Fig. 2 (e)). As a result, an internal circuit reset signal instructing the reset state is output from the AND circuit 28 (FIG. 2 (g)). In response to this, the state of the internal circuit 12 has changed from the operating state to the reset state (FIG. 2 (h)). That is, when any of the reset signals A, B, and C becomes a signal instructing the reset state, the AND circuit 28 outputs an internal circuit reset signal instructing the reset state.

After that, since the internal circuit voltage became less than the threshold value Vtv4 at time t7, the internal circuit voltage monitoring unit 22 outputs a reset signal A instructing the reset state (FIG. 2D).
After that, since the amplitude of the clock signal reached the threshold value Vtc2 at time t8 (the position of the clock pulse Cp2), the clock monitoring unit 26 outputs the reset signal C instructing the reset state (FIG. 2 (f)). However, the internal circuit reset signal is not affected by the transition of the reset signal A at time t7 and the transition of the reset signal C at time t8 (FIG. 2 (g)). Therefore, the state of the internal circuit 12 is changed to the reset state. It is maintained (Fig. 2 (h)).

As described in detail above, the receiving device 10 according to the present embodiment monitors the reception voltage generated by receiving the electromagnetic wave, the clock signal, and the internal circuit voltage obtained by converting the reception voltage, respectively. Three reset signals (reset signal A, reset signal B, and reset signal C) that control the reset state of the internal circuit are generated based on the monitoring result of. Then, when the device starts up, the internal circuit is set to the reset release state when all the reset signals become signals instructing the transition from the reset state to the reset release state. In other words, if the generated voltage and clock signal are not supplied enough to operate the internal circuit and the conditions required for the internal circuit to operate are not met, the reset will continue to be asserted ( By maintaining the reset state), the malfunction of the internal circuit is suppressed. On the other hand, when the device goes down, if any of the reset signals becomes a signal instructing the transition from the reset release state to the reset state, the internal circuit is changed from the reset release state to the reset state. In other words, when any one of the plurality of monitored conditions is no longer satisfied, the internal circuit is promptly reset to suppress the malfunction of the internal circuit.

According to the receiving device, the communication device, and the reset method according to the present embodiment having the above configuration, the reliability of the reset signal is enhanced, so that the supply state of the power supply and the clock signal is monitored and the internal circuit is used by the reset signal. When controlling the state of, the malfunction of the internal circuit due to the control is suppressed. In particular, since a highly reliable internal circuit voltage is supplied, it is possible to prevent erroneous writing to the non-volatile memory 14.

In the present embodiment, the reset state is set to the reset release state in the order of the reset signal C (clock signal), the reset signal B (received voltage), and the reset signal A (internal circuit voltage) when the device starts up, and the device goes down. Occasionally, a mode in which the reset release state is set to the reset state in the order of the reset signal B (received voltage), the reset signal A (internal circuit voltage), and the reset signal C (clock signal) has been described as an example. The issuing order is not limited to this, and may be an appropriate order according to the actual design conditions and the like. Further, the output order of each reset signal can be changed by adjusting the threshold values (Vtv1 to Vtv4, Vtc1 to Vtc2). These threshold values may be set by experiments, simulations, or the like, for example, at the design stage of the receiving device 10.

[Second Embodiment]
The receiving device 10a according to the present embodiment will be described with reference to FIG. The receiving device 10a is provided with a mask function for each reset signal (reset signal A, reset signal B, reset signal C) of the receiving device 10 according to the above embodiment. The communication device 1a according to the present embodiment is configured by the receiving device 10a and the transmitting device 40. The transmission device 40 is the same as the transmission device 40 of the communication device 1 according to the above embodiment. Although the non-volatile memory 14 is not shown in FIG. 3, the non-volatile memory 14 may be provided as needed and is not essential.

As shown in FIG. 3, the receiving device 10a is different in that the test unit 30, the OR circuits 32, 34, and 36 are added to the receiving device 10. Since there is no change in other configurations, the same reference numerals are given to similar configurations, and detailed description thereof will be omitted.

Here, not only in the receiving device 10a, but also in the semiconductor device, a test mainly performed on the internal circuit is performed, such as an evaluation for checking the performance of the semiconductor device before the product is shipped, or an inspection of the semiconductor device at the time of product shipment. Is common. However, in such a case, if the state of the internal circuit is controlled by the reset signal as in the receiving device 10 according to the above embodiment, the reset signal generation source (received voltage monitoring unit 18, internal circuit) is used one by one. It is inconvenient because it is necessary to reset the voltage monitoring unit 22 and the clock monitoring unit 26). Therefore, in the present embodiment, each reset signal can be masked at the time of testing.

The operation of the receiving device 10a will be described in more detail with reference to FIG. As shown in FIG. 3, the reset signal A from the internal circuit voltage monitoring unit 22 is input to the AND circuit 28 via the OR circuit 32. The reset signal B from the reception voltage monitoring unit 18 is input to the AND circuit 28 via the OR circuit 34. The reset signal C from the clock monitoring unit 26 is input to the AND circuit 28 via the OR circuit 36. Then, in the normal state (when the receiving device 10a is in operation), L is output from the test unit 30 to each of the OR circuits 32, 34, and 36. As a result, each of the OR circuits 32, 34, and 36 becomes equivalent to a simple gate, and the receiving device 10a operates in the same manner as the receiving device 10 according to the above embodiment.

On the other hand, at the time of the test, H is output from the test unit 30 to each of the OR circuits 32, 34, and 36. As a result, the outputs of the OR circuits 32, 34, and 36 are fixed to H, and the AND circuit 28 outputs a signal that puts H, that is, the internal circuit 12 in the reset release state. As a result, according to the receiving device 10a according to the present embodiment, the test can be performed in a state where the influence of each reset signal is eliminated at the time of the test (evaluation, inspection, etc.), and the test can be facilitated. There is. Here, a mode in which H is output from the test unit 30 to each of the OR circuits 32, 34, and 36 during the test has been described as an example, but the present invention is not limited to this, and depending on the test content, the OR circuits 32, 34, and 36 may be used. The form may be such that H is output to any of the above.

In each of the above embodiments, a mode in which a reception voltage, an internal circuit voltage, and a clock signal are monitored and a reset signal is generated from each of them has been illustrated and described, but the present invention is not limited thereto. For example, the received voltage or the internal circuit voltage and the clock signal may be monitored and a reset signal may be generated from each of them. On the contrary, if there are other conditions necessary for the operation of the internal circuit 12 (for example, a specific signal transmitted from the transmission device 40), the reset state is asserted until the conditions are satisfied. May be good.

1, 1a Communication device 10, 10a Reception device 12 Internal circuit 14 Non-volatile memory 16 Voltage generation unit 18 Reception voltage monitoring unit 20 Regulator 22 Internal circuit Voltage monitoring unit 24 Clock extraction unit 26 Clock monitoring unit 28 AND circuit 30 Test unit 32, 34, 36 OR circuit 40 Transmitter 100 Communication device 110 Receiver 112 Internal circuit 114 Non-volatile memory 116 Voltage generator 120 Regulator 124 Clock extraction unit 126 Clock monitoring unit 140 Transmitter ACT, ACR antenna coil, Cp1 to Cp4 clock pulse, i1, i2 current, Vtc1 to Vtc3, Vtv1 to Vtv6 threshold

Claims (8)

A semiconductor device that receives power and a clock to operate an internal circuit by electromagnetic waves supplied by a transmitter.
A first control signal for resetting or releasing the internal circuit is generated according to the power supply state, and a first threshold value of the voltage of the power supply for generating the first control signal is set. Power supply monitoring unit and
A second control signal for resetting or releasing the internal circuit is generated according to the supply state of the clock, and a second threshold value of the amplitude of the clock for generating the second control signal is set. With the clock monitoring unit
When both the first control signal and the second control signal are signals to be in the reset release state, the transition from the reset state of the internal circuit to the reset release state is executed, and the first control is performed. It is a logical product circuit that executes a transition from the reset release state of the internal circuit to the reset state when either the signal or the second control signal is a signal to be in the reset state, and is the first threshold value and the first threshold value. An execution unit that adjusts at least one of the second threshold values to change the emission order of the first control signal and the second control signal.
Semiconductor devices including. A voltage generator that generates the power supply from the electromagnetic waves,
A clock extraction unit that extracts the clock from the electromagnetic wave is further included.
The power supply monitoring unit generates the first control signal that puts the internal circuit in the reset release state when the voltage generated by the voltage generation unit becomes equal to or higher than the first threshold value.
According to claim 1, the clock monitoring unit generates the second control signal that puts the internal circuit in the reset release state when the amplitude of the clock extracted by the clock extraction unit becomes equal to or higher than the second threshold value. The described semiconductor device. A voltage conversion unit that converts the voltage of the power supply generated by the voltage generation unit into the operating voltage of the internal circuit, and
Further including an operating voltage monitoring unit that generates a third control signal that puts the internal circuit in a reset release state when the operating voltage converted by the voltage conversion unit becomes equal to or higher than a third threshold value.
When all of the first control signal, the second control signal, and the third control signal are signals to be in the reset release state, the execution unit is in the reset release state from the reset state of the internal circuit. The semiconductor device according to claim 2, which performs the transition to. The power supply monitoring unit generates the first control signal that resets the internal circuit when the voltage generated by the voltage generation unit becomes less than the fourth threshold value.
When the amplitude of the clock extracted by the clock extraction unit becomes less than the fifth threshold value, the clock monitoring unit generates the second control signal for resetting the internal circuit, and generates the operating voltage. When the operating voltage becomes less than the sixth threshold value, the monitoring unit generates the third control signal that resets the internal circuit.
When any of the first control signal, the second control signal, and the third control signal is a signal to be in the reset state, the execution unit is in the reset state from the reset release state of the internal circuit. The semiconductor device according to claim 3, which executes the transition to. Before SL first control signal, the second control signal, and each of said third control signal is a semiconductor device according to claim 3 or claim 4 which is a binary digital signal. The first control signal, the second control signal, and any one of claims 3 to 5, further comprising an invalidation unit that invalidates the generation of at least one of the third control signals. Semiconductor device. An antenna coil that receives electromagnetic waves supplied by the transmitter and
The semiconductor device according to any one of claims 1 to 6, which is connected to the antenna coil.
Communication equipment including. The electromagnetic waves supplied by the transmitter receive power and clock to operate the internal circuit, and generate a first control signal that puts the internal circuit in the reset state or the reset release state according to the power supply state. A reset method by a semiconductor device including a power supply monitoring unit for generating a second control signal for setting the internal circuit to a reset state or a reset release state according to a clock supply state, and a clock monitoring unit for generating a second control signal.
The power supply monitoring unit has a first threshold value of the voltage of the power supply for generating the first control signal.
The clock monitoring unit has a second threshold value of the amplitude of the clock for generating the second control signal.
When both the first control signal and the second control signal are signals to be in the reset release state by the execution unit which is a logical product circuit, the internal circuit is shifted from the reset state to the reset release state. Is executed, and when either the first control signal or the second control signal is a signal to be in the reset state, the transition from the reset release state of the internal circuit to the reset state is executed, and the first control signal is executed. A reset method in which at least one of the threshold value 1 and the second threshold value is adjusted to change the issuing order of the first control signal and the second control signal.

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