JP6871997B2 - Switch drive, light emitting device, vehicle - Google Patents

Description

The present invention relates to a switch drive device, and a light emitting device and a vehicle using the switch drive device.

FIG. 18 is an application diagram showing a first conventional example of a vehicle. The vehicle A100 of the first conventional example includes a battery A110, a power switch A120, a controller A130, and a light emitting device A140 (turn lamp, etc.). The controller A130 controls the simple point extinguishing of the light emitting device A140 by turning on / off the power switch A120 to conduct / cut off the power supply path from the battery A110 to the light emitting device A140.

On the other hand, in recent years, by turning on and off a plurality of light emitting elements at arbitrary timings, the area of the lighting area is increased or decreased, or the lighting area is moved so as to flow through the lighting area (so-called sequential turn function or sequential turn function). , Dynamic indicator function) has been put into practical use for in-vehicle light emitting devices.

FIG. 19 is an application diagram showing a second conventional example of the vehicle. The vehicle A200 in column (a) has a battery A210, a power switch A220, a controller A230, and a light emitting device A240. The light emitting device A240 is provided with the above-mentioned sequential lighting function, and is a light emitting element driving device A241 (1) to (m), a light emitting element A242 (1) to (m), and a light emitting element driving device A241 (1). ) To (m), a driver power supply A244 for supplying power to the light emitting element driving devices A241 (1) to (m), and a microcomputer power supply A245 for supplying power to the microcomputer A243. ..

On the other hand, in the vehicle A200 in column (b), the microcomputer A243, the driver power supply A244, and the microcomputer power supply A245 are deleted from the light emitting device A240, and the microcomputer A250, the driver power supply A260, and the microcomputer are replaced. The power supply A270 is provided outside the light emitting device A240.

FIG. 20 is an application diagram showing a third conventional example of the vehicle. The vehicle A300 in column (a) has a battery A310, a power switch A320, a controller A330, and a light emitting device A340. The light emitting device A340 has the above-mentioned sequential lighting function, and is a light emitting element driving device A341, m series of light emitting elements A342 (1) to (m), and light emitting elements A342 (1) to (m). It includes a switch drive device A343 that switches between short-circuit and non-short-circuit, a microcomputer A344 that controls the switch drive device A343, and a microcomputer power supply A345 that supplies power to the microcomputer A344 and the switch drive device A343.

On the other hand, in the vehicle A300 in column (b), the above-mentioned microcomputer A344 and the power supply A345 for the microcomputer are deleted from the light emitting device A240, and the microcomputer A350 and the power supply A360 for the microcomputer are provided outside the light emitting device A340. It is configured.

As an example of the prior art related to the above, Patent Document 1 can be mentioned.

Japanese Unexamined Patent Publication No. 2008-091311

Certainly, the sequential lighting type light emitting device (second conventional example or third conventional example) improves the design and safety of the vehicle as compared with the simple lighting type light emitting device (first conventional example). be able to. For example, by turning on the turn signals in sequence according to the turning direction of the vehicle, it becomes easier for pedestrians and other vehicles to intuitively recognize the traveling direction of the own vehicle.

However, in the light emitting device A240 of the second conventional example, m light emitting element driving devices A241 (1) to (m) are provided one-to-one for every m light emitting elements A242 (1) to (m). .. Therefore, the number of parts is increased, the board area is increased, and the power consumption efficiency is deteriorated.

Further, in the light emitting device A240 of the second conventional example, a microcomputer A243 (or A250) for controlling m light emitting element driving devices A241 (1) to (m) is required. Therefore, not only the driver power supply A244 (or A260) but also the microcomputer power supply A245 (or A270) is required, and software design must be performed.

Further, in the light emitting device A240 of the second conventional example, at least m control lines are required to transmit a control signal from the microcomputer A243 (or A250) to the light emitting element driving devices A241 (1) to (m). It was. Therefore, particularly when the microcomputer A250 is provided outside the light emitting device A240, the number of harnesses is increased, and the amount of work such as EMC [electromagnetic compatibility] test measures and abnormality mode verification is increased accordingly.

In the case of the light emitting device A340 of the third conventional example, the drive current can be supplied from the single light emitting element driving device A341 to the light emitting elements A342 (1) to (m) in series with each other. Compared with the example, it is possible to reduce the number of parts and the board area.

However, the light emitting device A340 of the third conventional example still requires the microcomputer A344 (or A350) for controlling the switch drive device A343, and the same problems as those of the second conventional example remain.

The invention disclosed in the present specification is a switch drive device capable of realizing sequential lighting control of light emitting elements without requiring microcomputer control in view of the above-mentioned problems found by the inventors of the present application. Another object of the present invention is to provide a light emitting device and a vehicle using the same.

The switch drive device disclosed in the present specification receives a plurality of channel switch elements connected in parallel to a plurality of light emitting elements included in an in-vehicle light emitting device, and a power-on to the device. The configuration (first configuration) includes a logic unit that automatically starts a series of switch drive sequences so as to sequentially switch the on / off state of each switch element in a predetermined pattern.

The switch drive device having the first configuration may have a configuration (second configuration) further including a start delay unit for arbitrarily setting the start delay time of the switch drive sequence using an external element.

Further, in the switch drive device having the first or second configuration, the logic unit refers to the light emitting element drive device outside the device after the operation indefinite period of each switch element elapses and before the start of the switch drive sequence. Therefore, it is preferable to have a configuration (third configuration) in which a current supply start trigger is output to each light emitting element.

Further, the switch drive device having any of the first to third configurations further includes a frequency setting unit for arbitrarily setting the operating frequency of the switch drive sequence using an external element (fourth configuration). It is good to set it to.

Further, in the switch drive device having any of the first to fourth configurations, the logic unit outputs a standby release trigger to another switch drive device after the switch drive sequence is completed (fifth). (Structure of).

Further, in the switch drive device having any of the first to fifth configurations, the logic unit may be configured to determine the number of light emitting element lights according to the external terminal voltage (sixth configuration).

Further, in the switch drive device having any of the first to sixth configurations, the logic unit turns off all the switch elements at once in addition to the sequential lighting mode in which each switch element is sequentially driven according to the switch drive sequence. It is preferable to have a configuration (seventh configuration) in which all lighting modes are implemented.

Further, in the switch drive device having the seventh configuration, the logic unit executes the switch drive sequence in synchronization with the first clock signal in the sequential lighting mode, while the first clock in the full lighting mode. The switch drive sequence may be performed in synchronization with the second clock signal having a higher frequency than the signal (eighth configuration).

Further, the switch drive device having the eighth configuration is necessary for the operation of the driver unit for driving the switch elements of the plurality of channels, the charge pump unit for supplying the boosted voltage to the driver unit, and the charge pump unit. It is preferable to have an oscillator unit for generating an internal clock signal, and to use the internal clock signal as the second clock signal (nineth configuration).

Further, in the switch drive device having any of the seventh to ninth configurations, the logic unit receives a hazard signal from the outside of the device, or when an abnormality in the switch drive sequence is detected. In addition, it is preferable to have a configuration (10th configuration) in which all the switch elements are turned off at the same time in the all lighting mode.

Further, the switch drive device having any of the first to tenth configurations is configured to further include a watchdog timer for monitoring an abnormality in the start delay time or the operating frequency of the switch drive sequence (11th configuration). Good.

Further, the light emitting device disclosed in the present specification includes a plurality of light emitting elements, a light emitting element driving device that generates a driving current for each light emitting element, and a switch drive having any of the above-mentioned first to eleventh configurations. It has a configuration (12th configuration) including the device.

In the light emitting device having the twelfth configuration, the plurality of light emitting elements may be a light emitting diode or an organic EL element (13th configuration), respectively.

Further, the light emitting device having the twelfth or thirteenth configuration may be mounted on a vehicle as a headlamp module, a turn lamp module, or a rear lamp module (fourth configuration).

Further, the vehicle disclosed in the present specification has a configuration (15th configuration) having a light emitting device having any of the above 12th to 14th configurations.

In the vehicle having the fifteenth configuration, the light emitting device has a configuration (16th configuration) used as at least one of a head lamp, a day / night traveling lamp, a tail lamp, a stop lamp, and a turn lamp. Good.

According to the invention disclosed in the present specification, a switch drive device capable of realizing sequential lighting control of light emitting elements without requiring microcomputer control, and a light emitting device and a vehicle using the switch drive device are provided. Is possible.

Application diagram showing an overall configuration example of a vehicle equipped with a light emitting device Block diagram showing an example of the internal configuration of a switch drive device Timing chart showing an example of switch drive sequence work Circuit diagram showing an example of the internal configuration of the start-up delay unit Timing chart showing an example of startup delay operation Circuit diagram showing an example of the internal configuration of the frequency setting unit Application diagram showing an example of multi-stage connection of a switch drive device Timing chart showing an example of multi-stage cooperation operation Diagram for explaining problems in multi-stage connection of switch drive device Timing chart showing an example of using the startup delay difference A table showing the relationship between the SEL terminal voltage and the number of light emitting element lights Application diagram showing an example of setting the number of lights using the SEL terminal Timing chart to explain all lighting modes Application diagram showing connection variations of HAZ terminals Timing chart showing an example of watchdog timer operation External view of the vehicle equipped with the light emitting device External view of in-vehicle lamp module Application diagram showing the first conventional example of a vehicle Application diagram showing a second conventional example of a vehicle Application diagram showing a third conventional example of a vehicle

<Overall configuration>
FIG. 1 is an application diagram showing an overall configuration example of a vehicle X equipped with a light emitting device 1. The vehicle X of this configuration example includes a light emitting device 1, a battery 2, power switches 3 and 4, and a controller 5.

The light emitting device 1 is a turn lamp or a hazard lamp that blinks when the vehicle X turns left or right, changes lanes, or has a hazard.

The battery 2 is a power source for the vehicle X, and a lead storage battery or the like is preferably used.

The power switches 3 and 4 are connected in parallel between the light emitting device 1 and the battery 2, respectively, and are turned on / off under the control of the controller 3.

The controller 5 controls the power switch 3 on / off according to the operation of the turn lever, and also controls the power switch 4 on / off according to the pressing of the hazard button. For example, when the light emitting device 1 is a right turn turn lamp, the controller 5 periodically turns on / off the power switch 3 while the turn lever is tilted in the right turn direction to intermittently turn on / off the light emitting device 1. Power is supplied. On the other hand, when the light emitting device 1 is a turn lamp for turning left, the controller 5 periodically turns on / off the power switch 3 while the turn lever is tilted in the left turning direction to intermittently turn on / off the power switch 1. Power is supplied. When the hazard button is pressed, the controller 5 periodically turns the power switch 4 on / off to turn on / off the power switch 4 regardless of whether the light emitting device 1 is a right turn turn signal lamp or a left turn signal lamp. Intermittent power supply to 1. Further, the controller 5 also has a function of monitoring the abnormality flag of the light emitting device 1 (the FAIL terminal voltage of the switch drive device 10) and notifying the driver of the abnormality.

<Light emitting device>
Subsequently, the internal configuration of the light emitting device 1 will be described with reference to FIG. The light emitting device 1 includes a switch driving device 10, a light emitting element driving device 20, a light emitting element group 30, and various discrete components (resistors R1 to R3, capacitors C1 to C5, diodes D1 to D3).

The switch drive device 10 operates by receiving an input voltage Vin from the battery 2, and switches between short-circuiting and non-short-circuiting of the light-emitting diodes LEDs 1 to LED8 forming the light-emitting element group 30 (so-called matrix switch driver IC). ). The switch drive device 10 has a plurality of external terminals (VIN terminal, CNT terminal, HAZ terminal, VREG terminal, SETDLY terminal, SETCLK terminal, SET terminal, SEL1 terminal) as means for establishing an electrical connection with the outside of the device. ~ SEL3 terminal, FAIL terminal, CMPLT terminal, SG terminal, VCP terminal, CH0 terminal ~ CH8 terminal, CNT terminal).

The light emitting element driving device 20 operates by receiving an input voltage Vin from the battery 2, and generates a driving current Id of the light emitting element group 30 (light emitting diodes LEDs 1 to LED 8) (so-called LED [light emitting diode]). ] Driver IC). The light emitting element drive device 20 monitors the SG terminal voltage (corresponding to the current supply start trigger) of the switch drive device 10 and waits for the start of supply of the drive current Id until the operation indefinite period of the switch drive device 10 elapses. It has a function.

The light emitting element group 30 is a series light emitting body (so-called LED string) including a plurality of light emitting elements (up to eight light emitting diodes LEDs 1 to LED 8 in this figure) connected in series between the light emitting element driving device 20 and the ground end. ). When the light emitting diode LEDs 1 to 8 are viewed individually, they can be understood as a single light emitting diode element, or as a light emitting element aggregate in which a plurality of light emitting diode elements are combined in series or in parallel. You can also do it.

Next, the connection state of each of the various discrete components and the external terminals of the switch drive device 10 will be described. The anode of the diode D1 is connected to the first end of the power switch 3. Each anode of the diodes D2 and D3 is connected to the first end of the power switch 4. The second ends of the power switches 3 and 4 are connected to the positive end of the battery 2. Each cathode of the diodes D1 and D2 is connected to the VIN terminal of the switch drive device 10 and is also connected to the power supply end of the light emitting element drive device 20. The cathode of the diode D3 is connected to the HAZ terminal.

The capacitor C1 is connected between the VIN terminal and the ground end. The capacitor C2 is connected between the VREG terminal and the ground end. The capacitor C3 is connected between the SETDLY terminal and the ground end. The capacitor C4 is connected between the SETCLK terminal and the ground end. The capacitor C5 is connected between the VCP terminal and the CH8 terminal.

The resistor R1 is connected between the SET terminal and the ground end. The resistor R2 is connected between the VIN terminal and the FAIL terminal. The resistor R3 is connected between the VREG terminal and the SG terminal.

Both the CH0 terminal and the GND terminal of the switch drive device 10 are connected to the cathode (grounded end) of the light emitting diode LED1. The CH (k) terminals (where k = 1, 2, ..., 7) of the switch drive device 10 are connected to the anode of the light emitting diode LED (k) and the cathode of the light emitting diode LED (k + 1), respectively. The CH8 terminal of the switch drive device 10 is connected to the anode of the light emitting diode LED8.

The CNT terminal of the switch drive device 10 is connected to the VIN terminal. Both the SEL1 terminal to the SEL3 terminal are connected to the ground end. The CMPLT terminal is in the open state. The significance of these connection states will be clarified in the following explanations.

By the way, the switch drive device 10 does not require any control signal from the microcomputer when sequentially controlling the lighting of the light emitting diodes LEDs 1 to 8 (details will be described later). Therefore, unlike the conventional configuration (see FIGS. 19 and 20), it is not necessary to provide a microcomputer or a power supply for the microcomputer, so that the number of parts of the light emitting device 1 can be reduced. Further, since the number of harnesses connected to the light emitting device 1 can be significantly reduced, the set design can be facilitated, and the amount of work such as EMC test measures and abnormality mode verification can be reduced.

In the following, the internal configuration and operation of the switch drive device 10 capable of performing the same sequential lighting control as in the conventional case without requiring microcomputer control will be described in detail with reference to the drawings.

<Switch drive device>
FIG. 2 is a block diagram showing an example of the internal configuration of the switch drive device 10. The switch drive device 10 of this configuration example includes a switch unit 100, a driver unit 110, a logic unit 120, an internal regulator unit 130, a UVLO [under voltage lock out] unit 140, a current setting unit 150, and an oscillator unit. 160, frequency setting unit 170, start delay unit 180, first watchdog timer unit 190, second watchdog timer unit 200, selector unit 210, charge pump unit 220, open / short detection unit 230. And, including. For convenience of illustration, the arrangement of the external terminals is partially different in FIGS. 1 and 2, but the external terminals having the same name correspond to each other.

The switch unit 100 includes switch elements SW1 to SW8 having a plurality of channels (8 channels in this figure). The switch elements SWx (where x = 1, 2, ..., 8) are connected between the CH (x-1) terminal and the CH (x) terminal, respectively. Therefore, when the light emitting diode LEDx is externally attached between the CH (x-1) terminal and the CH (x) terminal, the switch element SWx is connected in parallel to the light emitting diode LEDx. Therefore, during the ON period of the switch element SWx, both ends of the light emitting diode LEDx are short-circuited, so that the light emitting diode LEDx cannot be lit. On the other hand, during the off period of the switch element SWx, both ends of the light emitting diode LEDx are not short-circuited, so that the light emitting diode LEDx can be turned on.

The driver unit 110 includes drivers DRV1 to DRV8 that drive the switch elements SW1 to SW8 in response to an instruction from the logic unit 120. The drivers DRV1 to DRV8 operate by receiving a boost voltage Vcp from the charge pump unit 220.

As its main function, the logic unit 120 receives power on to the switch drive device 10 (more accurately, the UVLO signal Sublo has reached the logic level at the time of canceling the power reduction), and each switch element has a predetermined pattern. It has a function to automatically start a series of switch drive sequences so that the ON / OFF states of SW1 to SW8 are sequentially switched. The logic unit 120 has various functions other than the above, and the details thereof will be described later.

The internal regulator unit 130 lowers the input voltage Vin applied to the VIN terminal to generate a desired constant voltage Vreg (for example, 5V), and outputs this to the VREG terminal. As the internal regulator unit 130, an LDO [low drop out] regulator or a switching regulator can be preferably used.

The UVLO unit 140 monitors both (or one of) the input voltage Vin and the constant voltage Vreg to generate a UVLO signal Sublo, and outputs this to the logic unit 140. The UVLO signal Sublo becomes the logical level (for example, high level) at the time of power reduction cancellation when the input voltage Vin and the constant voltage Vreg become higher than the respective voltage reduction release voltages, and the input voltage Vin and the constant voltage Vreg are the respective. When the voltage becomes lower than the voltage reduction detection voltage (<voltage reduction release voltage), the logic level at the time of power reduction detection (for example, low level) is obtained.

The current setting unit 150 generates a predetermined reference current Issue and outputs it to the frequency setting unit 170 and the start delay unit 180. The current value of the reference current Issue can be adjusted according to the resistance value of the resistor R1 (see FIG. 1) externally attached to the SET terminal 150.

The oscillator unit 160 generates an internal clock signal INTCLK (for example, 2 MHz) necessary for the operation of the charge pump unit 220. The internal clock signal INTCLK is output not only to the charge pump unit 220 but also to the selector unit 210.

The frequency setting unit 170 arbitrarily sets the operating frequency of the switch drive sequence using an external element. Specifically, the frequency setting unit 170 uses the capacitance value of the capacitor C4 (see FIG. 1) externally attached to the SETCLK terminal and the current value of the reference current Issue (and thus the resistor R1 externally attached to the SET terminal). A variable clock signal CLK (for example, 500 Hz to 50 kHz) whose frequency changes according to the resistance value of) is generated, and this is output to the selector unit 210.

The start-up delay unit 180 arbitrarily sets the start delay time tDLY of the switch drive sequence using an external element. Specifically, the start-up delay unit 180 is the current value of the capacitor C3 (see FIG. 1) externally attached to the SETDLY terminal and the reference current Iset (and the resistance value of the resistor R1 externally attached to the SET terminal). ) Is generated, and the start delay signal Sdly whose logic transition timing changes is generated, and this is output to the logic unit 120.

The first watchdog timer unit 190 monitors an abnormality in the operating frequency of the switch drive sequence. Specifically, the first watchdog timer unit 190 monitors the variable clock signal CLK, generates the first abnormality detection signal Swdt1, and outputs this to the logic unit 120 and the selector unit 210, respectively. The first abnormality detection signal Swdt1 becomes, for example, a high level when an abnormality is not detected and a low level when an abnormality is detected.

The second watchdog timer unit 200 monitors an abnormality in the start delay time tDLY of the switch drive sequence. Specifically, the second watchdog timer unit 200 monitors the start delay signal Sdry and generates a second abnormality detection signal Swdt2, which is output to the logic unit 120 and the selector unit 210, respectively. The second abnormality detection signal Swdt2 becomes, for example, a high level when an abnormality is not detected and a low level when an abnormality is detected.

The selector unit 210 selectively outputs either the internal clock signal INTCLK or the variable clock signal CLK to the logic unit 120. More specifically, in the selector unit 210, the HAZ terminal voltage is at a low level (= logic level when the hazard lamp is not lit), and both the first abnormality detection signal Swdt1 and the second abnormality detection signal Swdt2 are high. When the level (= logic level when no abnormality is detected), the variable clock signal CLK is selectively output to the logic unit 120. On the other hand, in the selector unit 210, when the HAZ terminal voltage is at a high level (= logic level when the hazard lamp is lit), or at least one of the first abnormality detection signal Swdt1 and the second abnormality detection signal Swdt2 is at a low level (=). When the logic level at the time of abnormality detection), the internal clock signal INTCLK is selectively output to the logic unit 120.

The charge pump unit 220 generates a boosted voltage Vcp using a capacitor C5 (see FIG. 1) externally attached to the VCP terminal, and supplies this to the driver unit 110.

The open / short detection unit 230 monitors the node voltage appearing in each of the CH0 terminal to the CH8 terminal, generates an open / short detection signal Sdet, and outputs this to the logic unit 120. The open / short detection signal Sdet becomes the logic level (for example, high level) at the time when no abnormality is detected when no abnormality occurs in any of the light emitting diodes LEDs 1 to 8, and at least one of the light emitting diodes LEDs 1 to LED8. When an abnormality occurs, the logic level at the time of abnormality detection (for example, low level) is set.

<Switch drive sequence>
FIG. 3 is a timing chart showing an example of the switch drive sequence, in order from the top, input voltage Vin, constant voltage Vreg, UVLO signal Sublo, internal clock signal INTCLK, boost voltage Vcp, SETCLK terminal voltage, variable clock signal CLK. , SETDLY terminal voltage, start delay signal Sdly, SG terminal voltage, CMPLT terminal voltage, and LED * (however * = 8, 7, ... 1) on-off state (H: on, L: off) and switch element The ON / OFF state of SW * is depicted.

For convenience of illustration, the pulses of the internal clock signal INTCLK and the variable clock signal CLK are drawn larger than they actually are. Therefore, the time widths of the start-up delay time tDLY, the current supply standby time tdSG, and the lighting transition time tPS in this figure are not always consistent with the number of pulse counts.

When the UVLO signal Sublo rises to a high level (= logical level when the power reduction is released) at time t1 after the power is turned on to the switch drive device 10, the operation of generating the internal clock signal INTCLK and the variable clock signal CLK is started. , Each part of the switch drive device 10 is in an operable state.

At this time, the logic unit 120 controls the driver unit 110 so as to initialize the switch elements SW1 to SW8 from the previous off state to the on state. However, at time t1, the boosting operation of the charge pump unit 220 has just started, and the output operation of the driver unit 110 is unstable. Therefore, the operation of the switch elements SW1 to SW8 is indefinite (marked with x). See the hatched area). Therefore, if the drive current Id is output from the light emitting element driving device 20 before this operation indefinite period, the light emitting diodes LEDs 1 to 8 may unintentionally light up.

Therefore, the logic unit 120 triggers the light emitting element driving device 20 outside the device to start supplying current to the light emitting diodes LEDs 1 to LED 8 after the operation indefinite period of the switch elements SW1 to SW8 elapses and before the start of the switch driving sequence. Is output. More specifically, the logic unit 120 sets the SG terminal voltage to a low level (= logic level during current supply standby) over the irregular operation of the switch elements SW1 to SW8, and starts the current supply standby time tdSG from time t1. At the time t2 when the lapse of time, the SG terminal voltage is raised from the low level to the high level (= the logical level when the current supply standby is released).

With such a configuration, the drive current Id is not output from the light emitting element driving device 20 during the unsuitable period of operation of the switch elements SW1 to SW8, so that it is possible to avoid the flashing of the light emitting diodes LEDs 1 to LED8. It becomes.

The output timing of the current supply start trigger described above may be the time when the current supply standby time dSG has elapsed from the time t1 as described above, or the output levels of the drivers DRV1 to DRV8 exceed a predetermined threshold value. It may be the time point.

After that, when a predetermined start-up delay time tDLY elapses from time t1 and the start-up delay signal Sdly rises to a high level, the logic unit 120 switches every lighting transition time tPS according to the variable clock signal CLK after time t3. The elements SW1 to SW8 are sequentially and cumulatively turned off. For example, the lighting transition time tPS may be set to 256 counts of the variable clock signal CLK. In that case, if the oscillation frequency of the variable clock signal CLK is 5.12 kHz, the lighting transition time tPS is 50 ms.

By sequentially and cumulatively turning off the switch elements SW1 to SW8 as described above, the number of lights of the light emitting diodes LEDs 1 to LED8 is gradually increased, so that the area of the lighting area is expanded with the passage of time. I will go. That is, when a series of switch drive sequences are completed, all the switch elements SW1 to SW8 are turned off, and the light emitting diodes LEDs 1 to 8 are all turned on. When moving the lighting region so as to flow, the switch elements SW1 to SW8 may be sequentially and exclusively turned off.

After turning off all the switch elements SW1 to SW8 at the time t5, the logic unit 120 raises the CMPLT terminal voltage to a high level at the time t6 when the lighting transition time tPS has elapsed. The CMPLT terminal is an external terminal used when serially connecting a plurality of switch drive devices 10, and its function will be described in detail later.

After that, when the UVLO signal Sublo drops to a low level (= logical level at the time of power reduction detection) at time t7 due to the power cutoff to the switch drive device 10, the internal clock signal INTCLK and the variable clock signal CLK are generated. Is stopped, and each part of the switch drive device 10 becomes inoperable. At this time, since the switch elements SW1 to SW8 are already in the off state, the problem of blinking light as in the case of turning on the power does not occur.

The series of switch drive sequences is executed every time the power switch 3 or the power switch 4 is periodically turned on / off to supply power to the switch drive device 10 and shut off the power repeatedly.

<Startup delay part>
FIG. 4 is a circuit diagram showing an example of the internal configuration of the start-up delay unit 180. The start-up delay unit 180 includes a current source 181, a switch 182, an N-channel MOS [metal oxide semiconductor] field effect transistor 183, a comparator 184, a D flip-flop 185, and a filter 186.

The current source 181 generates a constant current I181 corresponding to the reference current Issue. The first end of the current source 181 is connected to a power supply end (for example, an application end of a constant voltage Vreg). Further, the second end of the current source 181 is connected to the SETDLY terminal via the switch 182.

The switch 182 conducts / cuts off between the second end of the current source 181 and the SETDLY terminal according to the UVLO signal Sublo. The switch 182 is turned on when the UVLO signal Sublo is at the logical level (for example, high level) when the power reduction is released, and is turned off when the UVLO signal Sublo is at the logical level (for example, low level) when the power reduction is detected.

The transistor 183 functions as a discharge switch of the capacitor C3 externally attached to the SETDLY terminal. The drain of the transistor 183 is connected to the SETDLY terminal. Both the source and the back gate of the transistor 183 are connected to the ground end. The gate of the transistor 183 is connected to the output end (Q) of the D flip-flop 185. The transistor 183 is turned on when the latch signal S2 (output signal of the D flip-flop 185) is at a high level, and is turned off when the latch signal S2 is at a low level.

The comparator 184 compares the SETDLY terminal voltage (charging voltage of the capacitor C3) input to the non-inverting input terminal (+) with the threshold voltage Vth input to the inverting input terminal (-) to generate a comparison signal S1. To do. The comparison signal S1 has a high level when the SETDLY terminal voltage is higher than the threshold voltage Vth, and has a low level when the SETDLY terminal voltage is lower than the threshold voltage Vth. It is desirable that the comparator 184 be provided with hysteresis in order to increase noise immunity.

The D flip-flop 185 takes in the data signal (fixed at high level) input to the data end (D) by using the rising edge of the comparison signal S1 input to the clock end as a trigger, and uses this as the latch signal S2 to output the output end ( Output from Q). On the other hand, the D flip-flop 185 resets the latch signal S2 to the low level when the UVLO signal Sublo input to the reset end is at the low level.

The filter 186 removes a noise component superimposed on the latch signal S2 to generate a start delay signal Sdry.

FIG. 5 is a timing chart (corresponding to an enlarged view of times t1 to t3 in FIG. 1) showing an example of the start-up delay operation, and in order from the top, UVLO signal Sublo, SETDLY terminal voltage, comparison signal S1, and latch signal S2. , And the start-up delay signal Sdly is depicted.

At time t11, when the UVLO signal Sublo rises to a high level, the switch 182 is turned on. At this time, the latch signal S2 is at a low level, and the transistor 183 is off. Therefore, since the capacitor C3 is charged by the constant current I181, the SETDLY terminal voltage starts to rise.

At time t12, when the SETDLY terminal voltage becomes higher than the threshold voltage Vth, the comparison signal S1 rises to a high level, and the latch signal S2 is latched to a high level. At this time, since the transistor 183 is turned on and the capacitor C3 is discharged, the SETDLY terminal voltage starts to decrease.

Then, at time t13, when the activation delay signal Sdly that has undergone the filtering process rises to a high level, a series of switch drive sequences by the logic unit 120 is started (see FIG. 3 above). The time required from the rise of the UVLO signal Suvlo to the high level until the start delay signal Sdry rises to the high level corresponds to the start delay time tDLY.

The start-up delay time tDLY can be arbitrarily adjusted according to the current value of the constant current I181 (and the resistance value of the resistor R1) and the capacitance value of the capacitor C3. Therefore, according to the start delay unit 180 of this configuration example, it is possible to arbitrarily set the start timing of the switch drive sequence by using the external elements (resistor R1 and capacitor C3).

For example, when the light emitting element driving device 20 that takes a long time from the power-on to the completion of the start-up is used, the start-up delay time tDLY may be set longer accordingly. By making such a setting, it is possible to avoid a problem that the switch drive sequence is started in a flying manner when a sufficient drive current Id is not supplied from the light emitting element drive device 20 to the light emitting element group 30. Is possible. As a matter of course, the start-up delay time tDLY needs to be set longer than the current supply standby time tdSG. Alternatively, the "UVLO signal Sublo" in this figure is read as "SG terminal voltage", and the timekeeping of the start delay time tDLY (= SETDLY terminal voltage) is triggered by the passage of the current supply standby time tdSG (= rising of the SG terminal voltage). It may be a specification to start charging).

<Frequency setting unit>
FIG. 6 is a circuit diagram showing an example of the internal configuration of the frequency setting unit 170. The frequency setting unit 170 in the column (a) of this figure includes a current source 171, a switch 172, an N-channel type MOS field effect transistor 173, and a comparator 174.

The current source 171 generates a constant current I171 corresponding to the reference current Issue. The first end of the current source 171 is connected to a power supply end (for example, an application end of a constant voltage Vreg). Further, the second end of the current source 171 is connected to the SETCLK terminal via the switch 172.

The switch 172 conducts / cuts off between the second end of the current source 171 and the SETCLK terminal according to the UVLO signal Sublo. The switch 172 is turned on when the UVLO signal Sublo is at the logic level (for example, high level) at the time of canceling the power reduction, and is turned off when the UVLO signal Sublo is at the logic level (for example, low level) at the time of detecting the power reduction.

The transistor 173 functions as a discharge switch of the capacitor C4 externally attached to the SETCLK terminal. The drain of the transistor 173 is connected to the SETCLK terminal. Both the source and backgate of transistor 173 are connected to the ground end. The gate of the transistor 173 is connected to the output end of the comparator 174 (= the output end of the variable clock signal CLK). The transistor 173 is turned on when the variable clock signal CLK (output signal of the comparator 174) is at a high level and turned off when the variable clock signal CLK is at a low level.

The comparator 174 has a SETCLK terminal voltage (charging voltage of the capacitor C4) input to the non-inverting input terminal (+) and a threshold voltage V1 / V2 (where V1> V2, first-out) input to the inverting input terminal (-). The variable clock signal CLK is generated by comparing with FIG. 3). The variable clock signal CLK becomes a high level when the SETCLK terminal voltage becomes higher than the threshold voltage V1, and becomes a low level when the SETDLY terminal voltage becomes lower than the threshold voltage V2. As described above, the comparator 174 has hysteresis.

The operation of generating the variable clock signal CLK will be described with reference to FIG. At time t1, when the UVLO signal Sublo rises to a high level, the switch 172 is turned on. At this time, the variable clock signal CLK is at a low level, and the transistor 173 is off. Therefore, since the capacitor C4 is charged by the constant current I171, the SETCLK terminal voltage starts to rise.

When the SETCLK terminal voltage becomes higher than the threshold voltage V1, the variable clock signal CLK rises to a high level. At this time, since the transistor 173 is turned on and the capacitor C4 is discharged, the SETCLK terminal voltage starts to decrease.

After that, when the SETCLK terminal voltage becomes lower than the threshold voltage V2, the variable clock signal CLK drops to a low level. At this time, since the transistor 173 is turned off and the discharge of the capacitor C4 is stopped, the SETCLK terminal voltage starts to rise again.

After that, by repeating the charging / discharging operation of the capacitor C4 in the same manner as described above, the SETCLK terminal voltage fluctuates between the threshold voltage V1 and the threshold voltage V2, and a periodic pulse is generated in the variable clock signal CLK. To.

The oscillation frequency of the variable clock signal CLK can be arbitrarily adjusted according to the current value of the constant current I171 (the resistance value of the resistor R1) and the capacitance value of the capacitor C4. In the logic unit 120, the above-mentioned switch drive sequence is executed in synchronization with the variable clock signal CLK. Therefore, according to the frequency setting unit 170 of this configuration example, it is possible to arbitrarily set the operating frequency of the switch drive sequence by using the external elements (resistor R1 and capacitor C4).

For example, the higher the oscillation frequency of the variable clock signal CLK, the shorter the lighting transition time tPS, and the lower the oscillation frequency of the variable clock signal CLK, the longer the lighting transition time tPS. That is, according to the frequency setting unit 170 of this configuration example, the sequential lighting control of the light emitting diodes LEDs 1 to 8 can be performed at an arbitrary speed, so that it is possible to flexibly respond to various user requests. ..

The external element is not limited to the example in column (a) of this figure. For example, as shown in column (b) of this figure, the variable clock signal CLK using only the external capacitor. The oscillation frequency of the variable clock signal CLK may be variably controlled, or as shown in the column (c) of this figure, the oscillation frequency of the variable clock signal CLK may be variably controlled by using only an external resistor. ..

<Multi-stage connection of switch drive device>
FIG. 7 is an application diagram showing an example of multi-stage connection of the switch drive devices 10a and 10b. The light emitting device 1 in this figure includes a switch driving device 10a and 10b (the internal configurations thereof are the same as those of the switch driving device 10 (FIG. 2) described above), a light emitting element driving device 20, and a light emitting element group 30a and 30b. And various discrete components (resistors R1 to R5, capacitors C1 to C9, diodes D1 to D3). In the following, the differences from FIG. 1 described above will be mainly described.

The light emitting element groups 30a and 30b are connected in series between the light emitting element driving device 20 and the grounding end. The light emitting element group 30a includes six light emitting diodes LEDs 1 to LED 6. On the other hand, the light emitting element group 30b includes 6 light emitting diodes LEDs 7 to 12. The switch drive device 10a switches between short-circuiting and non-short-circuiting of the light emitting diodes LEDs 1 to LED6 externally attached between the CH0 terminal to the CH6 terminal. On the other hand, the switch drive device 10b switches between short-circuiting and non-short-circuiting of the light emitting diodes LEDs 7 to 12 externally attached between the CH0 terminal to the CH6 terminal. In both the switch drive devices 10a and 10b, the unused channel terminals (between the CH6 terminal and the CH7 terminal and between the CH7 terminal and the CH8 terminal) are short-circuited, respectively.

In this way, the 12 light emitting diodes LEDs 1 to LED 12 are evenly distributed and connected to the switch drive devices 10a and 10b by 6 lights in order to evenly disperse the heat generation. However, the distribution ratio of the light emitting diodes LEDs 1 to 12 is not limited to this, and may be unevenly (for example, 8 lights: 4 lights) connected to the switch drive devices 10a and 10b.

When connecting 6 light emitting diodes to each of the switch drive devices 10a and 10b, the SEL1 terminal and the SEL3 terminal may be connected to the GND terminal, and the SEL2 terminal may be connected to the VREG terminal. The significance of these connection states will be described in detail later.

Next, the external connection state of the switch drive devices 10a and 10b will be described. However, since the switch drive device 10a can be basically understood as the switch drive device 10 of FIG. 1, duplicated explanations are omitted as much as possible, and in the following, the switch drive device 10b newly added in the present figure will be omitted. A detailed explanation will be given focusing on the external connection relationship of.

The capacitor C6 is connected between the VIN terminal of the switch drive device 10b and the ground end. The VIN terminal of the switch drive device 10b is connected to the cathodes (= application ends of the input voltage Vin) of the diodes D1 and D2. The HAZ terminal of the switch drive device 10b is connected to the cathode (= input end of the hazard signal) of the diode D3. The capacitor C7 is connected between the VREG terminal of the switch drive device 10b and the ground end. The SETDLY terminal of the switch drive device 10b is in an open state unlike the switch drive device 10a in the previous stage. This is because it is not necessary to set the start-up delay time tDLY in the switch drive device 10b in the subsequent stage. The capacitor C8 is connected between the SETCLK terminal of the switch drive device 10b and the ground end. The capacitor C9 is connected between the VCP terminal and the CH8 terminal of the switch drive device 10b.

The resistor R4 is connected between the SET terminal of the switch drive device 10b and the ground end. The resistor R5 is connected between the CNT terminal of the switch drive device 10b and the power supply end (for example, the VREG terminal). Further, the CNT terminal of the switch drive device 10b is connected to the CMPLT terminal of the switch drive device 10a. In this way, the switch drive devices 10a and 10b are connected to each other via one serial signal line, and both multi-stage cooperative operations (= light emitting diode LEDs 1 to 2 by the switch drive device 10a) are performed using the serial signal line. After the sequential lighting control of the LED 6 is completed, the operation of taking over the sequential lighting control of the light emitting diodes LEDs 7 to 12 by the switch drive device 10b) is realized. On the other hand, the CMPLT terminal of the switch drive device 10b is in an open state.

As can be seen from the fact that the capacitors C4 and C8 are externally attached to the SET CLK terminals of the switch drive devices 10a and 10b, the variable clock signals CLK are generated asynchronously with each other in the switch drive devices 10a and 10b. Will be done. With such a configuration, it is not necessary to transmit the variable clock signal CLK from the switch drive device 10a to the switch drive device 10b, so that it is not necessary to increase the number of signals between the two. Further, even if the variable clock signals CLK of each of the switch drive devices 10a and 10b are asynchronous, the lighting timing is such that humans can visually recognize them as long as the multi-stage cooperation operation of both is performed via the serial signal line. It can be said that there is almost no risk of deviation.

As described above, the light emitting element drive device 20 monitors the SG terminal voltage of the switch drive device 10a and waits for the start of supply of the drive current Id.

The FAIL terminal of the switch drive device 10b is connected to the FAIL terminal of the switch drive device 10a. The GND terminal of the switch drive device 10b is connected to the ground end.

In this way, by serially connecting the switch drive devices 10a and 10b and performing the multi-stage cooperation operation (details will be described later) of both, the light emission of 9 or more lights without increasing the number of channels of the switch drive devices 10a and 10b. The diodes can be turned on sequentially. Therefore, it is possible to flexibly respond to various user requests (the number of light emitting elements required for the light emitting device 1).

FIG. 8 is a timing chart showing an example of multi-stage cooperative operation by the switch drive devices 10a and 10b, in order from the top, the input voltage Vin, the behavior of the switch drive device 10a (CNT terminal voltage, start delay signal Sdry, CMPLT terminal voltage). , And the on-off state (H: on, L: off) of the light emitting diode LEDi (however, i = 6, ..., 2, 1), and the behavior of the switch drive device 10b (CNT terminal voltage, start delay signal Sdly). , CMPLT terminal voltage, and the on-off state (H: on, L: off) of the light emitting diode LEDj (however, j = 12, ..., 8, 7) are depicted.

At time t21, when the power is turned on to the light emitting device 1 (turning on of the power switch 3 or 4 in FIG. 1), the input voltage Vin starts to rise. In the switch drive device 10a, since the CNT terminal is connected to the VIN terminal, the CNT terminal voltage also increases as the input voltage Vin increases after the time t21. On the other hand, in the switch drive device 10b, since the CNT terminal is connected to the CMPLT terminal of the switch drive device 10a, the CNT terminal voltage is maintained at a low level even after the time t21.

At time t22, when the input voltage Vin becomes higher than the voltage reduction release voltage VTH1, the switch drive devices 10a and 10b are in an operable state. At this point, the CNT terminal voltage of the switch drive device 10a is at a high level (= higher than the standby release voltage VTH2). On the other hand, the CNT terminal voltage of the switch drive device 10b is maintained at a low level even at time t22.

The logic unit 120 provided in each of the switch drive devices 10a and 10b waits for the start of the switch drive sequence until the CNT terminal voltage to be monitored rises to a high level. Therefore, the switch drive device 10a is in a state in which the switch drive sequence can be started at any time after the time t22 when the power reduction state is released. On the other hand, the switch drive device 10b remains waiting for the start of the switch drive sequence even after the time t22.

After that, in the switch drive device 10a, at the time t23 when the start delay time tDLY elapses from the time t22, the start delay signal Sdry is raised to a high level, and a series of switch drive sequences are started. More specifically, in the switch drive device 10a, the light emitting diodes LEDs 1 to LED 6 are sequentially lit at each predetermined lighting transition time tPS after the time t23.

On the other hand, in the switch drive device 10b, since the SETDLY terminal is in the open state (see FIG. 7), the start delay signal Sdly is raised to a high level without delay in response to the cancellation of the power reduction at time t22. However, as described above, the CNT terminal voltage of the switch drive device 10b is maintained at a low level even after the time t22. Therefore, even if the start delay signal Sdry is raised to a high level, the switch drive sequence by the switch drive device 10b is not started.

After that, the logic unit 120 of the switch drive device 10a raises the CMPLT terminal voltage to a high level at the time t26 when the lighting transition time tPS has elapsed after all the light emitting diodes LEDs 1 to LED6 are turned on at the time t25. That is, the logic unit 120 of the switch drive device 10a outputs a standby release trigger to the switch drive device 10b after a series of switch drive sequences are completed.

At time t26, when the CMPLT terminal voltage of the switch drive device 10a rises to a high level, the CNT terminal voltage of the switch drive device 10b rises to a high level, so that a series of switch drive sequences by the switch drive device 10b are started. More specifically, in the switch drive device 10b, the light emitting diodes LEDs 7 to 12 are sequentially lit at each predetermined lighting transition time tPS after the time t26.

The logic unit 120 of the switch drive device 10b raises the CMPLT terminal voltage to a high level at the time t29 when the lighting transition time tPS has elapsed after all the light emitting diodes LEDs 7 to 12 are turned on at the time t28. However, since another switch drive device is not connected to the subsequent stage of the switch drive device 10b, the sequential lighting control of the light emitting diodes is not continued any more.

As described above, in the light emitting device 1 of the present configuration example, the switch is driven when the same lighting transition time tPS as before has elapsed after the sequential lighting control of the light emitting diodes LEDs 1 to 6 by the switch driving device 10a is performed. The sequential lighting control of the light emitting diodes LEDs 7 to 12 by the device 10b is continued. Therefore, when looking at the light emitting device 1 as a whole, it is possible to realize natural sequential lighting control as if the short circuit / non-short circuit of the light emitting diodes LEDs 1 to 12 is switched by using a single switch drive device. ..

In this configuration example, a configuration in which the CMPLT terminal voltage is used as a standby release trigger for the next stage is given as an example, but since the CMPLT terminal voltage has the meaning of "normally LED lighting is completed", this is used. By monitoring with an external controller 5, it is also possible to determine whether the LED lighting is normal / abnormal.

FIG. 9 is a diagram for explaining problems when the switch drive devices 10a and 10b are connected in multiple stages. The light emitting devices 1a and 1b in columns (a) and (b) are mounted on the vehicle X as turn signal modules for the rear. The light emitting device 1a is provided in the trunk, and the light emitting device 1b is provided in the body. As shown in the column (c), the light emitting device 1a includes a switch driving device 10a and a light emitting element group 30a. On the other hand, the light emitting device 1b includes a switch driving device 10b, a light emitting element driving device 20, and a light emitting element group 30b. The light emitting element groups 30a and 30b are connected in series between the light emitting element driving device 20 and the grounding end.

As shown in column (a), when the trunk is closed, the light emitting device 1a and the light emitting device 1b form a single turn signal lamp. However, as shown in column (b), the trunk is naturally attached to the body in a state where it can be opened and closed. Therefore, in order to serially connect the CMPLT terminal of the switch drive device 10a and the CNT terminal of the switch drive device 10b, it is necessary to once route the harness from the switch drive device 10a to the switch drive device 10b via the body.

Therefore, in the following, in the usage mode of the light emitting devices 1a and 1b shown in this figure, the switch drive devices 10a and 10b are not serially connected to each other, but the start delay unit 180 described above is used to emit light. A method of sequentially controlling the lighting of the element groups 30a and 30b as if they were integrated will be described.

FIG. 10 is a timing chart showing an example of use of the start-up delay difference, in that order from the top, the input voltage Vin, the behavior of the switch drive device 10a (CNT terminal voltage, start-up delay signal Sdry, and light emitting diode LEDi (however i). = 6, ..., 2, 1) point off state (H: on, L: off)), and the behavior of the switch drive device 10b (CNT terminal voltage, start delay signal Sdly, and light emitting diode LEDj (however, j) = 12, ..., 8, 7) point-off states (H: on, L: off)) are depicted.

As a precondition of the description, it is assumed that the CNT terminal of the switch drive device 10b is connected to the VIN terminal of the switch drive device 10b instead of the CMPLT terminal of the switch drive device 10a. That is, the switch drive devices 10a and 10b operate independently and independently without performing the multi-stage cooperative operation described above.

When the power is turned on (switching on the power switch 3 or 4 in FIG. 1) to the light emitting devices 1a and 1b at time t31, the input voltage Vin starts to rise. As described above, in the switch drive devices 10a and 10b, since the CNT terminals are connected to the VIN terminals, the CNT terminal voltage also increases as the input voltage Vin increases after the time t31.

At time t32, when the input voltage Vin becomes higher than the voltage reduction release voltage VTH1, the switch drive devices 10a and 10b are in an operable state. At this point, the CNT terminal voltages of the switch drive devices 10a and 10b are at a high level (= higher than the standby release voltage VTH2).

The logic unit 120 provided in each of the switch drive devices 10a and 10b waits for the start of the switch drive sequence until the CNT terminal voltage to be monitored rises to a high level. Therefore, both the switch drive devices 10a and 10b are in a state in which the switch drive sequence can be started at any time after the time t32 when the power reduction state is released.

After that, in the switch drive device 10a, the start delay signal Sdly is raised to a high level at the time t33 when the first start delay time tDLYa elapses from the time t32, and a series of switch drive sequences are started. More specifically, in the switch drive device 10a, the light emitting diodes LEDs 1 to LED 6 are sequentially lit at each predetermined lighting transition time tPS after the time t33.

On the other hand, in the switch drive device 10b, the start delay signal Sdly is maintained at a low level from the time t32 to the time t36 when the second start delay time tDLYb elapses. The second start-up delay time tDLYb may be set in advance to a length (= tDLYa + 6 × tPS) obtained by adding the lighting transition time tPS for six lights to the first start-up delay time tDLYa. By making such a setting, a series of switch drive sequences by the switch drive device 10b is started following the series of switch drive sequences by the switch drive device 10a. More specifically, after the time t36 when the lighting transition time tPS has elapsed after all the light emitting diodes LEDs 1 to LED6 are turned on, the switch drive device 10b has the light emitting diode LEDs 7 to every predetermined lighting transition time tPS. The LEDs 12 are turned on in sequence.

In this way, if the start-up delay times tDLYa and tDLYb are appropriately set and the switch drive sequence of the switch drive device 10b is started at the timing when the switch drive sequence of the switch drive device 10a ends, the switch drive device 10a It is possible to sequentially control the lighting of the light emitting element groups 30a and 30b without connecting the light emitting element groups 30a and 10b in multiple stages. Therefore, for example, even in the usage pattern of FIG. 9, it is not necessary to route the harness between the switch drive device 10a and the switch drive device 10b.

<SEL terminal>
FIG. 11 is a table showing the relationship between the SEL terminal voltage and the number of light emitting element lamps. The logic unit 120 determines the number of light emitting diodes externally attached to the CH0 terminal to the CH8 terminal according to the combination of a plurality of SEL terminal voltages (here, SEL1 terminal voltage, SEL2 terminal voltage, SEL3 terminal voltage). ..

When SEL1 = SEL2 = SEL3 = GND, the logic unit 120 recognizes that eight light emitting diodes LEDs 1 to LED 8 are externally attached between the CH0 terminal and the CH8 terminal.

When SEL1 = VREG and SEL2 = SEL3 = GND, the logic unit 120 has seven light emitting diodes LEDs1 to LED7 externally attached between the CH0 terminal to the CH7 terminal, and is a channel terminal that is not used. It is recognized that the space (between the CH7 terminal and the CH8 terminal) is short-circuited.

When SEL2 = VREG and SEL1 = SEL3 = GND, the logic unit 120 has six light emitting diodes LEDs1 to LED6 externally attached between the CH0 terminal to the CH6 terminal, and is a channel terminal that is not used. It is recognized that the space (between the CH6 terminal and the CH8 terminal) is short-circuited.

When SEL1 = SEL2 = VREG and SEL3 = GND, the logic unit 120 has five light emitting diodes LEDs1 to LED5 externally attached between the CH0 terminal to the CH5 terminal, and is a channel terminal that is not used. It is recognized that the space (between the CH5 terminal and the CH8 terminal) is short-circuited.

When SEL3 = VREG and SEL1 = SEL2 = GND, the logic unit 120 has four light emitting diodes LEDs1 to LED4 externally attached between the CH0 terminal to the CH4 terminal, and is a channel terminal that is not used. It is recognized that the space (between the CH4 terminal and the CH8 terminal) is short-circuited.

When SEL1 = SEL3 = VREG and SEL2 = GND, the logic unit 120 has three light emitting diodes LEDs1 to LED3 externally attached between the CH0 terminal to the CH3 terminal, and is a channel terminal that is not used. It is recognized that the space (between the CH3 terminal and the CH8 terminal) is short-circuited.

When SEL2 = SEL3 = VREG and SEL1 = GND, the logic unit 120 has two light emitting diodes LEDs1 to LED2 externally attached between the CH0 terminal and the CH2 terminal, and is a channel terminal that is not used. It is recognized that the space (between the CH2 terminal and the CH8 terminal) is short-circuited.

When SEL1 = SEL2 = SEL3 = VREG, in the logic unit 120, one light emitting diode LED1 is externally attached between the CH0 terminal and the CH1 terminal, and between the unused channel terminals (CH1 terminal to ~). It is recognized that each of the CH8 terminals) is short-circuited.

In this way, by using the three SEL1 terminals to the SEL3 terminals, the number of light emitting diode lights can be set in a total of eight ways, so that various user requests (the number of light emitting elements required for the light emitting device 1) can be set. ) Can also be flexibly dealt with. In this figure, the configuration in which the channels to be used are selected in order from the ground end side has been described as an example, but conversely, the channels to be used are selected in order from the light emitting element driving device 20 side. It may be configured as such.

FIG. 12 is an application diagram showing an example of setting the number of lights using a plurality of SEL terminals (SEL1 terminal to SEL3 terminal).

In the column (a), the light emitting diodes LEDs 1 to LED 8 are connected to each other between the CH0 terminal and the CH8 terminal. Therefore, in order for the logic unit 120 to recognize that the number of light emitting element lights is "8", all of the SEL1 terminal to the SEL3 terminal are connected to the ground end (see the first line of FIG. 11). In this case, the logic unit 120 raises the CMPLT terminal voltage to a high level after turning on all the light emitting diodes LEDs 1 to 8. Further, the logic unit 120 sends an instruction to the open / short detection unit 230 to monitor each of the CH0 terminal to the CH8 terminal.

In column (b), the light emitting diodes LEDs 1 to LED4 are connected between the CH0 terminal and the CH4 terminal, and the unused channel terminals (between the CH4 terminal and the CH8 terminal) are short-circuited. There is. Therefore, in order for the logic unit 120 to recognize that the number of light emitting element lights is "4", the SEL1 terminal and the SEL2 terminal are connected to the ground terminal, and the SEL3 terminal is connected to the VREG terminal (FIG. 11). See line 5). In this case, the logic unit 120 raises the CMPLT terminal voltage to a high level after turning on the light emitting diodes LEDs 1 to LED 4. Further, the logic unit 120 monitors each of the CH0 terminal to CH4 terminal with respect to the open / short detection unit 230, while excludes each of the CH4 terminal to CH8 terminal from the monitoring target. Send instructions to.

In this way, the logic unit 120 switches channels that should be ignored when determining the completion of the switch drive sequence based on the number of lights setting using a plurality of SEL terminals (SEL1 terminal to SEL3 terminal), and has an open / short detection function. It is possible to switch the necessity of masking for each channel.

<All lighting mode (hazard mode)>
FIG. 13 is a timing chart for explaining all the lighting modes of the light emitting diode LEDs 1 to LED 8, and in each of the columns (a) to (c), the CMPLT terminal voltage and the light emitting diode LED * are in order from the top. (However, * = 8, 7, ..., 2, 1) point-off states (H: on, L: off)) are depicted.

In the column (a), the light emitting diodes LEDs 1 to LED 8 are sequentially lit at predetermined lighting transition times tPS by sequentially driving the switch elements SW1 to SW8 according to the above-mentioned switch driving sequence (normal mode). Behavior is shown. The sequential lighting mode has an advantage that, for example, by sequentially lighting the light emitting diodes LEDs 1 to LED8 according to the turning direction of the vehicle X, it becomes easier for pedestrians and other vehicles to intuitively recognize the traveling direction of the own vehicle. is there. In view of these merits, it can be said that the sequential lighting mode is suitable as an operation mode when the vehicle X turns left or right or when the lane is changed (when the power switch 3 is turned on according to the operation of the turn lever).

On the other hand, in column (b), the behavior of the all-lighting mode (hazard mode) in which the light emitting diodes LEDs 1 to LED8 are turned on all at once by turning off all the switch elements SW1 to SW8 all at once is shown. For example, at the time of emergency stop or emergency deceleration of vehicle X (when the power switch 4 is turned on by pressing the hazard button), the light emitting diodes LEDs 1 to LED 8 are immediately set to notify other vehicles of high urgency. It can be said that it is desirable to turn on all lights.

However, when the switch elements SW1 to SW8 are turned off at the same time and the light emitting diodes LEDs 1 to LED8 are turned on at the same time, the load fluctuation for the charge pump unit 220 and the light emitting element driving device 20 becomes steep, and the operation stability thereof becomes steep. May be damaged.

Therefore, as shown in the column (c), the logic unit 120 does not turn on the light emitting diodes LEDs 1 to 8 completely at the same time, but turns on each of the light emitting diodes LEDs 1 to 8 sequentially every predetermined high-speed lighting transition time tPSH (<< tPS). To do. That is, in both the forward lighting mode and the full lighting mode, each switch drive sequence itself is exactly the same, and only the respective operating frequencies are different. The high-speed lighting transition time tPSH may be set to several hundred μs.

In this way, by sequentially controlling the lighting of the light emitting diodes LEDs 1 to LED 8 at a high speed that cannot be visually recognized by the human eye, it is possible to suppress sudden load fluctuations while apparently lighting the light emitting diodes LEDs 1 to LED 8 all at once. It will be possible. However, when it is not necessary to consider load fluctuations (for example, when the charge pump unit 220 and the light emitting element driving device 20 have sufficient output capacity), the light emitting diodes LEDs 1 to 1 are selected when the full lighting mode is selected. The LEDs 8 may be turned on completely at the same time.

The sequential lighting mode and the full lighting mode can be switched by using the selector unit 210. As described above, in the selector unit 210, the HAZ terminal voltage is at a low level, and both the first abnormality detection signal Swdt1 and the second abnormality detection signal Swdt2 are at the logic level when no abnormality is detected (for example, high level). ), The variable clock signal CLK is selectively output to the logic unit 120. This output state corresponds to the state in which the sequential lighting mode is selected. At this time, the logic unit 120 executes the switch drive sequence in synchronization with the variable clock signal CLK. Therefore, the light emitting diodes LEDs 1 to 8 are sequentially turned on every lighting transition time tPS (for example, 50 ms) corresponding to the variable clock signal CLK.

On the other hand, the selector unit 210 is when the HAZ terminal voltage is at a high level, or when at least one of the first abnormality detection signal Swdt1 and the second abnormality detection signal Swdt2 is at the logic level (for example, low level) at the time of abnormality detection. In addition, the internal clock signal INTCLK is selectively output to the logic unit 120. This output state corresponds to the state in which the all lighting mode is selected. At this time, the logic unit 120 executes the switch drive sequence in synchronization with the internal clock signal INTCLK having a frequency higher than that of the variable clock signal CLK. Therefore, the light emitting diodes LEDs 1 to 8 are sequentially turned on every high-speed lighting transition time tPSH (several hundred μs) corresponding to the internal clock signal INTCLK. That is, the logic unit 120 simultaneously presses all the switch elements SW1 to SW8 in the above-mentioned all lighting mode when a hazard signal is input from the outside of the device or when an abnormality in the switch drive sequence is detected. It is turned off and the light emitting diodes LEDs 1 to 8 are turned on all at once.

In the light emitting device 1 of this configuration example, the switch drive sequence in the full lighting mode is speeded up by diverting the internal clock signal INTCLK for driving the charge pump unit 220. Therefore, it is not necessary to add a dedicated oscillator unit in order to suppress sudden load fluctuations in the full lighting mode, so that the scale of the light emitting device 1 does not need to be increased unnecessarily.

FIG. 14 is an application diagram showing connection variations of HAZ terminals. In column (a), as in FIG. 1, a configuration in which power switches 3 and 4 are connected in parallel between the light emitting device 1 and the battery 2 is depicted. When the power switch 4 is turned on in response to the pressing of the hazard button, the HAZ terminal voltage becomes high level and the light emitting device 1 is lit in the full lighting mode. When this configuration is adopted, two power lines L1 and L2 are required between the light emitting device 1 and the battery 2.

In the column (b), the configuration in which the power switch 4, the diodes D2 and D3, and the power line L2 are omitted and the signal line L3 is connected from the controller 5 to the HAZ terminal is described. When this configuration is adopted, the controller 5 turns on the power switch 3 both when the turn lever is operated and when the hazard button is pressed. Further, the controller 5 sets the HAZ terminal to the high level during the period when the power switch 3 is turned on in response to the pressing of the hazard button, and sets the HAZ terminal to the low level during the other period. With such a configuration, it is possible to reduce the number of components as compared with the configuration in column (a).

If the above-mentioned full lighting mode is not used, the HAZ terminal may be connected to the ground end as shown in column (c).

<Watchdog timer part>
FIG. 15 is a timing chart showing an example of watchdog timer operation. The column (a) in this figure shows an operation example of the first watchdog timer unit 190, in which the UVLO signal Sublo, the variable clock signal CLK, and the first abnormality detection signal Swdt1 are displayed in order from the top. It is depicted. Further, the column (b) of this figure shows an operation example of the second watchdog timer unit 200, in which the UVLO signal Sublo, the start delay signal Sdly, and the second abnormality detection signal Swdt2 are displayed in order from the top. It is depicted.

If both ends of the capacitor C4 externally connected to the SETCLK terminal were short-circuited, the SETCLK terminal voltage stuck to the ground level even after the reduced power state was resolved and the UVLO signal Sublo rose to a high level. Will remain. As a result, the pulse of the variable clock signal CLK is not generated forever, so that the switch drive sequence by the logic unit 120 cannot be started.

Further, when both ends of the capacitor C3 externally connected to the SETDLY terminal are short-circuited, the SETDLY terminal voltage is kept at the ground level even after the reduced power state is resolved and the UVLO signal Sublo rises to a high level. It stays attached. As a result, the start delay signal Sdly does not rise to a high level forever, so that the switch drive sequence by the logic unit 120 cannot be started.

If at least one of the capacitors C3 and C4 is short-circuited in this way, the switch drive device 10 will not operate, and the light emitting diodes LEDs 1 to 8 will remain off. In such a state, the light emitting device 1 (turn lamp) is not turned on even though the driver is operating the turn lever and the hazard button, which is extremely dangerous.

Therefore, the first watchdog timer unit 190 monitors the variable clock signal CLK and generates the first abnormality detection signal Swdt1. More specifically, the first watchdog timer unit 190 is changed when a predetermined abnormality detection period T1 elapses without generating a pulse of the variable clock signal CLK after the UVLO signal Sublo rises to a high level, or is variable. When the pulse period T2 of the clock signal CLK is not within the predetermined normal range, it is determined that the SETCLK terminal is abnormal, and the first abnormality detection signal Swdt1 is set to the logical level (for example, low level) at the time of abnormality detection. Switch.

Further, the second watchdog timer unit 200 monitors the start delay signal Sdly and generates the second abnormality detection signal Swdt2. More specifically, the second watchdog timer unit 200 is used when a predetermined abnormality detection period T3 elapses while the start delay signal Sdry is maintained at a low level after the UVLO signal Sublo rises to a high level. It is determined that the SETDLY terminal is abnormal, and the second abnormality detection signal Swdt2 is switched to the logic level (for example, low level) at the time of abnormality detection.

The selector unit 210 is in a state of selectively outputting the internal clock signal INTCLK to the logic unit 120 in response to the fact that at least one of the first abnormality detection signal Swdt1 and the second abnormality detection signal Swdt2 is switched to the logic level at the time of abnormality detection. Become. With such a configuration, the logic unit 120 can execute the switch drive sequence in the full lighting mode in synchronization with the internal clock signal INTCLK.

Further, the logic unit 120 sets the FAIL terminal voltage to the logic level at the time of abnormality detection (for example, in response to the fact that at least one of the first abnormality detection signal Swdt1 and the second abnormality detection signal Swdt2 is switched to the logic level at the time of abnormality detection. Switch to low level). With such a configuration, the abnormality of the switch drive device 10 can be grasped by the external controller 5, so that it is possible to notify the driver and the like.

By implementing the above watchdog timer function, it is possible to provide a highly safe vehicle X that complies with FMEA [failure mode and effect analysis] standards and the like.

In the example of this figure, the configuration in which the variable clock signal CLK and the start delay signal Sdry are monitored is described as an example, but the first watchdog timer unit 190 and the second watchdog timer unit 200 have been described. The monitoring target is not limited to this, and the SETCLK terminal voltage and the SETDLY terminal voltage may be monitored.

<Summary>
As described above, in the switch drive device 10, when the relatively simple sequential lighting function is implemented, the basic lighting pattern is fixed, and only the parameters that require user adjustment are set to several external elements (resistors and the like). It is configured so that it can be set arbitrarily with a capacitor, etc.). With such a configuration, it is possible to perform almost the same sequential lighting as before without the need for microcomputer control, so the set design can be simplified, the number of parts can be reduced, the board area can be reduced, the cost can be reduced, and high efficiency can be achieved. It is possible to realize the stability of the set operation or the like.

<Use>
The light emitting device 1 is, for example, as shown in columns (a) to (b) of FIG. 16, headlamps (including high beam / low beam / small lamp / fog lamp, etc.) X11 of the vehicle X10, and daytime running (day and night). It can be suitably used as a DRL [daytime running lamps]) lamp X12, a tail lamp (including a small lamp, a back lamp and the like as appropriate) X13, a stop lamp X14, a turn lamp X15 and the like. In particular, as described above, the light emitting device 1 is suitable as a sequential type turn lamp X15.

Further, the above-mentioned switch drive device 10 and light emitting element driving device 20 together with the light emitting element group 30 to be driven are mounted on an in-vehicle lamp module (headlamp module Y10 in column 17 (a), turn in column 17 (b)). It may be provided as a lamp module Y20 and a rear lamp module Y30 in the column of FIG. 17C), or it may be provided as a single IC independently of the light emitting element group 30. May be good.

<Other variants>
In the above embodiment, a configuration using a light emitting diode as a light emitting element has been described as an example, but the configuration of the present invention is not limited to this, and for example, an organic EL [ It is also possible to use an electro-luminescence device.

As described above, the various technical features disclosed in the present specification can be modified in addition to the above-described embodiment without departing from the spirit of the technical creation. That is, it should be considered that the above embodiments are exemplary in all respects and are not restrictive, and the technical scope of the present invention is not the description of the above embodiments but the claims. It is shown and should be understood to include all modifications that fall within the meaning and scope of the claims.

The invention disclosed in the present specification can be used for an in-vehicle light emitting device (or a switch driving device used therein) having a sequential lighting function.

1,1a, 1b light emitting device (turn lamp module)
2 Battery 3, 4 Power switch 5 Controller 10, 10a, 10b Switch drive device (matrix switch driver IC)
20 Light emitting element drive device (LED driver IC)
30, 30a, 30b Light emitting element group (LED string)
100 Switch part 110 Driver part 120 Logic part 130 Internal regulator part 140 UVLO part 150 Current setting part 160 Oscillator part 170 Frequency setting part 180 Start delay part 171, 181 Current source 172, 182 Switch 173, 183 N-channel type MOS field effect transistor 174, 184 comparator 185 D flip flop 186 filter 190 1st watchdog timer part 200 2nd watchdog timer part 210 selector part 220 charge pump part 230 open / short detection part LED1 to LED12 light emitting element (light emitting diode)
R1 to R5 Resistors C1 to C9 Capsules D1 to D3 Diodes SW1 to SW8 Switch elements DRV1 to DRV8 Drivers L1, L2 Power lines L3 Signal lines X, X10 Vehicles X11 Headlamps X12 Light source for daytime running (DRL) X13 Tail lamp X14 Stop lamp X15 Turn lamp Y10 Headlamp module Y20 Turn lamp module Y30 Rear lamp module

Claims (15)

It is a point-off control device that controls whether or not the drive current supplied to each of a plurality of light emitting elements can be supplied.
A logic unit that automatically starts a series of drive sequences so that the supply availability is sequentially switched in a predetermined pattern when the power is turned on to the device.
A start delay unit that arbitrarily sets the start delay time of the drive sequence using an external element,
A point-off control device characterized by having. The point-off control device according to claim 1, further comprising a frequency setting unit for arbitrarily setting the operating frequency of the drive sequence using an external element. The point-off control device according to claim 1 or 2 , wherein the logic unit outputs a standby release trigger to another point-off control device after the drive sequence is completed. It is a point-off control device that controls whether or not the drive current supplied to each of a plurality of light emitting elements can be supplied.
It has a logic unit that automatically starts a series of drive sequences so that the supply availability is sequentially switched in a predetermined pattern when the power is turned on to the device.
The logic unit is a point-off control device characterized in that a standby release trigger is output to another point-off control device after the drive sequence is completed. It is a point-off control device that controls whether or not the drive current supplied to each of a plurality of light emitting elements can be supplied.
It has a logic unit that automatically starts a series of drive sequences so that the supply availability is sequentially switched in a predetermined pattern when the power is turned on to the device.
The logic unit implements a sequential lighting mode in which drive currents are sequentially supplied to each light emitting element according to the drive sequence, and an all lighting mode in which drive currents are simultaneously supplied to all light emitting elements. In the sequential lighting mode, the drive sequence is executed in synchronization with the first clock signal, while in the full lighting mode, the drive sequence is executed in synchronization with the second clock signal having a frequency higher than that of the first clock signal. A point-off control device characterized by A driver unit that drives a switch element for switching whether supply is possible or not,
A charge pump unit that supplies a boosted voltage to the driver unit and
An oscillator unit that generates an internal clock signal required for the operation of the charge pump unit, and an oscillator unit.
Have more
The point-off control device according to claim 5 , wherein the internal clock signal is diverted as the second clock signal. The logic unit supplies a drive current to all the light emitting elements at the same time in the all lighting mode when a hazard signal is input from the outside of the device or when an abnormality in the drive sequence is detected. The point-off control device according to claim 5 or 6 , wherein the lighting control device is characterized. The logic unit outputs a current supply start trigger to each light emitting element to the light emitting element driving device outside the device after the lapse of an indefinite period of operation of the switch element for switching the supply availability and before the start of the driving sequence. The point-off control device according to any one of claims 1 to 7, wherein the point-off control device is characterized. The point-off control device according to any one of claims 1 to 8 , wherein the logic unit determines the number of light emitting element lights according to an external terminal voltage. The point-off control device according to any one of claims 1 to 9 , further comprising a watchdog timer for monitoring an abnormality in the start delay time or the operating frequency of the drive sequence. With multiple light emitting elements
A light emitting element drive device that generates a drive current for each light emitting element,
The point-off control device according to any one of claims 1 to 10.
A light emitting device characterized by having. The light emitting device according to claim 11 , wherein each of the plurality of light emitting elements is a light emitting diode or an organic EL element. Head lamp module, turn lamp module emitting device according or in claim 11 or claim 12, characterized in that it is mounted on a vehicle as a rear lamp module. A vehicle having the light emitting device according to any one of claims 11 to 13. The vehicle according to claim 14 , wherein the light emitting device is used as at least one of a head lamp, a day and night traveling lamp, a tail lamp, a stop lamp, and a turn lamp.

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