JP6899250B2 - Semiconductor integrated circuit equipment and its manufacturing method - Google Patents

Description

The present embodiment relates to a semiconductor integrated circuit device and a method for manufacturing the same.

In semiconductor devices or semiconductor integrated circuits, heat dissipation design is becoming more important due to high-density mounting on a mounting board.

Since the miniaturized semiconductor element has a small surface area, heat dissipation from the surface cannot be expected, and heat dissipation from the substrate is the main. In addition, since the heat dissipation performance in the horizontal direction of the board is limited by thinning copper to reduce the cost of the board, the presence of through holes and vias that realize the heat dissipation path in the vertical direction is the heat dissipation performance of the entire board. Affects.

JP-A-2015-18857 Japanese Unexamined Patent Publication No. 2014-140002

The present embodiment provides a semiconductor integrated circuit device and a method for manufacturing the same, in which solder suction to vias can be avoided, reliability is improved, and heat dissipation performance is improved.

According to one aspect of the present embodiment, on the insulating substrate, the via penetrating the insulating substrate, the first metal layer arranged on the insulating substrate, and the first metal layer around the via. On the arranged first resist layer, the solder layer arranged on the first metal layer, the first gap region formed between the solder layer and the first resist layer, and the solder layer. Provided is a semiconductor integrated circuit device including an arranged semiconductor integrated circuit and a second gap region formed between the semiconductor integrated circuit and the first resist layer.

According to another aspect of the present embodiment, a step of preparing an insulating substrate and forming a via on the insulating substrate, and forming a first metal layer on the surface of the insulating substrate and forming a first metal layer on the back surface of the insulating substrate. A second metal layer is formed on the surface of the via, and a third metal layer is formed on the inner wall side surface of the via, a step of forming a resist on the first metal layer, and a step of patterning the resist to surround the via. A step of forming a first resist layer on the first metal layer, a step of forming a solder layer on the first metal layer, a step of mounting a semiconductor integrated circuit on the solder layer, and a reflow step. This was carried out to fuse the solder layer and the first metal layer, form a first gap region between the solder layer and the first resist layer, and form the semiconductor integrated circuit and the first resist layer. Provided is a method of manufacturing a semiconductor integrated circuit apparatus including a step of forming a second gap region between the two.

According to the present embodiment, it is possible to provide a semiconductor integrated circuit device and a method for manufacturing the same, in which solder suction to vias can be avoided, reliability is improved, and heat dissipation performance is improved.

FIG. 5 is a schematic plane pattern configuration diagram before forming a solder layer in the semiconductor integrated circuit apparatus according to the first embodiment. The schematic plane pattern block diagram of the metal mask applied in the manufacturing method of the semiconductor integrated circuit apparatus which concerns on 1st Embodiment. FIG. 5 is a schematic plane pattern configuration diagram after forming a solder layer in the semiconductor integrated circuit apparatus according to the first embodiment. In the semiconductor integrated circuit apparatus according to the first embodiment, an X-ray image diagram (schematic plane pattern configuration diagram) after performing the reflow process. (A) Schematic cross-sectional structure diagram (No. 1) for explaining one step of the method for manufacturing the semiconductor integrated circuit device according to the first embodiment, (b) The semiconductor integrated circuit device according to the first embodiment. Schematic cross-sectional structure diagram for explaining one step of the manufacturing method (No. 2), (c) Schematic cross-sectional structure diagram for explaining one step of the manufacturing method of the semiconductor integrated circuit device according to the first embodiment (No. 3). ). (A) Schematic cross-sectional structure diagram (No. 4) for explaining one step of the method for manufacturing the semiconductor integrated circuit device according to the first embodiment, (b) The semiconductor integrated circuit device according to the first embodiment. Schematic cross-sectional structure diagram for explaining one step of the manufacturing method (No. 5), (c) Schematic cross-sectional structure diagram for explaining one step of the manufacturing method of the semiconductor integrated circuit device according to the first embodiment (No. 6). ). FIG. 3 is a schematic planar pattern structure diagram after performing the solder layer formation, the semiconductor integrated circuit mounting, and the reflow process in the semiconductor integrated circuit apparatus according to the first embodiment. (A) Schematic cross-sectional structure diagram for explaining the heat dissipation performance of the semiconductor integrated circuit device according to the first embodiment, (b) As a comparative example, a schematic solder bridge (side surface at the time of mounting) when the amount of solder is large. Explanatory drawing. FIG. 5 is a schematic plane pattern configuration diagram before forming a solder layer in the semiconductor integrated circuit apparatus according to the second embodiment. The schematic plane pattern block diagram of the metal mask applied in the manufacturing method of the semiconductor integrated circuit apparatus which concerns on 2nd Embodiment. FIG. 3 is a schematic planar pattern structure diagram after performing the solder layer formation, the semiconductor integrated circuit mounting, and the reflow process in the semiconductor integrated circuit apparatus according to the second embodiment. FIG. 5 is a schematic plane pattern configuration diagram before forming a solder layer in the semiconductor integrated circuit apparatus according to the third embodiment. The schematic plane pattern block diagram of the metal mask applied in the manufacturing method of the semiconductor integrated circuit apparatus which concerns on 3rd Embodiment. FIG. 3 is a schematic planar pattern structure diagram after performing the solder layer formation, the semiconductor integrated circuit mounting, and the reflow process in the semiconductor integrated circuit apparatus according to the third embodiment.

Next, the present embodiment will be described with reference to the drawings. In the description of the drawings below, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimensions, the ratio of the thickness of each layer, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined in consideration of the following explanation. In addition, it goes without saying that the drawings include parts having different dimensional relationships and ratios from each other.

Further, the embodiments shown below exemplify devices and methods for embodying the technical idea, and do not specify the materials, shapes, structures, arrangements, etc. of the component parts to the following. .. This embodiment can be modified in various ways within the scope of the claims.

[First Embodiment]
(Structure before solder layer formation)
In the semiconductor integrated circuit device 100 according to the first embodiment, an example of a schematic planar pattern structure (land pattern) before the formation of the solder layer 24 is shown as shown in FIG. The planar pattern structure of FIG. 1 corresponds to an insulating substrate (mounting substrate) 12 on which the semiconductor integrated circuit 10 is mounted. FIG. 1 shows an example in which the semiconductor integrated circuit device 100 is mounted on a QFN (Quad Flat Non-leaded package) 20-pin package. As shown in FIG. 5A, the mounting substrate includes an insulating substrate 12, a metal layer 16 arranged on the insulating substrate 12, and a metal layer 14 arranged on the back surface of the insulating substrate 12. Here, for the sake of simplicity, the notation of the insulating substrate (mounting substrate) 12 is simply used as the mounting substrate.

As shown in FIG. 1, resist layers 20 and 20C are formed on the insulating substrate (mounting substrate) 12. That is, the resist layer 20 is arranged on the insulating substrate 12 excluding the terminal electrode 22 and the metal layer (copper foil layer) 16 corresponding to the Exposed PAD. Further, in a plan view, four vias 18 are arranged in the region corresponding to the Exposed PAD, and a resist layer 20C is arranged around each via 18.

(Metal mask)
A schematic planar pattern configuration of the metal mask (stencil) 200 applied in the method for manufacturing the semiconductor integrated circuit device 100 according to the first embodiment is shown as shown in FIG. The metal mask 200 can be formed of, for example, SUS, a nickel alloy, Cr, Al, or the like. Here, the metal mask 200 is arranged on the insulating substrate 12 before the formation of the solder layer 24 shown in FIG. As shown in FIG. 2, the metal mask 200 masks the via 18 and the portion of the resist layer 20C. In FIG. 2, the portion of the via 18 and the resist layer 20C masked by the metal mask 200 is shown by a broken line.

As shown in FIG. 2, the metal mask 200 has an opening 122 for forming the solder layer 24 on the terminal electrode 22 and a solder layer 24 for forming the solder layer 24 on the metal layer 16 corresponding to the Exposed PAD (EPAD). It is provided with an opening 120. Here, it is desirable that the opening 122 of the Exposed PAD (EPAD) portion is about 60% of the PAD size. This is to avoid a solder bridge between the solder layer 24 (16) on the metal layer 16 corresponding to the Exposed PAD (EPAD) and the solder layer 24 (22) on the terminal electrode 22.

(Structure after forming the solder layer)
In the semiconductor integrated circuit device 100 according to the first embodiment, the metal mask 200 shown in FIG. 2 is applied to the insulating substrate 12 shown in FIG. 1, and the solder layer 24 is formed into a schematic plane. The pattern configuration is represented as shown in FIG.

On the insulating substrate 12, as shown in FIG. 3, the solder layer 24 (22) on the terminal electrode 22 and the solder layer 24 (22)
A solder layer 24 (16) is formed on the metal layer 16 corresponding to the Exposed PAD (EPAD). Further, by applying the metal mask 200 having the opening 120, the via 18 in the Exposed PAD (EPAD) and the peripheral portion of the resist layer 20C around the via 18 have 16 portions of the metal layer corresponding to the four corners of the Exposed PAD. Be exposed. A solder layer 24 flows into the exposed metal layer 16 through a subsequent reflow process, and a solder layer 24 (16) on the metal layer 16 corresponding to the four corners of the Exposed PAD is formed.

(X-ray image)
In the semiconductor integrated circuit apparatus 100 according to the first embodiment, an X-ray image diagram (schematic planar pattern configuration diagram) after performing the reflow step is shown as shown in FIG.

As shown in FIG. 4, the package of the semiconductor integrated circuit 10 is mounted on the insulating substrate 12, so that the pattern on the surface of the insulating substrate (mounting substrate) 12 in the region where the semiconductor integrated circuit 10 is mounted is X-ray. It is shown by a broken line as an image. The pattern on the surface of the insulating substrate (mounting substrate) 12 outside the region where the semiconductor integrated circuit 10 is mounted is shown by a solid line as an X-ray image.

In the semiconductor integrated circuit device 100 according to the first embodiment, the semiconductor integrated circuit 10 is as shown in FIG. 4 with respect to the insulating substrate (mounting substrate) 12 after forming the solder layer 24 shown in FIG. After mounting, the reflow process is carried out. By this reflow step, the solder layer 24 flows into the metal layer 16 corresponding to the four corners of the Exposed PAD, and the solder layer 24 (16) on the metal layer 16 corresponding to the four corners of the Exposed PAD is formed. That is, as shown in FIG. 4, the solder layer 24 (16) is formed over the entire area on the metal layer 16 corresponding to the Exposed PAD (EPAD) except for the via 18 and the resist layer 20C around the via 18.

In the semiconductor integrated circuit device 100 according to the first embodiment, since the metal mask 200 is applied on the via 18 in the manufacturing process, the solder layer 24 is not applied on the via 18.

Further, at the time of reflow mounting, the solder under the Exposed PAD gets wet and spreads, but since there is a resist layer 20C around the via 18, the solder layer 24 is repelled and the solder sucking up by the via 18 does not occur. The solder layer 24 wets and spreads around the resist layer 20C.

In the semiconductor integrated circuit device 100 according to the first embodiment, by setting the metal mask opening 120 to about 60% of the Exposed PAD size, it is possible to avoid the formation of a solder bridge between the Exposed PAD and the terminal electrode (PIN). Is.

Here, as a comparative example, a schematic description of the solder bridge (side surface at the time of mounting) when the amount of solder is large is shown as shown in FIG. 8 (b). That is, FIG. 8B corresponds to the schematic cross-sectional structure along the IV-IV line in FIG. 7 when the amount of solder is large. If the amount of the solder layer 24 is large, there is a possibility of bridging (short-circuiting) at the adjacent portion S of the solder layer 24 (22) and the solder layer 24 (16) connected to the island 6 of the package. Here, the solder layer 24 (22) is a solder layer arranged on the terminal electrode 22, and the solder layer 24 (16) is a solder layer arranged on a metal layer 16 corresponding to an Exposed PAD (EPAD). is there. The metal layer 16 on the insulating substrate 12 is not shown in FIG. 8B.

A schematic cross-sectional structure (No. 1) for explaining one step of the method for manufacturing a semiconductor integrated circuit device according to the first embodiment is shown as shown in FIG. 5 (a), and the method for manufacturing a semiconductor integrated circuit device. The schematic cross-sectional structure (No. 2) for explaining one step is represented as shown in FIG. 5 (b), and the schematic cross-sectional structure (No. 3) for explaining one step of the method for manufacturing a semiconductor integrated circuit device is , As shown in FIG. 5 (c). Here, the schematic cross-sectional structure shown in FIGS. 5 (a) to 5 (c) corresponds to the schematic cross-sectional structure along the line I-I of FIG. That is, it corresponds to a schematic cross-sectional structure in the vicinity of one via 18.

Further, a schematic cross-sectional structure (No. 4) for explaining one step of the method for manufacturing a semiconductor integrated circuit device according to the first embodiment is shown as shown in FIG. 6A, and is a semiconductor integrated circuit device. The schematic cross-sectional structure (No. 5) for explaining one step of the manufacturing method is represented as shown in FIG. 6 (b), and the schematic cross-sectional structure for explaining one step of the manufacturing method of the semiconductor integrated circuit device (No. 6). ) Is represented as shown in FIG. 6 (c). The schematic cross-sectional structure shown in FIGS. 6 (a) and 6 (b) corresponds to the schematic cross-sectional structure along the line II-II of FIG. Further, the schematic cross-sectional structure shown in FIG. 6C corresponds to the schematic cross-sectional structure along the VV line of FIG. 7. That is, it corresponds to a schematic cross-sectional structure in the vicinity of one via 18.

Here, as shown in FIG. 5A, the mounting substrate includes an insulating substrate 12, a metal layer 16 arranged on the insulating substrate 12, and a metal layer 14 arranged on the back surface of the insulating substrate 12. Be prepared.

The substrate structure composed of the insulating substrate 12, the metal layer 16 arranged on the front surface of the insulating substrate 12, and the metal layer 14 arranged on the back surface of the insulating substrate 12 is, for example, a copper foil layer, an epoxy resin layer, and copper. It has a circuit board structure composed of a bonded body with a foil layer. For example, as a circuit board structure composed of a copper foil layer, an epoxy resin layer, and a copper foil layer, a PCB substrate such as CEM3, FR4, or FR5 can be applied. Further, a circuit board composed of a metal layer, a ceramic substrate, and a metal layer, or an insulating substrate (circuit board) such as a DBC substrate, a DBA substrate, or an AMB substrate may be provided.

As shown in FIG. 5A, the insulating substrate 12 includes a via 18 in which a metal layer 15 is arranged on the side surface of the inner wall. A plurality of vias 18 may be arranged. Further, as shown in FIG. 5A, the via 18 penetrates the insulating substrate 12, and the metal layer 15 connects between the metal layer 16 and the metal layer 14.

In the semiconductor integrated circuit device 100 according to the first embodiment, the semiconductor integrated circuit 10 is mounted on the metal layer 16 via the solder layer 24, and the schematic planar pattern structure after the reflow step is as shown in FIG. It is represented by. Further, in the semiconductor integrated circuit device 100 according to the first embodiment, a schematic cross-sectional structure along the line III-III of FIG. 7 is shown as shown in FIG. 8A.

As shown in FIGS. 6 (c) and 8 (a), the semiconductor integrated circuit device 100 according to the first embodiment is provided on the insulating substrate 12, the via 18 penetrating the insulating substrate 12, and the insulating substrate 12. The arranged metal layer 16, the first resist layer 20C arranged on the metal layer 16 around the via 18, the solder layer 24 arranged on the metal layer 16, the solder layer 24, and the resist layer 20C. A first gap region 26G formed between them and a semiconductor integrated circuit 10 arranged on the solder layer 24 are provided.

Further, a second gap region 28G formed between the semiconductor integrated circuit 10 and the resist layer 20C may be provided.

Here, the resist layer 20C is not substantially arranged on the upper part of the via 18. A part of the solder layer 24 arranged on the metal layer 16 may be stretched and arranged on the resist layer 20C arranged on the metal layer 16 around the via 18.

Further, the metal layer 14 arranged on the back surface of the insulating substrate 12 and facing the metal layer 16 via the insulating substrate 12 and the resist layer 20B arranged on the metal layer 14 may be provided.

Further, the metal layer 15 arranged on the side surface of the inner wall of the via 18 and connected to the metal layer 16 and the metal layer 14 may be provided.

Further, the metal layer 16, the metal layer 14, or the metal layer 15 may include the same material.

The resist layer 20C and the resist layer 20B may include the same material.

Further, as shown in FIG. 8A, the semiconductor integrated circuit 10 may include an island 6 that can be fused with the solder layer 24, and a semiconductor integrated circuit chip 8 arranged on the island 6.

Further, a plurality of vias 18 may be provided.

Further, as shown in FIGS. 4 and 7, a plurality of terminal electrodes 22 arranged on the insulating substrate 12 and arranged around the metal layer 16 may be provided.

Further, the terminal electrode 22 may be provided with the same material as the metal layer 16.

(Production method)
In the method of manufacturing the semiconductor integrated circuit device 100 according to the first embodiment, as shown in FIGS. 5 (a) to 5 (c) and FIGS. 6 (a) to 6 (c), the insulating substrate 12 is used. The step of preparing and forming the via 18 on the insulating substrate 12, the metal layer 16 is formed on the surface of the insulating substrate 12, the metal layer 14 is formed on the back surface of the insulating substrate 12, and the metal is formed on the inner wall side surface of the via 18. The step of forming the layer 15, the step of filling the metal layer 16 and the metal layer 14 and the via 18 to form the resist layer 20 ・ 20B ・ 20T, and the step of forming the resist layer 20 ・ 20B ・ 20T so as to penetrate the via 18 A step of patterning 20T to form a resist layer 20C on a metal layer 16 around a via 18, a step of forming a solder layer 24 on the metal layer 16, and a semiconductor integrated circuit 10 mounted on the solder layer 24. The solder layer 24 and the metal layer 16 are fused, and the first gap region 26G is formed between the solder layer 24 and the resist layer 20C, and the semiconductor integrated circuit 10 and the resist layer are formed. It has a step of forming a second gap region 28G with 20C.

Further, the step of forming the resist layer 20C includes a step of patterning the resist layers 20, 20B, and 20T so as to penetrate the via 18, and forming the resist layer 20C on the metal layer 16 around the via 18. The resist layer 20C is formed on the upper part of the metal layer 15 on the side surface of the inner wall of the via 18, but the upper part of the hollowed-out via 18 is not formed.

Further, the step of forming the metal layer 16, the metal layer 14, and the metal layer 15 may be carried out by a plating step.

Further, the step of forming the solder layer 24 may include a step of applying cream solder.

Further, the step of forming the solder layer 24 includes a step of applying the metal mask 200 shown in FIG. 2 to avoid coating the solder layer 24 on the via 18 and the resist layer 20C around the via 18. You may have.

Hereinafter, a method for manufacturing the semiconductor integrated circuit device 100 according to the first embodiment will be described with reference to FIGS. 5 (a) to 5 (c) and FIGS. 6 (a) to 6 (c).

(A) First, as shown in FIG. 5 (a), the insulating substrate 12 is prepared and the via 18 is formed.

(B) Next, as shown in FIG. 5A, a metal layer 16 is formed on the surface of the insulating substrate 12 by a plating step. At the same time, the metal layer 14 is formed on the back surface of the insulating substrate 12. At the same time, the metal layer 15 is formed on the inner wall side surface of the via 18 of the insulating substrate 12. In the plating step, for example, a seed electrode (Cu) for copper (Cu) plating is formed by a sputtering step. The inner wall side surface of the via 18 may be formed by an oblique sputtering process. Then, the metal layers 16, 15, and 14 are formed on the seeds electrode by using an electrolytic plating step or an electroless plating step. The metal layers 16, 15, and 14 are made of, for example, a copper foil layer.

(C) Next, as shown in FIG. 5 (b), the resist layer 20 is formed on the metal layer 16 on the surface of the insulating substrate 12. Similarly, the resist layer 20B is formed on the metal layer 14 on the back surface of the insulating substrate 12. Similarly, the via 18 penetrating the insulating substrate 12 is filled to form the resist layer 20T. The resist layers 20B and 20T can be formed of the same material as the resist layer 20. The resist layer can be formed using a printing process. In the above description, steps such as etching that are not related to the formation of the via 18 of the insulating substrate 12 are omitted.

(D) Next, as shown in FIG. 5 (c), the resist layers 20, 20B, and 20T are patterned so as to penetrate the via 18, and the resist layer 20C for the cap is formed. The structure of FIG. 5 (c) corresponds to the cross-sectional structure along the line I-I of FIG. The resist layer 20C is formed on the metal layer 16 around the via 18.

(E) Next, as shown in FIG. 6A, the solder layer 24 is formed on the metal layer 16. The structure of FIG. 6A corresponds to the cross-sectional structure along line II-II of FIG. Therefore, there are a portion where the solder layer 24 is formed and a portion where the solder layer 24 is not formed on the metal layer 16. In the step of forming the solder layer 24, the metal mask 200 shown in FIG. 2 is applied. By using the metal mask 200, it is possible to avoid coating the solder layer 24 on the via 18 and the resist layer 20C around the via 18. Further, the solder layer 24 may be formed by applying, for example, cream solder.

(F) Next, as shown in FIG. 6B, the semiconductor integrated circuit 10 is mounted on the solder layer 24. Here, when the semiconductor integrated circuit 10 is mounted on the solder layer 24, a part of the solder layer 24 is pushed out between the semiconductor integrated circuit 10 and the resist layer 20C. Further, a gap region 28G is formed between the semiconductor integrated circuit 10 and the resist layer 20C.

(G) Next, as shown in FIG. 6 (c), a reflow step is carried out. The structure of FIG. 6C corresponds to the cross-sectional structure along the VV line of FIG. The reflow step can be carried out, for example, by heat-treating from room temperature to a predetermined temperature within a predetermined time and then returning to room temperature within a predetermined time. Here, the predetermined temperature is, for example, about 240 ° C. to 260 ° C. in the case of lead-free solder (Sn-3Ag-0.5Cu) and about 200 ° C. to about 200 ° C. in the case of eutectic solder (Sn-37Pb). It is 220 ° C. By the reflow process, the solder layer 24 flows into the portion where the solder layer 24 is not formed on the metal layer 16. Further, after the reflow step, the solder layer 24 can be fused only to the metal layer 16 portion. Since the resist layer 20C has a property of repelling the solder layer 24 by the reflow step, a gap region 26G is formed between the solder layer 24 and the resist layer 20C.

By forming the gap regions 26G and 28G, it is possible to prevent the solder flow of the solder layer 24. By forming the gap regions 26G and 28G, it is possible to prevent the solder layer 24 from flowing into the via 18, avoid short circuits with other parts, and improve reliability.

(Heat dissipation performance)
FIG. 8A also corresponds to an explanatory diagram of heat dissipation performance of the semiconductor integrated circuit device 100 according to the first embodiment.

As shown in FIG. 8A, the solder layer 24 is fused to the metal layer 16, and a gap region 26G is formed between the metal layer 16 and the resist layer 20C. Further, a gap region 28G is formed between the semiconductor integrated circuit 10 and the resist layer 20C.

Further, as shown in FIG. 8A, the solder layer 24 is fused to the island 6 on which the semiconductor integrated circuit chip 8 of the semiconductor integrated circuit 10 is mounted. Arrows indicate heat dissipation paths.

In the semiconductor integrated circuit device 100 according to the first embodiment, as shown by the heat dissipation path indicated by the arrow in FIG. 8A, the heat generated from the semiconductor integrated circuit chip 8 is generated from the solder layer via the island 6. Lateral heat dissipation parallel to the insulating substrate 12 that conducts to 24 and further conducts the metal layer 16, and heat conduction through the metal layer 15 in the lateral direction parallel to the insulating substrate 12 that conducts the metal layer 14. Heat dissipation is also added.

In the semiconductor integrated circuit device 100 according to the first embodiment, the via 18 is arranged directly under the island 6 connected to the semiconductor integrated circuit chip (die) 8 as a heat generating source, and the solder is not sucked up. It is possible to secure good heat dissipation performance without deterioration of thermal resistance due to a decrease in the fusion rate.

In the method for manufacturing the semiconductor integrated circuit device 100 according to the first embodiment, a metal mask for avoiding solder suction to the via is applied.

According to the semiconductor integrated circuit device 100 according to the first embodiment, solder suction can be reduced by applying a resist layer around the through holes and vias directly under the Exposed PAD or Fin. Further, by adjusting the mask opening of the metal mask so that the through holes and vias are not arranged in the metal mask openings, the through holes and vias are covered and the solder layer is applied. Therefore, it is possible to further suppress the suction of the solder layer. By controlling the opening area at the same time, the solder bridge can also be suppressed.

According to the semiconductor integrated circuit device 100 according to the first embodiment, the resist is repelled by forming a resist on or around the through holes and vias at the time of forming the through holes and vias and after plating. To reduce the solder flow. Further, by applying the solder using a metal mask having a shape that covers the vias, the solder is not applied on the vias, so that the problem of solder suction can be further reduced.

[Second Embodiment]
(Structure before solder layer formation)
In the semiconductor integrated circuit device 100 according to the second embodiment, an example of a schematic planar pattern structure (land pattern) before the formation of the solder layer 24 is shown as shown in FIG. The planar pattern structure of FIG. 9 corresponds to an insulating substrate (mounting substrate) 12 on which the semiconductor integrated circuit 10 is mounted. FIG. 9 shows an example in which the semiconductor integrated circuit device 100 is mounted on a QFN 32-pin package.

As shown in FIG. 9, resist layers 20 and 20C are formed on the insulating substrate (mounting substrate) 12. That is, the resist layer 20 is arranged on the insulating substrate 12 excluding the terminal electrode 22 and the metal layer (copper foil layer) 16 corresponding to the Exposed PAD. Further, in a plan view, nine vias 18 are arranged in the region corresponding to the Exposed PAD, and a resist layer 20C is arranged around each of the vias 18.

(Metal mask)
The schematic planar pattern configuration of the metal mask (stencil) 200 applied in the manufacturing method of the semiconductor integrated circuit device 100 according to the second embodiment is shown as shown in FIG. The metal mask 200 can be formed of, for example, SUS, a nickel alloy, Cr, Al, or the like. Here, the metal mask 200 is arranged on the insulating substrate 12 before the formation of the solder layer 24 shown in FIG. As shown in FIG. 10, the metal mask 200 masks the via 18 and the portion of the resist layer 20C. In FIG. 10, the portion of the via 18 and the resist layer 20C masked by the metal mask 200 is shown by a broken line.

As shown in FIG. 10, the metal mask 200 has an opening 122 for forming the solder layer 24 on the terminal electrode 22 and a solder layer 24 for forming the solder layer 24 on the metal layer 16 corresponding to the Exposed PAD (EPAD). It has openings 120 ₁ , 120 ₂ , 120 ₃ , 120 ₄ . _{Here, it is desirable that the openings 120 1} , 120 ₂ , 120 ₃ , and 120 ₄ of the Exposed PAD (EPAD) portion are about 60% of the PAD size. This is to avoid a solder bridge between the solder layer 24 (16) on the metal layer 16 corresponding to the Exposed PAD (EPAD) and the solder layer 24 (22) on the terminal electrode 22.

(Solder layer formation, semiconductor integrated circuit mounting, configuration after reflow process)
In the semiconductor integrated circuit device 100 according to the second embodiment, the metal mask 200 shown in FIG. 10 is applied to the insulating substrate 12 shown in FIG. 9 to form a solder layer 24, and the semiconductor integrated circuit is mounted. The schematic plane pattern structure after the reflow process is performed is shown in FIG.

As shown in FIG. 11, a solder layer 24 (22) on the terminal electrode 22 and a solder layer 24 (16) on the metal layer 16 corresponding to the Exposed PAD (EPAD) are formed on the insulating substrate 12. Further, _{by applying the metal mask 200 having openings 120 1} , 120 ₂ , 120 ₃ , 120 ₄ , the via 18 in the Exposed PAD (EPAD) and the peripheral portion of the resist layer 20C around the via 18 are formed into a metal layer. 16 parts are exposed. The solder layer 24 flows into the exposed metal layer 16 through a subsequent reflow step, and the solder layer 24 (16) is formed on the exposed metal layer 16.

(X-ray image)
In the semiconductor integrated circuit apparatus 100 according to the second embodiment, the X-ray image diagram (schematic plane pattern configuration diagram) after the reflow step is performed is shown in the same manner as in FIG.

As shown in FIG. 11, the package of the semiconductor integrated circuit 10 is mounted on the insulating substrate 12, so that the pattern on the surface of the insulating substrate (mounting substrate) 12 in the region where the semiconductor integrated circuit 10 is mounted is X-ray. It is shown by a broken line as an image. The pattern on the surface of the insulating substrate (mounting substrate) 12 outside the region where the semiconductor integrated circuit 10 is mounted is shown by a solid line as an X-ray image.

In the semiconductor integrated circuit device 100 according to the second embodiment, as shown in FIG. 11, the semiconductor integrated circuit 10 is mounted on the insulating substrate (mounting substrate) 12 after the solder layer 24 is formed, and then reflows. Carry out the process. By this reflow step, the solder layer 24 flows into the metal layer 16 corresponding to the Exposed PAD, and the solder layer 24 (16) on the metal layer 16 corresponding to the Exposed PAD is formed. That is, as shown in FIG. 11, except for the via 18 and the resist layer 20C around the via 18, the solder layer 24 (16) is formed over the entire metal layer 16 corresponding to the Exposed PAD (EPAD).

In the semiconductor integrated circuit device 100 according to the second embodiment, since the metal mask 200 is applied on the via 18 in the manufacturing process, the solder layer 24 is not applied on the via 18.

Further, at the time of reflow mounting, the solder under the Exposed PAD gets wet and spreads, but since there is a resist layer 20C around the via 18, the solder layer 24 is repelled and the solder sucking up by the via 18 does not occur. The solder layer 24 wets and spreads around the resist layer 20C.

Also in the semiconductor integrated circuit device 100 according to the second embodiment, by setting the metal mask opening 120 to about 60% of the Exposed PAD size, it is possible to avoid the formation of a solder bridge between the Exposed PAD and the terminal electrode (PIN). Is.

[Third Embodiment]
(Structure before solder layer formation)
In the semiconductor integrated circuit device 100 according to the third embodiment, an example of a schematic planar pattern structure (land pattern) before the formation of the solder layer 24 is shown as shown in FIG. The planar pattern structure of FIG. 12 corresponds to an insulating substrate (mounting substrate) 12 on which the semiconductor integrated circuit 10 is mounted. FIG. 12 shows an example in which the semiconductor integrated circuit device 100 is mounted on the HTSOP-J8 type 8-pin package.

As shown in FIG. 12, resist layers 20 and 20C are formed on the insulating substrate (mounting substrate) 12. Further, on the insulating substrate 12 excluding the terminal electrode 22, the metal layer 16 corresponding to the Exposed PAD, and the via 18 ₁・ 18 ₂・ 18 ₃・ 18 ₄・ 18 ₅・ 18 ₆・ 18 ₇・ 18 ₈・ 18 ₉・ 18 _10. The resist layer 20 is arranged in the. _{That is, 10 vias 18 1}・ 18 ₂・ 18 ₃・ 18 ₄・ 18 ₅・ 18 ₆・ 18 ₇・ 18 ₈・ 18 ₉・ 18 ₁₀ are arranged around the metal layer 16 corresponding to the Exposed PAD. , 18 ₁・ 18 ₂・ 18 ₃・ 18 ₄・ 18 ₅・ 18 ₆・ 18 ₇・ 18 ₈・ 18 ₉・ 18 A resist layer 20 is arranged around the _{10 vias.}

_{Further, in a plan view, two vias 18 11} and 18 ₁₂ are arranged in the metal layer 16 region corresponding to the Exposed PAD, and a resist layer 20C is arranged around the _{vias 18 11} and 18 _12. ..

(Metal mask)
A schematic planar pattern configuration of the metal mask (stencil) 200 applied in the method for manufacturing the semiconductor integrated circuit device 100 according to the third embodiment is shown as shown in FIG. The metal mask 200 can be formed of, for example, SUS, a nickel alloy, Cr, Al, or the like. Here, the metal mask 200 is arranged on the insulating substrate 12 before the formation of the solder layer 24 shown in FIG. As shown in FIG. 13, by using the metal mask 200, the via 18 ₁・ 18 ₂・ 18 ₃・ 18 ₄・ 18 ₅・ 18 ₆・ 18 ₇・ 18 ₈・ 18 ₉・ 18 ₁₀・ 18 ₁₁・ 18 ₁₂ and the resist The portion of layer 20C is masked. In FIG. 13, the via 18 ₁・ 18 ₂・ 18 ₃・ 18 ₄・ 18 ₅・ 18 ₆・ 18 ₇・ 18 ₈・ 18 ₉・ 18 ₁₀・ 18 ₁₁・ 18 ₁₂ and the resist layer masked by the metal mask 200. The part of 20C is shown by a broken line.

As shown in FIG. 13, the metal mask 200 has an opening 122 for forming the solder layer 24 on the terminal electrode 22 and a solder layer 24 for forming the solder layer 24 on the metal layer 16 corresponding to the Exposed PAD (EPAD). It has openings 120 ₅ , 120 ₆ , and 120 ₇ . _{Here, it is desirable that the openings 120 5} , 120 ₆ and 120 ₇ of the Exposed PAD (EPAD) portion are about 60% of the PAD size. This is to avoid a solder bridge between the solder layer 24 (16) on the metal layer 16 corresponding to the Exposed PAD (EPAD) and the solder layer 24 (22) on the terminal electrode 22.

(Solder layer formation, semiconductor integrated circuit mounting, configuration after reflow process)
In the semiconductor integrated circuit device 100 according to the third embodiment, the metal mask 200 shown in FIG. 13 is applied to the insulating substrate 12 shown in FIG. 12 to form a solder layer 24, and the semiconductor integrated circuit 10 is formed. The schematic plane pattern structure after the reflow process is carried out is shown in FIG.

As shown in FIG. 14, a solder layer 24 (22) on the terminal electrode 22 and a solder layer 24 (16) on the metal layer 16 corresponding to the Exposed PAD (EPAD) are formed on the insulating substrate 12. Furthermore, by applying the metal mask 200 having _{openings 120 5} , 120 ₆ , 120 _{7 , vias 18 1}・ 18 ₂・ 18 ₃・ 18 ₄・ 18 ₅・ 18 ₆・ 18 ₇・ 18 ₈・ 18 ₉・ 18 ₁₀・ 18 ₁₁・ 18 ₁₂ and the resist layer 20 around it and via 18 ₁₁・ 18 ₁₂ and the peripheral part of the resist layer 20C around it are exposed with 16 metal layers. The solder layer 24 flows into the exposed metal layer 16 through a subsequent reflow step, and the solder layer 24 (16) is formed on the exposed metal layer 16.

(X-ray image)
In the semiconductor integrated circuit apparatus 100 according to the third embodiment, the X-ray image diagram (schematic plane pattern configuration diagram) after the reflow step is performed is shown in the same manner as in FIG.

As shown in FIG. 14, the package of the semiconductor integrated circuit 10 is mounted on the insulating substrate 12, so that the pattern on the surface of the insulating substrate (mounting substrate) 12 in the region where the semiconductor integrated circuit 10 is mounted is X-ray. It is shown by a broken line as an image. The pattern on the surface of the insulating substrate (mounting substrate) 12 outside the region where the semiconductor integrated circuit 10 is mounted is shown by a solid line as an X-ray image.

In the semiconductor integrated circuit device 100 according to the third embodiment, as shown in FIG. 14, the semiconductor integrated circuit 10 is mounted on the insulating substrate (mounting substrate) 12 after the solder layer 24 is formed, and then reflows. Carry out the process. By this reflow step, the solder layer 24 flows into the metal layer 16 corresponding to the Exposed PAD, and the solder layer 24 (16) on the metal layer 16 corresponding to the Exposed PAD is formed. That is, as shown in FIG. 14, 18 ₁・ 18 ₂・ 18 ₃・ 18 ₄・ 18 ₅・ 18 ₆・ 18 ₇・ 18 ₈・ 18 ₉・ 18 ₁₀・ 18 ₁₁・ 18 ₁₂ and the resist layer around it. A solder layer 24 (16) is formed over the entire metal layer 16 corresponding to the Exposed PAD (EPAD) except for the 20 and the vias 18 ₁₁ and 18 _{12 and the resist layer 20C around the vias 18 11.18 12.}

In the semiconductor integrated circuit device 100 according to the third embodiment, in order to apply the metal mask 200 on the via 18 in the manufacturing process, the via 18 ₁・ 18 ₂・ 18 ₃・ 18 ₄・ 18 ₅・ 18 ₆・ 18 ₇・ 18 ₈・ 18 ₉・ 18 ₁₀・ 18 ₁₁・ 18 _{12 No} solder layer 24 is applied on top.

Also, at the time of reflow mounting, the solder under the exposed PAD gets wet and spreads, but via 18 ₁・ 18 ₂・ 18 ₃・ 18 ₄・ 18 ₅・ 18 ₆・ 18 ₇・ 18 ₈・ 18 ₉・ 18 ₁₀・ 18 ₁₁・ 18 _{Since there are resist layers 20 and 20C around 12,} the solder layer 24 is repelled, and vias 18 ₁・ 18 ₂・ 18 ₃・ 18 ₄・ 18 ₅・ 18 ₆・ 18 ₇・ 18 ₈・ 18 ₉・ 18 ₁₀・18 ₁₁・ 18 ₁₂ does not cause solder suction. The solder layer 24 wets and spreads around the resist layers 20C and 20.

Also in the semiconductor integrated circuit device 100 according to the third embodiment, by setting the metal mask opening 120 to about 60% of the Exposed PAD size, it is possible to avoid the formation of a solder bridge between the Exposed PAD and the terminal electrode (PIN). Is.

In the above description, the solder layer 24 can be formed of, for example, lead-free solder (Sn-3Ag-0.5Cu), eutectic solder (Sn-37Pb), or the like.

Further, on the metal layers 16, 14, 15 made of copper (Cu) foil layer and the terminal electrode 22, Au flash layer, solder plating, Au plating treatment and the like are performed to form a layer structure made of Au / Cu. It may have been done.

Further, as a package on which the semiconductor integrated circuit device according to the embodiment is mounted, a Fin package, a TO-252 type package, a TO-263 thin package, a package having a heat sink such as an Exposed PAD or Fin, or the like can be applied. ..

Further, in addition to the semiconductor integrated circuit chip mounted on the semiconductor integrated circuit apparatus according to the embodiment, for example, a field effect transistor (FET), a diode, a three-terminal regulator and the like can be mounted.

As described above, according to the present embodiment, it is possible to provide a semiconductor integrated circuit device in which solder suction to vias can be avoided, reliability is improved, and heat dissipation performance is improved, and a method for manufacturing the same. ..

[Other embodiments]
As described above, although described by this embodiment, the statements and drawings that form part of this disclosure are exemplary and should not be understood to limit this embodiment. This disclosure will reveal to those skilled in the art various alternative embodiments, examples and operational techniques.

As described above, the present embodiment includes various embodiments not described here.

The semiconductor integrated circuit device of this embodiment can be applied to a wide range of fields such as mobile devices, in-vehicle devices, industrial devices, medical devices, and display devices.

24 ... Solder layer 6 ... Island 8 ... Semiconductor integrated circuit chip 10 ... Semiconductor integrated circuit 12 ... Insulated substrate (mounting substrate)
14, 15, 16 ... Metal layer (copper foil layer)
18 _1, 18 _2, 18 _3, 18 _4, 18 _5, 18 _6, 18 _7, 18 _8, 18 _9, 18 _10, 18 _11, 18 ₁₂ ... via 20 and 20B, 20C, 20T ... resist layer 22 ... Terminal electrodes 26G, 28G ... Gap region 100 ... Semiconductor integrated circuit device 120, 120 ₁ , 120 _{2 , 120 3} , 120 ₄ , 120 ₅ , 120 ₆ , 120 ₇ , 122 ... Opening 200 ... Metal mask

Claims (14)

Insulated substrate and
Vias penetrating the insulating substrate and
The first metal layer arranged on the insulating substrate and
A first resist layer arranged on the first metal layer around the via,
The solder layer arranged on the first metal layer and
A first gap region formed between the solder layer and the first resist layer,
A semiconductor integrated circuit disposed on the solder layer,
A semiconductor integrated circuit apparatus including a second gap region formed between the semiconductor integrated circuit and the first resist layer. A second metal layer arranged on the back surface of the insulating substrate and facing the first metal layer via the insulating substrate, and a second metal layer.
With the second resist layer arranged on the second metal layer
The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is provided. The semiconductor integrated circuit device according to claim 2, further comprising a third metal layer arranged on the side surface of the inner wall of the via and connected to the first metal layer and the second metal layer. The semiconductor integrated circuit device according to claim 3, wherein the first metal layer, the second metal layer, or the third metal layer includes the same material. The semiconductor integrated circuit apparatus according to claim 2, wherein the first resist layer or the second resist layer includes the same material. The semiconductor integrated circuit is
An island that can be fused with the solder layer,
With the semiconductor integrated circuit chip arranged on the island
The semiconductor integrated circuit device according to any one of claims 1 to 5, wherein the semiconductor integrated circuit device is provided. The semiconductor integrated circuit device according to any one of claims 1 to 6, further comprising a plurality of vias. The semiconductor integrated circuit device according to any one of claims 1 to 7, further comprising terminal electrodes arranged on the insulating substrate and arranged around the first metal layer. The semiconductor integrated circuit device according to claim 8, wherein the terminal electrode includes the same material as the first metal layer. The process of preparing an insulating substrate and forming vias on the insulating substrate,
A step of forming a first metal layer on the surface of the insulating substrate, forming a second metal layer on the back surface of the insulating substrate, and forming a third metal layer on the inner wall side surface of the via.
A step of filling the first metal layer, the second metal layer, and the via to form a resist.
A step of patterning the resist to form a first resist layer on the first metal layer around the via.
The process of forming a solder layer on the first metal layer and
The process of mounting a semiconductor integrated circuit on the solder layer and
A reflow step is carried out to fuse the solder layer and the first metal layer, form a first gap region between the solder layer and the first resist layer, and form the semiconductor integrated circuit and the first metal layer. With the step of forming a second gap region with the resist layer
A method for manufacturing a semiconductor integrated circuit device. The method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein the first metal layer, the second metal layer, and the third metal layer are formed by a plating step. The method for manufacturing a semiconductor integrated circuit device according to claim 10 or 11, wherein the step of forming the solder layer includes a step of applying cream solder. The step of forming the first resist layer includes a step of patterning the resist so as to penetrate the via and forming the first resist layer on the first metal layer around the via. The method for manufacturing a semiconductor integrated circuit apparatus according to any one of claims 10 to 12. 10. The step of forming the solder layer is characterized by including a step of applying a metal mask to avoid coating the solder layer on the via and the first resist layer around the via. The method for manufacturing a semiconductor integrated circuit apparatus according to any one of 13 to 13.

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