JP6900780B2 - Circuit equipment, electronic devices and cable harnesses - Google Patents

Description

The present invention relates to circuit devices, electronic devices, cable harnesses, and the like.

Conventionally, a circuit device that realizes USB (Universal-Serial-Bus) data transfer control has been known. As a conventional technique of such a circuit device, for example, there is a technique disclosed in Patent Documents 1 and 2.

For example, Patent Document 1 discloses a technique for activating an enable control signal of a current source of a transmission circuit for HS (High Speed) mode at a timing prior to a packet transmission start timing. Patent Document 2 discloses a technique for disabling the self-propelled operation of the PLL that generates a high-speed clock for the HS mode when the HS mode is switched to the FS (Full Speed) mode.

Japanese Unexamined Patent Publication No. 2006-135397 Japanese Unexamined Patent Publication No. 2002-141911

In USB, the eye pattern is measured in the authentication test. Therefore, the transmission circuit for the USB HS mode needs to output a transmission signal that can pass the USB standard certification test for the eye pattern. However, since the signal path of the transmission signal of the transmission circuit for HS mode has a parasitic capacitance and a parasitic resistance, it becomes difficult to pass the eye pattern authentication test due to the parasitic capacitance and the parasitic resistance. Things will happen. As an example, when the transmission signal from the transmission circuit of the main controller is output to the peripheral device via the cable harness or the like, if the cable is long or the protection circuit or the like is present in the signal path, proper signal transfer is performed. Cannot be realized and the certification test cannot be passed.

Further, during USB HS mode communication, if a large parasitic capacitance is added to the bus or switch noise is propagated, there arises a problem that the communication quality of the HS mode deteriorates.

According to some aspects of the present invention, it is possible to provide a circuit device, an electronic device, a cable harness, and the like that can improve the deterioration of the signal characteristics of the USB signal.

One aspect of the present invention includes a first physical layer circuit to which the first bus of the USB standard is connected, a second physical layer circuit to which the second bus of the USB standard is connected, and the first physical layer circuit. Packets received from the bus via the first physical layer circuit are transmitted to the second bus via the second physical layer circuit, and from the second bus via the second physical layer circuit. A processing circuit that performs a transfer process for transmitting the received packet to the first bus via the first physical layer circuit, and a connection between the first bus and the second bus are connected for a first period. A bus switch circuit that is turned on in the second period and turned off in the second period, and a switch signal that controls turning on and off of the connection between the first bus and the second bus are generated, and the switch signal is used as the bus. The switch signal generation circuit includes a switch signal generation circuit supplied to the switch circuit, and the switch signal generation circuit has a charge pump circuit that operates the charge pump based on a clock signal for the charge pump, and boosts the pressure boosted by the charge pump circuit. It relates to a circuit device that generates the switch signal based on a power supply voltage.

According to one aspect of the present invention, the first and second physical layer circuits to which the first and second buses of the USB standard are connected, the processing circuit for performing packet transfer processing, the first bus and the first bus. A bus switch circuit that turns on the connection of the two buses in the first period and turns it off in the second period, and a switch signal generation circuit are provided. In this way, by turning on the connection between the first bus and the second bus, the first device connected to the first bus and the second device connected to the second bus can be used. It is possible to exchange signals between them. Further, a transfer process for transferring a packet from one of the first and second buses to the other of the first and second buses via the first and second physical layer circuits becomes possible, and the first and second buses can be transferred. Even if the signal characteristics of the signal of the bus 2 have deteriorated, this can be improved. Then, in one aspect of the present invention, the switch signal generation circuit has a charge pump circuit and controls on / off of the connection of the first and second buses based on the boosted power supply voltage boosted by the charge pump circuit. Generates a switch signal. By using the switch signal based on the boosted power supply voltage in this way, it is possible to appropriately turn on or off the switch element of the bus switch circuit. As a result, for example, a circuit device capable of appropriately exchanging signals on the first bus, the bus switch circuit, and the second bus path in the first period, and improving the deterioration of the signal characteristics of the USB signal, etc. Can be provided.

Further, in one aspect of the present invention, the charge pump circuit performs the charge pump operation when the connection between the first bus and the second bus is on, and also performs the charge pump operation, and the first bus and the second bus. The charge pump operation may be performed even when the bus connection is off.

In this way, for example, when switching from the second period to the first period, the long start-up time of the charge pump circuit becomes a time lag, and the switch signal of the appropriate boost voltage level cannot be supplied. Can be suppressed.

Further, in one aspect of the present invention, the charge pump circuit operates the charge pump based on the clock signal of the first frequency in the first period, and in the second period, the first frequency. The charge pump operation may be performed based on the clock signal of the lower second frequency.

In this way, in the first period, the switch signal based on the appropriately boosted boosted power supply voltage can be supplied to the bus switch circuit, and in the second period, the switch noise caused by the charge pump operation can be reduced. Will be.

Further, in one aspect of the present invention, the switch signal generation circuit changes the frequency of the clock signal from the second frequency to the first frequency after a given period of time has elapsed since the bus activity disappeared. You may let me.

By doing so, the frequency of the clock signal returns to the first frequency higher than the second frequency, so that the switch signal based on the appropriate boosted power supply voltage can be supplied to the bus switch circuit.

Further, in one aspect of the present invention, the given period may be a period having a length of 2 ms or more.

In this way, it is possible to change the frequency of the clock signal from the second frequency to the first frequency at an appropriate timing after the bus activity disappears.

Further, in one aspect of the present invention, the clock signal generation circuit for generating the clock signal for the charge pump and supplying the clock signal to the charge pump circuit is included, and the clock signal generation circuit is used in the second period. , The clock signal for the charge pump may be generated based on the signals of the packets transferred by the first bus and the second bus.

In this way, the clock signal for the charge pump can be generated by effectively utilizing the packet transferred in the second period.

Further, in one aspect of the present invention, the clock signal generation circuit may generate the clock signal for the charge pump based on the packet of the SOF in the second period.

In this way, the clock signal for the charge pump can be generated by effectively using the SOF packet transferred on the bus.

Further, in one aspect of the present invention, the clock signal generation circuit may generate the clock signal for the charge pump based on the EOP in the second period.

In this way, the charge pump operation can be performed at a timing that avoids the packet transfer period.

Further, in one aspect of the present invention, the clock signal generation circuit for generating the clock signal for the charge pump and supplying the clock signal to the charge pump circuit is included, and the clock signal generation circuit is used during a data packet transfer period. , The clock signal supplied to the charge pump circuit may be stopped.

In this way, it becomes possible to suppress the switch noise caused by the charge pump operation from adversely affecting the communication of the data packet.

Further, in one aspect of the present invention, the clock signal generation circuit sets the signal level of the clock signal to the first voltage level and the second voltage level when a given set period elapses after the clock signal is stopped. The voltage level of is changed from one voltage level to the other voltage level.

In this way, when the communication period of the data packet becomes long, it is possible to change the voltage level of the clock signal to perform the charge pump operation.

Further, in one aspect of the present invention, the bus switch circuit may have a switch element composed of a first conductive transistor.

By doing so, it is possible to reduce the parasitic capacitance caused by the drain capacitance of the first conductive transistor and the like, and it is possible to suppress the deterioration of communication quality.

Further, in one aspect of the present invention, the first conductive transistor may be an N transistor.

In this way, the switch element of the bus switch circuit can be realized by using the N-type transistor having high mobility.

Further, in one aspect of the present invention, the bus monitor circuit for monitoring the first bus and the second bus is included, and the bus switch circuit is based on the monitoring result of the bus monitor circuit. The connection between the bus 1 and the second bus may be turned on in the first period and turned off in the second period, and the processing circuit may perform the transfer process in the second period.

In this way, in the first period, by turning on the connection between the first bus and the second bus, the first device and the second bus connected to the first bus are connected. It becomes possible to exchange signals with the second device. Then, in the second period, the connection between the first bus and the second bus is turned off, and packets from one of the first and second buses are sent through the first and second physical layer circuits. The transfer process of transferring to the other of the first and second buses can be realized.

Another aspect of the present invention relates to an electronic device including the circuit device according to any one of the above and a processing device connected to the first bus.

Further, another aspect of the present invention relates to a cable harness including the circuit device according to any one of the above and a cable.

Explanatory drawing about the problem of deterioration of the signal characteristic of a transmission signal. Configuration example of the circuit device of this embodiment. A detailed configuration example of the circuit device of this embodiment. An operation explanatory diagram of a circuit device. An operation explanatory diagram of a circuit device. An operation explanatory diagram of a circuit device. Configuration example of switch signal generation circuit and bus switch circuit. The operation explanatory drawing of the charge pump circuit. Configuration example of the charge pump circuit. A signal waveform diagram illustrating the operation of a circuit device. A signal waveform diagram illustrating the operation of a circuit device. A signal waveform diagram illustrating the operation of a circuit device. A signal waveform diagram illustrating detailed operation of a circuit device. A signal waveform diagram illustrating detailed operation of a circuit device. A signal waveform diagram illustrating detailed operation of a circuit device. Detailed configuration example of the physical layer circuit. Configuration example of electronic equipment. Cable harness configuration example.

Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unreasonably limit the content of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as a means for solving the present invention. Not necessarily.

1. 1. Signal Characteristics of Transmission Signal Deterioration of signal characteristics of transmission signals by USB will be described with reference to FIG. FIG. 1 shows an example of an in-vehicle electronic device system, in which a USB-HUB210 is connected to a main controller 200 (host controller). For example, the upstream port of USB-HUB210 is connected to the main controller 200, and devices such as SD211 (SD card), BT212 (Bluetooth (registered trademark)), and DSRC213 (Dedicated Short Range Communications) are connected to the downstream port. To.

A portable terminal device 250 such as a smartphone is connected to the USB receptacle 226 of the cable harness 220 having the cable 224. A charging circuit 221, an electrostatic protection circuit 222, a short-circuit protection circuit 223, and the like are provided between the main controller 200 and the USB receptacle 226.

In FIG. 1, since the cable 224 is laid in the vehicle while avoiding the interior, for example, the cable length becomes long, for example, 1 to 3 m, and parasitic capacitance or the like occurs. In addition, parasitic capacitance and the like caused by circuits such as the charging circuit 221 and the electrostatic protection circuit 222 and the short-circuit protection circuit 223 also occur. Due to these parasitic capacitances and the like, the signal characteristics of the transmission signal of the USB transmission circuit (HS) of the main controller 200 are deteriorated.

In the USB authentication test, it is required that the waveform of the transmission signal does not overlap with the prohibited area of the eye pattern. However, if the cable 224 routed in the vehicle becomes long in FIG. 1 or is caused by circuits such as the charging circuit 221 and the electrostatic protection circuit 222 and the short circuit protection circuit 223, a parasitic capacitance or the like is generated, the transmission signal is transmitted. The signal quality of the is deteriorated. Therefore, there is a problem that proper signal transfer cannot be realized and the eye pattern authentication test (for example, near-end authentication test) cannot be passed. Further, during USB HS mode communication, if a large parasitic capacitance is added to the bus or switch noise is propagated, there is also a problem that the communication quality of the HS mode deteriorates.

2. Circuit device FIG. 2 shows a configuration example of the circuit device 10 of the present embodiment that can solve the above problems. The circuit device 10 of the present embodiment includes physical layer circuits 11 and 12, a processing circuit 20, a bus switch circuit 40, and a switch signal generation circuit 70. The switch signal generation circuit 70 includes a charge pump circuit 80. The circuit device 10 is not limited to the configuration shown in FIG. 2, and various modifications such as omitting some of these components or adding other components can be performed.

A USB standard bus BS1 (first bus) is connected to the physical layer circuit 11 (first physical layer circuit). A USB standard bus BS2 (second bus) is connected to the physical layer circuit 12 (second physical layer circuit). Each of the physical layer circuits 11 and 12 is composed of an analog circuit of the physical layer. The analog circuit of the physical layer is, for example, a transmission circuit for HS and FS, a reception circuit, various detection circuits, a pull-up resistor circuit, and the like. For link layers such as serial / parallel conversion circuits that convert serial data received via USB to parallel data, parallel / serial conversion circuits that convert parallel data to serial data, elastic buffers, and NRZI circuits. The corresponding circuit is included in the processing circuit 20. For example, a circuit corresponding to a link layer or the like in a USB transceiver macro cell is included in the processing circuit 20, and analog circuits such as a transmission circuit, a reception circuit, and a detection circuit are included in the physical layer circuits 11 and 12.

The bus BS1 is, for example, a bus to which the main controller side is connected, and the bus BS2 is, for example, a bus to which the peripheral device side is connected. However, this embodiment is not limited to such a connection configuration. The buses BS1 and BS2 are USB standard (in a broad sense, a given data transfer standard) bus including signal lines such as signals DP and DM (first and second signals) constituting a differential signal. Buses BS1 and BS2 can include signal lines of power supply VBUS and GND.

The processing circuit 20 is a circuit that performs transfer processing and various control processing, and can be realized by a logic circuit or the like by automatic arrangement and wiring such as a gate array. The processing circuit 20 may be realized by a processor such as a CPU or MPU. Then, the processing circuit 20 transmits (transfers) the packet received from the bus BS1 via the physical layer circuit 11 to the bus BS2 via the physical layer circuit 12, and transmits the packet received from the bus BS2 via the physical layer circuit 12. A transfer process of transmitting (transferring) to the bus BS1 via the physical layer circuit 11 is performed. For example, a packet is transferred from the bus BS1 side to the bus BS2 side, or from the bus BS2 side to the bus BS1 side without changing the packet format. At this time, the processing circuit 20 performs a packet bit resynchronization process in the transfer process. For example, when receiving a packet, each bit of the packet is sampled based on the clock signal generated by the circuit device 10. When transmitting the packet, each bit of the packet is transmitted in synchronization with the clock signal generated by the circuit device 10.

The bus switch circuit 40 turns on or off the connection (electrical connection) between the bus BS1 and the bus BS2. That is, the bus BS1 and the bus BS2 are electrically connected or electrically disconnected. Turning the connection between the bus BS1 and the bus BS2 on or off (electrically connected or disconnected) means, for example, between the signal line of the DP and DM of the bus BS1 and the signal line of the DP and DM of the bus BS2. This is to turn on or off the provided switch elements (first and second switch elements) and the like.

Specifically, as shown in FIG. 4 described later, the bus switch circuit 40 turns on the connection between the bus BS1 and the bus BS2 in the period T1 (first period). That is, the bus switch circuit 40 has a switch element provided between the bus BS1 and the bus BS2, and the switch element is turned on during the period T1. As a result, the main controller 200 (first device in a broad sense) connected to the bus BS1 and the peripheral device 260 (second device in a broad sense) connected to the bus BS2 are directly USB by the USB bus. It becomes possible to perform the signal transfer of. Further, as shown in FIG. 5 described later, the bus switch circuit 40 turns off the connection between the bus BS1 and the bus BS2 in the period T2 (second period). That is, in the period T2, the switch element provided between the bus BS1 and the bus BS2 is turned off. The processing circuit 20 performs the above transfer processing during this period T2.

Further, as shown in FIG. 2, the circuit device 10 of the present embodiment includes a switch signal generation circuit 70. The switch signal generation circuit 70 generates a switch signal SWS that controls on and off of the connection between the bus BS1 and the bus BS2, and supplies the switch signal SWS to the bus switch circuit 40. Then, due to the switch signal SWS, the switch element of the bus switch circuit 40 is turned on during the period T1 of FIG. 4, and the switch element is turned off during the period T2 of FIG. When the bus switch circuit 40 has a plurality of switch elements, the switch signal generation circuit 70 supplies a plurality of switch signal SWS for turning on or off the plurality of switch elements.

The switch signal generation circuit 70 has a charge pump circuit 80 that operates the charge pump based on the clock signal. The charge pump operation is a circuit operation of a method in which an output voltage is obtained by transitioning an electric charge and superimposing an input voltage and a voltage charged on a capacitor. The switch signal generation circuit 70 generates a switch signal SWS based on the boosted power supply voltage boosted by the charge pump circuit 80. For example, the charge pump circuit 80 generates a boosted power supply voltage higher than the normal power supply voltage by the charge pump operation. For example, when the threshold voltage of the transistor constituting the switch element of the bus switch circuit 40 is Vth and the power supply voltage is VD, the charge pump circuit 80 generates a boosted power supply voltage VH such that VH> VD + Vth. The switch signal generation circuit 70 generates a switch signal SWS based on this boosted power supply voltage. The charge pump circuit 80 supplies a boosted power supply voltage as a power supply voltage of a circuit (buffer circuit, level sister, etc.) included in the switch signal generation circuit 70, and these circuits operate based on this boosted power supply voltage.

As described above, in the present embodiment, the bus switch circuit 40 for electrically connecting or disconnecting the buses BS1 and BS2 is provided. Then, the switch signal generation circuit 70 generates a switch signal SWS based on the boosted power supply voltage boosted by the charge pump circuit 80, and supplies the switch signal SWS to the bus switch circuit 40. By using the switch signal SWS based on the boosted power supply voltage in this way, it is possible to appropriately turn on or off the switch element of the bus switch circuit 40. For example, in the transfer path TR1 of the period T1 of FIG. 4 described later. Appropriate signal exchange is possible. That is, by supplying the switch signal SWS based on the boosted power supply voltage to the gate of the transistor constituting the switch element, the transistor can be turned on appropriately. For example, by setting the boosted power supply voltage to VH> VD + Vth as described above, it is possible to prevent the voltage range passing through the switch element from being limited. In addition, the on-resistance of the transistor can be made sufficiently small. Further, by configuring the switch element only with, for example, a first conductive type (for example, N type) transistor, it is possible to reduce the parasitic capacitance caused by the drain capacitance of the first conductive type transistor, and the parasitic capacitance caused by the drain capacitance of the first conductive transistor can be reduced. Deterioration of communication quality during the period T2 can be suppressed.

Further, in the present embodiment, the charge pump circuit 80 performs a charge pump operation when the connection between the bus BS1 and the bus BS2 is on, and also performs a charge pump operation when the connection between the bus BS1 and the bus BS2 is off. .. Here, the charge pump operation may be an intermittent operation as well as a continuous operation.

For example, during the period T1 of FIG. 4, the charge pump circuit 80 operates the charge pump, a switch signal SWS based on the boosted power supply voltage of the charge pump circuit 80 is supplied to the switch element of the bus switch circuit 40, and the switch signal SWS causes the bus. The connection between BS1 and bus BS2 is turned on. When the switch element is an N-type transistor, a high-level (active) switch signal SWS is supplied to the gate of the N-type transistor to turn on the N-type transistor. On the other hand, even when the connection between the bus BS1 and the bus BS2 is off as in the period T2 of FIG. 5, the charge pump circuit 80 operates the charge pump, and the switch signal SWS based on the boosted power supply voltage of the charge pump circuit 80 is generated. It is supplied to the switch element of the bus switch circuit 40. When the switch element is an N-type transistor, a low-level (inactive) switch signal SWS is supplied to the gate of the N-type transistor.

If the charge pump circuit 80 operates the charge pump even in the period T2 in this way, even when the period T2 is switched to the period T1, the switch signal SWS of the appropriate voltage level is transmitted to the switch element of the bus switch circuit 40. Will be able to supply to. That is, if the charge pump operation is turned off in the period T2, when the charge pump operation is switched from off to on when the period T2 is switched to the period T1, the boosted voltage due to the charge pump operation does not rise immediately, so that the bus There is a possibility that the switch element of the switch circuit 40 cannot be turned off properly. When the switch element is an N-type transistor, it takes time to raise the switch signal SWS to a high level boosted voltage, and the N-type transistor cannot be properly turned on during the period T1.

In this respect, in the present embodiment, since the charge pump circuit 80 operates the charge pump even during the period T2 when the connection between the bus BS1 and the bus BS2 is off, an appropriate boost is applied when the period T2 is switched to the period T1. The switch signal SWS, which is the level of the power supply voltage, can be supplied to the switch element of the bus switch circuit 40.

Further, the charge pump circuit 80 operates the charge pump based on the clock signal CK of the frequency f1 (first frequency) in the period T1 of FIG. 4, and in the period T2 of FIG. 5, the frequency f2 (third) lower than the frequency f1. The charge pump is operated based on the clock signal CK (frequency of 2).

For example, in the period T1, the charge pump circuit 80 can supply the switch signal SWS based on the appropriately boosted boosted power supply voltage to the bus switch circuit 40 by performing the charge pump operation based on the clock signal CK of the high frequency f1. .. On the other hand, in the period T2, the charge pump circuit 80 operates the charge pump based on the clock signal CK of the slow frequency f2, so that the switch noise caused by the charge pump operation can be reduced, and the charge pump circuit 80 becomes a noise source. It is possible to suppress deterioration of the communication (HS mode) characteristics during the period T2. For example, in the period T2, since it is sufficient that the switch element of the bus switch circuit 40 can be turned off, it is permissible to some extent that the level of the boosted power supply voltage is lowered due to the low frequency f2. For example, when the switch element is an N-type transistor, it is necessary to supply an appropriately boosted high-level switch signal SWS to the N-type transistor during the period T1 to turn on the N-type transistor. On the other hand, in the period T2, since the voltage level of the switch signal SWS becomes low level, even if the voltage level of the boosted power supply voltage decreases due to the lowering of the frequency f2, there is not so much adverse effect. By lowering the frequency f2, the switch noise caused by the charge pump operation can be reduced, and the deterioration of the communication characteristics during the period T2 can be suppressed.

Further, the switch signal generation circuit 70 changes the frequency (clock frequency) of the clock signal CK from the frequency f2 to the frequency f1 after a given period has elapsed since the bus activity disappeared. That is, the low frequency f2 is changed to the high frequency f1. This given period is, for example, a period having a length of 2 ms or more (for example, a period having a length of 2 ms or more and less than 3 ms). No bus activity is, for example, a state in which packets are not being forwarded on the bus. For example, in USB, when 3 ms has passed since the bus activity disappeared, it is determined whether a reset request or a suspend request has been made. Therefore, for example, when a period of about 2 ms has elapsed, the frequency of the clock signal CK is returned from the frequency f2 to the frequency f1. That is, the clock frequency of the charge pump is returned to the high frequency f1 so that an appropriate boosted power supply voltage is generated. As a result, the switch element of the bus switch circuit 40 can be properly turned on during the period T1, and the occurrence of a situation in which the voltage range passing through the switch element can be limited can be suppressed.

FIG. 3 is a detailed configuration example of the circuit device 10 of the present embodiment. In FIG. 3, the circuit device 10 further includes a bus monitor circuit 30 and a clock signal generation circuit 50. Further, a bus BS3 for the charging circuit 221 is further provided.

The charging circuit 221 is, for example, a circuit that operates in accordance with the USB BC1.2 specification (Battery Charging Specification Rev1.2). In BC1.2, the power supply limit of VBUS, which is, for example, 500 mA or less, is extended to, for example, 2 A or less. In FIG. 3, the charging circuit 221 has, for example, a regulator circuit or the like, and an external power source is supplied to supply power to the VBUS. Further, in the past, power could be supplied only from the master side to the slave side, but in BC1.2, power can be supplied from the slave side to the master side as well. For example, even when the peripheral device 260 plays the role of the master and the main controller 200 plays the role of the slave, the power of VBUS can be supplied from the slave main controller 200 to the master peripheral device 260.

In order to realize BC1.2, the charging circuit 221 needs to perform signal transfer using DP and DM with the peripheral device 260 during the charge arbitration period and execute the BC1.2 protocol. Therefore, as will be described later with reference to FIG. 13, the bus switch circuit 40 has a bus BS3 (third bus) and a bus connected to the charging circuit 221 during the charging arbitration period (execution period of the BC1.2 protocol). Turn on the connection of BS2 (second bus) (switch from off to on). For example, the switch element provided between the bus BS3 and the bus BS2 is turned on so that the charging circuit 221 can execute signal transfer using DP and DM between the peripheral device 260 and the peripheral device 260. By doing so, it becomes possible to execute the BC1.2 protocol and perform the charge arbitration process during the charge arbitration period. For example, since the charging current can be set to an appropriate level, the charging speed can be increased.

Further, as shown in FIG. 3, the circuit device 10 includes a bus monitor circuit 30, and the bus monitor circuit 30 monitors the buses BS1 and BS2. For example, a monitor operation for monitoring the state of at least one of buses BS1 and BS2 is performed. Specifically, based on the signals from the physical layer circuit 11 and the physical layer circuit 12 (at least one physical layer circuit), a monitoring operation for monitoring the state of the bus BS1 and the bus BS2 (at least one bus) is performed. Then, the bus switch circuit 40 turns on or off the connection (electrical connection) between the bus BS1 and the bus BS2 based on the monitoring result in the bus monitor circuit 30. For example, the bus switch circuit 40 turns on the connection between the bus BS1 and the bus BS2 in the period T1 and turns it off in the period T2 based on the monitoring result in the bus monitor circuit 30. Then, the processing circuit 20 performs the transfer processing shown in FIG. 5 during the period T2 (at least in a part of the period T2). That is, the packet received from the bus BS1 via the physical layer circuit 11 is transmitted to the bus BS2 via the physical layer circuit 12, and the packet received from the bus BS2 via the physical layer circuit 12 is transmitted via the physical layer circuit 11. Performs transfer processing to be transmitted to bus BS1. As a result, packet bit resynchronization processing is performed, and high-quality signal transfer with improved deterioration of signal characteristics of the USB transmission signal can be realized.

Specifically, the bus monitor circuit 30 outputs a control signal for switch control to the switch signal generation circuit 70. That is, the bus monitor circuit 30 outputs a control signal instructing the connection of the buses BS1 and BS2 to be turned on in the period T1 and the connection of the buses BS1 and BS2 to be turned off in the period T2 to the switch signal generation circuit 70. The switch signal generation circuit 70 activates (for example, high level) the switch signal SWS (switching control signal) and turns on the switch element in the period T1 based on the control signal (monitor result) from the bus monitor circuit 30. To do. Further, based on the control signal from the bus monitor circuit 30, in the period T2, the switch signal SWS is deactivated (for example, low level) and the switch element is turned off. Further, the bus monitor circuit 30 causes the processing circuit 20 to perform the transfer processing during the period T2. For example, the bus monitor circuit 30 activates an instruction signal (permission signal) for transfer processing to the processing circuit 20.

Further, as shown in FIG. 3, the circuit device 10 includes a clock signal generation circuit 50 that generates a clock signal CK for the charge pump and supplies the clock signal CK to the charge pump circuit 80. The clock signal generation circuit 50 is a circuit that generates various clock signals used in the circuit device 10, and includes, for example, an oscillation circuit 52. An oscillator and a capacitor (not shown), which are external components, are connected to the oscillator circuit 52. The oscillator is realized by, for example, a crystal oscillator or the like. Then, the oscillation circuit 52 performs an oscillation operation of the oscillator to generate a clock signal based on the oscillation signal. Further, the clock signal generation circuit 50 can include a PLL circuit (not shown), and the PLL circuit is a multi-phase clock signal used in a DLL circuit for packet resynchronization processing based on the generated clock signal. To generate.

Then, the clock signal generation circuit 50 generates a clock signal CK for the charge pump in the period T2 based on the signals of the packets transferred by the bus BS1 and the bus BS2. Specifically, the clock signal CK is generated based on the SOF packet. For example, a clock signal CK is generated based on EOP (End Of Packet). Further, the clock signal generation circuit 50 stops the clock signal CK supplied to the charge pump circuit 80 during the data packet transfer period. Then, when a given set period elapses after the clock signal CK is stopped, the signal level of the clock signal CK is changed from one voltage level of the first and second voltage levels to the other voltage level. Details of these will be described later.

The processing circuit 20 includes a link layer circuit 22, a repeater logic circuit 24, and the like. The link layer circuit 22 is a circuit that performs processing corresponding to the link layer. The link layer circuit 22 has, for example, a serial / parallel conversion process for converting serial data received by USB into parallel data, a parallel / serial conversion process for converting parallel data into serial data for transmission, and NRZI coding and decoding. Perform processing for conversion. The repeater logic circuit 24 performs logic processing for transmitting the packet received from the bus BS1 side to the bus BS2 side and transmitting the packet received from the bus BS2 side to the bus BS1 side. For example, each bit of the received packet is sampled using a clock signal, and the serial data obtained by sampling is converted into parallel data. Then, the parallel data after various logic processing such as NRZI is performed is converted into serial data and transmitted in synchronization with the clock signal in the circuit device 10. By doing so, the packet bit resynchronization process (resynchronization) is realized.

4, 5 and 6 are operation explanatory views of the circuit device 10 of the present embodiment. In the present embodiment, the bus monitor circuit 30 performs a monitor operation for monitoring the states of the buses BS1 and BS2 based on the signals from the physical layer circuits 11 and 12, as will be described in detail in FIG. 16 described later. Then, the bus switch circuit 40 performs a switch operation for turning on / off the connection between the bus BS1 and the bus BS2 based on the result of monitoring the bus state in the bus monitor circuit 30.

Specifically, as shown in FIG. 4, during the period T1, the bus switch circuit 40 turns on the connection of the buses BS1 and BS2. For example, when the switch signal SWS (switching control signal) from the switch signal generation circuit 70 becomes active, the switch elements provided corresponding to each of the DP and DM signal lines are turned on, and the buses BS1 and BS2 are turned on. It is electrically connected. As a result, the main controller 200 connected to the bus BS1 and the peripheral device 260 connected to the bus BS2 (for example, the portable terminal device 250 in FIG. 1) are transferred to the bus BS1, the bus switch circuit 40, and the transfer path TR1 of the bus BS2. In, it becomes possible to perform USB signal transfer. That is, signal transfer using signals DP and DM becomes possible.

On the other hand, as shown in FIG. 5, in the period T2 after the period T1, the bus switch circuit 40 turns off the connection between the bus BS1 and the bus BS2. For example, when the switch signal SWS from the switch signal generation circuit 70 becomes inactive, the switch elements provided corresponding to the signals DP and DM are turned off, and the buses BS1 and BS2 are electrically disconnected. Become. Then, the processing circuit 20 performs a transfer process for transferring packets between the buses BS1 and BS2 via the physical layer circuits 11 and 12 during this period T2 (at least a part of the period T2). That is, the packet transfer process is performed on the transfer path TR2 of FIG. For example, in the period T2, when the instruction signal (permission signal) for the transfer process from the bus monitor circuit 30 becomes active, the processing circuit 20 starts the packet transfer process on the transfer path TR2. In this transfer process, the bit resynchronization process of the packet is performed to improve the signal quality.

FIG. 6 is an operation explanatory view of the circuit device 10 when the bus BS3 for the charging circuit 221 is provided as shown in FIG. In FIG. 6, the bus switch circuit 40 turns on the connection between the bus BS3 and the bus BS2 connected to the charging circuit 221 during the charging arbitration period. For example, a switch element provided between the bus BS3 and the bus BS2 corresponding to each of the signals DP and DM is turned on during the charge arbitration period, and the bus BS3 and the bus BS2 are electrically connected. As a result, for example, the BC1.2 protocol is executed between the charging circuit 221 and the peripheral device 260, and charging arbitration processing and the like are realized. Then, after this charge arbitration period (protocol execution period of BC1.2), the signal is transferred on the transfer path TR1 by switching to the period T1 of FIG. After that, the packet is transferred on the transfer path TR2 by switching to the period T2 of FIG.

As described above, in the present embodiment, the processing circuit 20 that transfers packets between the buses BS1 and BS2 via the physical layer circuits 11 and 12 and the bus switch circuit 40 that turns on / off the connection of the buses BS1 and BS2 are provided. It will be provided. By doing so, for example, even when the signal characteristics of the signals on the buses BS1 and BS2 are deteriorated, the deterioration of the signal characteristics is improved by the resynchronization process of the packet bits on the transfer path TR2 of FIG. become able to.

For example, if the cable 224 is long as shown in FIG. 1, or if a large parasitic capacitance or a parasitic resistance exists in the transfer path, the signal characteristics are significantly deteriorated, and there is a problem that proper signal transfer cannot be realized. .. In this respect, for example, if the circuit device 10 of the present embodiment is arranged between the main controller 200 and the portable terminal device 250 (peripheral device), the deteriorated signal characteristics can be improved. Therefore, proper signal transfer between the main controller 200 and the portable terminal device 250 can be realized.

Further, in the present embodiment, the state of the buses BS1 and BS2 is monitored by the bus monitor circuit 30, and the connection of the buses BS1 and BS2 is turned on and off by the bus switch circuit 40 based on the monitoring result. Therefore, for example, in the period T1 before the high-speed packet transfer in the HS mode is performed, the buses BS1 and BS2 can be electrically connected by the bus switch circuit 40 as shown in FIG. As a result, during this period T1, it becomes possible to perform signal transfer using the signals DP and DM between the main controller 200 and the peripheral device 260, and various types of signals are transferred in the stage before the packet transfer in the HS mode. Communication becomes possible. Then, in the period T2, as shown in FIG. 5, the connections of the buses BS1 and BS2 are turned off, and the HS mode packet transfer is performed on the transfer path TR2. Then, at the time of this packet transfer, since the bit of the packet is resynchronized, it is possible to realize a high quality packet transfer in which the deterioration of the signal characteristics as described with reference to FIG.

The USB-HUB210 shown in FIG. 1 has a USB standard product ID and vendor ID. On the other hand, the circuit device 10 of the present embodiment does not have such a product ID or vendor ID, and the circuit device 10 of the present embodiment is different from the USB-HUB210 in this respect.

Further, as a circuit device for improving the deterioration of signal characteristics, there is also a circuit device called a redriver that adjusts the amplitude and aperture of signals DP and DM by an analog circuit. However, since the redriver does not perform packet transfer as in the transfer path TR2 of FIG. 5, the signal characteristics of the deteriorated signal cannot be improved by the resynchronization process, and in this respect, the present embodiment It is different from the circuit device 10.

Further, the peripheral device 260 of FIGS. 4 to 6 may be a device such as CarPlay or USB OTG (On-The-GO) that can exchange the role of the master (host) and the role of the slave (device). .. For example, it is assumed that the portable terminal device 250 of FIG. 1 is a peripheral device 260 capable of performing CarPlay or the like. In this case, a method of arranging a USB-HUB for improving the deterioration of signal characteristics is also conceivable between the main controller 200 and the peripheral device 260 (portable terminal device 250). However, when the peripheral device 260 becomes the master, the master peripheral device 260 will be connected to the downstream port of the USB-HUB, and there is a problem that proper packet forwarding cannot be realized. ..

In this respect, the circuit device 10 of the present embodiment is different from the USB-HUB, and corresponds to, for example, even when the role of the peripheral device 260 connected to the bus BS2 of FIGS. 4 to 6 is switched to the master. There is an advantage that it can be done. For example, the switching process and the setting process for the roles of the master and the slave may be performed in the period T1. Then, after the role of the peripheral device 260 is determined to be the master or the slave, packet transfer may be performed on the transfer path TR2 as shown in FIG. 5 during the period T2. Therefore, according to the method of the present embodiment, even if the peripheral device 260 is a device such as CarPlay, there is an advantage that proper packet forwarding can be realized.

3. 3. Details of the switch signal generation circuit, the bus switch circuit, and the clock signal generation circuit FIG. 7 shows a detailed configuration example of the switch signal generation circuit 70 and the bus switch circuit 40. The switch signal generation circuit 70 includes a charge pump circuit 80 and a control circuit 72. The charge pump circuit 80 receives the charge pump enable signal ENCP and the clock signal CK, and generates a boosted power supply voltage VH based on the power supply voltages VD and VS. Then, the generated boost power supply voltage VH is supplied to the corresponding circuit of the control circuit 72.

The control circuit 72 includes inverter circuits IV1 to IV4, level shifters 74 and 76, and NAND circuits NA1 and NA2. A buffer circuit is composed of NAND circuits NA1 and NA2 and inverter circuits IV3 and IV4.

An enable signal ENSW and a select signal SEL for switch signal generation are input to the switch signal generation circuit 70. The level shifter 74 receives the enable signal ENSW and its inversion signal, performs a level shift operation based on the boosted power supply voltage VH from the charge pump circuit 80, and outputs the level-shifted enable signal ENH. The level shifter 76 receives a select signal SEL and its inverting signal, performs a level shift operation based on the boosted power supply voltage VH from the charge pump circuit 80, and outputs the level-shifted select signals SELH and XSELH. XSELH is an inverted signal of SELH. "I" and "XI" of the level shifters 74 and 76 represent normal rotation input terminals and inverting input terminals, respectively, and "Q" and "XQ" represent normal rotation output terminals and inverting output terminals, respectively. ..

The NAND circuits NA1 and NA2 and the inverter circuits IV3 and IV4 constituting the buffer circuit are the switch signals SWS1 and SWS2 (FIGS. 2 and 3) based on the enable signals ENH, select signals SELH and XSELH from the level shifters 74 and 76. Switch signal SWS) is generated and output to the bus switch circuit 40.

The bus switch circuit 40 includes transistors TN1, TN2, TN3, and TN4. The transistors TN1 to TN4 form a switch element of the bus switch circuit 40.

Specifically, the transistors TN1 and TN2 correspond to switch elements that turn on or off the connection of the buses BS1 and BS2 of FIGS. 2 and 3. For example, the transistor TN1 is provided between the signal line of DP1 of bus BS1 and the signal line of DP2 of bus BS2. The transistor TN2 is provided between the signal line of DM1 of bus BS1 and the signal line of DM2 of bus BS2.

Transistors TN3 and TN4 correspond to switch elements that turn on or off the connection of buses BS2 and BS3 in FIG. For example, the transistor TN3 is provided between the signal line of DP2 of bus BS2 and the signal line of DP3 of bus BS3. The transistor TN4 is provided between the signal line of DM2 of bus BS2 and the signal line of DM3 of bus BS3.

When the enable signal ENSW (ENH) becomes low level, the switch signal generation operation is set to disable. In this case, when the switch signals SWS1 and SWS2 become low level, the N-type transistors TN1 to TN4 are turned off, and the connection between the bus BS1 and the bus BS2 and between the bus BS2 and the bus BS3 is turned off. Become.

On the other hand, when the enable signal ENSW (ENH) becomes high level, the switch signal generation operation is set to enable. In this state, when the select signal SEL becomes a high level (VD level), the select signal SELH after the level shift becomes a low level (VS level), and the select signal XSELH becomes a high level (VH level). As a result, the switch signal SWS1 becomes a high level (VH level), and the switch signal SWS2 becomes a low level (VS level). As a result, the transistors TN1 and TN2 are turned on, the transistors TN3 and TN4 are turned off, the connection between the bus BS1 and the bus BS2 is turned on, and the connection between the bus BS2 and the bus BS3 is turned off. Therefore, signals can be exchanged between the main controller 200 and the peripheral device 260 during the period T1 as shown in FIG.

On the other hand, when the enable signal ENSW becomes high level and the switch signal generation operation is set to enable and the select signal SEL becomes low level (VS level), the select signal SELH after the level shift becomes high level (V). VH level), and the select signal XSELH becomes low level (VS level). As a result, the switch signal SWS1 becomes a low level (VS level), and the switch signal SWS2 becomes a high level (VH level). As a result, the transistors TN3 and TN4 are turned on, the transistors TN1 and TN2 are turned off, the connection between the bus BS2 and the bus BS3 is turned on, and the connection between the bus BS1 and the bus BS2 is turned off. Therefore, signals can be exchanged between the peripheral device 260 and the charging circuit 221 as shown in FIG.

Further, in the present embodiment, the bus switch circuit 40 has a switch element composed of a first conductive transistor. The first conductive transistor is one of N-type and P-type conductive transistors. In FIG. 7, the first conductive transistor included in the bus switch circuit 40 is an N-type transistor TN1 to TN4. For example, the substrates of the transistors TN1 to TN4 are set to the voltage level of VS.

For example, in order to reduce the on-resistance of the switch element of the bus switch circuit 40, a method of configuring the switch element with a transfer gate (transmission gate having a CMOS structure) can be considered. In the transfer gate, since the N-type transistor and the P-type transistor are connected in parallel, the overall on-resistance can be reduced.

However, when the transfer gate is used, the N-type transistor and the P-type transistor are connected in parallel, so that the parasitic capacitance added to the buses BS1 and BS2 becomes large, and the HS in the period T2 of FIG. 5 becomes large. The communication characteristics in the mode deteriorate.

In this regard, in FIG. 7, the switch element of the bus switch circuit 40 is composed of only a single-channel first conductive transistor such as an N-transistor. Therefore, the parasitic capacitance added to the buses BS1 and BS2 can be reduced, and the deterioration of the communication characteristics in the HS mode in the period T2 of FIG. 5 can be reduced as compared with the method using the transfer gate.

Then, in the present embodiment, the on / off of the N-type transistors TN1 to TN4 is controlled by using the switch signals SWS1 and SWS2 (SWS) based on the boosted power supply voltage VH from the charge pump circuit 80. Therefore, since the switch signals SWS1 and SWS2 having a voltage level such that VH> Vth + VD are input to the gates of the transistors TN1 to TN4, it is possible to suppress the limitation of the voltage range passing through the transistors TN1 to TN4. Both can reduce the on-resistance of the transistors TN1 to TN4. In this embodiment, it is possible to carry out the modification using the transfer gate as the switch element.

FIG. 8 is an operation explanatory view of the charge pump circuit 80. In FIG. 8, the charge pump circuit 80 operates the charge pump using the capacitors CA1, CA2, and CB. The capacitors CA1, CA2, and CB are preferably capacitors built in the circuit device 10, but may be external capacitors (capacitors). In the case of a built-in capacitor, the capacitors CA1 and CA2 can be realized by, for example, a MIM (Metal-Insulator-Metal) capacitor. Capacitor CB can be realized by a capacitor based on gate capacitance, a polysilicon-polysilicon capacitor, a MIM capacitor, or the like.

In H1 of FIG. 8, the capacitors CA1 and CA2 are connected in series between the VD (high potential side power supply voltage) node and the VS (low potential side power supply voltage) node. Further, one end of the capacitor CB is connected to the VH node, and the other end is connected to the VS node. Therefore, assuming that VS = 0V and the capacitance values of CA1 and CA2 are the same, the voltage between the terminals of the capacitors CA1 and CA2 becomes VD / 2. Next, as shown in H2, the capacitors CA1 and CA2 are connected in parallel between the VH node and the VD node. As a result, the boosting operation of VH = VD + VD / 2 is performed. Then, in the charge pump operation, the connection state of H1 and the connection state of H2 in FIG. 8 are alternately switched based on the clock signal CK.

FIG. 9 is a detailed configuration example of the charge pump circuit 80. The charge pump circuit 80 includes transistors TA1 to TA3, TB1 to TB5, capacitors CA1, CA2, and CB. The transistor TA3 is an N-type transistor, and the others are P-type transistors. The clock signals AP, BP, and AN are clock signals for the charge pump corresponding to the clock signal CK, and are generated based on the clock signal CK. The clock signals AP and BP are exclusively low-level or high-level with each other, and are, for example, non-overlapping signals with each other. The clock signal AN is an inverted signal of the clock signal AP. When the enable signal ENCP becomes low level (inactive) and the transistor TB5 is turned on, the VH node and the VD node are connected, and the operation of the charge pump circuit 80 is set to disable.

The capacitor CB is provided between the VH node and the VS node, and is, for example, a capacitor having a variable capacitance value. When the clock signals AP and AN are activated, the transistors TA1, TA2 and TA3 are turned on. AP is a signal at which the low level is the active level, and AN is a signal at which the high level is the active level. When the transistors TA1, TA2, and TA3 are turned on, the connection state shown in H1 of FIG. 8 is established. That is, the capacitors CA1 and CA2 are connected in series between the VD node and the VS node.

On the other hand, when the clock signal BP becomes active, the transistors TB1, TB2, TB3, and TB4 are turned on. The BP is a signal in which the low level becomes the active level. When the transistors TB1, TB2, TB3, and TB4 are turned on, the connection state shown in H2 of FIG. 8 is obtained. That is, the capacitors CA1 and CA2 are connected in parallel between the VH node and the VD node. Then, based on the clock signal CK, the clock signals AP, AN, and BP become active or inactive, so that the connection state of H1 and the connection state of H2 in FIG. 8 are alternately switched, and the boosted power supply voltage VH that boosts VD. = VD + VD / 2 is generated. For example, if VD = 3.0V to 3.6V, VH = 4.5V to 5.4V, and VD + Vth or more (for example, Vth =) with respect to the gates of transistors TN1 to TN4 of the bus switch circuit 40 of FIG. A voltage of 0.6 to 1.0 V) can be applied. Therefore, when the voltage range of the signal passing through the bus is VS (= 0V) to VD, a boosted power supply voltage VH = VD + VD / 2, which is higher than VD + Vth, is applied to the gates of the N-type transistors TN1 to TN4. Since it can be driven, it is possible to prevent the voltage range passing through the transistors TN1 to TN4 from being limited. That is, when a signal in the voltage range of VS to VD is input from the bus BS1 side, it can be output as a signal in the voltage range of VS to VD to the bus BS2 side. Further, when a signal in the voltage range of VS to VD is input from the bus BS2 side, it can be output as a signal in the voltage range of VS to VD to the bus BS1 side.

FIG. 10 is a diagram illustrating the operation of the present embodiment when switching from the FS mode to the HS mode. During the period T1 shown in FIG. 4, signal transfer in the FS mode (LS mode) is performed between the main controller 200 and the peripheral device 260, as will be described later in FIG. That is, signal transfer in the FS mode using the signals DP and DM is performed in the transfer path TR1 of FIG. On the other hand, in the period T2 shown in FIG. 5, signal transfer in HS mode is performed between the main controller 200 and the peripheral device 260. That is, packet communication in HS mode is performed on the transfer path TR2 of FIG.

Then, in E1 of FIG. 10, the bus state is switched from the FS mode to the HS mode, but in the period T1 before the switching timing of E1, the clock signal CK for the charge pump has a frequency f1 (first) as shown in E2. Frequency) is set. For example, the charge pump circuit 80 described with reference to FIGS. 8 and 9 operates the charge pump based on the clock signal CK having a frequency f1 of about 10 KHz to 100 KHz. By operating the charge pump at such a high frequency f1, the charge pump circuit 80 of FIG. 7 has a sufficient power supply capacity, and the buffer circuits (IV3, IV4, NA1, NA2) of the control circuit 72 and the level shifter 74. , 76 can supply the boosted power supply voltage VH. Therefore, the switch signals SWS1 and SWS2 whose voltage levels have been appropriately boosted can be supplied to the transistors TN1 to TN4 of the bus switch circuit 40. As a result, it is possible to suppress the limitation of the voltage range passing through the transistors TN1 to TN4, and it is possible to reduce the on-resistance of the transistors TN1 to TN4. For example, in order to properly perform signal transfer in the period T1, it is necessary to reduce the on-resistance of the transistors TN1 to TN4, and for that purpose, it is necessary to sufficiently increase the gate width W of the transistors TN1 to TN4 (for example). W = 100 μm to 1000 μm). As the gate width increases, the gate capacitance of the transistors TN1 to TN4 increases, so that the power supply capacity of the charge pump circuit 80 that supplies the boosted power supply voltage VH to the buffer circuits (IV3, IV4, NA1, NA2) of the control circuit 72. Need to be increased. By setting the clock signal CK for the charge pump to a high frequency f1 as shown in E2 of FIG. 10, the power supply capacity of the charge pump circuit 80 can be increased.

Further, in the present embodiment, during the period T1 (FS mode) in which the connection between the bus BS1 and the bus BS2 is turned on, the charge pump circuit 80 is made to perform the charge pump operation by using the clock signal CK as shown in E2, and the bus is operated. Even in the period T2 (HS mode) in which the connection between the BS1 and the bus BS2 is turned off, the charge pump circuit 80 is made to perform the charge pump operation by using the clock signal CK as shown in E3.

That is, during the period T2 when the connection between the bus BS1 and the bus BS2 is turned off, the switch signals SWS1 and SWS2 are at a low level in order to turn off the transistors TN1 to TN4 in FIG. It is not necessary to generate the boosted power supply voltage VH. However, it takes a long start time, for example, about several tens of ms, until the charge pump circuit 80 starts and can supply an appropriate boost power supply voltage VH. Therefore, if the charge pump circuit 80 is completely stopped in the period T2, when the period T2 is switched to the period T1, the long start-up time of the charge pump circuit 80 becomes a time lag, and an appropriate boost voltage level (VH) is generated. ) Switch signals SWS1 and SWS2 cannot be supplied to the transistors TN1 to TN4. For this reason, the voltage range passing through the transistors TN1 to TN4 is limited, the on-resistance becomes high, and a problem occurs in signal transfer in the period T1 (FS mode).

On the other hand, in the present embodiment, as shown in E3 of FIG. 10, the clock signal generation circuit 50 supplies the clock signal CK for the charge pump to the charge pump circuit 80 even in the period T2 (HS mode) to charge the charge pump circuit 80. The pump circuit 80 is operating. Therefore, when the period T2 is switched to the period T1, the switch signals SWS1 and SWS2 having an appropriate boost voltage level can be supplied to the transistors TN1 to TN4. As a result, it is possible to prevent a situation in which the voltage range passing through the transistors TN1 to TN4 is limited and a situation in which the on-resistance becomes high, and it becomes possible to realize an appropriate signal transfer in the period T1.

Further, in the present embodiment, the charge pump circuit 80 operates the charge pump based on the clock signal CK of the frequency f1 in the period T1 as shown in E2 of FIG. 10, and in the period T2, the frequency f2 lower than the frequency f1. The charge pump is operated based on the clock signal CK. That is, in the period T2, the frequency of the clock signal CK is lowered as compared with the period T1. For example, in FIG. 13 described later, when the switch element of the bus switch circuit 40 is switched from on to off during the HS idle period after the host chirp K / J, the clock signal CK is changed from the frequency f1 to f2 at this switching timing. Switch.

In this way, the adverse effect of the switch noise due to the charge pump operation of the charge pump circuit 80 on the packet communication in the HS mode in the period T2 can be reduced. That is, since packet communication is performed using a differential signal with a small amplitude in the HS mode, if the charge pump operation is performed at a high frequency f1 such as the period T1, a communication error or the like is caused by switch noise due to the charge pump operation. May cause problems.

In this regard, in the present embodiment, in the period T2, the clock signal CK is set to a low frequency f2 as shown in E3 of FIG. This makes it possible to suppress the occurrence of communication error problems due to switch noise. On the other hand, during the period T1 when the FS (LS) communication is performed, the switch element of the bus switch circuit 40 is turned on, but since the signal passing through the switch element is voltage-driven, the influence of the switch noise of the charge pump operation is affected. Few. Therefore, the charge pump operation is performed as usual with the clock signal CK having a high frequency f1.

For example, in the present embodiment, in the period T2, the clock signal CK for the charge pump is generated based on the signal of the packet transferred by the buses BS1 and BS2. For example, as shown in E4 of FIG. 10, a clock signal CK is generated based on a packet of SOF (Start Of Frame). Specifically, the clock signal CK is generated based on the EOP (End Of Packet) of SOF. For example, in USB, SOF packets are sent every 125 μs during the idle period of HS mode, and EOP is set at the end of SOF. In HS mode, EOP is indicated by 8-bit NRZ 01111111 without bit stuffing. The toggle counter is operated by, for example, EOP of this SOF. For example, the toggle operation of the toggle counter is performed, and the clock signal CK is changed from the first voltage level (for example, low level) to the second voltage level (for example, high level) at the timing of the toggle operation, or the second voltage level is changed. Change from voltage level to first voltage level. For example, the clock signal CK is generated so that the rising timing and the falling timing are synchronized with the SOF (EOP). By doing so, in the period T2, it becomes possible to effectively utilize packets such as SOF to generate a clock signal CK having a low frequency f2 and cause the charge pump circuit 80 to perform a charge pump operation. Then, by using EOP, it becomes possible to operate the clock signal CK at a timing avoiding the SOF transmission period.

Further, in the present embodiment, the clock signal CK supplied to the charge pump circuit 80 is stopped during the data packet transfer period, which is the communication period of the HS mode. Stopping the clock signal CK means, for example, not changing the voltage level of the clock signal CK from one voltage level of the first and second voltage levels to the other voltage level. For example, in E5 and E6 of FIG. 10, the bus is activated and HS data packets are communicated. In such an HS mode communication period, as shown in E7, the clock signal CK is fixed at a predetermined voltage level such as a low level and stopped. That is, the clock signal CK is masked so that the charge pump circuit 80 does not operate. By doing so, the charge pump operation of the charge pump circuit 80 is stopped, and the switch noise caused by the charge pump operation can be suppressed from adversely affecting the packet communication in the HS mode. Then, when the communication of the data packet is completed and the HS idle period is reached, the clock signal CK is operated based on the SOF packet as shown in E8 and E9.

FIG. 11 is a diagram illustrating a detailed operation of the present embodiment during the communication period of the HS mode. In the present embodiment, as shown in E7 of FIG. 10, the clock signal CK is masked and stopped during the communication period of the HS mode. However, if the clock signal CK is left stopped when this communication period becomes long, the voltage level of the boosted power supply voltage VH gradually decreases due to the leakage current in the control circuit 72 of FIG. Resulting in. As a result, the start-up time of the charge pump circuit 80 when switching from the period T2 to the period T1 becomes long, and this long start-up time becomes a timing lag, and the switch signals SWS1 and SWS2 of the appropriate boost voltage level are transmitted to the transistor TN1. ~ It becomes impossible to supply to TN4.

Therefore, in the present embodiment, when a given setting period elapses after the clock signal CK is stopped, the signal level of the clock signal CK is changed from one voltage level of the first and second voltage levels to the other voltage level. Change to.

For example, in F1 of FIG. 11, the bus is active and the communication period of the HS mode is started. In this case, for example, when a given setting period TS as shown in F2 elapses after the timing of the last toggle operation of the toggle counter, the signal level of the clock signal CK is changed to, for example, a low level (third) as shown in F3. 1. Change from one voltage level of the second voltage level) to a high level (the other voltage level). After that, when the set period TS elapses, the signal level of the clock signal CK is changed from, for example, a high level to a low level as shown in F4. In this way, even if the communication period in the HS mode becomes long, the charge pump operation can be performed by using the clock signal CK having the minimum necessary frequency. Therefore, when the period T2 is switched to the period T1, the switch signals SWS1 and SWS2 having an appropriate boost voltage level can be supplied to the transistors TN1 to TN4, and the above-mentioned problems can be prevented from occurring. Will be.

For example, during the communication period in the HS mode, the communication flag set in the register of the circuit device 10 is set, and the clock signal CK supplied to the charge pump circuit 80 is stopped. On the other hand, the maximum stop time (minimum clock frequency) is set for the clock signal CK, and the clock signal CK is managed so that the stop time does not exceed the maximum stop time (below the minimum clock frequency). For example, the time constant τ of the voltage change of the boosted power supply voltage VH is obtained from the value of the stabilized capacitance of the charge pump circuit 80 and the value of the leak current. Then, based on this time constant τ, the time during which the boost power supply voltage VH does not fall below, for example, VD + Vth is obtained as the maximum stop time, and the set period TS in FIG. 11 is set to a length equal to or less than the maximum stop time. Specifically, the set period TS is set to a length of, for example, about 1 ms. By doing so, even when the clock signal CK is stopped during the communication period of the HS mode, the boosted power supply voltage VH does not fall below, for example, VD + Vth, and the above-mentioned problems can be prevented from occurring.

Further, in the present embodiment, the frequency of the clock signal CK is changed from the frequency f2 to the frequency f1 after a given period has elapsed since the bus activity disappeared. This given period is, for example, a period having a length of 2 ms or more. For example, in G1 of FIG. 12, SOF transmission is stopped, the bus is in the SE0 state, and there is no bus activity. With USB, it is determined whether a reset request has been made or a suspend request has been made 3 ms or more after the bus activity has disappeared. Therefore, in G2 of FIG. 12, when a given period TWA (for example, a period of 2 ms or more and less than 3 ms) elapses after the SOF transmission is stopped and the bus activity disappears, the clock signal is shown in G3 and G4. The CK is changed from the frequency f2 to the frequency f1. That is, the frequency changed from f1 to f2 in E2 and E3 in FIG. 10 is returned from f2 to f1. By supplying the clock signal CK having a high frequency f1 to the charge pump circuit 80 in this way, the charge pump circuit 80 can supply the boosted power supply voltage VH to the control circuit 72 of FIG. 7 with an appropriate power supply capacity. .. As a result, the transistors TN1 to TN4 can be properly set to the ON state by the switch signals SWS1 and SWS2 having an appropriate boost voltage level. By doing so, it becomes possible to realize a bus switch control method that realizes low noise and high quality HS communication.

4. Detailed operation example Next, a detailed operation example of the present embodiment in switching the switch element in the bus switch circuit 40 will be described. FIG. 13 is a signal waveform diagram showing a USB operation sequence after cable attachment. FIG. 13 shows various states of the differential signals DP and DM, and on / off states of the switch elements of the bus switch circuit 40.

In FIG. 13, the BC switch and the USB switch are switch elements provided in the bus switch circuit 40. Specifically, the BC switch is a switch element provided between the bus BS3 and the bus BS2 in FIG. 6 in the bus switch circuit 40. That is, it is a switch element realized by the transistors TN3 and TN4 of FIG. The USB switch is a switch element provided between the bus BS1 and the bus BS2 in the bus switch circuit 40. That is, it is a switch element realized by the transistors TN1 and TN2 of FIG. The off / on of the transfer process indicates the off / on of the transfer process in the transfer path TR2 of FIG.

After the cable attach (timing t1), the BC1.2 protocol described above is executed. The period shown in B1 in which the BC1.2 protocol is executed is the charge arbitration period.

Next, when the device side (peripheral device) turns on the pull-up resistor, the voltage of the signal DP is pulled up and the mode shifts to the FS mode (t2). That is, it shifts to the FS idle, and if there is nothing for a certain period of time, it shifts to the suspend state.

Next, when the host side (main controller) starts resetting (t3), the voltage of the signal DP that has been pulled up becomes the L level. The device side detects this, and the device side sends out the device chirp K (t4). After that, when a certain period of time elapses, the device side stops the device chirp K (t5). Then, the host side executes the host chirp K / J (t6). By detecting the host chirp K / J, the device side recognizes that the host side supports the HS mode and turns on the HS termination (t7). As a result, the amplitudes of the signals DP and DM are reduced to, for example, 400 mV, and the mode shifts to the HS mode. Then, when the host side finishes the reset (t8), it shifts to the HS idle, and the host side starts sending the SOF (t9).

In the present embodiment, it is possible to enable and disable the BC switch that connects the bus BS3 and the bus BS2. When the BC switch is enabled, during the charge arbitration period (protocol execution period of BC1.2) shown in period B1 of FIG. 13, the BC switch is turned on and the USB switch is turned off as shown in the state B2. become. For example, in FIG. 6, when the BC switch is turned on, the connection between the bus BS3 and the bus BS2 is turned on, and when the USB switch is turned off, the connection between the bus BS1 and the bus BS2 is turned off. As a result, signal processing for charge arbitration or the like using signals DP and DM becomes possible between the charging circuit 221 and the peripheral device 260.

When the mode shifts to the FS mode, the USB switch is turned on and the BC switch is turned off as shown in the state B3. When the USB switch is turned on, the connection between the bus BS1 and the bus BS2 is turned on, and when the BC switch is turned off, the connection between the bus BS3 and the bus BS2 is turned off. As a result, as shown in FIG. 4, the signal can be transferred between the main controller 200 and the peripheral device 260 on the transfer path TR1 using the signals DP and DM. At this time, as shown in the state B4, the transfer process on the transfer path TR2 in FIG. 5 is turned off.

Then, in the present embodiment, the on / off switching timing of the connection between the bus BS1 and the bus BS2 (switching timing of the periods T1 and T2) is set to a timing within the range shown in the period B5 of FIG. That is, at least after the start timing (t4) of the device chirp K, the connection between the bus BS1 and the bus BS2 is switched from on to off (the period T1 is switched to T2). Alternatively, at least after the end timing (t8) of the host chirp K / J, the connection between the bus BS1 and the bus BS2 is switched from on to off. For example, at least after the start timing (t4) of the device chirp K, for example, before the start timing (t9) of SOF transmission, the connection between the bus BS1 and the bus BS2 is switched from on to off, and the transfer path TR2 in FIG. The transfer process in is switched from off to on.

When the BC switch is set to disable, the BC switch is not switched on and off as shown in states B2 and B3, and the BC switch remains off as shown in state B7. .. Further, since the switching timing is within the range of the period B5, in FIG. 13, the range of the USB switch on / off switching timing and the transfer processing on / off switching timing is shown by a dotted line.

As described above, in the present embodiment, at least after the start timing (t4) of the device chirp K, the bus switch circuit 40 switches the connection between the bus BS1 and the bus BS2 from on to off, and the processing circuit 20 switches the transfer path of FIG. The transfer process in TR2 is started. For example, after the start timing of the device chirp K, the USB switch is switched from on (B3) to off (B6), and the transfer processing of the processing circuit 20 is switched from off (B4) to on (B6).

That is, when the start (t4) of the device chirp K is detected, it can be determined that the device side corresponds to the HS mode. On the other hand, it is extremely rare that the host side does not support HS mode. Therefore, when the start of the device chirp K (t4) is detected, the USB switch is switched from on to off, and the HS mode transfer process by the processing circuit 20 is switched from off (disable) to on (enabled). be able to. Therefore, the switching timing within the period B5 may be at least the timing after the start timing (t4) of the device chirp K.

Alternatively, considering the possibility that the host side does not support the HS mode, for example, when the start (t6) of the host chirp K / J is detected, the USB switch is switched from on to off, and the HS by the processing circuit 20 is used. The mode transfer process may be switched from off to on.

For example, in the present embodiment, at least after the end timing (t8) of the host chirp K / J, the bus switch circuit 40 switches the connection between the bus BS1 and the bus BS2 from on to off, and the processing circuit 20 switches the transfer path of FIG. The transfer process in TR2 may be started.

By doing so, for example, after it is determined that both the host side and the device side are compatible with the HS mode and it is determined that the mode is completely switched to the HS mode, the transfer process of the processing circuit 20 can be started properly. become.

As described above, the switching timing within the period B5 of FIG. 13 may be at least after the start timing of the device chirp K. However, it is also necessary to consider the adverse effect of the generation of glitches due to switching. Therefore, it is desirable that the switching timing is within a period set to a predetermined voltage level (for example, L level) of the signals DP and DM. For example, the period between timings t5 to t6 and the period between t8 and t9 in FIG. 13 and the like.

As described above, in the present embodiment, before the switching timing of the period B5 in FIG. 13, by turning on the USB switch as shown in the state B3, on the USB bus between the host side and the device side. Signals can be exchanged. The bus monitor circuit 30 monitors the exchange of signals on the USB bus. Then, for example, when it is determined that the HS mode transfer is possible by detecting the device chirp K or the host chirp K / J, the USB switch is switched from on to off, and the transfer process by the processing circuit 20 is switched from off to on. By doing so, after exchanging signals between the host side and the device side, it is possible to properly shift to the HS mode transfer process.

Further, in the charge arbitration period by the charging circuit 221 of FIG. 6 as shown in the period B1 of FIG. 13, the BC switch is turned on and the USB switch is turned off as shown in the state B2. By doing so, for example, in FIG. 6, it becomes possible to realize an appropriate charge arbitration process between the charging circuit 221 and the peripheral device 260.

FIG. 14 is a signal waveform diagram showing an operation sequence when a reset is performed in the transfer in HS mode. In the HS mode, the host side sends out SOF packets every 125 μs (t11, t12). When the host side starts resetting (t12), the mode shifts to FS mode, and when 3 ms or more have passed since the packets disappeared on the bus, the device side turns off the HS termination and turns on the pull-up resistor (t13). Then, since it is confirmed that the bus state is SE0 (t14), the device side determines that the reset has started and sends out the device chirp K. On the other hand, when the host side sends out the host chirp K / J, the mode shifts from the FS mode to the HS mode.

As shown in C1 of FIG. 14, in the present embodiment, when the host starts resetting, the USB switch is switched from off to on, and the transfer processing of the processing circuit 20 is switched from on to off. That is, when the reset is performed, the bus switch circuit 40 switches the connection between the bus BS1 and the bus BS2 from off to on, and the processing circuit 20 stops the transfer processing.

In this way, for example, when a reset is performed during the transfer in HS mode, the buses BS1 and BS2 are electrically connected, and the signals DP and DM are connected between the main controller 200 and the peripheral device 260, for example. It becomes possible to perform signal transfer using. After that, for example, at the switching timing within the range shown in the period C2 of FIG. 14, the USB switch is switched from on to off, and the transfer processing of the processing circuit 20 is switched from off to on. This makes it possible to properly shift to the HS mode transfer process after exchanging signals between the host side and the device side.

FIG. 15 is a signal waveform diagram showing an operation sequence when shifting from HS mode transfer to suspend and resume. When the host side starts suspending (t22), the mode shifts to FS mode, and when 3 ms or more have passed since the packets disappeared on the bus, the device side turns off the HS termination and turns on the pull-up resistor (t23). Then, the device side determines that the suspend has been started because it is confirmed that the state of the bus is J (t24). Then, when the host side starts the resume (t25) and the resume ends (t26), the device side returns to the mode at the time of suspending at the same time as the resume ends. Then, the pull-up resistor is turned off, HS termination is turned on, and the mode returns to HS mode.

As shown in D1 of FIG. 15, in the present embodiment, the USB switch is switched from off to on and the transfer process of the processing circuit 20 is switched from on to off even when the host starts suspending. That is, when suspend is performed, the bus switch circuit 40 switches the connection between the bus BS1 and the bus BS2 from off to on, and the processing circuit 20 stops the transfer processing.

In this way, for example, when suspend is started during transfer in HS mode, buses BS1 and BS2 are electrically connected, and signals DP and DM are transmitted between the main controller 200 and the peripheral device 260, for example. It becomes possible to perform the signal transfer used.

Then, after suspending, the host side resumes, so that the USB switch is switched from on to off and the transfer processing of the processing circuit 20 is switched from off to on, as shown in D2 of FIG. That is, in the present embodiment, when the resume is performed after the suspend is performed (at the end timing of the resume), the bus switch circuit 40 switches the connection between the bus BS1 and the bus BS2 from on to off, and the processing circuit 20 Starts the transfer process. In this way, the resume after suspend enables the data transfer in HS mode to be resumed properly. The operation sequence of the transition from suspend to reset is the same as the operation sequence of entering reset from suspend after cable attach to FS idle.

FIG. 16 is a configuration example of the physical layer circuit (11, 12). This physical layer circuit includes a pull-up resistor Rpu, switch elements SW_Rpu, SW_Dm, and pull-down resistors Rpd1 and Rpd2. The switch element SW_Rpu is turned on or off based on the control signal Rpu_Enable. As a result, the pull-down operation is realized. The physical layer circuit also includes a transmission circuit HSD (current driver) for HS mode, a transmission circuit LSD (driver) for LS / FS mode, resistors Rs1 and Rs2. The physical layer circuit includes a differential receiving circuit HSR (data receiver) for HS mode, a squelch detection circuit SQL (transmission envelope detector), a differential receiving circuit LSR (data receiver) for LS / FS mode, and disconnection. Includes detection circuit DIS (disconnection envelope detector), single-ended receiving circuit DP_SER, DM_SER (receiver).

Then, in the present embodiment, the bus monitor operation of the bus monitor circuit 30 is performed based on the signal from the analog circuit constituting the physical layer circuit. Specifically, as shown in FIG. 16, for example, a differential receiving circuit HSR for HS mode, a detection circuit SQL for squelch, a differential receiving circuit LSR for LS / FS mode, a disconnection detection circuit DIS, or The bus monitor circuit 30 performs a bus monitoring operation based on the signals from the single-ended receiving circuits DP_SER and DM_SER. That is, based on the signals from these analog circuits, each state of the bus such as device chirp K, host chirp K / J, idle, reset, suspend, resume, SE0, J, K, bus reset, or HS disconnection is performed. , The bus monitor circuit 30 can be monitored. Then, the bus monitor circuit 30 controls to turn on or off the switch elements (USB switch, BC switch) of the bus switch circuit 40 as described with reference to FIGS. 13, 14, and 15 based on the monitor results. , Controls to turn on or off the transfer process of the processing circuit 20. By doing so, it becomes possible to realize appropriate switch control of the bus switch circuit 40 and transfer control of the processing circuit 20 in which the state of the bus is appropriately determined.

Further, in the present embodiment, as shown in FIG. 16, during the period T1, the transmission circuit HSD for the HS mode of the physical layer circuits 11 and 12 is set to the operation off or the power saving mode. That is, in the present embodiment, during the period T1, the bus switch circuit 40 turns on the connection of the buses BS1 and BS2, and enables the direct signal exchange on the transfer path TR1 between the main controller 200 and the peripheral device 260. ing. Then, the bus monitor circuit 30 performs a bus monitoring operation based on a signal from one of the physical layer circuits 11 and 12.

In this case, the transmission circuit HSD for the HS mode of the physical layer circuits 11 and 12 does not need to operate because the HS transfer process is not performed. Therefore, in the period T1, for example, the bus monitor circuit 30 (or the processing circuit 20) sets the transmission circuit HSD for the HS mode to the operation off or the power saving mode. By doing so, it is possible to prevent unnecessary power consumption in the transmission circuit HSD for the HS mode, and it becomes possible to reduce the power consumption.

5. Electronic device, cable harness FIG. 17 shows a configuration example of the electronic device 300 including the circuit device 10 of the present embodiment. The electronic device 300 includes the circuit device 10 of the present embodiment and the main controller 200 (in a broad sense, a processing device). The main controller 200 is connected to the bus BS1. For example, the main controller 200 and the circuit device 10 are connected via the bus BS1. Further, for example, a peripheral device 260 is connected to the bus BS2 of the circuit device 10.

The main controller 200 (processing device) is realized by a processor such as a CPU or an MPU, for example. Alternatively, the main controller 200 may be realized by various ASIC circuit devices. Further, the main controller 200 may be realized by a circuit board on which a plurality of circuit devices (ICs) and circuit components are mounted. As the peripheral device 260, for example, the portable terminal device 250 as shown in FIG. 1 can be assumed, but the peripheral device 260 is not limited thereto. The peripheral device 260 may be a wearable device or the like.

The electronic device 300 can further include a storage unit 310, an operation unit 320, and a display unit 330. The storage unit 310 stores data, and its function can be realized by a semiconductor memory such as RAM or ROM, an HDD (hard disk drive), or the like. The operation unit 320 is for the user to perform an input operation, and can be realized by an operation device such as an operation button or a touch panel display. The display unit 330 displays various types of information, and can be realized by a display such as a liquid crystal or an organic EL. When a touch panel display is used as the operation unit 320, the touch panel display also functions as the operation unit 320 and the display unit 330.

The electronic device 300 realized by the present embodiment measures, for example, an in-vehicle device, a printing device, a projection device, a robot, a head-mounted display device, a biological information measuring device, a physical quantity such as a distance, a time, a flow velocity, or a flow rate. Various devices such as measuring devices, network-related devices such as base stations or routers, content providing devices for distributing content, and video devices such as digital cameras or video cameras can be assumed.

FIG. 18 shows a configuration example of the cable harness 350 including the circuit device 10 of the present embodiment. The cable harness 350 includes the circuit device 10 and the cable 360 of the present embodiment. The cable 360 is a cable for USB. The cable harness 350 may also include a USB receptacle 370. Alternatively, the cable harness 350 may include the electrostatic protection circuit 222, the short-circuit protection circuit 223, and the like shown in FIG. The cable 360 is connected to, for example, the bus BS2 of the circuit device 10. For example, a main controller 200 (processing device) or the like is connected to the bus BS1 side of the circuit device 10. The cable harness 350 is used, for example, for routing wiring in a vehicle. The cable harness 350 may be a harness other than that for a car.

Although the present embodiment has been described in detail as described above, those skilled in the art will easily understand that many modifications that do not substantially deviate from the novel matters and effects of the present invention are possible. Therefore, all such modifications are included in the scope of the present invention. For example, a term described at least once in a specification or drawing with a different term in a broader or synonymous manner may be replaced by that different term anywhere in the specification or drawing. All combinations of the present embodiment and modifications are also included in the scope of the present invention. Further, the configuration / operation of circuit devices, electronic devices, and cable harnesses, switch signal generation processing, charge pump processing, bus monitor processing, bus switch processing, transfer processing, etc. are not limited to those described in this embodiment, and various types are used. It is possible to carry out transformation.

BS1, BS2, BS3 ... Buses (first, second, third buses),
SWS, SWS1, SWS2 ... switch signal, CK ... clock signal,
TN1 to TN4 ... Transistor, IV1 to IV4 ... Inverter circuit,
NA1, NA2 ... NAND circuit, CA1, CA2, CB ... capacitor,
TA1 to TA3, TB1 to TB5 ... Transistors,
10 ... Circuit device, 11, 12 ... Physical layer circuit (first and second physical layer circuits),
20 ... processing circuit, 22 ... link layer circuit, 24 ... repeater logic circuit,
30 ... Bus monitor circuit, 40 ... Bus switch circuit, 50 ... Clock signal generation circuit,
52 ... Oscillation circuit, 70 ... Switch signal generation circuit, 72 ... Control circuit,
74, 76 ... Level shifter, 80 ... Charge pump circuit,
200 ... Main controller, 210 ... USB-HUB,
220 ... Cable harness, 221 ... Charging circuit, 222 ... Static electricity protection circuit,
223 ... Short circuit protection circuit, 224 ... Cable, 226 ... USB receptacle,
250 ... Portable terminal device, 260 ... Peripheral device,
300 ... Electronic equipment, 310 ... Storage unit, 320 ... Operation unit,
350 ... Cable harness, 360 ... Cable, 370 ... USB receptacle

Claims (13)

The first physical layer circuit to which the first bus of the USB standard is connected,
A second physical layer circuit to which the second bus of the USB standard is connected, and
A packet received from the first bus via the first physical layer circuit is transmitted to the second bus via the second physical layer circuit, and the second physical from the second bus. A processing circuit that performs transfer processing for transmitting a packet received via the layer circuit to the first bus via the first physical layer circuit, and a processing circuit that performs transfer processing.
A bus switch circuit that turns on the connection between the first bus and the second bus in the first period and turns it off in the second period.
A switch signal generation circuit that generates a switch signal that controls on and off of the connection between the first bus and the second bus and supplies the switch signal to the bus switch circuit.
Including
The switch signal generation circuit is
It has a charge pump circuit that operates the charge pump based on the clock signal for the charge pump, and generates the switch signal based on the boosted power supply voltage boosted by the charge pump circuit .
The charge pump circuit
The charge pump is operated when the connection between the first bus and the second bus is on, and the charge pump is also operated when the connection between the first bus and the second bus is off. A circuit device characterized by performing an operation. The first physical layer circuit to which the first bus of the USB standard is connected,
A second physical layer circuit to which the second bus of the USB standard is connected, and
A packet received from the first bus via the first physical layer circuit is transmitted to the second bus via the second physical layer circuit, and the second physical from the second bus. A processing circuit that performs transfer processing for transmitting a packet received via the layer circuit to the first bus via the first physical layer circuit, and a processing circuit that performs transfer processing.
A bus switch circuit that turns on the connection between the first bus and the second bus in the first period and turns it off in the second period.
A switch signal generation circuit that generates a switch signal that controls on and off of the connection between the first bus and the second bus and supplies the switch signal to the bus switch circuit.
Including
The switch signal generation circuit is
It has a charge pump circuit that operates the charge pump based on the clock signal for the charge pump, and generates the switch signal based on the boosted power supply voltage boosted by the charge pump circuit .
The charge pump circuit
In the first period, the charge pump operation is performed based on the clock signal of the first frequency, and in the second period, the charge pump operation is performed based on the clock signal of the second frequency lower than the first frequency. A circuit device characterized by performing charge pump operation. In claim 2 ,
The switch signal generation circuit is
A circuit device characterized in that the frequency of the clock signal is changed from the second frequency to the first frequency after a given period of time has elapsed since the bus activity disappeared. In claim 3 ,
A circuit device, characterized in that the given period is a period having a length of 2 ms or more. The first physical layer circuit to which the first bus of the USB standard is connected,
A second physical layer circuit to which the second bus of the USB standard is connected, and
A packet received from the first bus via the first physical layer circuit is transmitted to the second bus via the second physical layer circuit, and the second physical from the second bus. A processing circuit that performs transfer processing for transmitting a packet received via the layer circuit to the first bus via the first physical layer circuit, and a processing circuit that performs transfer processing.
A bus switch circuit that turns on the connection between the first bus and the second bus in the first period and turns it off in the second period.
A switch signal generation circuit that generates a switch signal that controls on and off of the connection between the first bus and the second bus and supplies the switch signal to the bus switch circuit.
Clock signal generation circuit and
Including
The switch signal generation circuit is
It has a charge pump circuit that operates the charge pump based on the clock signal for the charge pump, and generates the switch signal based on the boosted power supply voltage boosted by the charge pump circuit .
The clock signal generation circuit is
In the second period, the clock signal for the charge pump is generated based on the signals of the packets transferred by the first bus and the second bus, and the clock signal is supplied to the charge pump circuit. A circuit device characterized by In claim 5 ,
The clock signal generation circuit is
A circuit device comprising generating the clock signal for a charge pump based on a packet of SOF in the second period. In claim 5 or 6 ,
The clock signal generation circuit is
A circuit device comprising generating the clock signal for a charge pump based on the EOP in the second period. The first physical layer circuit to which the first bus of the USB standard is connected,
A second physical layer circuit to which the second bus of the USB standard is connected, and
A packet received from the first bus via the first physical layer circuit is transmitted to the second bus via the second physical layer circuit, and the second physical from the second bus. A processing circuit that performs transfer processing for transmitting a packet received via the layer circuit to the first bus via the first physical layer circuit, and a processing circuit that performs transfer processing.
A bus switch circuit that turns on the connection between the first bus and the second bus in the first period and turns it off in the second period.
A switch signal generation circuit that generates a switch signal that controls on and off of the connection between the first bus and the second bus and supplies the switch signal to the bus switch circuit.
Clock signal generation circuit and
Including
The switch signal generation circuit is
It has a charge pump circuit that operates the charge pump based on the clock signal for the charge pump, and generates the switch signal based on the boosted power supply voltage boosted by the charge pump circuit .
The clock signal generation circuit is
The clock signal for the charge pump is generated, the clock signal is supplied to the charge pump circuit, the clock signal supplied to the charge pump circuit is stopped, and the clock signal is stopped during the data packet transfer period. After a given set period elapses, the signal level of the clock signal is changed from one voltage level of the first voltage level and the second voltage level to the other voltage level. Circuit device. In any of claims 1 to 8 ,
The bus switch circuit is a circuit device including a switch element composed of a first conductive transistor. In claim 9 .
A circuit device characterized in that the first conductive transistor is an N transistor. In any of claims 1 to 10 ,
A bus monitor circuit for monitoring the first bus and the second bus is included.
The bus switch circuit
Based on the monitoring result in the bus monitor circuit, the connection between the first bus and the second bus is turned on in the first period and turned off in the second period.
The processing circuit
A circuit device characterized in that the transfer process is performed in the second period. The circuit device according to any one of claims 1 to 11.
The processing device connected to the first bus and
An electronic device characterized by including. The circuit device according to any one of claims 1 to 11.
With the cable
A cable harness characterized by including.

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