JP6902865B2 - Semiconductor light emitting device and manufacturing method of semiconductor light emitting device - Google Patents

Description

The present invention relates to a semiconductor light emitting device and a method for manufacturing the same.

The light emitting diode of Patent Document 1 has an ohmic contact layer, a second metal layer, a first metal layer, an insulating layer, a p-type contact layer, a p-type clad layer, and MQW (Multiple Quantum Well) on one surface of a support substrate. The light emitting layer, the n-type clad layer, and the n-type contact layer have a semiconductor layer laminated in this order, and also have an ODR structure. That is, a contact portion is embedded in a part of the insulating layer between the p-type contact layer and the first metal layer, whereby the first metal layer and the p-type contact layer are electrically connected. There is. A p-side electrode is provided on the back surface of the support substrate, and a ring-shaped n-side electrode is provided on the n-type contact layer.

Japanese Unexamined Patent Publication No. 2007-2221029

According to the invention of Patent Document 1, the output of the diode is increased by providing the ODR structure. However, in order to form the ODR structure, the manufacturing process is increased and the structure is complicated, so that the yield tends to be poor.
An object of the present invention is to provide a method capable of manufacturing a semiconductor light emitting device with a simple structure and a high yield, and to provide a semiconductor light emitting device manufactured by the method.

The method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention includes a step of forming a semiconductor layer including a light emitting layer, a translucent conductive layer, and a first metal layer on the first substrate in this order, and on the second substrate. In addition, a step of forming the second metal layer, a step of bonding the first substrate and the second substrate by joining the first metal layer and the second metal layer to each other, and after the bonding. A step of removing the first substrate, a step of selectively forming a surface electrode on the surface of the semiconductor layer after removing the first substrate, and a step of forming the front electrode on the back surface side of the second substrate. A step of thinning from the surface, a step of attaching a support substrate to the front surface side of the semiconductor layer after the thinning step, and a back surface of the second substrate with the semiconductor layer supported by the support substrate. It includes a step of forming an electrode and a step of forming a fine concavo-convex structure on the surface of the semiconductor layer by removing the support substrate and frosting the surface of the semiconductor layer.

According to this method, since the frost treatment is performed after the thinning step of the second substrate, the semiconductor light emitting device can be manufactured with a high yield. For example, in the method in which the frost treatment is performed before the thinning step, the support substrate may not be successfully peeled from the semiconductor layer after the back surface electrode is formed. On the other hand, according to one embodiment of the present invention, the support substrate can be satisfactorily peeled off, and the subsequent frost treatment step can be smoothly proceeded.

In the method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention, the second substrate has a thickness of 300 μm to 600 μm before the thinning step, and 35 μm to 80 μm by the thinning step. It may be processed to the thickness of.
The semiconductor light emitting device according to the embodiment of the present invention thus obtained includes a substrate having a thickness of 35 μm to 80 μm, a metal layer on the substrate, a translucent conductive layer on the metal layer, and the translucent light. A light emitting layer formed on the conductive layer, a first conductive type layer arranged on the substrate side with respect to the light emitting layer, and a second conductive type layer arranged on the opposite side of the substrate with respect to the light emitting layer. A semiconductor layer containing the above, a front electrode selectively formed on the surface of the semiconductor layer, a back electrode formed on the back surface of the substrate, and a fine concavo-convex structure selectively formed on the surface of the semiconductor layer. And include.

According to this configuration, since the substrate is as thin as 35 μm to 80 μm and the resistance is low, it is possible to provide a high-output semiconductor light emitting device without having an ODR structure. That is, it is possible to increase the output of the semiconductor light emitting device with a simple structure.
Further, in the method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention, a continuity test of the surface electrode is performed by bringing a probe into contact with the surface electrode after the formation of the surface electrode and before the thinning step. It may include a step to be performed.

Warpage may occur in the thinned second substrate (wafer), and it is difficult to perform a continuity test with a probe in such a state. However, as described above, the electrical characteristics of the semiconductor light emitting device can be satisfactorily measured by performing the continuity test before the thinning step.
In the method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention, the frost treatment may include a step of wet etching the surface of the semiconductor layer.

Further, in the semiconductor light emitting device according to the embodiment of the present invention, the total thickness of the substrate and the semiconductor layer may be 250 μm to 600 μm.
In the semiconductor light emitting device according to the embodiment of the present invention, the optical film thickness of the translucent conductive layer may be 0.125λ to 0.5λ (however, the emission wavelength λ = 750 nm to 1000 nm).
According to this configuration, the output of the semiconductor light emitting device can be increased by setting the optical film thickness of the translucent conductive layer within the above range.

In the semiconductor light emitting device according to the embodiment of the present invention, the second conductive type layer is a second conductive type clad layer, a second conductive type window layer and a second conductive type, which are sequentially laminated on the light emitting layer. The second conductive window layer including the contact layer has an exposed surface selectively exposed from the second conductive contact layer, and the fine uneven structure is an exposed surface of the second conductive window layer. The second conductive window layer may have a thickness of 2 μm to 6 μm.

Compared with the case where the thickness of the second conductive window layer exceeds the above range, the warp of the substrate can be suppressed while maintaining the output.
In the semiconductor light emitting device according to the embodiment of the present invention, the metal layer may have a thickness of 4000 Å to 10000 Å.
According to this configuration, in the manufacturing process of the semiconductor light emitting device, for example, when the bonding wire is bonded to the surface electrode, the metal layer is peeled off (for example, the peeling between the first metal layer and the second metal layer). In addition to being able to suppress it, it is also possible to suppress chipping, chip cracking, etc. at the time of wafer division.

In the semiconductor light emitting device according to the embodiment of the present invention, the metal layer may contain Au.
In the semiconductor light emitting device according to the embodiment of the present invention, the substrate may include a silicon substrate.

FIG. 1 is a schematic plan view of a semiconductor light emitting device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view that appears when the semiconductor light emitting device is cut along the line II-II of FIG. FIG. 3 is a diagram for explaining the layer structure of the light emitting layer of FIG. FIG. 4A is a diagram showing a part of the manufacturing process of the semiconductor light emitting device of FIG. FIG. 4B is a diagram showing the next step of FIG. 4A. FIG. 4C is a diagram showing the next step of FIG. 4B. FIG. 4D is a diagram showing the next step of FIG. 4C. FIG. 4E is a diagram showing the next step of FIG. 4D. FIG. 4F is a diagram showing the next step of FIG. 4E. FIG. 4G is a diagram showing the next step of FIG. 4F. FIG. 4H is a diagram showing the next step of FIG. 4G. FIG. 4I is a diagram showing the next step of FIG. 4H. FIG. 4J is a diagram showing the next step of FIG. 4I. FIG. 4K is a diagram showing the next step of FIG. 4J. FIG. 4L is a diagram showing the next step of FIG. 4K. FIG. 5 is a graph showing the relationship between the ITO film thickness and the pulse output (PO). 6A and 6B are photographs showing the appearance of the back surface of the chip after dicing the semiconductor wafer. FIG. 6A shows a case where Au film thickness> 10000 Å, and FIG. 6B shows a case where Au film thickness = 5000 Å. There is. 7A to 7C are external photographs showing the warped state of the semiconductor wafer, and show the cases where the thickness of the n-type window layer = 2 μm, 6 μm, and 10 μm, respectively. FIG. 8 is a diagram showing the relationship between wavelength and output based on the results of a continuity test using a probe. FIG. 9 is a diagram showing the thickness of the semiconductor wafer for each measurement point.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic plan view of the semiconductor light emitting device 1 according to the embodiment of the present invention. FIG. 2 is a cross-sectional view that appears when the semiconductor light emitting device 1 is cut along the line II-II of FIG. FIG. 3 is a diagram for explaining the layer structure of the light emitting layer 8 of FIG.
The semiconductor light emitting device 1 includes a substrate 2, a metal layer 3 on the substrate 2, a translucent conductive layer 4 on the metal layer 3, and III-V as an example of the semiconductor layer of the present invention on the translucent conductive layer 4. The group semiconductor structure 5, the p-side electrode 6 as an example of the back surface electrode of the present invention formed so as to contact the back surface of the substrate 2 (the surface opposite to the group III-V semiconductor structure 5), and III-V. The n-side electrode 7 (surface electrode) as an example of the surface electrode of the present invention formed so as to be in contact with the surface of the group semiconductor structure 5 is included.

The substrate 2 is made of a silicon substrate in this embodiment. Of course, the substrate 2 may be composed of a semiconductor substrate such as GaAs (gallium arsenide) or GaP (gallium phosphide). In this embodiment, the substrate 2 is formed in a substantially square shape in a plan view as shown in FIG. 1, but the plan shape of the substrate 2 is not particularly limited, and may be, for example, a rectangular shape in a plan view. Further, the thickness of the substrate 2 may be, for example, 35 μm to 80 μm. Further, the refractive index of the substrate 2 (silicon substrate) may be about 3.705.

In this embodiment, the metal layer 3 is composed of Au or an alloy containing Au. The metal layer 3 may be a single layer of each of the Au layer and the Au alloy layer, or may be a layer in which a plurality of these layers and other metal layers are laminated. When the metal layer 3 has a plurality of laminated structures, at least the contact surface of the first metal layer 26 in contact with the translucent conductive layer 4 is an Au layer or an Au alloy layer (for example, AuBeNi). It is preferably composed of. On the other hand, it is preferable that at least the contact surface of the second metal layer 27 in contact with the substrate 2 with the substrate 2 is made of a Ti layer. In this embodiment, for example, the metal layer 3 has a laminated structure shown by (translucent conductive layer 4 side) Au layer 28 / Au layer 29 / Ti layer 30 (substrate 2 side). Further, in the metal layer 3, a clear boundary is not formed between the plurality of metal materials constituting the metal layer 3, and even if the plurality of metal materials are sequentially distributed from the substrate 2 side, for example. Good. On the other hand, in this embodiment, as will be described later, the metal layer 3 has a first metal layer 26 (described later) and a second metal layer 27 (described later) formed by bonding the growth substrate 46 (described later) and the substrate 2 together. It is formed by joining. Therefore, in FIG. 2, the boundary (bonded surface) between the first metal layer 26 and the second metal layer 27 is shown for convenience, but this boundary may not be clearly visible.

The metal layer 3 is formed so as to cover the entire surface of the substrate 2. The total thickness of the metal layer 3 is, for example, 4000 Å to 10000 Å, preferably 5000 Å to 7000 Å. The thickness of the individual layers 28 to 30 constituting the metal layer 3 is, for example, Au layer 28 = 5000 Å ± 500 Å, Au layer 29 = 1000 Å ± 100 Å, and Ti layer 30 = 500 Å ± 50 Å. May be good.

In this embodiment, the translucent conductive layer 4 is made of ITO (indium tin oxide). Of course, the translucent conductive layer 4 may be made of a transparent electrode material such as ZnO (zinc oxide) or IZO (indium oxide-zinc oxide). The optical film thickness of the translucent conductive layer 4 is preferably 0.125λ to 0.5λ (however, the emission wavelength λ = 750 nm to 1000 nm), and the physical film thickness is 500 Å to 5000 Å (for example, about 700 Å). It may be. Further, the refractive index of the translucent conductive layer 4 (ITO) may be about 1.60 (emission wavelength λ = 870 nm).

The group III-V semiconductor structure 5 includes a light emitting layer 8, a p-type semiconductor layer 9 as an example of the first conductive type layer of the present invention, and an n-type semiconductor layer 10 as an example of the second conductive type layer of the present invention. And include. The p-type semiconductor layer 9 is arranged on the substrate 2 side with respect to the light emitting layer 8, and the n-type semiconductor layer 10 is arranged on the n-side electrode 7 side with respect to the light emitting layer 8. In this way, the light emitting layer 8 is sandwiched between the p-type semiconductor layer 9 and the n-type semiconductor layer 10, and a double heterojunction is formed. Electrons are injected into the light emitting layer 8 from the n-type semiconductor layer 10, and holes are injected from the p-type semiconductor layer 9. Light is generated by recombination of these in the light emitting layer 8. The total thickness of the substrate 2 and the III-V semiconductor structure 5 may be, for example, 250 μm to 600 μm.

The p-type semiconductor layer 9 includes a p-type GaP contact layer 11 (for example, 0.8 μm thickness), a p-type AlGaAs window layer 12 (for example, 3.2 μm thickness), and a p-type AlGaAs clad layer 13 (for example, 1) in this order from the substrate 2 side. It is constructed by laminating (0.0 μm thickness). On the other hand, the n-type semiconductor layer 10 is, in order, on the light emitting layer 8, the n-type AlGaAs clad layer 14 (for example, 1.0 μm thickness) as an example of the second conductive clad layer of the present invention, and the second of the present invention. An n-type AlGaAs window layer 15 (for example, 2.0 μm thickness) as an example of a conductive window layer and an n-type GaAs contact layer 16 (for example, 0.8 μm thickness) as an example of a second conductive contact layer of the present invention are laminated. It is composed of.

The p-type GaP contact layer 11 and the n-type GaAs contact layer 16 are low resistance layers for making ohmic contact with the translucent conductive layer 4 and the n-side electrode 7, respectively.
The p-type GaP contact layer 11 is made into a p-type semiconductor by doping GaP with, for example, C (carbon) or Zn (zinc) as a p-type dopant at a high concentration. In this embodiment, the p-type GaP contact layer 11 is composed of a first layer 31 formed by doping GaP with C and a second layer formed by doping GaP with Zn in order from the substrate 2 side. It is configured by laminating 32 and. The thickness of each of the first layer 31 and the second layer 32 may be, for example, the first layer 31 = about 3000 Å and the second layer 32 = about 4600 Å. Further, the refractive indexes of the first layer 31 and the second layer 32 may be the same as each other (for example, about 3.180).

The n-type GaAs contact layer 16 is formed into an n-type semiconductor layer by doping GaAs with, for example, Si as an n-type dopant at a high concentration. Further, the refractive index of the n-type GaAs contact layer 16 may be about 3.654.
The p-type AlGaAs window layer 12 is made into a p-type semiconductor by doping AlGaAs with Zn as a p-type dopant, for example. In this embodiment, the p-type AlGaAs window layer 12 is composed of the first layer 33 having a composition ratio in which the Al composition is smaller than the Ga composition (for example, Al: 30%, Ga: 70%) in order from the substrate 2 side. It is configured by laminating a second layer 34 having a composition ratio having an Al composition higher than that of the Ga composition (for example, Al: 60%, Ga: 40%). The thickness of each of the first layer 33 and the second layer 34 may be, for example, about 10000 Å for the first layer 33 = about 22000 Å for the second layer 34. Further, the refractive indexes of the first layer 33 and the second layer 34 may be smaller in the second layer 34, which is closer to the light emitting layer 8. For example, the refractive index of the first layer 33 may be about 3.431, and the refractive index of the second layer 34 may be about 3.234.

On the other hand, the n-type AlGaAs window layer 15 is made into an n-type semiconductor layer by doping AlGaAs with, for example, Si as an n-type dopant. In this embodiment, the n-type AlGaAs window layer 15 has a composition ratio of an Al composition higher than that of the Ga composition (for example, Al: 60%, Ga: 40%) in order from the substrate 2 side, and the first layer 35. It is configured by laminating a second layer 36 having a composition ratio having an Al composition smaller than that of the Ga composition (for example, Al: 30%, Ga: 70%). The thickness of each of the first layer 35 and the second layer 36 may be, for example, about 16000 Å for the first layer and about 4000 Å for the second layer 36. Further, the refractive indexes of the first layer 35 and the second layer 36 may be smaller in the first layer 35, which is closer to the light emitting layer 8. For example, the refractive index of the first layer 33 may be about 3.234, and the refractive index of the second layer 34 may be about 3.431.

The p-type AlGaAs clad layer 13 is made into a p-type semiconductor by doping AlGaAs with Zn as a p-type dopant, for example. On the other hand, the n-type AlGaAs clad layer 14 is formed as an n-type semiconductor layer by doping AlGaAs with Si as an n-type dopant. The thickness of these layers 13 and 14 may be, for example, the p-type AlGaAs clad layer 13 = about 10000 Å and the n-type AlGaAs clad layer 14 = about 10000 Å. Further, the refractive index of the p-type AlGaAs clad layer 13 may be about the same as that of the p-type AlGaAs window layer 12 in contact with the p-type AlGaAs window layer 12 on the side closer to the light emitting layer 8 (second layer 34). That is, the refractive index of the p-type AlGaAs clad layer 13 may be about 3.234. On the other hand, the refractive index of the n-type AlGaAs clad layer 14 may be about the same as that of the n-type AlGaAs window layer 15 in contact with the n-type AlGaAs window layer 15 on the side closer to the light emitting layer 8 (first layer 35). That is, the refractive index of the n-type AlGaAs clad layer 14 may be about 3.234.

The light emitting layer 8 has an MQW (multiple-quantum well) structure (multiple-quantum well structure), and light is generated by recombination of electrons and holes, and the generated light is amplified. It is a layer.
In this embodiment, as shown in FIG. 3, the light emitting layer 8 alternately repeats a quantum well layer 37 (for example, 80 Å thickness) made of an InGaAs layer and a barrier layer 38 (for example, 52 Å thickness) made of an AlGaAs layer for a plurality of cycles. It has a multiple-quantum well (MQW) structure 45 formed by stacking, and a p-type AlGaAs guide layer 39 and an n-type AlGaAs guide layer 40 sandwiching the multiple quantum well structure 45 from both upper and lower sides. ing. For example, the quantum well layer 37 (InGaAs) and the barrier layer 38 (AlGaAs) are alternately and repeatedly laminated for 2 to 50 cycles, thereby forming a light emitting layer 8 having a multiple quantum well structure. The emission wavelength corresponds to the band gap of the quantum well layer 37, and the band gap can be adjusted by adjusting the composition ratio of In or Ga. In this embodiment, the emission wavelength is set to 750 nm to 1000 nm (for example, 870 nm) by adjusting the composition of In and Ga in the quantum well layer 37 (InGaAs).

The p-type AlGaAs guide layer 39 is made into a p-type semiconductor layer by doping AlGaAs with Zn as a p-type dopant at a high concentration, for example. On the other hand, the n-type AlGaAs guide layer 40 is made into an n-type semiconductor layer by doping AlGaAs with Si as an n-type dopant. The thickness of these layers 13 and 14 may be, for example, the p-type AlGaAs clad layer 13 = about 10000 Å and the n-type AlGaAs clad layer 14 = about 10000 Å. Further, the refractive index of the p-type AlGaAs guide layer 39 may be larger than that of the p-type AlGaAs clad layer 13 in contact with the p-type AlGaAs guide layer 39. For example, the refractive index of the p-type AlGaAs guide layer 39 may be about 3.431. On the other hand, the refractive index of the n-type AlGaAs guide layer 40 may be larger than that of the n-type AlGaAs clad layer 14 in contact with the n-type AlGaAs guide layer 40. For example, the refractive index of the n-type AlGaAs guide layer 40 may be about 3.431.

As shown in FIGS. 1 and 2, the semiconductor light emitting device 1 forms the mesa portion 17 by removing a part thereof. More specifically, from the surface of the group III-V semiconductor structure 5, the n-type semiconductor layer 10, the light emitting layer 8 and the p-type semiconductor layer 9 (part) extend over the entire circumference of the group III-V semiconductor structure 5. It is removed by etching to form a mesa portion 17 having a substantially quadrangular cross section. The shape of the mesa portion 17 is not limited to a substantially square shape in cross-sectional view, and may be, for example, a trapezoidal shape. As a result, the p-type semiconductor layer 9 (in this embodiment, the p-type GaP contact layer 11) constitutes a lead-out portion 18 that is laterally drawn out from the mesa portion 17. As shown in FIG. 1, in a plan view, the mesa portion 17 is surrounded by the drawer portion 18.

A fine uneven structure 19 is formed on the surface of the mesa portion 17. The fine concavo-convex structure 19 can diffuse the light extracted from the III-V semiconductor structure 5. In this embodiment, as will be described later, the n-type AlGaAs window layer 15 is exposed by selectively removing the n-type GaAs contact layer 16 according to the shape of the n-side electrode 7, and the exposed surface is fine. Concavo-convex structure 19 is formed. In FIG. 1, the fine concavo-convex structure 19 is omitted for clarification.

In this embodiment, the p-side electrode 6 as the back surface electrode is composed of Au or an alloy containing Au. Specifically, the laminated structure shown by the Ti layer 41 / Au layer 42 (on the substrate 2 side) may be used. Further, the p-side electrode 6 is formed so as to cover the entire back surface of the substrate 2. The total thickness of the p-side electrode 6 is, for example, 1300 Å to 1700 Å. Further, the thickness of the individual layers 41 and 42 constituting the p-side electrode 6 may be, for example, about Ti layer 41 = 500 Å ± 50 Å and about Au layer 42 = 1000 Å ± 100 Å.

In this embodiment, the n-side electrode 7 as the surface electrode is composed of Au or an alloy containing Au. Specifically, the laminated structure shown by the AuGeNi layer 43 / Au layer 44 (on the III-V semiconductor structure 5 side) may be used. The total thickness of the n-side electrode 7 is, for example, 1300 Å to 1700 Å. The thickness of the individual layers 43 and 44 constituting the n-side electrode 7 may be, for example, AuGeNi layer 43 = 2000 Å ± 200 Å and Au layer 44 = 17000 Å ± 1700 Å.

Further, the n-side electrode 7 integrally includes a substantially circular pad electrode portion 20 and a branched electrode portion 21 extending radially around the pad electrode portion 20. In this embodiment, in a plan view, the pad electrode portion 20 is arranged substantially in the center of the mesa portion 17, and the plurality of branched electrode portions 21 are formed from the pad electrode portion 20 to the four side surfaces and the four corners of the substrate 2. It extends in eight directions toward the part. In this embodiment, as shown in FIG. 1, four of the substrate 2 are formed so that a substantially quadrangular feeding region 22 is defined by connecting the ends of the plurality of branched electrode portions 21 in a plan view. The branched electrode portion 21 (first portion 23) facing the corner portion is longer than the branched electrode portion 21 (second portion 24) facing the four side surfaces of the substrate 2.

4A to 4L are diagrams showing the manufacturing process of the semiconductor light emitting device 1 of FIGS. 1 to 3 in order of process. Although FIGS. 4A to 4L show a cross section of the semiconductor light emitting device 1, a part of the configuration shown in the cross section of FIG. 2 is omitted.
To manufacture the semiconductor light emitting device 1, for example, as shown in FIG. 4A, a group III-V semiconductor structure 5 is formed by epitaxial growth on a growth substrate 46 (wafer) as an example of the first substrate of the present invention made of GaAs or the like. Is formed. As the growth method of the III-V group semiconductor structure 5, known growth methods such as a molecular beam epitaxial growth method and a metalorganic vapor phase growth method can be applied. At this stage, the group III-V semiconductor structure 5 is composed of the n-type GaAs contact layer 16, the n-type AlGaAs window layer 15, the n-type AlGaAs clad layer 14, the light emitting layer 8, and the p-type AlGaAs clad in this order from the growth substrate 46 side. It includes a layer 13, a p-type AlGaAs window layer 12, and a p-type GaP contact layer 11. Next, the translucent conductive layer 4 is formed on the group III-V semiconductor structure 5 (p-type GaP contact layer 11) by, for example, a thin-film deposition method.

Next, as shown in FIG. 4B, the first metal layer 26 is formed on the translucent conductive layer 4 by, for example, a thin-film deposition method. The first metal layer 26 is made of Au or an alloy containing Au, and at least the outermost surface is made of an Au layer.
The next step is a bonding step between the growth substrate 46 and the substrate 2. In the bonding step, the first metal layer 26 on the growth substrate 46 and the second metal layer 27 on the substrate 2 are joined. The second metal layer 27 is made of Au or an alloy containing Au, and at least the outermost surface is made of an Au layer. The second metal layer 27 is formed on the surface of the substrate 2 as an example of the second substrate of the present invention (opposite the surface on which the above-mentioned p-side electrode 6 is formed) before bonding, for example, by a vapor deposition method. It was done.

More specifically, as shown in FIG. 4C, the growth substrate 46 and the substrate 2 are overlapped with the first and second metal layers 26 and 27 facing each other, and the first and second metal layers 26, 27 is joined. The first and second metal layers 26 and 27 may be joined by, for example, thermocompression bonding. The conditions for thermocompression bonding are, for example, a temperature of 250 ° C. to 700 ° C., preferably about 300 ° C. to 400 ° C., and a pressure of 10 MPa to 20 MPa. By this joining, as shown in FIG. 4D, the first and second metal layers 26 and 27 are combined to form the metal layer 3.

Next, as shown in FIG. 4D, the growth substrate 46 is removed by, for example, wet etching.
The next step is a step of forming the n-side electrode 7. In this embodiment, the n-side electrode 7 is formed by the lift-off method. More specifically, first, a resist (not shown) having an opening having the same pattern as the electrode pattern of the n-side electrode 7 is formed on the group III-V semiconductor structure 5 (n-type GaAs contact layer 16). .. Next, for example, an electrode material film (not shown) is laminated on the group III-V semiconductor structure 5 by a vapor deposition method. Next, the electrode material film on the resist is removed together with the resist. As a result, the n-side electrode 7 made of the electrode material film remaining on the n-type GaAs contact layer 16 is formed. After that, although not shown, the n-type GaAs contact layer 16 exposed from the n-side electrode 7 is removed by etching. As a result, the n-type AlGaAs window layer 15 is exposed to the portion other than the n-side electrode 7.

Next, as shown in FIG. 4F, the mesa portion 17 and the drawer portion 18 are formed by selectively removing the peripheral portion of the group III-V semiconductor structure 5. The mesa portion 17 and the pull-out portion 18 may be formed by, for example, wet etching. Next, the continuity test of the n-side electrode 7 is performed by bringing the probe 47 into contact with the n-side electrode 7.
Next, as shown in FIG. 4G, the substrate 2 is thinned, for example, by grinding the substrate 2 from the back surface side. The substrate 2 may be thinned by, for example, etching such as dry etching or wet etching. As a result, the substrate 2 having a thickness of 300 μm to 600 μm is processed to a thickness of 35 μm to 80 μm before the thinning step.

Next, as shown in FIG. 4H, the support substrate 48 is attached to the surface side of the III-V semiconductor structure 5. For example, the n-side electrode 7 may be bonded to the support substrate 48.
Next, as shown in FIG. 4I, the p-side electrode 6 is formed on the back surface of the substrate 2 by, for example, a thin-film deposition method.
Next, as shown in FIG. 4J, the support substrate 48 is removed from the group III-V semiconductor structure 5, and instead, the support substrate 49 is attached to the back surface side of the substrate 2. For example, the p-side electrode 6 may be bonded to the support substrate 49.

Next, as shown in FIG. 4K, a fine uneven structure 19 is formed on the surface of the III-V group semiconductor structure 5 (n-type AlGaAs window layer 15) by, for example, frost treatment (wet etching) or the like. The frost treatment may be performed by dry etching. Next, as shown in FIG. 4L, the support substrate 49 is removed from the substrate 2. After that, the substrate 2 (wafer) is divided into chip sizes to obtain the semiconductor light emitting device 1 shown in FIGS. 1 to 3.

According to the above manufacturing method, since the frost treatment is performed after the substrate 2 shown in FIG. 4G is thinned (see FIG. 4K), the semiconductor light emitting device 1 can be manufactured with a high yield. For example, if the frost treatment is performed before the thinning step, the support substrate 48 supports the III-V semiconductor structure 5 to form a back surface electrode (p-side electrode 6), and then the III-V semiconductor structure 5 is used. The support substrate 48 may not be peeled off well. On the other hand, according to this embodiment, the support substrate 48 can be satisfactorily peeled off, and the subsequent frost treatment step can be smoothly proceeded.

Further, as shown in FIG. 4F, a continuity test using the probe 47 is performed before the thinning step of FIG. 4G. Warpage may occur in the thinned substrate 2 (wafer), and it is difficult to perform a continuity test with the probe 47 in such a state. However, as described above, the electrical characteristics of the semiconductor light emitting device 1 can be satisfactorily measured by performing the continuity test before the thinning step.

In the obtained semiconductor light emitting device 1, since the substrate 2 is as thin as 35 μm to 80 μm and the resistance is low, it is possible to provide the high output semiconductor light emitting device 1 without having an ODR structure. That is, it is possible to increase the output of the semiconductor light emitting device 1 with a simple structure.
Next, how the thickness of the layer or film constituting the semiconductor light emitting device 1 affects the electrical characteristics and yield of the semiconductor light emitting device 1 will be described.

FIG. 5 shows the influence of the increase / decrease in the film thickness of ITO as an example of the translucent conductive layer 4 on the output of the semiconductor light emitting device 1, and shows the ITO (physical) film thickness and the pulse output (PO). ) Is a graph showing the relationship with.
More specifically, the relationship between the ITO film thickness and the pulse output was investigated by simulation. Simulation sample No. used The optical film thicknesses 1 to 6 and the physical film thicknesses are shown in Table 1 below. As shown in FIG. 5, the thinner the physical film thickness of ITO, the higher the output tends to be. In FIG. 5, the lower limit of the physical film thickness is 680 Å, but if the physical film thickness of ITO is less than 500 Å, the adhesion to ITO / Au is likely to decrease, so the film thickness of ITO is, for example, 500 Å. It is preferably ~ 3000 Å, more preferably 600 Å ~ 2000 Å.

Table 2 below shows the effect of increasing or decreasing the film thickness of the Au layer constituting the metal layer 3 on the yield of the semiconductor light emitting device 1.
More specifically, the semiconductor light emitting device was manufactured in a wafer state according to the structure of the semiconductor light emitting device 1 described above, and after the manufacturing, the bonding wire was bonded to the surface electrode (pad electrode portion 20 in FIG. 1) (number of samples). Is 4000 pieces). At the time of this bonding, the number of peeling of the Au layer at the central portion and the outer peripheral portion of the wafer was examined for each film thickness of the Au layer. The results are shown in Table 2. In Table 2, "100% peeling" indicates that the Au layer was completely peeled off at the corresponding evaluation site, and "50% peeling" indicates that the Au layer was completely peeled off at the corresponding evaluation site. There is.

From the results in Table 2, when the Au film thickness was 2000 Å and 3000 Å, 100% peeling occurred on the outer periphery of the wafer. On the other hand, when the Au film thickness was 4000 Å, two 50% peeling occurred on the outer periphery of the wafer, but 100% peeling did not occur. Furthermore, when the Au film thickness was 5000 Å, even 50% peeling did not occur. As a result, it was found that when the Au film thickness is thin, peeling is likely to occur during wire bonding, and the Au film thickness is preferably 4000 Å or more. However, when the Au film thickness exceeds 10000 Å, as shown in FIG. 6A, back surface chipping and chip cracking are likely to occur due to clogging of the blade during dicing and the like. On the other hand, when the Au film thickness was 5000 Å, the occurrence of backside chipping was suppressed as shown in FIG. 6B. Therefore, it can be said that the Au film thickness is more preferably 4000 Å to 10000 Å.

7A to 7C show the influence of the increase / decrease in the thickness of the n-type AlGaAs window layer 15 on the warpage of the wafer after the FAB (fabrication) step of the semiconductor light emitting device 1, and shows the state of warpage of the semiconductor wafer. It is an external photograph showing. 7A to 7C show the cases where the thickness of the n-type AlGaAs window layer 15 is 2 μm, 6 μm, and 10 μm, respectively. Of the three samples, the n-type AlGaAs window layer 15 with a thickness of 2 μm and 10 μm has the same active layer conditions (number of pairs of multiple quantum well structures, etc.). The conditions for a sample with a thickness of 6 μm are different from those with a thickness of 2 μm and 10 μm.

From FIGS. 7A to 7C, when the thickness of the n-type AlGaAs window layer 15 is 2 μm, the wafer after the FAB step is not warped, and when the thicknesses are 6 μm and 10 μm, 1 mm and 1 mm, respectively. There was a warp in which the outer peripheral portion of the wafer was lifted by about 2 mm. On the other hand, it was investigated whether or not the electrical characteristics of the semiconductor light emitting device 1 were not affected by changing the thickness of the n-type AlGaAs window layer 15. More specifically, the output was measured at each of three stages: before the removal of the n-type GaAs contact layer 16, after the removal of the n-type GaAs contact layer 16 (see FIG. 4F), and after the frost treatment (see FIG. 4K). .. The results are shown in Table 3 and FIG. 8 below. Note that FIG. 8 also shows the output of a semiconductor light emitting device having an existing ODR structure for reference.

According to Table 3 and FIG. 8, when the sample having the same n-window thickness = 2 μm and the sample having the same active layer conditions were compared, the output after the frost treatment was almost the same. .. Further, although the output is slightly lower than that of the device having the ODR structure, a sufficient output value can be realized in practical use. Therefore, the thickness of the n-type AlGaAs window layer 15 is preferably about 2 μm to 6 μm from the viewpoint of achieving both sufficient output and reduction of wafer warpage.

As described above, it was found that by optimizing the film thickness of the translucent conductive layer 4 and the metal layer 3 (Au layer), defects such as peeling of the Au layer during wire bonding and backside chipping during dicing can be suppressed (for example). See Table 2). It was also found that the warpage of the wafer can be reduced by optimizing the epitaxial growth conditions (epi film thickness) of the III-V semiconductor structure 5 (see, for example, FIGS. 7A to 7C). All of these cause a decrease in yield, and by improving these points, it is possible to provide the semiconductor light emitting device 1 having a high yield and thinner than the conventional one. FIG. 9 is a diagram showing the thickness of the semiconductor wafer after the FAB process is performed according to the above manufacturing process for each measurement point. However, according to the above manufacturing process, the thickness is 65 over the entire wafer. It can be suppressed within ± 5 μm.

Although one embodiment of the present invention has been described above, the present invention can also be implemented in other embodiments. Further, the present invention can make various design changes within the scope of the matters described in the claims.

1 Semiconductor light emitting device 2 Substrate 3 Metal layer 4 Translucent conductive layer 5 III-V group semiconductor structure 6 p-side electrode 7 n-side electrode 8 Light emitting layer 9 p-type semiconductor layer 10 n-type semiconductor layer 11 p-type GaP contact layer 12 p Type AlGaAs window layer 13 p-type AlGaAs clad layer 14 n-type AlGaAs clad layer 15 n-type AlGaAs window layer 16 n-type GaAs contact layer 19 Fine concavo-convex structure 26 1st metal layer 27 2nd metal layer 28 Au layer 29 Au layer 46 Growth substrate 47 Probe 48 Support substrate

Claims (11)

A step of forming a semiconductor layer including a light emitting layer and a first metal layer on the first substrate in this order, and
The process of forming the second metal layer on the second substrate and
A step of bonding the first substrate and the second substrate by joining the first metal layer and the second metal layer to each other.
A step of removing the first substrate after the bonding and
After removing the first substrate, a step of selectively forming a surface electrode on the surface of the semiconductor layer and
After forming the front surface electrode, the step of thinning the second substrate from the back surface side and
After the thinning step, a step of attaching the support substrate to the surface side of the semiconductor layer and
A step of forming a back electrode on the back surface of the second substrate while the semiconductor layer is supported by the support substrate.
A method for manufacturing a semiconductor light emitting device, which comprises a step of forming a fine concavo-convex structure on the surface of the semiconductor layer by removing the support substrate and frosting the surface of the semiconductor layer. The semiconductor light emitting according to claim 1, wherein the second substrate has a thickness of 300 μm to 600 μm before the thinning step, and is processed to a thickness of 35 μm to 80 μm by the thinning step. Manufacturing method of the device. The production of the semiconductor light emitting device according to claim 1 or 2, which comprises a step of performing a continuity test of the surface electrode by bringing the probe into contact with the surface electrode after the formation of the surface electrode and before the thinning step. Method. The method for manufacturing a semiconductor light emitting device according to any one of claims 1 to 3, wherein the frost treatment includes a step of wet etching the surface of the semiconductor layer. Claims 1 to 4 include a step of forming the semiconductor layer and the first metal layer on the first substrate, including a step of forming a translucent conductive layer between the semiconductor layer and the first metal layer. The method for manufacturing a semiconductor light emitting device according to any one of the above. A substrate having a thickness of 35 μm to 80 μm and
With the metal layer on the substrate,
A light emitting layer formed on the metal layer, a first conductive type layer arranged on the substrate side with respect to the light emitting layer, and a second conductive type layer arranged on the opposite side of the substrate with respect to the light emitting layer. A semiconductor layer including a layer and
A surface electrode selectively formed on the surface of the semiconductor layer and
The back electrode formed on the back surface of the substrate and
A fine concavo-convex structure selectively formed on the surface of the semiconductor layer ,
Look including a ToruHikarishirube conductive layer between the metal layer and the semiconductor layer,
The optical film thickness of the translucent conductive layer is 0.125λ to 0.5λ (however, the emission wavelength λ = 750nm to 1000nm).
A semiconductor light emitting device having a physical film thickness of the translucent conductive layer of 600 Å to 2000 Å. The semiconductor light emitting device according to claim 6, wherein the total thickness of the substrate and the semiconductor layer is 250 μm to 600 μm. The second conductive layer includes a second conductive clad layer, a second conductive window layer, and a second conductive contact layer, which are sequentially laminated on the light emitting layer.
The second conductive window layer has an exposed surface selectively exposed from the second conductive contact layer.
The fine uneven structure is formed on the exposed surface of the second conductive window layer.
The semiconductor light emitting device according to claim 6 or 7 , wherein the second conductive window layer has a thickness of 2 μm to 6 μm. The semiconductor light emitting device according to any one of claims 6 to 8 , wherein the metal layer has a thickness of 4000 Å to 10000 Å. The semiconductor light emitting device according to any one of claims 6 to 9 , wherein the metal layer contains Au. The semiconductor light emitting device according to any one of claims 6 to 10 , wherein the substrate includes a silicon substrate.

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