JP6904122B2 - Manufacturing method of semiconductor devices - Google Patents

Description

The techniques disclosed herein relate to methods of manufacturing semiconductor devices.

Patent Document 1 discloses a semiconductor device. This semiconductor device includes a semiconductor element having a top electrode and a bottom electrode, a first conductor plate bonded to the bottom electrode via a first bonding material, and a second conductor bonded to the top electrode via a second bonding material. It is equipped with a conductor plate. Since a semiconductor element or the like generates heat when energized, this type of semiconductor device is used in combination with a cooler in order to suppress a temperature rise of the semiconductor device. Therefore, when the energization and interruption of the semiconductor device are repeated, the temperature of the semiconductor device also fluctuates up and down in synchronization with the repetition, and the semiconductor device alternately repeats thermal expansion and contraction.

Japanese Unexamined Patent Publication No. 2016-46497

In the above-mentioned semiconductor device, the area of the first bonding region where the first conductor plate is bonded to the lower surface electrode via the first bonding material is such that the second conductor plate is bonded to the upper surface electrode via the second bonding material. It is larger than the area of the second junction region, and the structure is asymmetric above and below the semiconductor element. With such a structure, the thermal expansion that occurs in the semiconductor device is also asymmetrical above and below the semiconductor device, so that the semiconductor device may be deformed so as to warp when the temperature of the semiconductor device fluctuates. Since such deformation locally increases the stress generated in the semiconductor element, it can be a factor that causes damage to the semiconductor element such as generation of cracks.

In view of the above, the present specification provides a technique capable of suppressing damage to a semiconductor element due to thermal expansion of a semiconductor device.

The present inventor analyzed the deformation and stress generated in the semiconductor element and obtained the following findings. When a current flows through the semiconductor device, the components of the semiconductor device including each conductor plate thermally expand, and the bonding materials located above and below the semiconductor device move toward the outer periphery. When such thermal expansion is repeated, the movement of the second bonding material located on the upper side of the semiconductor element is restricted by the mold resin or the like located around the semiconductor element, so that the semiconductor element has a relatively low rigidity. Move downward toward. As a result, the outer peripheral portion of the semiconductor element is pressed by the second bonding material and displaced downward. Under the influence of this, in the first bonding material located on the lower side of the semiconductor element, the movement toward the outer peripheral side is restricted (or because it is pushed back toward the center side), so that the central portion of the semiconductor element is It is pressed by the first joint material and displaced upward. In this way, the outer peripheral portion of the semiconductor element is pushed downward and displaced, while the central portion of the semiconductor element is pushed upward and displaced. As a result, in a semiconductor device, a relatively large tensile stress can be generated in the region between the outer peripheral portion that is displaced downward and the central portion that is displaced upward.

From the above findings, it has been found that the region in which damage is likely to occur in the semiconductor element is the region between the outer peripheral portion and the central portion where a large tensile stress can be generated. Therefore, in order to suppress damage to the semiconductor element, it is effective to increase the strength of the semiconductor element at least in the region between the outer peripheral portion and the central portion. Therefore, in this technology, we focused on the annealing process. Generally, in the manufacture of a semiconductor device, in order to form good ohmic contact between a semiconductor substrate and an electrode, the semiconductor element after forming the electrode is annealed. However, the annealing process of heating the semiconductor element has a secondary effect of reducing the strength of the semiconductor element. In this regard, in the case of laser annealing in which a semiconductor element is locally heated using a laser, the presence or absence or degree of annealing treatment is selectively selected by distinguishing between the region where the strength of the semiconductor element is required and other regions. Can be changed to. That is, in a region where a large tensile stress can be generated, the strength of the semiconductor element can be maintained by omitting the annealing treatment or relaxing the degree thereof. On the other hand, in a region where a large tensile stress cannot be generated, a good ohmic contact can be formed between the semiconductor substrate and the electrode by sufficiently performing the annealing treatment.

Based on the techniques described above, the present specification provides a method for manufacturing a semiconductor device. This manufacturing method includes a step of preparing a semiconductor element having a top electrode and a bottom electrode, a step of joining a first conductor plate to the bottom electrode via a first bonding material, and a step of joining the top electrode to the top electrode via a second bonding material. It includes a step of joining the second conductor plate. The area of the first bonding region where the first conductor plate is bonded to the bottom electrode via the first bonding material is the area of the second bonding region where the second conductor plate is bonded to the second conductor plate via the second bonding material. Greater than. The step of preparing the semiconductor element includes an annealing step of irradiating the lower surface electrode of the semiconductor element with a laser. In this annealing step, the first region of the bottom electrode is irradiated with a laser having the first intensity, while the second region surrounding the first region of the bottom electrode has a second intensity weaker than the first intensity. Irradiate a laser with. Alternatively, the second region is not irradiated with the laser. Here, the boundary between the first region and the second region is located closer to the center than the outer peripheral edge of the second junction region in a plan view.

In the above-mentioned manufacturing method, in the step of preparing the semiconductor element, an annealing step of irradiating the lower surface electrode of the semiconductor element with a laser is performed. In this annealing step, the first region of the bottom electrode is irradiated with a laser having the first intensity, while the second region surrounding the first region of the bottom electrode has a second intensity weaker than the first intensity. Irradiate a laser with. Alternatively, the second region is not irradiated with the laser. As a result, in the second region of the semiconductor element, the decrease in strength due to the annealing treatment does not occur or is small, and the mechanical strength of the semiconductor element is maintained. Here, the second region is a region surrounding the first region, and the boundary between the first region and the second region is arranged on the central side of the outer peripheral edge of the second junction region in a plan view. Due to such a relationship, the second region includes a region in which a large tensile stress can be generated in the semiconductor element (that is, a region between the outer peripheral portion and the central portion described above). Since the strength of the semiconductor element is maintained in the region where a large tensile stress can occur, damage to the semiconductor element is suppressed. On the other hand, in the first region including the central portion of the semiconductor element, the tensile stress generated is relatively small, so that the annealing treatment can be sufficiently performed, and good ohmic contact between the semiconductor substrate and the electrode is possible. Can be formed.

The plan view of the semiconductor device 10 of an Example is shown. FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 1 and shows a cross-sectional structure of the semiconductor device 10. The deformation of the semiconductor device 10 due to temperature fluctuation is schematically shown. The analysis result of the tensile stress generated in the semiconductor element 12 is shown. (A) is a cross-sectional view of the semiconductor device 10, (B) is a graph showing the tensile stress generated in the semiconductor element 12 at a low temperature, and (C) is a plan view of the semiconductor element 12 viewed from the bottom electrode 16 side. is there. It is an example of setting the first region R1 and the second region R2 in the annealing process, (A) shows an example in which the first region R1 is set to the maximum, and (B) is an example in which the first region R1 is set to the minimum. Shown.

The semiconductor device 10 of the embodiment and the manufacturing method thereof will be described with reference to the drawings. As shown in FIG. 1, the semiconductor device 10 includes a semiconductor element 12, a lower surface side conductor plate 18, an upper surface side conductor plate 20, a conductor spacer 22, and a mold resin 24. The semiconductor element 12 is sealed in the mold resin 24. The mold resin 24 is made of a material having an insulating property. Although not particularly limited, the material constituting the mold resin 24 may be a thermosetting resin material such as an epoxy resin.

The semiconductor element 12 includes an upper surface electrode 14 and a lower surface electrode 16. The upper surface electrode 14 is located on the upper surface 12a of the semiconductor element 12, and the lower surface electrode 16 is located on the lower surface 12b of the semiconductor element 12. The specific type and structure of the semiconductor element 12 are not particularly limited. The semiconductor element 12 may be a power semiconductor element such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). Further, the semiconductor element 12 can be configured by using various semiconductor materials such as silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). The material constituting the upper surface electrode 14 and the lower surface electrode 16 is not particularly limited, but for example, an aluminum-based material or other metal can be adopted.

The lower surface side conductor plate 18 is generally a plate-shaped member, and has an upper surface 18a and a lower surface 18b located on the opposite side of the upper surface 18a. The upper surface 18a of the lower surface side conductor plate 18 is joined to the lower surface electrode 16 of the semiconductor element 12 via the solder 26 inside the mold resin 24. As a result, the lower surface side conductor plate 18 is electrically connected to the semiconductor element 12. Here, the lower surface side conductor plate 18 is an example of the first conductor plate in the technique disclosed in the present specification, and the solder 26 is an example of the first bonding material in the technique disclosed in the present specification. The lower surface side conductor plate 18 (that is, an example of the first conductor plate) can be constructed by using a conductive material such as copper or other metal. Further, the lower surface side conductor plate 18 and the semiconductor element 12 are not limited to the solder 26, and may be joined by another joining material.

The conductor spacer 22 is generally a plate-shaped or block-shaped member, and has an upper surface 22a and a lower surface 22b located on the opposite side of the upper surface 22a. The conductor spacer 22 is located in the mold resin 24. The lower surface 22b of the conductor spacer 22 is joined to the upper surface electrode 14 of the semiconductor element 12 via the solder 28. As a result, the top electrode 14 of the semiconductor element 12 is electrically connected to the conductor spacer 22. The conductor spacer 22 is an example of a second conductor plate in the technique disclosed herein, and the solder 28 is an example of a second bonding material in the technique disclosed herein. The conductor spacer 22 (ie, an example of the second conductor plate) can be constructed using a conductive material such as copper or other metal. Further, the conductor spacer 22 and the semiconductor element 12 are not limited to the solder 28, and may be joined by another joining material.

Like the lower surface side conductor plate 18, the upper surface side conductor plate 20 is also a generally plate-shaped member, and has an upper surface 20a and a lower surface 20b located on the opposite side of the upper surface 20a. The lower surface 20b of the upper surface side conductor plate 20 is joined to the upper surface 22a of the conductor spacer 22 via the solder 30 inside the mold resin 24. As a result, the upper surface side conductor plate 20 is electrically connected to the conductor spacer 22 and is electrically connected to the semiconductor element 12 via the conductor spacer 22. The upper surface side conductor plate 20 can be constructed by using a conductive material such as copper or other metal.

The lower surface 18b of the lower surface side conductor plate 18 is exposed to the outside of the mold resin 24. The lower surface side conductor plate 18 is also thermally connected to the semiconductor element 12, and also functions as a heat radiating plate that releases the heat generated by the semiconductor element 12 to the outside. Similarly, the upper surface 20a of the upper surface side conductor plate 20 is exposed to the outside of the mold resin 24. The upper surface side conductor plate 20 is also thermally connected to the semiconductor element 12 via the conductor spacer 22, and also functions as a heat radiating plate that releases the heat generated by the semiconductor element 12 to the outside. That is, the semiconductor device 10 of this embodiment has a double-sided cooling structure in which heat sinks are exposed on both sides of the mold resin 24.

Since the semiconductor element 12 and the like generate heat when the semiconductor device 10 is energized, the semiconductor device 10 of this embodiment is used in combination with a cooler (not shown) in order to suppress a temperature rise of the semiconductor device 10. Therefore, when the semiconductor device 10 is repeatedly energized and cut off, the temperature of the semiconductor device 10 also fluctuates up and down in synchronization with the repetition, and the semiconductor device 10 alternately repeats thermal expansion and contraction. Here, the region where the lower surface side conductor plate 18 (that is, an example of the first conductor plate) is bonded to the lower surface electrode 16 of the semiconductor element 12 via the solder 26 (that is, an example of the first bonding material) is defined as the first. 1 Join region C1. Further, the region where the conductor spacer 22 (that is, an example of the second conductor plate) is bonded to the upper surface electrode 14 of the semiconductor element 12 via the solder 28 (that is, an example of the second bonding material) is the second bonding region. Let it be C2. Comparing the areas of both, the area of the first junction region C1 is larger than the area of the second junction region C2, and the structure of the semiconductor device 10 is asymmetrical above and below the semiconductor element 12. With such a structure, the thermal expansion that occurs in the semiconductor device 10 is also asymmetrical above and below the semiconductor element 12. Therefore, as shown in FIG. 3, when the temperature of the semiconductor device 10 fluctuates, the semiconductor element 12 moves. It may be deformed to warp. Since such deformation locally increases the stress generated in the semiconductor element 12, it can be a factor that causes damage to the semiconductor element 12 such as generation of cracks.

Here, FIG. 3 (X) shows a state when the temperature of the semiconductor device 10 rises, and FIG. 3 (Y) shows a state when the temperature of the semiconductor device 10 decreases. In this way, when the temperature of the semiconductor device 10 fluctuates, the semiconductor device 10 is deformed so that the semiconductor element 12 warps, or the warp returns. However, the direction in which the temperature changes (that is, the increase or decrease) and the direction in which the semiconductor element 12 is warped are not limited to the modes illustrated in FIG. 3, and the specific structure of the semiconductor device 10 or the industrial product. It can change in various ways depending on individual differences and the like.

The present inventor analyzed the deformation and stress generated in the semiconductor element and obtained the following findings. When a current flows through the semiconductor device 10, the components of the semiconductor device 10 including the lower surface side conductor plate 18 and the conductor block 22 are thermally expanded, respectively, and the solders 26 and 28 located above and below the semiconductor element 12 move toward the outer periphery. To do. When such thermal expansion is repeated, the solder 28 located on the upper side of the semiconductor element 12 is restricted in its movement by the mold resin 24 located around it, so that the semiconductor element 12 having a relatively low rigidity is restricted. (See arrow S2 in FIG. 3 (Y)). As a result, the outer peripheral portion A2 of the semiconductor element 12 is pressed by the solder 28 and displaced downward. Under the influence of this, in the solder 26 located on the lower side of the semiconductor element 12, the movement toward the outer peripheral side is restricted (or because it is pushed back toward the center side), so that the central portion A1 of the semiconductor element 12 is , Pressed by the solder 26 and displaced upward (see arrow S1 in FIG. 3 (Y)). In this way, the outer peripheral portion of the semiconductor element 12 is pushed downward and displaced, while the central portion of the semiconductor element is pushed upward and displaced. As a result, in a semiconductor device, a relatively large tensile stress can be generated in the region between the outer peripheral portion that is displaced downward and the central portion that is displaced upward.

FIG. 4 shows the results obtained by CAE (Computer aided Engineering) analysis of the tensile stress generated in the semiconductor element 12. FIG. 4B shows the tensile stress (at low temperature) generated in the semiconductor element 12 for each number of power cycles (1000 times, 2000 times, 3000 times) in which energization and its stop are repeated. (C) is a cross-sectional view schematically showing the positions where the tensile stress is generated and a plan view of the bottom electrode 16. As can be seen from FIG. 4, a relatively large tensile stress is generated in the region A3 between the outer peripheral portion A2 that is displaced downward and the central portion A1 that is displaced upward. Further, it can be seen that stress is relatively unlikely to occur in the central portion A1 of the semiconductor element.

As described above, it can be seen that the region in which damage is likely to occur in the semiconductor element 12 is a region in which a large tensile stress can occur, that is, a region A3 between the outer peripheral portion A2 and the central portion A1. Therefore, in order to suppress damage to the semiconductor element 12, it is effective to increase the strength of the semiconductor element 12 at least in the region A3 between the outer peripheral portion A2 and the central portion A1. Therefore, in this technique, attention is paid to the annealing treatment of the semiconductor element 12. Generally, in the manufacturing process of the semiconductor element 12, after the upper surface electrode 14 and the lower surface electrode 16 are formed in order to form a good ohmic contact between the upper surface electrode 14 or the lower surface electrode 16 and the semiconductor substrate (not shown). An annealing treatment step is performed on the semiconductor element 12 of the above. The annealing process of heating the semiconductor element 12 has a secondary effect of reducing the strength of the semiconductor element 12. In this regard, in the case of laser annealing in which the semiconductor element 12 is locally heated by using a laser, the presence or absence or degree of the annealing treatment is determined by distinguishing between the region where the strength of the semiconductor element 12 is required and the other regions. It can be changed selectively. That is, in the region A3 where a large tensile stress can be generated, the strength of the semiconductor element 12 can be maintained by omitting the annealing treatment or relaxing the degree thereof. On the other hand, in the region A1 where a large tensile stress cannot be generated, a good ohmic contact can be formed between the upper surface electrode 14 or the lower surface electrode 16 and the semiconductor substrate by sufficiently performing the annealing treatment.

Based on the above technique, the manufacturing method applied to the semiconductor device 10 of this embodiment will be described. This manufacturing method includes a step of preparing a semiconductor element 12 having an upper surface electrode 14 and a lower surface electrode 16, a step of joining a lower surface side conductor plate 18 to the lower surface electrode 16 via a solder 26, and a step of joining a solder 28 to the upper surface electrode 14. A step of joining the conductor spacers 22 via the interposition is provided. As described above, the area of the first bonding region C1 to which the lower surface side conductor plate 18 is bonded to the lower surface electrode 16 via the solder 26 is such that the conductor spacer 22 is bonded to the conductor spacer 22 via the solder 28. It is larger than the joint region C2. The step of preparing the semiconductor element 12 includes an annealing step of irradiating the semiconductor element 12 with a laser. In this annealing step, as shown in FIG. 5, the first region R1 of the semiconductor element 12 is irradiated with the laser having the first intensity, while the second region R2 surrounding the first region R1 of the semiconductor element 12 is covered. , Irradiates a laser having a second intensity weaker than the first intensity. Alternatively, the second region R2 is not irradiated with the laser. Here, the boundary BL between the first region R1 and the second region R2 is located closer to the center than the outer peripheral edge of the second junction region C2 in a plan view.

In the above-mentioned manufacturing method, in the step of preparing the semiconductor element 12, an annealing step of irradiating the lower surface electrode 16 of the semiconductor element 12 with a laser is performed. In this annealing step, first, the first region R1 of the bottom electrode 16 is irradiated with a laser having a first intensity. On the other hand, the second region R2 surrounding the first region R1 of the bottom electrode 16 is irradiated with a laser having a second intensity weaker than the first intensity. Alternatively, the second region R2 is not irradiated with the laser. As a result, in the second region R2 of the semiconductor element 12, the decrease in strength due to the annealing treatment does not occur or is small, and the mechanical strength of the semiconductor element is maintained. Here, the second region R2 is a region surrounding the first region R1, and the boundary BL between the first region R1 and the second region R2 is closer to the center than the outer peripheral edge of the second junction region C2 in a plan view. Be placed. Due to such a relationship, the second region R2 is a region (that is, a region A3 between the outer peripheral portion A2 and the central portion A1 described above) in which a large tensile stress (particularly, the maximum tensile stress) can be generated in the semiconductor element 12. ) Is included. Since the strength of the semiconductor element is maintained in the region where a large tensile stress can occur, damage to the semiconductor element is suppressed. On the other hand, in the first region R1 including the central portion of the semiconductor element, the tensile stress generated is relatively small, so that the annealing treatment can be sufficiently performed, and the space between the semiconductor substrate and the electrodes 14 and 16 is reached. Can form good ohmic contacts.

Here, the position of the boundary BL between the first region R1 and the second region R2 can be variously determined according to the configuration of the semiconductor device 10, the analysis result of the tensile stress, and the like. In the example shown in FIG. 5 (A), the first region R1 that irradiates the laser having the first intensity (that is, the strong intensity) is maximized to a position corresponding to the outer peripheral edge of the second junction region C2. Has been done. In this case, the first region R1 is substantially equal to the size of the outer shape of the conductor spacer 22. On the other hand, in the example shown in FIG. 5B, the first region R1 is set to be relatively narrow. Specifically, the size of the first region R1 is half the size of the outer shape of the conductor spacer 22. Is set to. If the first region R1 to be sufficiently annealed is set to a size of at least one half or more of the outer shape of the conductor spacer 22, it is necessary between the semiconductor substrate and the electrodes 14 and 16. It is possible to secure the ohmic contact property.

Although some specific examples have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. The technical elements described herein or in the drawings exhibit their technical usefulness alone or in various combinations.

10: Semiconductor element 12: Semiconductor element 12a: Upper surface 12b of semiconductor element: Lower surface 14 of semiconductor element: Upper surface electrode 16: Lower surface electrode 18: Lower surface side conductor plate (example of first conductor plate)
18a: Upper surface of the lower surface side conductor plate 18b: Lower surface of the lower surface side conductor plate 20: Upper surface side conductor plate 20a: Upper surface of the upper surface side conductor plate 20b: Lower surface of the upper surface side conductor plate 22: Conductor spacer (an example of the second conductor plate)
22a: Upper surface of conductor spacer 22b: Lower surface of conductor spacer 24: Molded resin 26: Solder (example of first bonding material)
28: Solder (an example of the second bonding material)
30: Solder

Claims (1)

It is a manufacturing method of semiconductor devices.
A process of preparing a semiconductor element having a top electrode and a bottom electrode, and
A step of joining the first conductor plate to the lower surface electrode via the first joining material, and
A step of joining the second conductor plate to the upper surface electrode via the second joining material, and
With
The area of the first bonding region where the first conductor plate is bonded to the lower surface electrode via the first bonding material is such that the second conductor plate is bonded to the upper surface electrode via the second bonding material. Larger than the area of the second junction region,
The step of preparing the semiconductor element includes an annealing step of irradiating the lower surface electrode of the semiconductor element with a laser.
In the annealing step, the first region of the bottom electrode is irradiated with a laser having a first intensity, while the second region surrounding the first region of the bottom electrode is weaker than the first intensity. With or without a laser with a second intensity
The boundary between the first region and the second region is located on the central side of the outer peripheral edge of the second junction region in a plan view.
Manufacturing method of semiconductor devices.

Images