JP6904286B2 - Electronic information storage medium and IC card - Google Patents

Description

The present invention relates to a technical field of an electronic information storage medium such as an IC (Integrated Circuit) chip.

An electronic information storage medium such as an IC chip mounted on an IC card or the like includes a CPU, RAM, a non-volatile memory, and the like. When the CPU of the electronic information storage medium receives a command from the outside such as a card issuing machine or a reader / writer, it executes a process according to the command and transmits a SW (Status Word) related to the execution result as a response. Therefore, the non-volatile memory of the electronic information storage medium stores a program (hereinafter, may be referred to as a "command execution program") in which a process for executing a series of processes according to a command by the CPU is described. There is.

There are a plurality of types of commands transmitted to the electronic information storage medium. For example, as described in Patent Document 1, when inspecting an electronic information storage medium such as an inspection command or an issuing command, or electronic information. It contains commands that are used only before the storage medium is issued (hereinafter, may be referred to as "pre-issue commands").

Japanese Unexamined Patent Publication No. 2012-243133

However, since the pre-issue command is not used after it is issued (that is, during operation after the product is shipped), the program corresponding to the pre-issue command is non-volatile without being deleted from the non-volatile memory. The memory storage area remains wasted.

On the other hand, the pre-issue command and the command used only after the electronic information storage medium is issued (during the operation of the electronic information storage medium) (hereinafter, may be referred to as "post-issue command") are when the command is received. There is a command that has some common processing included in the executed program.

Therefore, the present invention relates to an electronic information storage medium or the like that can save a storage area for storing a pre-issue command and a post-issue command by integrating and sharing a program executed at the time of command reception. The challenge is to provide.

In order to solve the above problems, the invention according to claim 1 is an electronic device including a storage unit for storing a program corresponding to a command and an execution unit for executing the program corresponding to the command received from the outside. In the information storage medium, the plurality of types of the commands include a pre-issue command, which is a command received before the issuance of the electronic information storage medium, and a post-issue command, which is a command received after the issuance. included, the storage unit, among a plurality of types of said commands, a predetermined program corresponding to the sets of the pre-issuing command and the issuing post command to perform common process to the electronic information storage medium the store and the electronic data storage medium issuing information indicating whether after issuing either before issuing the said predetermined program, said issuing constituting the set and when receiving the issued before command constituting the group and said common processing which are executed in both the case of receiving the post command, a process of the issuance information is performed when the identification information indicates previous the issuing, on the issue before commands that configure the group It includes a process executed in response to the issue and a process executed when the issue information indicates after the issue, and includes a process executed in response to the post-issue command constituting the set. It is characterized by.

The invention according to claim 2 is the electronic information storage medium according to claim 1, wherein the CLA part of the pre-issuance command constituting the set, the CLA part of the post-issuance command constituting the set, and the CLA part of the post-issue command constituting the set. , wherein each common value in the INS unit of the issuing post commands constituting the set and INS portion of said issued before command constituting sets of the set, the predetermined program, the issue before configuring the sets process for the issuing post CLA unit set value commands constituting CLA of commands and the set is performed in common, and constitute the set and INS portion of said issued before command constituting the group It is characterized by including a process commonly executed for a value set in the INS part of the post-issue command.

The invention according to claim 3 is the electronic information storage medium according to claim 1, wherein the CLA part of the pre-issuance command constituting the set and the CLA part of the post-issuance command constituting the set, or , at least one of INS portion of the issuing post commands constituting the set and INS portion of said issued before command constituting said set are set different values, said predetermined program, said constituting the group It is characterized in that it includes processing that is commonly executed for the storage unit both when the pre-issuance command is received and when the post-issue command that constitutes the set is received.

The invention according to claim 4 is the electronic information storage medium according to claim 3, and the process commonly executed for the storage unit is a process for writing data to the storage unit or the storage unit. It is characterized in that it is a process of reading the data of a part.

The invention according to claim 5 is the electronic information storage medium according to claim 4, and the processing commonly executed for the storage unit is the pre-issuance command and the set that constitute the set. It is characterized in that it is a process of writing the data set in the Data unit in the constituent post-issue command to the storage unit.

The invention according to claim 6 is an IC card including the electronic information storage medium according to any one of claims 1 to 5.

According to the present invention, the storage unit is a predetermined program corresponding to both the pre-issue command and the post-issue command, and is common to both the case where the pre-issue command is received and the case where the post-issue command is received. A predetermined program including a process to be executed is stored, and when the execution unit receives a pre-issue command and a post-issue command, the predetermined program is executed. That is, the storage area for storing the pre-issue command and the post-issue command can be saved by integrating and sharing the program executed when the command is received.

It is a figure which shows the hardware configuration example of the IC chip 1a mounted on the IC card 1 which concerns on this embodiment. It is a command list including an example of a command before issuance and a command after issuance. It is a figure which shows an example of the command format of a VERIFY (IS) command and a VERIFY (USR) command. (A) is a flowchart showing a conventional processing example of a command execution program corresponding to a VERIFY (IS) command, and (B) shows a conventional processing example of a command execution program corresponding to a VERIFY (USR) command. It is a flowchart. It is a flowchart which shows the processing example of the command execution program corresponding to the VERIFY (IS) command and VERIFY (USR) command which concerns on this embodiment. (A) is a diagram showing an example of the command format of the STORE DATA command, and (B) is a diagram showing an example of the command format of the WRITE BINARY command. (A) is a flowchart showing a conventional processing example of a command execution program corresponding to the STORE DATA command, and (B) is a flowchart showing a conventional processing example of a command execution program corresponding to WRITE BINARY. It is a flowchart which shows the processing example of the command execution program corresponding to the STORE DATA command and WRITE BINARY command which concerns on this embodiment. (A) is a diagram showing an example of the command format of the READ DATA command, and (B) is a diagram showing an example of the command format of the READ BINARY command. (A) is a flowchart showing a conventional processing example of a command execution program corresponding to the READ DATA command, and (B) is a flowchart showing a conventional processing example of a command execution program corresponding to the READ BINARY. It is a flowchart which shows the processing example of the command execution program corresponding to the READ DATA command and READ BINARY command which concerns on this embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiment described below is an embodiment when the present invention is applied to an IC chip and an IC card on which the IC chip is mounted.

[1. Configuration of IC chip 1a]
First, the configuration of the IC chip 1a mounted on the IC card 1 will be described with reference to FIG. FIG. 1 is a diagram showing a hardware configuration example of an IC chip 1a mounted on an IC card 1. The IC card 1 of the present embodiment is a dual interface type IC card having two communication functions of contact data communication and non-contact data communication. However, the type of the IC card 1 is not limited to the dual interface type IC card, and may be a contact type IC card in which the IC chip 1a is embedded in a plastic card having the same size as a cash card or a credit card. Further, it may be a non-contact type IC card having a built-in antenna coil and wirelessly communicating data with a reader / writer.

As shown in FIG. 1, the IC chip 1a includes a CPU (Central Processing Unit) 10, a RAM (Random Access Memory) 11, a ROM (Read Only Memory) 12, a non-volatile memory 13, and an I / O circuit 14. It is composed. The CPU 10 is a processor (computer) that executes various programs stored in the ROM 12 or the non-volatile memory 13. The I / O circuit 14 serves as an interface with the external device 2. As a result, the IC chip 1a can communicate with the external device 2 including the reader / writer in contact or non-contact. In the case of the contact type IC chip 1a, the I / O circuit 14 is provided with, for example, eight terminals C1 to C8. For example, the C1 terminal is a power supply terminal (terminal that supplies power to the IC chip 1a), the C2 terminal is a reset terminal, the C3 terminal is a clock terminal, the C5 terminal is a ground terminal, and the C7 terminal communicates with an external device 2. It is a terminal of. On the other hand, in the case of the non-contact type IC chip 1a, the I / O circuit 14 is provided with, for example, an antenna and a modulation / demodulation circuit. Examples of the external device 2 include an IC card issuing machine and a server device.

The non-volatile memory 13 is composed of, for example, a flash memory or an "Electrically Erasable Programmable Read-Only Memory", and stores an OS, various applications, and data used by these. The non-volatile memory 13 may store a part of the OS, and the ROM 12 may store the other part. Further, the non-volatile memory 13 is a command execution program including a process for the OS to execute a process corresponding to the command when a command is received from the external device 2 and to send a SW related to the execution result as a response. Is remembered.

[2. Command type]
When the CPU 10 receives a command from the external device 2, it executes a command execution program corresponding to the command and transmits the SW as a response to the external device 2. Conventionally, there are pre-issue commands and post-issue commands as commands, and there are similar commands between pre-issue commands and post-issue commands. Some of the processing included in the command execution program corresponding to each of them is common. Here, an example thereof will be described with reference to FIG.

As shown in FIG. 2, the VERIFY (IS) command, which is a pre-issue command for authenticating the issuer, and the VERIFY (USR) command, which is a post-issue command for authenticating the user, are for executing the corresponding commands. Some processes included in the program are common. Further, the STORE DATA command, which is a pre-issuance command for writing data to the non-volatile memory 13, and the WRITE BINARY command, which is a post-issue command for writing data to a file, are included in the corresponding command execution programs. The processing of the parts is common. Furthermore, the READ DATA command, which is a pre-issue command for reading data for the purpose of confirming that the data is written correctly, and the READ BINARY command, which is a post-issue command for reading file data, are used, respectively. Some processes included in the corresponding command execution program are common.

[2.1. VERIFY (IS) command and VERIFY (USR) command]
[2.1.1. Command format]
Next, the command formats of the VERIFY (IS) command and the VERIFY (USR) command will be described with reference to FIG. Note that FIG. 3 is a diagram showing an example of the command formats of the VERIFY (IS) command and the VERIFY (USR) command. As shown in FIG. 3, the command formats of the VERIFY (IS) command and the VERIFY (USR) command are common. That is, each command is "00h (fixed)" for the CLA part, "10h (fixed)" for the INS part, "00h (fixed)" for the P1 part, and "00h (fixed)" for the P2 part. , "01h" to "10h" are set in the Lc part, and the PIN (Personal Identification Number for VERIFY (IS) command is the issuer PIN (Personal Identification Number) for the Data part, and the VERIFY (USR) command is used for the Data part. User PIN) is set respectively.

[2.1.2. Conventional processing flow]
[2.1.2.1. When receiving a VERIFY (IS) command]
Next, a processing example of a VERIFY (IS) command and a conventional command execution program executed when a VERIFY (USR) command is received will be described with reference to FIG. Note that FIG. 4A is a flowchart showing a conventional processing example of a command execution program corresponding to the VERIFY (IS) command, and FIG. 4B is a command execution program corresponding to the VERIFY (USR) command. It is a flowchart which shows the conventional processing example of.

As shown in FIG. 4A, the CPU 10 of the IC chip 1a that has received the VERIFY (IS) command first checks the value set in the CLA unit (step S101). For example, in the command format shown in FIG. 3, it is checked whether "00h" is set.

Next, the CPU 10 checks the value set in the INS unit (step S102). For example, in the command format shown in FIG. 3, it is checked whether "10h" is set.

Next, it is checked whether the value set in the Lc portion and the length of the Data portion are consistent (step S103).

Although not shown, when the CPU 10 determines that the command is not normal as a result of the checks in the processes of steps S101 to S103, the CPU 10 responds with a SW (“abnormal SW”) indicating an abnormality to the command source (“abnormal SW”). Step S108), the process shown in the flowchart is terminated.

Next, the CPU 10 authenticates based on the PIN of the issuer set in the Data unit (step S104). Next, the CPU 10 determines whether or not the authentication results match (step S105).

When the CPU 10 determines that the authentication results match (step S105: YES), the CPU 10 sets the issuer authentication completed as the authentication result (step S106), and sets the command source to indicate normality (“normal SW”). ”) (Step S107), and the process shown in the flowchart is terminated. On the other hand, when the CPU 10 determines that the authentication results do not match (step S105: NO), the CPU 10 responds to the command source by the abnormal SW (step S108), and ends the process shown in the flowchart.

[2.1.2.2. When receiving a VERIFY (USR) command]
On the other hand, as shown in FIG. 4B, the CPU 10 of the IC chip 1a that has received the VERIFY (USR) command first checks the value set in the CLA unit (step S111). For example, in the command format shown in FIG. 3, it is checked whether "00h" is set.

Next, the CPU 10 checks the value set in the INS unit (step S112). For example, in the command format shown in FIG. 3, it is checked whether "10h" is set.

Next, it is checked whether the value set in the Lc portion and the length of the Data portion are consistent (step S113).

As described above, the processes of steps S111 to S113 are the same as the processes of steps S101 to S103 of FIG. 4 (A).

Next, the CPU 10 authenticates based on the PIN of the user set in the Data unit (step S114). Next, the CPU 10 determines whether or not the authentication results match (step S115).

When the CPU 10 determines that the authentication results match (step S115: YES), the CPU 10 sets the user authentication completed as the authentication result (step S116), and responds to the command source by the normal SW (step S117). ), The process shown in the flowchart is terminated. On the other hand, when the CPU 10 determines that the authentication results do not match (step S115: NO), the CPU 10 responds to the command source by the abnormal SW (step S118), and ends the process shown in the flowchart.

As described above, comparing the conventional processing examples when the VERIFY (IS) command and the VERIFY (USR) command are received, the processing of steps S101 to S103 (steps S111 to S113) is common. This is based on the fact that the VERIFY (IS) command and the VERIFY (USR) command have a common command format. Therefore, in the present embodiment, a command execution program in which a command execution program corresponding to the VERIFY (IS) command and a command execution program corresponding to the VERIFY (USR) command are shared is created and stored, and is stored in the conventional command execution program. The storage area of the non-volatile memory 13 is saved by not storing the command execution program corresponding to the VERIFY (IS) command and the command execution program corresponding to the VERIFY (USR) command.

[2.1.3. Processing flow of this embodiment]
Hereinafter, a processing example by the common command execution program will be described with reference to FIG. Note that FIG. 5 is a flowchart showing a processing example of a command execution program corresponding to the VERIFY (IS) command and the VERIFY (USR) command.

As shown in FIG. 5, the CPU 10 of the IC chip 1a first checks the value set in the CLA unit (step S121). For example, in the command format shown in FIG. 3, it is checked whether "00h" is set.

Next, the CPU 10 checks the value set in the INS unit (step S122). For example, in the command format shown in FIG. 3, it is checked whether "10h" is set.

Next, it is checked whether the value set in the Lc portion and the length of Data are consistent (step S123). Although not shown, if the CPU 10 determines that the command is not normal as a result of the checks in the processes of steps S121 to S123, the CPU 10 responds to the command source by an abnormal SW (step S129), and is shown in the flowchart. End the process.

As described above, the processes of steps S121 to S123 are the same as the processes of steps S101 to S103 of FIG. 4 (A) (steps S111 to S113 of FIG. 4 (B)).

Next, the CPU 10 determines whether or not the issue flag is on (step S124). The issuance flag is set to "on" if the state is before the issuance of the IC card 1, and is set to "off" if the state is after the issuance of the IC card 1. When the CPU 10 determines that the issuance flag is on (before issuance) (step S124: YES), the CPU 10 authenticates based on the issuer's PIN set in the Data unit (step S125). Next, the CPU 10 determines whether or not the authentication results match (step S126).

When the CPU 10 determines that the authentication results match (step S126: YES), the CPU 10 sets the issuer authentication completed as the authentication result (step S127), and responds to the command source by the normal SW (step S126). S128), the process shown in the flowchart is terminated. On the other hand, when the CPU 10 determines that the authentication results do not match (step S126: NO), the CPU 10 responds to the command transmission source by the abnormal SW (step S129), and ends the process shown in the flowchart.

On the other hand, when the CPU 10 determines that the issuance flag is not on (after issuance) (step S124: NO), the CPU 10 authenticates based on the PIN of the user set in the Data unit (step S130). Next, the CPU 10 determines whether or not the authentication results match (step S131).

When the CPU 10 determines that the authentication results match (step S131: YES), the CPU 10 sets the user authentication completed as the authentication result (step S132), and responds to the command source by the normal SW (step S133). ), The process shown in the flowchart is terminated. On the other hand, when the CPU 10 determines that the authentication results do not match (step S131: NO), the CPU 10 responds to the command transmission source by the abnormal SW (step S129), and ends the process shown in the flowchart.

[2.2. STORE DATA command and WRITE BINARY command]
[2.2.1. Command format]
Next, the command formats of the STORE DATA command and the WRITE BINARY command will be described with reference to FIG. Note that FIG. 6A is a diagram showing an example of the command format of the STORE DATA command, and FIG. 6B is a diagram showing an example of the command format of the WRITE BINARY command. As shown in FIG. 6A, the command format of the STORE DATA command is "00h (fixed)" for the CLA part, "20h (fixed)" for the INS part, and "00h (fixed)" for the P1 part. , "00h (fixed)" is set in the P2 section, the length of the Data section is set in the Lc section, and the address (4 bytes) on the non-volatile memory 13 to which the data is written is set in the Data section and the data to be written. (Arbitrary data length) is set.

On the other hand, as shown in FIG. 6B, the command format of the WRITE BINARY command is "00h (fixed)" for the CLA part, "30h (fixed)" for the INS part, and "FID (File)" for the P1 part. "Identifier)", "FID" is set in the P2 part, the length of the Data part is set in the Lc part, and the data to be written (arbitrary data length) is set in the Data part. The FIDs set in the P1 part and the P2 part indicate a file on the non-volatile memory 13 to which the data is written.

That is, since the address to which the data is written is set in the STORE DATA command, the CPU 10 can directly write the data to the storage area indicated by the address. On the other hand, since the file to which the data is written is set in the WRITE BINARY command, the CPU 10 specifies the address to which the data is written based on the file, and then stores the specified address. You need to write data to the area. On the other hand, both the STORE DATA command and the WRITE BINARY command are common in that once the data writing destination is determined, the data is written thereafter.

In the example of FIG. 6, "00h" is set in common for the CLA part in the STORE DATA command and the WRITE BINARY command, but different values may be set. In this case, a common value may be set in the INS part of the STORE DATA command and the WRITE BINARY command.

[2.2.2. Conventional processing flow]
[2.2.2.1. When receiving STORE DATA command]
Next, a processing example of a conventional command execution program executed when a STORE DATA command and a WRITE BINARY command are received will be described with reference to FIG. 7. Note that FIG. 7 (A) is a flowchart showing a conventional processing example of a command execution program corresponding to the STORE DATA command, and FIG. 7 (B) is a conventional processing example of a command execution program corresponding to LIGHT BINARY. It is a flowchart which shows.

As shown in FIG. 7A, the CPU 10 of the IC chip 1a that has received the STORE DATA command first checks the value set in the CLA unit (step S201). For example, in the case of the command format shown in FIG. 6A, it is checked whether "00h" is set.

Next, the CPU 10 checks the value set in the INS unit (step S202). For example, in the case of the command format shown in FIG. 6A, it is checked whether "20h" is set.

Next, the CPU 10 checks whether the value set in the Lc unit and the length of the Data unit are consistent (step S203). Although not shown, if the CPU 10 determines that the command is not normal as a result of the checks in the processes of steps S201 to S203, the CPU 10 responds to the command source by an abnormal SW (step S208), and is shown in the flowchart. End the process.

Next, the CPU 10 acquires the address set in the Data unit (step S204).

Next, the CPU 10 writes the data set in the Data unit to the address acquired in the process of step S204 (step S205). Next, the CPU 10 determines whether or not the writing is successful (step S206).

When the CPU 10 determines that the writing is successful (step S206: YES), the CPU 10 responds to the command source by the normal SW (step S207), and ends the process shown in the flowchart. On the other hand, when it is determined that the writing is not successful (step S206: NO), the CPU 10 responds to the command source by the abnormal SW (step S208), and ends the process shown in the flowchart.

[2.2.2.2. When receiving the LIGHT BINARY command]
On the other hand, as shown in FIG. 7B, the CPU 10 of the IC chip 1a that has received the WRITE BINARY command first checks the value set in the CLA unit (step S211). For example, in the case of the command format shown in FIG. 6B, it is checked whether "00h" is set.

Next, the CPU 10 checks the value set in the INS unit (step S212). For example, in the case of the command format shown in FIG. 6B, it is checked whether "30h" is set.

Next, the CPU 10 checks whether the value set in the Lc unit and the length of the Data unit are consistent (step S213). Although not shown, if the CPU 10 determines that the command is not normal as a result of the checks in the processes of steps S211 to S213, the CPU 10 responds to the command source by an abnormal SW (step S218) and is shown in the flowchart. End the process.

Next, the CPU 10 acquires the address of the data writing destination based on the FID set in the P1 unit and the P2 unit (step S214).

Next, the CPU 10 writes the data set in the Data unit to the address acquired in the process of step S214 (step S215). Next, the CPU 10 determines whether or not the writing is successful (step S216).

When the CPU 10 determines that the writing is successful (step S216: YES), the CPU 10 responds to the command source by the normal SW (step S217), and ends the process shown in the flowchart. On the other hand, when it is determined that the writing is not successful (step S216: NO), the CPU 10 responds to the command transmission source by the abnormal SW (step S218), and ends the process shown in the flowchart.

As described above, comparing the conventional processing examples when the STORE DATA command and the LIGHT BINARY command are received, the processing of steps S205 to S208 (steps S215 to S218) is common. This is because the functions of the STORE DATA command and the WRITE BINARY command (the function of writing data to the non-volatile memory 13) are common. Therefore, in the present embodiment, a command execution program in which a command execution program corresponding to the STORE DATA command and a command execution program corresponding to the LIGHT BINARY command are shared is created and stored, and stored in the conventional STORE DATA command. The storage area of the non-volatile memory 13 is saved by not storing the corresponding command execution program and the command execution program corresponding to the LIGHT BINARY command.

[2.22.3. Processing flow of this embodiment]
Hereinafter, a processing example by the common command execution program will be described with reference to FIG. Note that FIG. 8 is a flowchart showing a processing example of a command execution program corresponding to the STORE DATA command and the WRITE BINARY command.

As shown in FIG. 8, the CPU 10 of the IC chip 1a first determines whether or not the received command is a STORE DATA command (step S221). When the CPU 10 determines that the received command is a STORE DATA command (step S221: YES), the CPU 10 then checks the value set in the CLA unit (step S222). For example, in the case of the command format shown in FIG. 6A, it is checked whether "00h" is set.

Next, the CPU 10 checks the value set in the INS unit (step S223). For example, in the case of the command format shown in FIG. 6A, it is checked whether "20h" is set.

Next, the CPU 10 checks whether the value set in the Lc unit and the length of the Data unit are consistent (step S224). Although not shown, if the CPU 10 determines that the command is not normal as a result of the check in the processes of steps S222 to S224, the CPU 10 responds to the command source by an abnormal SW (step S233), and is shown in the flowchart. End the process.

Next, the CPU 10 acquires the address set in the Data unit (step S225), and proceeds to the process of step S230.

On the other hand, when the CPU 10 determines that the received command is not a STORE DATA command (step S221: NO), the CPU 10 then checks the value set in the CLA unit (step S226). For example, in the case of the command format shown in FIG. 6B, it is checked whether "00h" is set.

Next, the CPU 10 checks the value set in the INS unit (step S227). For example, in the case of the command format shown in FIG. 6B, it is checked whether "30h" is set.

Next, the CPU 10 checks whether the value set in the Lc unit and the length of the Data unit are consistent (step S228). Although not shown, if the CPU 10 determines that the command is not normal as a result of the checks in the processes of steps S226 to S227, the CPU 10 responds to the command source by an abnormal SW (step S233), and is shown in the flowchart. End the process.

Next, the CPU 10 acquires the address of the data writing destination based on the FID set in the P1 unit and the P2 unit (step S229), and proceeds to the process of step S230.

Next, the CPU 10 writes the data set in the Data unit to the address acquired in the process of step S225 or step S229 (step S230). Next, the CPU 10 determines whether or not the writing is successful (step S231).

When the CPU 10 determines that the writing is successful (step S231: YES), the CPU 10 responds to the command source by the normal SW (step S232), and ends the process shown in the flowchart. On the other hand, when it is determined that the writing is not successful (step S231: NO), the CPU 10 responds to the command transmission source by the abnormal SW (step S233), and ends the process shown in the flowchart.

[2.3. READ DATA command and READ BINARY command]
[2.3.1. Command format]
Next, the command formats of the READ DATA command and the READ BINARY command will be described with reference to FIG. Note that FIG. 9A is a diagram showing an example of the command format of the READ DATA command, and FIG. 9B is a diagram showing an example of the command format of the READ BINARY command. As shown in FIG. 9A, the command format of the READ DATA command is "00h (fixed)" for the CLA part, "40h (fixed)" for the INS part, and "00h (fixed)" for the P1 part. , P2 part has "00h (fixed)", Lc part has "08h (fixed)", and Data part has a start address (4 bytes) and an end address (4 bytes) on the non-volatile memory 13 of the data to be read. Set.

On the other hand, as shown in FIG. 9B, the command format of the READ BINARY command is "00h (fixed)" in the CLA part, "50h (fixed)" in the INS part, and "FID (File)" in the P1 part. "Identifier)", "FID" is set in the P2 part. The FIDs set in the P1 part and the P2 part indicate a file on the non-volatile memory 13 including the data to be read.

That is, since the READ DATA command is set with an address indicating an area in which the data to be read is stored, the CPU 10 can read the data from the storage area indicated by the address. On the other hand, since a file including data to be read is set in the READ BINARY command, the CPU 10 specifies an address indicating a storage area of data included in the file based on the file, and then the specified address. It is necessary to read the data stored in the storage area indicated by. On the other hand, both the READ DATA command and the READ BINARY command are common in that once the storage area in which the data to be read is stored is specified, the data is read after that.

In the example of FIG. 9, "00h" is set in common for the CLA part in the READ DATA command and the READ BINARY command, but different values may be set. In this case, a common value may be set in the INS part of the READ DATA command and the READ BINARY command.

[2.3.3. Conventional processing flow]
[2.3.2.1. When receiving the READ DATA command]
Next, a processing example of a conventional command execution program executed when a READ DATA command and a READ BINARY command are received will be described with reference to FIG. Note that FIG. 10A is a flowchart showing a conventional processing example of a command execution program corresponding to the READ DATA command, and FIG. 10B is a conventional processing example of a command execution program corresponding to the READ BINARY. It is a flowchart which shows.

As shown in FIG. 10A, the CPU 10 of the IC chip 1a that has received the READ DATA command first checks the value set in the CLA unit (step S301). For example, in the case of the command format shown in FIG. 9A, it is checked whether "00h" is set.

Next, the CPU 10 checks the value set in the INS unit (step S302). For example, in the case of the command format shown in FIG. 9A, it is checked whether "40h" is set.

Next, the CPU 10 checks the value set in the Lc unit (step S303). For example, in the case of the command format shown in FIG. 9A, it is checked whether "08h" is set. Although not shown, if the CPU 10 determines that the command is not normal as a result of the checks in the processes of steps S301 to S303, the CPU 10 responds to the command source by an abnormal SW (step S308), and is shown in the flowchart. End the process.

Next, the CPU 10 acquires the start address and the end address set in the Data unit (step S304).

Next, the CPU 10 acquires the data stored in the storage area specified by the start address and the end address acquired in the process of step S304 (step S305). Next, the CPU 10 determines whether or not the acquisition is successful (step S306).

When the CPU 10 determines that the acquisition is successful (step S306: YES), the CPU 10 responds to the command source with the data acquired in the process of step S305 and the normal SW (step S307), and is shown in the flowchart. End the process. On the other hand, when it is determined that the acquisition is not successful (step S306: NO), the CPU 10 responds to the command transmission source by the abnormal SW (step S308), and ends the process shown in the flowchart.

[2.3.2.2. When receiving the READ BINARY command]
On the other hand, as shown in FIG. 10B, the CPU 10 of the IC chip 1a that has received the READ BINARY command first checks the value set in the CLA unit (step S311). For example, in the case of the command format shown in FIG. 9B, it is checked whether "00h" is set.

Next, the CPU 10 checks the value set in the INS unit (step S312). For example, in the case of the command format shown in FIG. 9B, it is checked whether "50h" is set. Although not shown, if the CPU 10 determines that the command is not normal as a result of the checks in the processes of steps S311 to S312, the CPU 10 responds to the command source by an abnormal SW (step S317) and is shown in the flowchart. End the process.

Next, the CPU 10 acquires a start address and an end address indicating a storage area in which data to be read based on the FID set in the P1 unit and the P2 unit is stored (step S313).

Next, the CPU 10 acquires the data stored in the storage area specified by the start address and the end address acquired in the process of step S313 (step S314). Next, the CPU 10 determines whether or not the acquisition is successful (step S315).

When the CPU 10 determines that the acquisition is successful (step S315: YES), the CPU 10 responds to the command source with the data acquired in the process of step S314 and the normal SW (step S316), and is shown in the flowchart. End the process. On the other hand, when it is determined that the acquisition is not successful (step S315: NO), the CPU 10 responds to the command transmission source by the abnormal SW (step S317), and ends the process shown in the flowchart.

As described above, comparing the conventional processing examples when the READ DATA command and the READ BINARY command are received, the processing of steps S305 to S308 (steps S314 to S317) is common. This is because the functions of the READ DATA command and the READ BINARY command (the function of reading data to the non-volatile memory 13) are common. Therefore, in the present embodiment, a command execution program in which a command execution program corresponding to the READ DATA command and a command execution program corresponding to the READ BINARY command are shared is created and stored, and stored in the conventional READ DATA command. The storage area of the non-volatile memory 13 is saved by not storing the corresponding command execution program and the command execution program corresponding to the READ BINARY command.

[2.3.3. Processing flow of this embodiment]
Hereinafter, a processing example by the common command execution program will be described with reference to FIG. Note that FIG. 11 is a flowchart showing a processing example of a command execution program corresponding to the READ DATA command and the READ BINARY command.

As shown in FIG. 11, the CPU 10 of the IC chip 1a first determines whether or not the received command is a READ DATA command (step S321). When the CPU 10 determines that the received command is a READ DATA command (step S321: YES), the CPU 10 then checks the value set in the CLA unit (step S322). For example, in the case of the command format shown in FIG. 9A, it is checked whether "00h" is set.

Next, the CPU 10 checks the value set in the INS unit (step S323). For example, in the case of the command format shown in FIG. 9A, it is checked whether "40h" is set.

Next, the CPU 10 checks the value set in the Lc unit (step S324). For example, in the case of the command format shown in FIG. 9A, it is checked whether "08h" is set. Although not shown, if the CPU 10 determines that the command is not normal as a result of the check in the processes of steps S322 to S324, the CPU 10 responds to the command source by an abnormal SW (step S332) and is shown in the flowchart. End the process.

Next, the CPU 10 acquires the start address and end address set in the Data unit (step S325), and proceeds to the process of step S329.

On the other hand, when the CPU 10 determines that the received command is not a READ DATA command (step S321: NO), the CPU 10 then checks the value set in the CLA unit (step S326). For example, in the case of the command format shown in FIG. 9B, it is checked whether "00h" is set.

Next, the CPU 10 checks the value set in the INS unit (step S327). For example, in the case of the command format shown in FIG. 9B, it is checked whether "50h" is set. Although not shown, if the CPU 10 determines that the command is not normal as a result of the checks in the processes of steps S326 to S327, the CPU 10 responds to the command source by an abnormal SW (step S332) and is shown in the flowchart. End the process.

Next, the CPU 10 acquires a start address and an end address indicating a storage area in which data to be read based on the FID set in the P1 unit and the P2 unit is stored (step S328), and proceeds to the process of step S329. To do.

Next, the CPU 10 acquires the data stored in the storage area specified by the start address and the end address acquired in the process of step S325 or step S328 (step S329). Next, the CPU 10 determines whether or not the acquisition is successful (step S330).

When the CPU 10 determines that the acquisition is successful (step S330: YES), the CPU 10 responds to the command source with the data acquired in the process of step S325 or step S328 and the normal SW (step S331). The process shown in the flowchart ends. On the other hand, when it is determined that the acquisition is not successful (step S330: NO), the CPU 10 responds to the command transmission source by the abnormal SW (step S332), and ends the process shown in the flowchart.

As described above, the IC chip 1a (an example of the "electronic information storage medium") of the present embodiment is derived from the non-volatile memory 13 (an example of the "storage unit") for storing the program corresponding to the command and the external device 2. The non-volatile memory 13 includes a CPU 10 (an example of an "execution unit") that executes a command execution program (an example of a "program") corresponding to a received command, and the non-volatile memory 13 is a command before issuance and a command after issuance. A common command execution program (an example of a "predetermined command execution program") corresponding to both is stored, and the common command execution program receives a pre-issue command and a post-issue command. In both cases, the processes commonly executed (for example, the processes of steps S121 to S123 in FIG. 5, the processes of steps S230 to S233 in FIG. 8, and the processes of steps S329 to S332 in FIG. 11) are included.

Therefore, according to the IC chip 1a of the present embodiment, the non-volatile memory 13 is a common command execution program corresponding to both the pre-issue command and the post-issue command, and the case where the pre-issue command is received. A common command execution program including processes to be executed in common is stored in both cases when a post-issue command is received, and when the CPU 10 receives a pre-issue command and a post-issue command, the command execution program is stored. Execute. That is, the storage area for storing the command execution program can be saved by integrating and sharing the command execution program executed when the command is received for the pre-issue command and the post-issue command.

In the common command execution program described with reference to FIG. 5, the amount of source code data is increased by the amount of the issuance flag and the determination using the issuance flag (step S124), and the non-volatile memory 13 is increased. Although the amount of data to be stored increases, the amount of data reduction by unifying the processes (processes of steps S121 to S123) in the command execution program is larger. In particular, since the amount of source code data related to the check processing in steps S121 to S123 is large, the amount of data reduction by standardizing the check processing is larger.

Further, the CLA part of the VERIFY (IS) command (an example of the "pre-issue command") of the present embodiment, the CLA part of the VERIFY (USR) command (an example of the "post-issue command"), and the VERIFY (IS) command. Common values are set in the INS part and the INS part of the VERIFY (USR) command, and the common command execution program is set in the CLA part of the VERIFY (IS) command and the CLA part of the VERIFY (USR) command. Processes that are commonly executed for the values (process in step S121 in FIG. 5) and processes that are commonly executed for the values set in the INS part of the VERIFY (IS) command and the INS part of the VERIFY (USR) command. (Processing in step S122 of FIG. 5) and. As a result, the processes executed in steps S121 and S122 can be shared, and the storage area for storing the command execution program can be saved.

Further, the CLA part of the STORE DATA command (an example of "pre-issuance command") and the CLA part of the WRITE command (an example of "post-issue command") of the present embodiment, or the INS part and WRITE BINARY command of the STORE DATA command. A different value is set for at least one of the INS parts of the above, and the common command execution program is for the non-volatile memory 13 both when the STORE DATA command is received and when the WRITE BINARY command is received. A commonly executed process (processes in steps S230 to S233 in FIG. 8) is included. As a result, the processes commonly executed for the non-volatile memory 13 can be shared, and the storage area for storing the command execution program can be saved.

Furthermore, the process commonly executed for the non-volatile memory 13 in the common command execution program corresponding to the STORE DATA command and the WRITE BINARY command is a process of writing data to the non-volatile memory 13, and is more specific. Specifically, it is a process of writing the data set in the Data unit in the STORE DATA command and the WRITE BINARY command to the non-volatile memory 13. As a result, the process of writing data to the non-volatile memory 13 (processes of steps S230 to S233 in FIG. 8) can be shared, and the storage area for storing the command execution program can be saved.

Furthermore, the CLA part of the READ DATA command (an example of the "pre-issue command") and the CLA part of the READ BINARY command (an example of the "post-issue command") of the present embodiment, or the INS part and the READ BINARY of the READ DATA command. Different values are set for at least one of the INS parts of the command, and the common command execution program is for the non-volatile memory 13 both when the READ DATA command is received and when the READ BINARY command is received. The processes commonly executed (processes in steps S329 to S332 of FIG. 11) are included. As a result, the processes commonly executed for the non-volatile memory 13 (processes in steps S329 to S332 of FIG. 11) can be shared, and the storage area for storing the command execution program can be saved. it can.

Furthermore, the process commonly executed for the non-volatile memory 13 in the common command execution program corresponding to the READ DATA command and the READ BINARY command is the process of reading the data of the non-volatile memory 13 (step of FIG. 11). (Processing of S329 to S332). As a result, the process of reading the data of the non-volatile memory 13 (processes of steps S329 to S332 of FIG. 11) can be shared, and the storage area for storing the command execution program can be saved.

1 IC card 1a IC chip 10 CPU
11 RAM
12 ROM
13 Non-volatile memory 14 I / O circuit 2 External device

Claims (6)

An electronic information storage medium including a storage unit for storing a program corresponding to a command and an execution unit for executing the program corresponding to the command received from the outside.
The plurality of types of the commands include a pre-issuance command, which is a command received before the issuance of the electronic information storage medium, and a post-issue command, which is a command received after the issuance.
The storage unit
Among a plurality of types of said commands, a predetermined program corresponding to the set to be the pre-issuing command to perform common process to the electronic information storage medium from the after issuing the command,
Issuance information indicating whether the electronic information storage medium is before or after issuance, and
Remember,
The predetermined program
And said common processing which are executed in both the case of receiving the issued after the command to configure the set with the case of receiving the issued before command constituting the sets,
A process that is executed when the issue information indicates before the issue, and a process that is executed in response to the pre-issue command that constitutes the set.
A process that is executed when the issue information indicates the post-issue, and a process that is executed in response to the post-issue command that constitutes the set.
An electronic information storage medium comprising. The electronic information storage medium according to claim 1.
CLA portion of the issuing post commands that configure the set with CLA portion of said issued before command constituting the sets, and said after issuance command to configure the set with INS portion of said issued before command constituting the group Common values are set for each INS part of
The predetermined program constitutes a process commonly executed for a value set in the CLA part of the pre-issuance command constituting the set and the CLA part of the post-issuance command constituting the set, and the set. An electronic information storage medium comprising: a process commonly executed for a value set in the INS unit of the pre-issue command and the INS unit of the post-issue command constituting the set. The electronic information storage medium according to claim 1.
CLA portion of the issuing post commands that configure the set with CLA portion of said issued before command constituting the group or the after issuance command to configure the set with INS portion of said issued before command constituting the group Different values are set for at least one of the INS parts of
The predetermined program performs processing that is commonly executed for the storage unit both when the pre-issuance command constituting the set is received and when the post-issue command constituting the set is received. An electronic information storage medium comprising. The electronic information storage medium according to claim 3.
An electronic information storage medium characterized in that a process commonly executed for the storage unit is a process of writing data to the storage unit or a process of reading data from the storage unit. The electronic information storage medium according to claim 4.
It processing performed in common for the memory unit, the process of writing the data set in the Data part of the issuing post commands constituting the issue prior command and said set constituting the sets in the storage unit An electronic information storage medium characterized by being present. An IC card including the electronic information storage medium according to any one of claims 1 to 5.

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