JP6904656B2 - Pachinko machine - Google Patents

Description

The present invention relates to a gaming machine.

Conventionally, every time the number of game balls actually paid out reaches a predetermined number by detecting the game balls paid out as prize balls from the payout device (prize ball device) by a counting switch provided in the payout device. A gaming machine has been proposed in which this is output to a hall computer via an external terminal board (external output means) (for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2013-081862 (paragraph [0068] and FIG. 12)

Where there is, in the gaming machine described in Patent Document 1, when a big hit is occurring, when the game ball from the island equipment is not supplied by some trouble, the player game balls as winning balls from dispensing apparatus Since it becomes impossible to pay out to the player, the player will call a clerk in the hall or the like to solve the trouble. When this trouble is resolved and the jackpot is completed at this point, in the gaming machine described in Patent Document 1, the gaming balls that were not paid out in the jackpot are paid out one after another as prize balls from the payout device. Therefore, every time the number of game balls paid out as prize balls from the payout device reaches a predetermined number, that fact is output to the hall computer via the external terminal board, and the game of the game machine. state and, and the ball number game balls are paid out in this gaming state and Tsu problem hall computer the relationship will not be able to accurately grasp there.

The present invention has been made in view of such circumstances, and an object of the present invention is that a hall computer accurately determines the relationship between the gaming state of a gaming machine and the number of gaming balls paid out in the gaming state. The purpose is to provide a gaming machine that can be grasped by.

(Solution 1)
In a game board in which a game area is formed and a game machine provided with a game window on a door frame so that the game area of the game board can be visually recognized, a game ball flowing down the game area is provided in the game area. Based on the main control means that outputs a prize ball command that defines the number of game balls to be paid out as a prize ball based on the balls entering the various winning openings, and the prize ball command from the main control means. The prize ball device is provided with a payout control means for controlling a prize ball device for paying out a game ball as a prize ball, and an external output means in which a plurality of terminals electrically connected to the outside and capable of transmitting various information are arranged. Is to pay out the game ball by the drive signal from the payout control means, the game ball to be paid out is detected by a predetermined counting switch, and the main control means is a game ball flowing down the game area. Main control prize ball number schedule information output signal every time the number of game balls scheduled to be paid out by the prize ball device as prize balls reaches a predetermined number based on the balls entering the various winning openings. A main control microprocessor that performs an operation to output to the external output means, and a prize ball command output control means that outputs the prize ball command to the payout control means are provided, and the main control prize ball number schedule information output. When the signals are continuously output, the signals are output at intervals equivalent to the signal width of the main control prize ball number schedule information output signal so that the main control prize ball number schedule information output signal is not continuously output. The payout control means outputs, and the payout control microprocessor, the payout control side output circuit capable of outputting various signals, and the number of game balls detected by the counting switch provided in the prize ball device are predetermined. The payout control prize ball number information output means that outputs to the external output means as a payout control prize ball number information output signal each time the number of balls is reached, and the fact that the opening of the door frame is detected is used as an opening information signal. The terminal of the payout control prize ball number information output signal and the terminal of the main control prize ball number schedule information output signal are adjacent to each other in the external output means, including an open information output means for outputting to an external output means. The signal width of the payout control prize ball number information output signal is set in advance based on the interrupt cycle of the payout control means, and the payout control side output circuit has an output circuit having a reset function. And an output circuit that does not have a reset function, and the payout control prize ball number information output signal is an output circuit having the reset function of the payout control side output circuit by the payout control prize ball number information output means. The output circuit that is output from the above and does not have the reset function includes a first output circuit that does not have the reset function and a second output circuit that does not have the reset function, and is from the first output circuit that does not have the reset function. Outputs a signal from the serial port of the payout control microprocessor, and does not output a signal from the payout control microprocessor from the second output circuit having no reset function, and the opening information output means. The opening information signal is output by the output circuit, and the output circuit having the reset function of the payout control side output circuit is reset at the time of power recovery .

In the gaming machine of the present invention , the hall computer can accurately grasp the relationship between the gaming state of the gaming machine and the number of gaming balls paid out in the gaming state.

It is a perspective view which shows the state which opened the main body frame with respect to the outer frame of a pachinko game machine, and opened the door frame with respect to the main body frame. It is a front view of a pachinko machine. It is a rear view of a pachinko machine. It is a front perspective view of the outer frame. It is a front perspective view of the main body frame. It is a rear perspective view of the substrate unit in the main body frame. It is a perspective view of a door frame. It is a front view of a game board. FIG. 8 is an exploded perspective view of the game board of FIG. 8 as viewed from the front by disassembling. It is a figure which shows the outline of the mode that the movable liquid crystal display device moves in the up, down, left and right directions. It is a front view which shows the function display unit in the game board enlarged in the state which attached to the pachinko game machine. It is a block diagram of a main control board, a payout control board, and a peripheral control board. It is a block diagram which shows the continuation of FIG. It is a schematic diagram of various detection signals input / output to a game ball rental device connection terminal board which relays an electrical connection between a payout control board which constitutes a main board, a CR unit, and a frequency display board. It is a block diagram which shows the continuation of FIG. It is a block diagram which shows the outline of the peripheral control MPU. It is a block diagram around the sound source built-in VDP in a liquid crystal and a sound control unit. It is a block diagram which shows the power-source system of a pachinko machine. It is a block diagram (a) which shows the power-source making circuit, and is the figure (b) which shows the relationship between the power consumption and the power consumption suppression level with the power consumption. It is a block diagram which shows the continuation of FIG. It is a circuit diagram which shows the circuit of a main control board. It is a circuit diagram which shows the power failure monitoring circuit. It is a circuit diagram which shows the communication interface circuit between the main control board and the peripheral control board. It is a circuit diagram which shows the circuit of the payout control unit and the like. It is a circuit diagram which shows the payout control input circuit. It is a circuit diagram which shows the continuation of FIG. It is a circuit diagram which shows the payout motor drive circuit. It is a circuit diagram which shows the CR unit input / output circuit. It is an input / output diagram which shows various input / output signals with a main control board, and various output signals to an external terminal board. It is a figure which shows the arrangement of the output terminal of an external terminal board. It is a block diagram which shows the circuit structure of the liquid crystal output board. It is a figure which shows an example of the creation method of drawing data. It is a figure which shows an example of the production example of the liquid crystal display device on the game board side and the movable liquid crystal display device. It is a figure which shows the continuation of the example of the effect of FIG. 33. It is a circuit diagram which shows the liquid crystal module circuit which draws the display area of the liquid crystal display device on the upper plate side. It is a block diagram of the touch panel circuit which detects and controls the contact state of a touch panel. It is a schematic diagram which detects the position where a finger is touching a touch panel. It is the schematic which shows the continuation of FIG. 37. This is a table showing an example of various commands transmitted from the main control board to the payout control board. This is a table showing an example of various commands transmitted from the main control board to the peripheral control board. It is a table which shows the continuation of various commands transmitted from the main control board of FIG. 40 to the peripheral control board. It is a table which shows an example of various commands from a payout control board received by a main control board. It is a flowchart which shows an example of the processing at the time of power-on of the main control side. It is a flowchart which shows the continuation of the process at the time of power-on of the main control side of FIG. 43. It is a flowchart which shows an example of the timer interrupt processing on the main control side. It is a flowchart which shows an example of the processing at the time of power-on of a payout control unit. It is a flowchart which shows the continuation of the process at the time of power-on of the payout control unit of FIG. It is the flowchart which shows the continuation of the process at the time of power-on of the payout control unit following FIG. 47. It is a flowchart which shows an example of the payout control part timer interrupt processing. It is a flowchart which shows an example of the rotation angle switch history creation processing. It is a flowchart which shows an example of the sprocket fixed position determination skip process. It is a flowchart which shows an example of the ball squeeze determination process. It is a flowchart which shows an example of the prize ball stock number addition processing for prize balls. It is a flowchart which shows an example of the prize ball stock number addition processing for ball rental. It is a flowchart which shows an example of a stock monitoring process. It is a flowchart which shows an example of the payout ball operation judgment setting process. It is a flowchart which shows an example of payout setting processing. It is a flowchart which shows an example of a sphere motion setting process. It is a flowchart which shows an example of a retry operation monitoring process. It is a flowchart which shows an example of the inconsistency counter reset determination process. It is a flowchart which shows an example of an error release operation determination process. It is a timing chart which shows the signal processing (a) at the time of payout operation by ball lending, and the input signal confirmation processing (b) from a CR unit. It is a flowchart which shows an example of the processing at the time of power-on of a peripheral control unit. It is a flowchart which shows an example of peripheral control part V blank interrupt processing. It is a flowchart which shows an example of the peripheral control part 1ms timer interrupt processing. It is a flowchart which shows an example of the peripheral control part command reception interrupt processing. It is a flowchart which shows an example of the peripheral control part power failure advance notice signal interrupt processing. It is a flowchart which shows an example of the power saving mode transition determination process at the time of power recovery. It is a flowchart which shows an example of the power consumption monitoring process. The figure which shows the relationship between the value set as the master volume value for power suppression and the power consumption suppression stage (a), and the figure which shows the relationship between the brightness set as the brightness for power suppression and the power consumption suppression stage (b). ). It is a flowchart which shows an example of the LOCKN signal history creation process. It is a flowchart which shows an example of connection failure determination processing. It is a flowchart which shows an example of the connection recovery processing. It is a timing chart explaining the timing of outputting the connection confirmation signal to the INIT terminal of the upper plate side liquid crystal transmitter IC. It is a figure which shows an example of the display content of a maintenance screen. It is a figure which shows the display content that the clerk should be called during a big hit. It is a figure which shows an example of the display content of a service mode screen. It is a figure which shows an example of the display content of the break timer setting screen. It is a figure which shows an example of the display content of the screen during a break. It is a figure which shows an example of the operation menu screen. It is a figure which shows an example of the operation menu screen. It is a figure which shows an example of the operation menu screen. It is a figure which shows an example of the operation menu screen. It is a figure which shows an example of the operation menu screen. It is a figure which shows an example which the title of the selected display object is displayed. It is a figure which shows an example which the title of the selected display object is displayed. It is a figure which shows an example of the operation menu screen. It is a figure which shows an example of the operation menu screen. It is a figure which shows an example of the operation menu screen. It is a figure which shows an example of the operation menu screen. It is a figure which shows an example of a volume adjustment screen. It is a figure which shows an example of a volume adjustment screen. It is a figure which shows an example of a volume adjustment screen. It is a figure which shows an example of a volume adjustment screen. It is a figure which shows an example of a volume adjustment screen. It is a figure which shows an example of the variation display effect displayed in the display area of the liquid crystal display device on the game board side. It is a figure which shows an example of the firing operation trouble notification effect displayed in the display area of the liquid crystal display device on the game board side. It is a schematic perspective view of a slot machine.

[1. Overall configuration of pachinko game machines]
Hereinafter, the pachinko gaming machine as the gaming machine of the present invention will be described with reference to the drawings. First, the entire pachinko gaming machine according to the embodiment will be described with reference to FIGS. 1 to 3. FIG. 1 is a perspective view showing a state in which the main body frame is opened with respect to the outer frame of the pachinko gaming machine according to the embodiment and the door frame is opened with respect to the main body frame, and FIG. 2 is a front view of the pachinko gaming machine. Yes, FIG. 3 is a rear view of the pachinko gaming machine.

As shown in FIGS. 1 to 3, the pachinko gaming machine 1 has an outer frame 2 installed in an island facility (not shown) of a game hall and a box that is pivotally supported by the outer frame 2 and has an open front side. A game board 4 having a frame-shaped main body frame 3, a game board 4 having a game area 1100 mounted and fixed to the main body frame 3 from the front side and into which a game ball as a game medium is driven, and a player side of the main body frame 3 and the front surface of the game board 4 It is provided with a door frame 5 that is pivotally supported with respect to the main body frame 3 so as to be closed from the door frame 3. In the door frame 5 of the pachinko game machine 1, a game window 101 formed so that the game area 1100 of the game board 4 can be seen from the player side, and a game ball arranged below the game window 101 are stored. The dish-shaped upper plate 301 and lower plate 302 (see FIG. 7), and the handle device 500 operated by the player to drive the game ball stored in the upper plate 301 into the game area 1100 of the game board 4. , Is equipped.

Further, in the pachinko gaming machine 1, when viewed from the front, the outer frame 2, the main body frame 3, and the door frame 5 are each formed in a vertically long rectangular shape extending in the vertical direction, and the horizontal widths in the left and right directions are substantially the same. In addition to the dimensions, the vertical width in the vertical direction is formed so that the dimensions of the main body frame 3 and the door frame 5 are slightly shorter than those of the outer frame 2. A decorative cover 23 is attached to the front surface of the outer frame 2 at a position below the main body frame 3 and the door frame 5, and the front surface of the outer frame 2 is completely closed by the door frame 5 and the decorative cover 23. It has become so. Further, the outer frame 2, the main body frame 3, and the door frame 5 are arranged so that the upper ends are substantially aligned with each other, and the main body frame 3 and the door frame 5 can be rotated at a position on the front side of the left end of the outer frame 2. It is supported, and the right end of the main body frame 3 and the door frame 5 moves to the front side with respect to the outer frame 2 to open the door frame 2.

Further, in the pachinko gaming machine 1, when viewed from the front, the gaming area 1100 in which the gaming ball is driven is facing through the substantially circular gaming window 101, and the pachinko gaming machine 1 projects forward to the lower side of the gaming window 101. As described above, the two upper plates 301 and the lower plates 302 are arranged one above the other. Further, a handle device 500 for the player to operate is arranged in the lower right corner of the front surface of the door frame 5, and the player operates the handle device 500 in a state where the game balls are stored in the upper plate 301. When the rotation operation is performed, the game ball in the upper plate 301 is driven into the game area 1100 of the game board 4 with the hitting strength corresponding to the rotation angle, and the game can be played.

The game window 101 of the door frame 5 is closed by a transparent glass unit 590, and although the inside of the game area 1100 can be visually recognized by the player, the player inserts a hand or the like into the game area 1100 to play the game. It is not possible to touch the game balls, obstacle nails, various winning openings, and accessories in the area 1100.

[2. Overall composition of the outer frame]
Next, the outer frame 2 installed in the island equipment of the game hall will be described with reference to FIG. FIG. 4 is a front perspective view of the outer frame. As shown in FIG. 4, the outer frame 2 includes upper and lower upper frame plates 10 and lower frame plates 11 extending in the horizontal direction, left and right side frame plates 12 and 13 extending in the vertical (up and down) direction, and their respective frame plates. It is provided with four connecting members 14 that connect the ends of 10, 11, 12, and 13, and by connecting the frame plates 10, 11, 12, and 13 to each other with the connecting member 14, a vertically long rectangular shape ( It is assembled in a square shape). The upper frame plate 10 and the lower frame plate 11 in the outer frame 2 are made of solid wood (for example, wood, plywood, etc.) having a predetermined thickness. An upper support metal fitting 20, which will be described later, is attached to the upper surface and the front surface of the left end portion of the upper frame plate 10.

On the other hand, the side frame plates 12 and 13 are made of lightweight metal mold materials (for example, aluminum alloy) having a constant cross-sectional shape. A plurality of grooves extending in the vertical direction are formed on the outer side surface and the inner side surface of the side frame plates 12 and 13, and work is performed when installing the pachinko game machine 1 in the pachinko island facility of the game hall. The pachinko gaming machine 1 can be easily held by a person's finger, and the design of the appearance can be enhanced.

The outer frame 2 is arranged so as to face the upper support metal fitting 20 fixed to the upper surface of the left end of the upper frame plate 10 and the upper support metal fitting 20, and is fixed to a predetermined position inside the lower part of the left side frame plate 12. A support metal fitting 21, a reinforcing metal fitting 22 arranged to support the lower surface of the lower support metal fitting 21 and fixed so as to connect the left and right side frame plates 12, 13 and a decorative cover fixed to the front surface of the reinforcing metal fitting 22. 23 and. The upper support metal fitting 20 and the lower support metal fitting 21 are for pivotally supporting the main body frame 3 and the door frame 5 so as to be openable and closable. The shaft support pin 633 (see FIG. 5) of the upper shaft support metal fitting 630 in the main body frame 3 described later is detachably engaged with the support hook hole 20c in the upper support metal fitting 20. The main body frame shaft support formed on the main body frame shaft support metal fitting 644 of the main body frame 3 described later is inserted into the support protrusion 21d of the lower support metal fitting 21, and the support protrusion 21d of the lower support metal fitting 21 is inserted. After inserting into the support hole of the main body frame shaft support metal fitting 644 in the main body frame 3, the main body frame 3 can be easily locked by locking the shaft support pin 633 of the upper shaft support metal fitting 630 of the main body frame 3 to the support hook hole 20c. It can be opened and closed freely.

Further, the outer frame 2 is attached and fixed to the inside of the right side frame plate 13 with two closing plates 24, 25 (see FIG. 1) arranged vertically separated by a predetermined distance. These closing plates 24 and 25 are formed in a substantially L shape in a plan view. The closing plates 24 and 25 are hook portions 1054, 1065 (FIG. 1) of the locking device 1000 (locking device) attached along the open side of the main body frame 3 when the main body frame 3 is closed with respect to the outer frame 2. The hook portion 1054, 1065 and the closing plates 24, 25 are connected by inserting the key into the cylinder lock 1010 of the locking device 1000 and rotating it in one direction, which will be described in detail later. The engagement can be disengaged and the closed state of the main body frame 3 with respect to the outer frame 2 can be released.

[3. Overall configuration of the main body frame]
Next, the main body frame 3 provided on the front surface side of the outer frame 2 so as to be openable and closable will be described with reference to FIGS. 5 and 6. FIG. 5 is a front perspective view of the main body frame, and FIG. 6 is a rear perspective view of the substrate unit in the main body frame. As shown in FIG. 5, the main body frame 3 has a main body frame base 600 having a rectangular game board holding port 601 for forming the skeleton of the main body frame 3 and penetrating in the front-rear direction to hold the game board 4. The upper shaft support bracket 630 and the lower shaft support bracket 640, which are attached to the upper and lower ends of the left end portion of the main body frame base 600 in front view and are pivotally supported by the outer frame 2 and the door frame 5 are pivotally supported, A ball launching device 650 attached to the lower front surface of the main body frame base 600 to drive a game ball into the game area 1100 of the game board 4, and a game to the upper plate 301 of the plate unit 300 attached to the rear side of the main body frame base 600. A prize ball unit 700 for paying out balls and a game ball from the prize ball unit 700 to the plate unit 300 of the door frame 5 when the door frame 5 is opened with respect to the main body frame 3 attached to the front surface of the main body frame base 600. It is provided with a ball outlet opening / closing unit 790 that blocks the flow of the door.

Further, the main body frame 3 is attached to the lower rear surface of the main body frame base 600, and various control boards, power supply boards 851, etc. for controlling the door frame 5 excluding the game board 4 and the electrical parts provided in the main body frame 3 and the like. The board unit 800 that is unitized as a unit, the back cover 900 that covers the rear opening of the game board holding port 601 in the main body frame base 600, and the side security plate 950 that covers the left end of the main body frame base 600 in front view. A locking device 1000 attached to the right end of the main body frame base in front view to open / close the main body frame 3 to the outer frame 2 and to open / close the door frame 5 to the main body frame 3 is mainly provided.

[3-1. Body frame base]
Next, the main body frame base 600 will be described. The main body frame base 600 is integrally molded with synthetic resin, and the outer shape of the front view is a vertically long rectangular shape along the outer shape of the door frame 5, and is formed so as to have a predetermined amount of depth in the front-rear direction. Has been done. The main body frame base 600 has a game board holding port 601 capable of fitting and holding the outer periphery of the game board 4 through a rectangular shape in the front-rear direction within a range of about 3/4 of the whole from the upper part to the lower part, and the main body frame. The U-shaped front end frame portion 602 forming the outer periphery of the front end excluding the left side of the base 600 in front view, and the front end frame portion 602 are recessed from the front to the rear, and the door frame 5 is recessed from the lower end to the rear. The protruding door frame projecting piece 110c (see FIG. 1), the upper bent projecting piece 167 (see FIG. 1) projecting rearward from the upper reinforcing sheet metal 151 in the reinforcing unit 150 of the door frame 5, and the open side reinforcing sheet metal 153. It includes an engaging groove 603 into which an open-side outer bent projectile 164 (see FIG. 1) projecting rearward is inserted and engaged.

Further, the main body frame base 600 extends from the lower side of the game board holding port 601 to the lower end of the main body frame base 600, and is recessed from the front end of the front end frame portion 602 to the rear side by a predetermined amount and spreads in a plate shape in the left-right direction. 604 and a peripheral wall portion 605 that protrudes rearward from the front end frame portion 602 and forms an inner peripheral wall of the game board holding port 601 are provided. The peripheral wall portion 605 connects the free ends of the U-shaped front end frame portion 602 (upper and lower left end portions when viewed from the front) so that the outer shape of the main body frame base 600 becomes a frame shape. It has become.

Further, the main body frame base 600 is formed by forming the lower side of the game board holding port 601 at the upper end of the lower rear wall portion 604 and mounting the game board 4 on the game board mounting portion 606 and the game board mounting portion 606. A positioning protrusion 607 that protrudes upward from approximately the center in the left-right direction and engages with the out-ball discharge groove of the game panel 1150 in the game board 4, and a game board stop of the game board 4 formed at a predetermined position on the inner wall on the right side of the front view of the peripheral wall portion 605. A game board locking portion to which the tool 1120 is fastened, and a plate-shaped upper end regulating rib 609 that hangs downward from the upper inner wall of the peripheral wall portion 605 and has a lower end that can contact the upper end of the game board 4 in the left-right direction. And have. By fitting the positioning protrusion 607 of the main body frame base 600 with the out ball discharge groove of the game board 4, it is possible to regulate the lower end of the game board 4 from moving in the left-right direction and the rear direction. There is. Further, the game board locking portion can regulate the movement of the right side of the game board 4 in the front-rear direction by locking the game board stopper 1120 of the game board 4. .. Although the details of the left side of the game board 4 in the front view will be described later, the movement in the front-rear direction is restricted by the positioning member 956 of the side security plate 950.

Further, the main body frame base 600 is formed at a position where the lower rear wall portion 604 is recessed one step toward the rear side from the front surface of the front end frame portion 602, and the ball striking device is formed on the right front surface of the lower rear wall portion 604 in front view. The ball launching device 650 is attached from the front side so that the launching solenoid 654 of the 650 is accommodated in the solenoid accommodating recess. When the ball launching device 650 is attached to the front surface of the lower rear wall portion 604, a foul space 626 extending to the left and downward is formed on the left side of the front view of the upper end of the launch rail 660 in the ball launching device 650. It has become like. In the present embodiment, when the door frame 5 is closed with respect to the main body frame 3, the foul ball entrance 542e (see FIG. 1) in the foul cover unit 540 is located at the lower part of the foul space 626. The game ball descending from the foul space 626 is received by the foul ball inlet 542e of the foul cover unit 540 and discharged to the lower plate 302 (see FIG. 7) of the plate unit 300.

Further, the main body frame base 600 is formed with a plurality of openings that penetrate in a rectangular shape in the front-rear direction to the left of the left-right center of the lower rear wall portion 604 in the front view, and a plurality of openings on the upper side of the openings and on the left and right sides in the front-rear direction. It is provided with a through hole 615 penetrating through. The opening of the main body frame base 600 is closed by the relay terminal board cover 692 from the front side, and the board unit is attached to the rear surface of the lower rear wall portion 604 through the opening 692a of the relay terminal board cover 692. The main door relay terminal board 880 of 800 and the peripheral door relay terminal board 882 face the front side.

Further, the main body frame base 600 detects the opening of the door frame 5 with respect to the main body frame 3 on the lower front surface of the substantially circular cylinder lock through hole 611 penetrating in the front-rear direction through the upper right end of the lower rear wall portion 604 in front view. A door frame opening switch 618 is attached to the door frame, and when the door frame 5 is opened (opened) with respect to the main body frame 3, the pressure is released and the opening of the door frame 5 can be detected. It has become like. Further, the main body frame base 600 is provided with a main body frame opening switch 619 for detecting the opening of the main body frame 3 with respect to the outer frame 2 on the rear surface below the position where the door frame opening switch 618 is attached. When the main body frame 3 is opened (opened) with respect to the outer frame 2, the pressing is released so that the opening of the main body frame 3 can be detected.

[3-2. Upper shaft support and lower shaft support]
Next, the upper shaft support metal fitting 630 and the lower shaft support metal fitting 640 will be described. The upper shaft support bracket 630 and the lower shaft support bracket 640 are attached to the metal fitting mounting portions on the upper and lower rear surfaces of the left end of the main body frame base 600 by using predetermined screws, so that the door frame 5 can be attached to the main body frame 3. The main body frame 3 can be pivotally supported with respect to the outer frame 2 while being able to be pivotally supported so as to be openable and closable.

The upper shaft support bracket 630 has a plate-shaped mounting portion 631 that is attached to the upper bracket mounting portion of the main body frame base 600 and extends in the vertical and horizontal directions, and a plate-shaped forward extending that extends forward from the upper end of the mounting portion 631. The shaft pin 632, the shaft support pin 633 projecting upward from the vicinity of the front end of the front extension portion 632, and the shaft pin 155 of the door frame 5 arranged on the left side of the front view of the shaft support pin 633 (FIG. 7). The door frame shaft support hole 634 that penetrates in the vertical direction into which the door frame 5 is inserted, and the front extension portion 632 that hangs downward from the left end portion in the front view to regulate the rotation end of the door frame 5 toward the open side. It is equipped with a stopper. The upper shaft support metal fitting 630 is integrally formed with a mounting portion 631, a front extending portion 632, and a stopper by bending and molding a single metal plate.

The lower shaft support bracket 640 is arranged below the door frame shaft support bracket 642 for pivotally supporting the door frame 5 and the door frame shaft support bracket 642 to pivotally support the main body frame 3 with respect to the outer frame 2. Main body frame shaft support bracket 644 and. The door frame shaft support bracket 642 in the lower shaft support bracket 640 has a plate-shaped mounting portion that is attached to the lower bracket mounting portion of the main body frame base 600 and extends in the vertical and horizontal directions, and extends forward from the lower end of the mounting portion. A plate-shaped front extension portion 642b, a door frame shaft support hole 642c through which a shaft pin 157 (see FIG. 7) of the door frame 5 is inserted in the vicinity of the front end of the front extension portion 642b in the vertical direction, and a front The extension portion 642b is provided with a stopper 642d which is erected upward from the left end portion in the front view and regulates the rotation end of the door frame 5 toward the open side. The door frame shaft support bracket 642 has a mounting portion, a forward extending portion 642b, and a stopper 642d integrally formed by bending and molding a single metal plate.

Further, the main body frame shaft support metal fitting 644 in the lower shaft support metal fitting 640 has a plate-shaped mounting portion that is attached to the metal fitting mounting portion on the lower side of the main body frame base 600 and extends in the vertical and horizontal directions, and extends forward from the lower end of the mounting portion. It is provided with a front extending portion 644b to be extended and a main body frame shaft support hole penetrating in the vertical direction near the front end of the front extending portion 644b. The main body frame shaft support bracket 644 also has a mounting portion and a front extending portion 644b integrally formed by bending and molding a single metal plate.

The lower shaft support bracket 640 is in a state in which the mounting portion of the door frame shaft support bracket 642 and the mounting portion of the main body frame shaft support bracket 644 are overlapped (contacted) in the front-rear direction, and the door frame shaft support bracket 642 The front extension portion 642b and the front extension portion 644b of the main body frame shaft support metal fitting 644 are separated from each other by a predetermined distance in the vertical direction, and are attached to the lower metal fitting attachment portion of the main body frame base 600.

When the upper shaft support metal fitting 630 and the lower shaft support metal fitting 640 are attached to the main body frame base 600, the shaft support pin 633 of the upper shaft support metal fitting 630 and the main body frame shaft support hole of the lower shaft support metal fitting 640 are coaxially above each other. The main body frame shaft support hole of the main body frame shaft support metal fitting 644 in the lower shaft support metal fitting 640 fits into the support protrusion 21d (see FIG. 4) of the lower support metal fitting 21 in the outer frame 2. The front extension portion 644b of the main body frame shaft support bracket 644 is placed on the support protrusion 21c (see FIG. 4) of the lower support bracket 21 so as to be inserted, and then the shaft of the upper shaft support bracket 630 is inserted. By inserting the support pin 633 into the support hook hole 20c (see FIG. 4) of the upper support metal fitting 20 in the outer frame 2, the main body frame 3 can be pivotally supported with respect to the outer frame 2 so as to be openable and closable. It has become like.

Further, the upper shaft support metal fitting 630 and the lower shaft support metal fitting 640 are attached to the main body frame base 600, and the door frame shaft support hole 634 of the upper shaft support metal fitting 630 and the door frame shaft support hole of the lower shaft support metal fitting 640 are attached. The door frame is positioned coaxially with 642c, and the door frame is inserted so that the shaft pin 157 of the door frame 5 is inserted into the door frame shaft support hole 642c of the door frame shaft support metal fitting 642 in the lower shaft support metal fitting 640. After placing the lower shaft support portion 158 of 5 (see FIG. 7) on the front extension portion 642b of the door frame shaft support bracket 642, the shaft pin 155 of the door frame 5 is placed on the door frame of the upper shaft support bracket 630. By inserting it into the shaft support hole 634, the door frame 5 can be pivotally supported with respect to the main body frame 3. In the present embodiment, the upper shaft pin 155 of the door frame 5 is slidable in the vertical direction, and the shaft pin 155 is inserted into the door frame shaft support hole 634 of the upper shaft support bracket 630. Is once slid downward so that the upper shaft support portion 156 of the door frame 5 and the front extension portion 632 of the upper shaft support metal fitting 630 overlap each other, and then the shaft pin 155 is slid upward. It can be inserted into the door frame shaft support hole 634.

[3-3. Hitting ball launcher]
Next, the hitting ball launching device 650 will be described. The ball striking launcher 650 is attached to the launch base 652 of a metal plate attached to the front predetermined position of the lower rear wall portion 604 of the main body frame base 600 so that the rotation drive shaft 654a projects forward on the lower rear surface of the launch base 652. The launching solenoid 654, the hammer 656 fixed integrally with the rotation drive shaft 654a of the launching solenoid 654, the mallet 658 fixed to the tip of the hammer 656, and the predetermined position on the movement trajectory of the mallet 658. The hammer tip 658 at the tip of the ball hammer 656 passes between the launch rail 660 attached to the front of the launch base 652 and the launch rail 660 above the base end of the launch rail 660. At the same time as being possible, a ball stop piece 662 that forms a gap through which the game ball cannot pass and holds the game ball at the base end of the launch rail 660, and a game held at the base end of the launch rail 660 by the ball stop piece 662. It is provided with a stopper 664 that restricts the hammer 656 (hammer tip 658) from rotating toward the launch rail 660 side from the hitting position where the ball can be hit.

Although detailed illustration is omitted, the firing solenoid 654 in the hitting ball launching device 650 is configured such that the rotation drive shaft 654a reciprocates with a strength (speed) according to the rotation operation angle of the handle device 500. .. Further, the hitting mallet 656 of the hitting ball launching device 650 has a fixed portion 656a fixed to the rotary drive shaft 654a of the launch solenoid 654 and a tip extending from the fixed portion 656a in a gentle arc shape to the axial center of the rotary drive shaft 654a. On the other hand, there are a rod portion 656b in which the mallet tip 658 is fixed to the tip facing the normal direction, and a stopper portion 656c that can come into contact with the stopper 664 extending to the opposite side with the fixing portion 656a sandwiched between the rod portion 656b. It has. When the stopper portion 656c of the hitting mallet 656 comes into contact with the stopper 664, the mallet tip 658 at the tip rotates toward the launch rail 660 from the hitting position (rotating end in the counterclockwise direction when viewed from the front). It is becoming regulated.

When the ball striking device 650 is attached to the lower rear wall portion 604 of the main body frame base 600, the upper end of the launch rail 660 is substantially in the center in the left-right direction and the upper end of the lower rear wall portion 604, that is, the game board mounting portion. It is located below 606 (the lower side of the game board holding port 601), and has a predetermined width in the left-right direction with the lower end of the outer rail 1111 in the game board 4 held by the game board holding port 601. A foul space 626 that extends downward is formed at. Then, the ball striking device 650 launches the game ball so as to jump over the foul space 626 on the left side of the launch rail 660 so that the game ball can be driven into the game area 1100 of the game board 4. It has become. In the state where the door frame 5 is closed with respect to the main body frame 3, the foul ball entrance 542e of the foul cover unit 540 attached to the door frame 5 is located at the lower part of the foul space 626, and the game is played. A game ball that has become a foul ball without being driven into the area 1100 falls in the foul space 626, is received by the foul ball entrance 542e, and is discharged to the lower plate 302.

[3-4. Prize ball unit]
Next, the prize ball unit 700 will be described. In the pachinko island facility in the hall where the pachinko game machine 1 is installed, after storing the game balls supplied from the pachinko island facility side to the pachinko game machine 1, the upper plate 301 of the pachinko game machine 1 is stored based on a predetermined payout instruction. It is to be paid out to. The prize ball unit 700 receives and stores the prize ball base 710 attached to the rear surface of the main body frame base 600 and the game balls attached to the upper part of the rear surface of the prize ball base 710 and supplied from the pachinko island equipment side. The 720, the tank rail unit 730 arranged under the prize ball tank 720 and storing the game balls stored in the prize ball tank 720 and sent to the downstream side, and the game balls aligned by the tank rail unit 730 are predetermined. The prize ball device 740 to be paid out based on the payout instruction and the game ball paid out by the prize ball device 740 can be guided to the upper plate 301 of the plate unit, and the upper plate 301 is paid out when the game ball is full. It mainly includes a full tank branch unit 770 capable of branching and guiding the game ball to the lower plate 302 side.

Further, the prize ball unit 700 includes an external terminal board 784 attached to the rear surface of the prize ball base 710, and an external terminal board cover 786 that covers the rear side of the external terminal board 784.

[3-4-1. Prize ball tank]
In the prize ball tank 720, the outer circumference of the bottom wall portion 721 is surrounded by the outer peripheral wall portion 722, and a predetermined amount of game balls can be stored on the bottom wall portion 721. Further, the prize ball tank 720 is inclined so that the upper surface of the bottom wall portion 721 is lowered toward the discharge port 723, so that the game ball on the bottom wall portion 721 rolls toward the discharge port 723. It has become.

Further, the prize ball tank 720 includes two ball leveling members 727 that are rotatably supported by the shaft portion 725. One end side of the ball leveling member 727 is pivotally supported by the shaft portion 725 and holds a weight inside, so that the other end side hangs down due to its own weight. The ball leveling member 727 hangs down in the tank rail unit 730, which will be described later, and allows the game balls circulating in the tank rail unit 730 to be leveled and aligned.

[3-4-2. Tank rail unit]
The tank rail unit 730 includes a tank rail 731 that is arranged below the prize ball tank 720 and extends long in the left-right direction. The tank rail 731 has a gutter shape with an open upper part and a predetermined depth, and has a width (depth) that allows game balls to be aligned in two rows in the front-rear direction. The bottom is tilted so that

Further, the tank rail unit 730 is continuously connected to the alignment gear 732 rotatably supported above the discharge port of the tank rail 731, the gear cover 733 covering the upper portion of the alignment gear 732, and the right end of the gear cover 733 in the front view. A ball holding plate 734 that closes the upper part of the rail 731, and a ball stop piece 735 that can advance and retreat into the tank rail 731 and stop the game ball in the tank rail 731 from rolling toward the discharge port side. , Is equipped. Two alignment gears 732 are provided side by side in the front-rear direction so as to correspond to the two flow paths of the game balls partitioned in two rows by the partition wall of the tank rail 731.

[3-4-3. Prize ball device]
The prize ball device 740 is for paying out the game balls discharged and supplied from the discharge port of the tank rail unit 730 to the upper plate 301 of the plate unit 300 based on a predetermined payout instruction. The prize ball device 740 has a supply passage that opens at the upper end and extends to a position slightly lower than the center in the vertical direction with a width slightly wider than the outer shape of the game ball, and a predetermined width that communicates with the lower end of the supply passage. The distribution space with space, the prize ball passage that communicates with the lower end of the left side (open side) of the distribution space and opens in the left side of the back view, and the right side of the back view of the distribution space. (Shaft support side) It is equipped with a ball-drawing passage that communicates with the lower end and extends downward to open at the lower end. The supply passage, the distribution space, the prize ball passage, and the ball removal passage are formed in a state of being open to the rear.

The prize ball device 740 is integrally rotatably fixed to the rotating shaft of the payout motor 744 and is arranged on the rear side of the motor support plate. The first gear, the second gear that meshes with the first gear, and the second gear mesh with each other. The third gear, the payout rotating body as a sprocket that rotates integrally with the third gear and is arranged in the distribution space, and the payout rotating body are fixed to the opposite side of the third gear so as to be integrally rotatable around the circumference. A rotation detection board in which a plurality of detection slits (three in the present embodiment) are formed at equal intervals in the direction, and a ball-out switch 750 for detecting the presence or absence of a game ball in the supply passage. A counting switch 751 for detecting a game ball flowing down in the prize ball passage, a rotation angle switch 752 for detecting a detection slit formed in a rotation detection board that rotates integrally with the payout rotating body, and a rotation angle switch 752. Includes a rotation angle switch board 753 for holding the rotation angle switch board 753, a payout motor 744, a ball out switch 750, a counting switch 751, and a prize ball case inner board 754 that relays the connection between the rotation angle switch 752 and the payout control board described later. ing.

The payout rotating body as a sprocket is provided with three recesses having a size capable of accommodating one game ball at equal intervals in the circumferential direction, and the game supplied from the supply passage by rotating the payout rotating body. The balls are housed one by one in the recess and can be paid out to the prize ball passage or the ball removal passage side. Further, the three detection slits formed in the rotation detection board that rotates integrally with the payout rotating body are formed in equal parts (every 120 degrees) on the outer circumference of the rotation detection board, and correspond to the recesses of the payout rotating body. Each position is provided, and the rotation position of the payout rotating body can be detected by detecting the detection slit with the rotation angle switch 752. In the present embodiment, the rotation between the detection slits (120 degrees) of the rotation detection board (delivery rotating body) is designed to correspond to the rotation of 18 steps of the payout motor 744.

In the prize ball device 740, when the payout rotating body is rotated in the direction counterclockwise when viewed from the rear by the payout motor 744, the game balls in the supply passage are paid out to the prize ball passage, and the payout rotation is performed. The game balls paid out to the prize ball passage by the rotation of the body are counted one by one by the counting switch 751 and then delivered to the prize ball passage. On the other hand, when the ball removal operation member is operated by a clerk in the hall or the like, the game balls in the supply passage are discharged to the ball removal passage, and the game balls discharged to the ball removal passage are discharged to the ball removal passage. It can be discharged from the lower end of the passage to the outside of the rear side of the pachinko gaming machine 1 via the full tank branch unit 770 described later.

[3-4-4. Full tank branch unit]
The full tank branch unit 770 is formed in a box shape so that the whole becomes lower from the rear end to the front end, and opens upward at substantially the center in the left-right direction at the upper part of the rear end to win the prize ball device 740. The prize ball receiving port that receives the game ball that has flowed down the ball passage, the branch space that is placed under the prize ball receiving port and spreads in the left-right direction, and the game from directly below the prize ball receiving port in the branch space to the front side. The normal passage that guides the ball, the normal ball outlet 774 that discharges the game ball that has passed through the normal passage forward and opens at the right end of the front view, and the normal ball outlet 774 that opens at the right end of the front end, and the distance from directly below the prize ball receiving port in the branch space to the right side of the rear view. It is equipped with a full tank passage that guides the game ball from the vertical position toward the front side, and a full tank outlet 776 that discharges the game ball that has passed through the full tank passage to the front and opens to the left side of the front view of the normal ball outlet 774. ing.

Further, the full tank branch unit 770 has a ball ejection port that opens upward to the left end of the front end of the upper part of the rear end and receives a game ball that has flowed down the ball ejection passage of the prize ball device 740, and a ball ejection / receiving port. A ball pulling passage that guides the game ball received in the mouth to the front side, and a game ball that has passed through the ball pulling passage are released forward and at the left end of the front view, at a position behind the normal ball exit 774 and the full tank exit 776. It is equipped with an open ball outlet.

In the full tank branch unit 770, assuming that the door frame 5 is closed with respect to the main body frame 3, the normal ball outlet 774 and the full tank outlet 776 are the first ball inlets 542a of the foul cover unit 540 in the door frame 5, respectively. And the second ball inlet 542c (see FIG. 1) are opposed to each other, and the game ball released from the normal ball outlet 774 passes through the first ball entrance 542a of the foul cover unit 540 and serves as a plate. The game ball supplied to the upper plate 301 of the unit 300 and released from the full tank outlet 776 is supplied to the lower plate 302 of the plate unit 300 through the second ball inlet 542c of the foul cover unit 540. ing. Further, the ball outlet is formed so as to communicate with the upper right end of the rear view of the main body frame base ball extraction passage in the main body frame base 600, and the game ball released from the ball extraction outlet is formed in the main body frame of the main body frame base 600. It is designed to be handed over to the base ball removal passage.

When the upper plate 301 of the plate unit 300 is full of game balls and the game balls are further discharged from the prize ball unit 700 (prize ball device 740), the foul cover unit 540 is moved up from the first ball outlet. The game ball that cannot go out to the plate 301 side stagnates in the first ball passage of the foul cover unit 540, and eventually fills the upstream normal passage through the normal ball outlet 774 in the full tank branch unit 770. In this state, the game ball that has entered the branch space from the prize ball socket cannot normally enter the passage, starts to move laterally in the branch space, and the game ball that has moved laterally is full. It enters the tongue passage and is supplied from the full tank outlet to the lower plate 302 of the plate unit 300 via the second ball entrance 542c of the foul cover unit 540, the second ball passage, and the second ball outlet. It has become.

[3-5. Board unit]
Next, the substrate unit 800 will be described. As shown in FIG. 6, the board unit 800 includes a board unit base 810 attached to the rear surface of the lower rear wall portion of the main body frame base 600, a speaker box 820 attached to the left rear surface of the board unit base 810 in front view, and a substrate. The power supply board box holder 840 attached to the rear surface of the unit base 810 and the power supply board box attached to the rear surface of the power supply board box holder 840 and having a rear end substantially flush with the rear end of the speaker box 820. The 850, the payout control board box 860 attached to the rear surfaces of the power supply board box 850 and the speaker box 820, and the terminal board box 870 attached to the rear surface of the speaker box 820 so as to cover the left end of the payout control board box 860 in the front view. A main door relay terminal plate 880 and a peripheral door relay terminal plate 882 attached to the front surface of the board unit base 810 are provided.

The power supply board box holder 840 has a discharge ball receiving portion 841 that is opened upward and receives the game balls discharged downward from the out ball discharge portion of the game board 4 on the left front side of the left and right centers when viewed from the front. The discharge passage 842 that guides and discharges the game ball received by the discharge ball receiving portion 841 downward, and the discharge passage 842 and the discharge ball receiving portion 841 are opened forward and upward in front of the side (right side in front view). It is provided with a box accommodating portion that is formed so that the entire rear surface of the power supply board box holder 840 is recessed toward the front side and can accommodate the front end of the power supply board box 850.

Further, in the power supply board box holder 840, the open front end side of the discharge passage 842 is closed by the rear surface of the board unit base 810, and the opening of the board unit base 810 faces the discharge passage 842. It is formed and flows down through the opening of the board unit base 810 to the rear side of the board unit base 810 through the body frame base ball pulling passage formed on the rear surface of the lower rear wall portion of the body frame base 600. The game ball and the game ball discharged from the out ball discharging part of the game board 4 and received by the discharging ball receiving part 841 can be discharged downward to the rear side of the pachinko gaming machine 1 through the discharging passage 842. It has become.

The power supply board box 850 is formed in a horizontally long box shape with an open front, and includes a power supply board 851 attached so as to close the front end opening thereof. The power supply board box 850 accommodates various electronic components attached to the power supply board 851, and externally receives heat from the electronic components and the like through a plurality of slits 850a formed on the upper surface and the lower surface. It can be released to. The power switch 852 attached to the power supply board 851 faces the rear surface of the power supply board box 850.

The payout control board box 860 is a horizontally long thin box-shaped box base 861 with an open rear, a thin box-shaped cover 862 fitted into the box base 861 from the rear side and an open front, and a box base 861. It includes a payout control board 4110 which is attached to the rear surface and whose rear surface is covered by the cover 862. Further, the payout control board box 860 includes a plurality of separated cutting portions 863 formed on both the box base 861 and the cover 862 protruding outward from the left end of the rear view, and at one location of the plurality of separated cutting portions 863. The box base 861 and the cover 862 are caulked and fixed. As a result, in order to separate the box base 861 and the cover 862, it is not possible to separate the box base 861 and the cover 862 without cutting the separation cutting portion 863, and when the payout control board box 860 is opened, the trace remains. .. Therefore, it is possible to know whether or not the payout control board box 860 has been opened or closed illegally. In this embodiment, the payout control board box 860 can be opened and closed only once for inspection and the like.

Further, in the payout control board box 860, the operation switch 860a (error canceling unit) attached to the payout control board 4110, the inspection output terminal 860c, and the like face rearward through the cover 862. Further, in the payout control board box 860, terminals for various connections for connecting to the main control board 4100 and the like face rearward through the cover 862. The operation switch 860a is operated when the RAM built in the microprocessor of the payout control board 4110 and the RAM built in the microprocessor of the main control board 4100 are cleared when the power is turned on, or after the power is turned on. When an error is notified, it is operated to clear the error, and the function to clear the RAM at the time of turning on the power and the period to play the function as clearing the RAM have passed after the power was turned on. It has a function to cancel the error in (later). A detailed description of this point will be described later.

The terminal board box 870 includes a board base 871 attached to the rear surface of the speaker box 820, a frame peripheral relay terminal board 868 attached to the rear surface of the board base 871 and fixed to the peripheral panel relay terminal 872 toward the rear, and a board base. A board so that the game ball rental device connection terminal plate 869, which is attached to the rear surface of 871 and the CR unit relay terminal 873 is fixed to the rear, and the peripheral panel relay terminal 872 and the CR unit relay terminal 873 face the rear side. It includes a substrate cover 874 that covers the rear side of the base 871. The peripheral panel relay terminal 872 is for connecting to a frequency display for displaying the operating status of the pachinko gaming machine 1 provided on the pachinko island facility side where the pachinko gaming machine 1 is installed, and is for connecting to a CR unit relay. Terminal 873 is for connecting to a CR unit installed adjacent to the pachinko gaming machine 1.

The main door relay terminal plate 880 and the peripheral door relay terminal plate 882 are provided on the door frame 5 together with the peripheral control board 4140 provided on the game board 4 attached to the main body frame 3, the payout control board 4110 of the board unit 800, and the like. This is for relaying the connection with the handle device 500, each decorative board, the operation unit 400, and the like. The main door relay terminal board 880 and the peripheral door relay terminal board 882 are attached to the board mounting portion formed on the front surface of the board unit base 810 so that they face from the front side to the front side of the main body frame base 600. The wiring extending from the door frame 5 can be connected.

The front side of the main door relay terminal board 880 and the peripheral door relay terminal board 882 is covered by the relay terminal board cover 692 attached to the front surface of the main body frame base 600, and the relay terminal board cover 692 Only the connection terminals face the front side through the opening 692a, so that the front surface of the main body frame 3 has a neat appearance.

Further, the main door relay terminal plate 880 includes a ball rental button 361, a return button 362, a loan balance display unit 363, a potentiometer 512 of the handle device 500, and a touch of the ball rental unit 360 in the dish unit 300 arranged on the door frame 5 side. This is for relaying the connection between the full switch 550 of the switch 516, the launch stop switch 518, and the foul cover unit 540, and the payout control board 4110 arranged on the main body frame 3 side. Regarding the ball rental button 361 of the ball rental unit 360, the return button 362, the loan balance display unit 363, the potentiometer 512 of the handle device 500, the touch switch 516, the launch stop switch 518, and the full tank switch 550 of the foul cover unit 540. The description will be described later.

Further, the peripheral door relay terminal plate 882 is provided in each of the decorative units 200, 240, 280 arranged on the door frame 5 side, each of the decorative boards provided in the dish unit 300 and the operation unit 400, and the operation unit 400. , To relay the connection between various switches that detect the operations of the dial drive motor 414, the dial operation unit 401, and the pressing operation unit 405, and the peripheral control board 4140 of the game board 4 arranged on the main body frame 3 side. Is. The decorative units 200, 240, 280 arranged on the door frame 5 side, the decorative boards provided on the dish unit 300 and the operation unit 400, and the dial drive motor 414 and dial operation provided on the operation unit 400. A description of various switches for detecting the operation of the unit 401 and the pressing operation unit 405 will be described later.

[4. Overall configuration of door frame]
Next, the door frame 5 provided on the front side of the main body frame 3 so as to be openable and closable will be described with reference to FIG. 7. FIG. 7 is a perspective view of the door frame. As shown in FIG. 7, the door frame 5 includes a door frame base unit 100 having a game window 101 having an outer shape formed into a vertically long rectangular shape and an inner peripheral shape having a slightly vertically long circular shape (elliptical shape), and a door. The right side decoration unit 200 attached to the right outer circumference of the game window 101 on the front surface of the frame base unit 100, and the left side attached to the left outer circumference of the game window 101 on the front surface of the door frame base unit 100 facing the right side decoration unit 200. The decoration unit 240, the upper decoration unit 280 attached to the upper outer periphery of the game window 101 in front of the door frame base unit 100, and the door frame base unit arranged below the lower ends of the right side decoration unit 200 and the left side decoration unit 240. It includes a pair of side speaker covers 290 that are attached to the front of the 100.

Further, the door frame 5 is attached to the front of the door frame base unit 100, the plate unit 300 attached to the lower part of the game window 101, the operation unit 400 attached to the upper center of the plate unit 300, and the right side of the plate unit 300. The upper plate side liquid crystal display device 470 and the capacitance type having a contact surface which is provided so as to cover the display area of the upper plate side liquid crystal display device 470 (second display device) and has a contact surface capable of detecting a contact state. The door frame base unit 100 is sandwiched between the handle device 500, which is attached to the lower right corner of the door frame base unit 100 through the touch panel 480 (contact type input device) and the dish unit 300, and for driving the game ball. The foul cover unit 540, which is arranged on the rear side of the dish unit 300 and attached to the rear surface of the door frame base unit 100, the ball feed unit 580, which is attached to the rear surface of the door frame base unit 100 on the right side of the foul cover unit 540, and the door. A glass unit 590 attached to the rear side of the frame base unit 100 so as to close the game window 101 is provided. The touch panel 480 is a type of 4.3 inches and a resolution of 10 × 20 in this embodiment. The touch panel drive board 450 that detects and controls the contact state of the touch panel 480 is arranged near the lower side of the upper plate side liquid crystal display device 470 and is housed in the plate unit 300.

[4-1. Door frame base unit]
Next, the door frame base unit 100 will be described. The door frame base unit 100 has a door frame base body 110 having a game window 101 having an outer shape formed in a vertically long rectangular shape and a game window 101 having a substantially elliptical shape with an inner circumference penetrating in the front-rear direction and a door frame. An upper bracket 120 attached to the center of the upper part of the game window 101 on the front surface of the base body 110 to fix the upper decorative unit, and a pair of sides attached to the lower left and right sides of the game window 101 on the front surface of the door frame base body 110. It includes a speaker 130 and a handle bracket attached to the lower right corner of the front view on the front surface of the door frame base main body 110 to support the handle device 500.

Further, the door frame base unit 100 is a metal frame-shaped reinforcing unit 150 (see FIG. 1) fixed to the rear side of the door frame base main body 110, and a game window 101 on the rear surface of the door frame base main body 110. A security cover 180 (see FIG. 1) that is attached so as to cover the lower portion, and a glass unit locking member 190 that is rotatably attached to a predetermined position on the outer periphery of the game window 101 on the rear surface of the door frame base body 110 (FIG. 1). 1) and the launch cover 191 (see FIG. 1) which is arranged on the left side (open side) from the center in the left-right direction in the rear view and is attached to the rear surface of the door frame base main body 110 along the lower end of the game window 101. , A handle relay terminal plate attached to the rear surface of the door frame base main body 110 under the launch cover 191 and relaying the connection between the potentiometer 512 of the handle device 500 described later and the main control board 4100 provided in the game board 4 described later. 192 (see FIG. 1), the handle relay terminal plate cover 193 (see FIG. 1) that covers the rear side of the handle relay terminal plate 192, and the launch cover 191 and the handle relay terminal plate 192 with the center in the left-right direction sandwiched. Frame decoration drive amplifier board 194 (see Fig. 1), which is arranged on the opposite side (rear view, to the right of the center in the left-right direction (shaft support side)) and attached to the rear surface of the door frame base body, and frame decoration drive. It includes a frame-decorated drive amplifier board cover 195 (see FIG. 1) that covers the rear side of the amplifier board 194.

The frame decoration drive amplifier board 194 is electrically connected to the side speakers 130 and the upper speakers of the left and right side decoration units 200 and 240, and is also electrically connected to the peripheral control board 4140 provided in the game board 4 described later. It is provided with an amplifier circuit that amplifies the acoustic signal sent from the peripheral control board 4140 and outputs it to each speaker 130. Although specific illustration is omitted, in the present embodiment, each of the decorative units 200, 240, 280, the dish unit 300, each decorative board provided in the operation unit 400, and the dial drive motor provided in the operation unit 400. The wiring that electrically connects the switch, the handle relay terminal board 192, the ball rental unit 360 of the dish unit 300, the payout control board 4110, the peripheral control board 4140, etc. is the rear view of the frame decoration drive amplifier board 194. After being bundled at the position on the right side (shaft support side), it extends rearward and is connected to the main door relay terminal board 880 and the peripheral door relay terminal board 882 of the main body frame 3.

[4-1-1. Door frame base body]
The door frame base body 110 is formed of a synthetic resin in a vertically long frame shape, and is formed in such a form that the game window 101, which penetrates in the front-rear direction and has a vertically long inner shape and a substantially elliptical shape, is offset upward as a whole. Has been done. In the game window 101, the left and right side and the upper inner peripheral edge are formed in a continuous smooth curved shape, while the lower inner peripheral edge is formed in a straight line extending to the left and right. Further, on the inner peripheral edge of the door frame base body 110 on the lower side of the game window 101, a square notch is formed on the shaft support side (left side in front view) through which the first ball outlet of the foul cover unit 540 can be inserted. The right (open side) end of the front surface, which is arranged on both the left and right outer sides of the lower side of the game window 101 and is arranged in the lower right corner of the front view to attach and fix the side speaker 130. A handle mounting part for mounting the handle bracket, a wiring passage port that penetrates in the front-rear direction at a predetermined position of the handle mounting part and allows wiring from the handle device 500 to pass through, and an upper side of the handle mounting part. A lock hole 116 is formed which is formed in a tubular shape extending shortly toward the front and through which a cylinder lock 1010, which will be described later, can be inserted. The width of the upper side and the left and right side sides of the door frame base body 110 formed by the game window 101 is the upper reinforcing sheet metal 151, the shaft support side reinforcing sheet metal 152, and the open side reinforcing sheet metal 153 of the reinforcing unit 150 described later. The width is substantially the same as the width of the game window 101, and the game window 101 is formed as large as possible with respect to the size of the door frame base body in the front view.

[4-1-2. Reinforcement unit]
The reinforcing unit 150 includes an upper reinforcing sheet metal 151 (see FIG. 1) attached along the back surface of the upper side of the door frame base body 110 and a shaft support attached along the back surface of the shaft support side of the door frame base body 110. The side reinforcing sheet metal 152 (see FIG. 1), the open side reinforcing sheet metal 153 attached along the back surface of the open side of the door frame base body 110 (see FIG. 1), and the game window 101 of the door frame base body 110. It is provided with a lower reinforcing sheet metal 154 (see FIG. 1) that is attached along the lower back surface of the lower side, and they are fastened to each other with screws, rivets, or the like to form a square shape.

At the upper and lower ends of the shaft support side reinforcing sheet metal 152, an upper shaft support 156 having a shaft pin 155 slidably provided on the upper surface thereof in the vertical direction and a lower shaft support 158 having a shaft pin 157 on the lower surface thereof are provided. It is provided integrally. Then, the upper and lower shaft pins 155 and 157 are pivotally supported by the upper shaft support metal fittings 630 and the lower shaft support metal fittings 640 formed above and below the shaft support side of the main body frame 3, so that the door frame 5 is pivotally supported with respect to the main body frame 3. It is designed to be pivotally supported so that it can be opened and closed.

Further, a hook cover 165 that comes into contact with the door frame hook portion 1041 of the lock device 1000 is provided in the lower rear portion of the open side reinforcing sheet metal 153. The hook cover 165 engages with the door frame hook portion 1041 of the lock device 1000 (locking device) attached along the open side of the main body frame 3 when the door frame 5 is closed with respect to the main body frame 3. By inserting the key into the cylinder lock 1010 of the lock device 1000 and rotating it in one direction (rotating the main body frame 3 in the direction opposite to the opening direction with respect to the outer frame 2), the hook portion for the door frame The engagement between the 1041 and the hook cover 165 is disengaged, and the closed state of the door frame 5 with respect to the main body frame 3 can be released.

[4-2. Dish unit]
Next, the dish unit 300 will be described. The plate unit 300 includes an upper plate 301 and a lower plate 302 for storing the game balls paid out from the prize ball device 740, and launches the game balls stored in the upper plate 301 via the ball feeding unit. It can be supplied to the device 650.

The shape of the upper plate upper panel 314 of the plate unit 300 is formed in a curved shape so as to project forward from the left to the center when viewed from the front, and is linearly forward from the center to the right. It is formed so as to protrude. An operation unit mounting portion to which the operation unit 400 is mounted is formed in the upper center of the plate unit 300, and a liquid crystal mounting portion 314d for mounting the upper plate side liquid crystal display device 470 is formed on the right side of the operation unit mounting portion. .. The shape of the upper plate upper panel 314 on which the liquid crystal mounting portion 314d is formed is formed in a plate shape, and when a player presses this portion downward by hand, for example, the upper plate upper panel 314 bends downward. When the pressing force exceeds a predetermined force, the upper plate upper panel 314 is broken. This is because the upper plate side liquid crystal display device 470 is expensive, so when the player presses the screen of the upper plate side liquid crystal display device 470, the force is received by the upper plate upper panel 314. By bending the upper plate upper panel 314, the upper plate side liquid crystal display device 470 is prevented from being damaged. That is, a structure is adopted in which the upper plate upper panel 314 is damaged before the upper plate side liquid crystal display device 470 is damaged. If the upper plate upper panel 314 is damaged, the plate unit 300 will be replaced. In this case, the upper plate side liquid crystal display device 470 is removed from the broken upper plate upper panel 314 and attached to the upper plate upper panel 314 of the plate unit 300 to be replaced for reuse.

Further, the plate unit 300 has an upper plate ball removing mechanism 340 for pulling out the game balls stored in the upper plate 301 to the lower plate 302 in response to the operation of the upper plate ball removing button 341, and a lower plate ball removing button 354. A lower plate ball removing mechanism 350 for pulling out the game ball stored in the lower plate 302 downward through the lower plate ball removing hole 324b in response to the operation of, and a lower plate ball removing mechanism 350 installed adjacent to the pachinko gaming machine 1 (not shown). It includes a ball rental unit 360 that operates the CR unit.

[4-2-1. Operation unit]
The operation unit 400 is arranged in front of the upper plate 301 at substantially the center in the left-right direction of the front view, and has a dial operation unit 401 (operation unit) that can be rotated by the player and a pressing operation unit 405 (operation unit) that the player can press. The operation unit) is provided, and the player's operation can be received according to the game state, and the dial operation unit 401 can be moved, so that the player can not only drive the game ball but also operate the game ball. , It is intended to be able to participate in the production during the game. The rotation (rotation direction) of the dial operation unit 401 is detected by the rotation detection switch provided in the operation unit 400, and the operation of the pressing operation unit 405 is detected by the pressure detection switch provided in the operation unit 400.

Further, the operation unit 400 can rotate the dial operation unit 401 in the clockwise direction or the counterclockwise direction by the driving force of the dial drive motor 414. Further, the operation unit 400 rotates the dial operation unit 401 stepwise by the driving force of the dial drive motor 414 using the stepping motor, or when the player rotates the dial operation unit 401, the operation unit 400 rotates the dial operation unit 401. It is possible to assist the rotation, prevent it from rotating intentionally, and give a click feeling to the rotation. Further, the operation unit 400 can vibrate the dial operation unit 401 by alternately repeating the rotation of rotating the dial drive motor 414 in the forward direction and the rotation in which the dial drive motor 414 is rotated in the reverse direction in small steps.

[4-2-2. Ball rental unit]
The ball lending unit 360 includes a ball lending button 361 and a return button 362 that can be pressed backward, and also includes a lending balance display unit 363 between the ball lending button 361 and the return button 362. When the ball lending button 361 is operated, it is detected by the ball lending switch 365a, and when the return button 362 is operated, it is detected by the return switch 365b. The display content of the residual frequency display 365c can be visually recognized via the loan residual display unit 363. The CR unit lamp 365d is arranged adjacent to the residual power display 365c, and the light emitting mode of the CR unit lamp 365d can be visually recognized via the rental residual display unit 363. The ball rental switch 365a, the return switch 365b, the remaining frequency indicator 365c, and the CR unit lamp 365d are mounted on the frequency display board 365, and the frequency display plate 365 is mounted inside the ball rental unit 360. .. The ball lending unit 360 inserts cash or a prepaid card into the ball lending machine provided adjacent to the pachinko gaming machine 1, and then presses the ball lending button 361 to release a predetermined number of game balls into the dish unit. You can rent (pay out) into the upper plate 301 of 300, and when you press the return button 362, the balance of cash and prepaid card that you put in after subtracting the rest of the lent amount will be returned. ing. In addition, the loan balance display unit 363 displays the remaining number of cash and prepaid cards inserted into the ball lending machine.

[4-3. Ball feed unit]
Next, the ball feeding unit 580 will be described. The ball feeding unit 580 can supply the game balls supplied from the upper plate 301 in the plate unit 300 to the hitting ball launching device 650 one by one, and the game balls stored in the upper plate 301 can be used as the upper plate balls. It can be pulled out to the lower plate 302 by operating the upper plate ball removing button 341 of the pulling mechanism 340.

In the ball feed unit 580, the game balls stored in the upper plate 301 of the plate unit 300 are supplied through the upper plate ball discharge port of the upper plate 301 and the ball feed opening of the door frame base main body 110 and penetrate in the front-rear direction. , And a box-shaped front cover that has a ball outlet that opens under the entrance and is open at the rear, and a box-shaped front that closes the rear end of the front cover and is open at the front, penetrating in the front-rear direction. Rotates around an axis extending in the front-rear direction between the rear cover having a hit ball supply port 582a for supplying the game ball invading from the entry port of the front cover to the hit ball launcher 650, and the rear cover and the front cover. A ball pulling member that is pivotally supported and has a partition portion that separates the entrance and the ball pulling port on the rear side of the front cover, and a game ball on the partition portion of the ball pulling member are hit by the rear cover one by one. A ball feed member rotatably supported around an axis extending in the vertical direction between the front cover and the rear cover to the supply port 582a, and a ball feed solenoid 585 for rotating the ball feed member are provided. There is.

When the ball feeding solenoid 585 is driven (ON state), the ball feeding member accepts one game ball, while when the driving of the ball feeding solenoid 585 is released (OFF state), the ball feeding member accepts it. The game ball is sent (supplied) to the hit ball launching device 650 side.

[4-4. Handle device]
Next, the handle device 500 will be described. The handle device 500 includes a handle base that is fixed to a handle bracket attached to the front surface of the door frame base main body 110 and has a cylindrical shape and a front end that bulges round in the direction perpendicular to the axis, and a handle base that can rotate relative to the handle base. Arranged on the front side of the annular rotary handle body arranged on the front side, the rotary handle body front 506 fixed to the front surface after the rotary handle body and integrally rotatable with the rotary handle body rear, and the front surface of the rotary handle body front 506. It is also provided with a front end cover 508 that is fixed to the handle base and rotatably supports the front 506 of the rotary handle body and the rear of the rotary handle body in cooperation with the handle base.

Further, the handle device 500 is fitted to a shaft member which is attached and fixed to the center of rotation in front of the rotary handle body so as to project from the front side to the rear side and has a non-circular bearing portion at the rear end, and a bearing portion of the shaft member. Detection of the potentiometer 512, which has a detection shaft portion that can be rotated and is non-rotatably fitted to the front surface of the handle base, and the potentiometer 512, which is fixed to the front surface of the handle base so as to sandwich the potentiometer 512 with the handle base. A switch support member having a through hole through which the shaft portion can pass, a touch switch 516 attached to the rear surface of the switch support member, and a launch stop switch 518 attached to a different position on the rear surface of the switch support member from the touch switch 516. , A single-shot button that is rotatably supported by the switch support member to operate the launch stop switch 518, and is arranged so as to cover the outer periphery of the shaft member, and the original rotation position (front) is in front of the rotary handle body 506 and after the rotary handle body. It is equipped with a handle return spring that urges the user to return to the (rotating end in the counterclockwise direction). The potentiometer 512 is for electrically adjusting the strength of launching the game ball toward the game area 1100 according to the rotation position of the rotation handle main body front 506. Further, the front 506 of the rotary handle body and the rear of the rotary handle body rotate from the original rotation position to the limit rotation position (rotation end in the clockwise direction in the front view) which is the maximum rotation position in the clockwise direction in the front view. do.

Further, in the handle device 500, the potentiometer 512 is a variable resistor, and when the front 506 of the rotary handle body and the rear of the rotary handle body are rotated, the detection shaft portion of the potentiometer 512 is rotated via the shaft member. .. Then, the internal resistance of the potentiometer 512 changes according to the rotation position (rotation angle) of the detection shaft portion, and the driving force of the launch solenoid 654 in the ball launching device 650 changes according to the internal resistance of the potentiometer 512. The game ball is driven into the game area 1100 with a firing angle corresponding to the rotation angle in front of the main body 506 and after the main body of the rotary handle, that is, the rotation position in front of the main body of the rotary handle 506 and after the main body of the rotary handle. There is.

[4-5. Foul cover unit]
Next, the foul cover unit 540 will be described. The foul cover unit 540 is attached to the rear surface of the door frame base unit 100 below the game window 101, and is a game despite being fired by the game ball paid out from the prize ball unit 700 or the hit ball launching device 650. A game ball (foul ball) that has not reached the area 1100 is guided to the upper plate 301 or the lower plate 302 of the plate unit 300. The foul cover unit 540 includes a cover base whose front side is open and which has a plurality of game ball flow paths inside, and a front cover that closes the front end of the cover base.

The cover base of the foul cover unit 540 is arranged in the upper right corner in the rear view and penetrates in the front-rear direction. Inside the one-ball passage, the second ball entrance 542c, which is located outside the first ball entrance 542a (on the right side when viewed from the rear) and is larger than the first ball entrance 542a, and inside the cover base that communicates with the second ball passage. The second ball entrance 542c, which extends downward and is inclined so as to be lowered toward the lower right corner of the front view, is provided. The first ball entrance 542a and the second ball entrance 542c are the normal ball outlet 774 and the full tank outlet 77 of the full tank branch unit 770 in the prize ball unit 700 in a state where the door frame 5 is closed with respect to the main body frame 3. It is formed at a position opposite to each other. In the second ball passage in the cover base, the height of the portion extending in the left-right direction along the lower end is about three times as high as the outer diameter of the game ball, and a predetermined amount of the game ball can be used. A storage space that can be accommodated is formed.

Further, the cover base 542 communicates with the foul ball inlet 542e, which is arranged at the substantially central upper part in the left-right direction and opens upward, and the foul ball inlet 542e, which can guide the game ball to the upper part near the downstream of the second ball passage. It has a ball passage and. Further, the cover base is provided with an opening / closing operating piece for operating the opening / closing shutter 792 of the ball outlet opening / closing unit 790 on the lower rear surface of the second ball entrance. When the door frame 5 is closed with respect to the main body frame 3, the opening / closing actuating piece comes into contact with the spherical contact portion of the opening / closing crank in the ball outlet opening / closing unit 790 to rotate the opening / closing crank and open / close the shutter 792. It can be opened.

The front cover of the foul cover unit 540 is formed in a substantially plate shape that closes the front surface of the cover base, and is arranged in the upper left corner of the front view and communicates with the first ball passage of the cover base and penetrates in the front-rear direction. It includes an exit and a second ball outlet that is arranged in the lower right corner of the front view and communicates with the downstream end of the second ball passage of the cover base 542 and penetrates in the front-rear direction. The first ball outlet of the front cover is connected to the upper plate ball supply port of the plate unit 300 through the notch of the door frame base unit 100. Further, the second ball outlet is connected to the rear end of the lower plate ball supply gutter in the plate unit 300 through the ball passage port of the door frame base main body 110.

The foul cover unit 540 allows the game ball supplied from the normal ball outlet 774 of the full tank branch unit 770 in the prize ball unit 700 to the first ball inlet 542a to pass through the first ball passage from the first ball outlet to the plate unit 300. It can be supplied to the upper plate 301 through the upper plate ball supply port. Further, the foul cover unit 540 allows the game ball supplied from the full tank outlet 776 of the full tank branch unit 770 in the prize ball unit 700 to the second ball inlet 542c from the second ball outlet through the second ball passage. It can be supplied to the lower plate 302 through the lower plate ball supply gutter and the lower plate ball supply port of the plate unit 300.

Further, in the foul cover unit 540, when the door frame 5 is closed with respect to the main body frame 3, the foul ball entrance 542e is located at the lower part of the foul space 626 of the main body frame 3, and the ball hitting device. When the game ball launched by the 650 does not reach the game area 1100 and becomes a foul ball and falls in the foul space 626, it is received by the foul ball entrance 542e. Then, the foul cover unit 540 can discharge (supply) the game ball received at the foul ball entrance 542e from the second ball outlet to the lower plate 302 of the plate unit 300 through the foul ball passage and the second ball passage. You can do it.

Further, the foul cover unit 540 forms a side surface on the upstream side (left side in the front view) of the accommodation space in the second ball passage, and is oscillated by a game ball stored in the accommodation space and is pivotally supported by the cover base. It includes a member, a full tank switch 550 that detects the swing of the swing member, and a spring that urges the swing member in a direction in which the swing member is not detected by the full tank switch 550. The lower end of this swing member is rotatably supported with respect to the cover base, and the upper end rotates to the left side when viewed from the front. It is designed to form. Further, the swing member is urged by a spring to a position where it is in a substantially vertical state. Further, the swing member is formed with a detection piece protruding outward on the side surface opposite to the accommodation space side, and this detection piece is detected by the full tank switch 550. That is, based on the detection signal from the full tank switch 550, it is possible to determine whether or not the game ball in which the accommodation space is stored is full.

[5. Overall configuration of the game board]
Next, the overall configuration of the game board 4 will be described with reference to FIGS. 8 and 9. FIG. 8 is a front view of the game board, and FIG. 9 is an exploded perspective view of the game board of FIG. 8 as viewed from the front. As shown in FIGS. 8 and 9, the game board 4 has an outer rail 1111 and an inner rail 1112, and a game area 1100 in which a game ball as a game medium is driven by a player operating a handle device 500. A frame-shaped front component 1110 that divides the outer periphery, and a position that can be visually recognized from the game window 101 of the door frame 5 to the player side when attached to the pachinko game machine 1 at the lower right corner of the front component 1110. A function display unit 1180 arranged in the above, and a plurality of openings 1158 attached to the rear side of the front component 1110 so as to close the game area 1100 and penetrating in the front-rear direction at a position corresponding to the game area 1100. It includes a plate-shaped game panel 1150, a front unit 2000 attached to the opening 1158 of the game panel 1150 from the front side, and a back unit 3000 attached to the rear surface of the game panel 1150.

Further, the game board 4 is arranged between the game panel 1150 and the back unit 3000, and is inserted from the rear side of the game panel 1150 into a plurality of light emitting decorative holes formed so as to penetrate the game panel 1150. A liquid crystal display device that is detachably attached to the rear side of the panel lens member 2500 and the back unit 3000 and can display a predetermined effect image that is visible from the player side according to the game state, and the lower part of the back unit 3000. A board holder 1160 attached to the lower part of the rear surface of the game panel 1150 and a main control board box 1170 attached to the rear surface of the board holder 1160 so as to cover the game panel 1150 from the rear side.

[5-1. Front component]
Next, the front component 1110 will be described. The outer component 1110 has a substantially rectangular shape that can be inserted into the game board holding port 601 of the main body frame 3, and the inner shape penetrates in the front-rear direction in a substantially circular shape. The outer circumference of the region 1100 is partitioned. The front component 1111 includes an outer rail 1111 extending in an arc shape from the lower end to the left from the center in the left-right direction in a front view along the circumferential direction in the clockwise direction, passing through the upper end in the center in the left-right direction in the front view, and extending diagonally to the upper right. The inner rail 1112, which is arranged inside the outer rail 1111 along the outer rail 1111 and extends in an arc shape from the lower center in the left-right direction of the front view to the diagonally upper left side of the front view, and the inner rail 1112 so as to be smoothly continuous from the lower end of the inner rail 1112. The inner peripheral rail 1113 extending in an arc shape to a position below the end (upper end) of the outer rail 1111 along the circumferential direction counterclockwise when viewed from the front, and the end (upper end) and outer rail 1111 of the inner peripheral rail 1113. At the boundary between the abutting portion 1114 where the game ball that has rolled along the outer rail 1111 and the end (upper end) of the inner rail 1111 can come into contact with the game ball, and the inner rail 1113 and the inner peripheral rail 1113, the game area 1100 From the upper end of the inner rail 1112 so as to close between the out port guide surface 1115 arranged at the lowermost end and lowered toward the rear and the outer rail 1111 rotatably supported by the upper end of the inner rail 1112. It is possible to rotate only between the closed position extending upward and the open position where it rotates clockwise in the front view and opens between the outer rail 1111 and returns to the closed position side. It includes a backflow prevention member 1116 urged by a spring.

Assuming that the game board 4 is attached to the main body frame 3, the lower end opening between the outer rail 1111 and the inner rail 1112 of the front component 1110 is the launch rail 660 in the ball launching device 650 of the main body frame 3 (FIG. 1). It is located on the extension line of). A space extending in the left-right direction and downward is formed between the lower end of the outer rail 1111 and the upper end of the launch rail 660, and the game ball launched along the launch rail 660 of the ball launcher 650 is formed. The space is jumped over, and the lower end opening between the outer rail 1111 and the inner rail 1112 is driven into the space between the outer rail 1111 and the inner rail 1112. The game ball driven between the outer rail 1111 and the inner rail 1112 rolls upward along the outer rail 1111 according to the momentum, and the backflow prevention member 1116 pivotally supported at the upper end of the inner rail 1112. By rotating to the open position side against the urging force, it is possible to invade the game area 1100.

Further, when the game ball is strongly hit by the hit ball launching device 650, the game ball that has rolled along the outer rail 1111 in the game area 1100 comes into contact with the abutment portion 1114 provided at the end of the outer rail 1111. When the game ball comes into contact with the abutting portion 1114, the rolling direction of the game ball can be forcibly changed, and the game ball continuously rolls from the outer rail 1111 to the inner rail 1113. It is designed to prevent it from moving. Even if the game ball that has entered (dried) into the game area 1100 tries to return between the outer rail 1111 and the inner rail 1112, the backflow prevention member 1116 returns to the closed position by the urging force before that. As a result, the backflow prevention member 1116 prevents the backflow of the game ball.

Further, if the game ball driven into the game area 1100 is not accepted by the start ports 2101, 1022 and the winning ports 2103, 2104, 2201 of the front unit 2000, it flows down to the lower end of the game area 1100. The out port guiding surface 1115 at the boundary between the inner rail 1112 and the inner peripheral rail 1113 guides the game panel 1150 to the out port 1151 and discharges the game board 4 downward from the out port 1151. ..

On the other hand, if the game ball launched from the ball striking device 650 cannot enter the game area 1100 beyond the backflow prevention member 1116 at the tip of the inner rail 1112, the outer rail 1111 and the inner rail 1112 are combined. A foul space 626 formed between the upper end of the launch rail 660 and the lower end of the outer rail 1111 from the lower end opening between the outer rail 1111 and the inner rail 1112, rolling downward in the opposite direction. (See FIG. 1) will fall and will be accepted by the foul ball inlet 542e (see FIG. 1) of the foul cover unit 540 attached to the door frame 5 located at the bottom of the foul space 626 in the dish unit 300. It is designed to be discharged to the lower plate 302 (see FIG. 7).

A metal plate is attached to the surface of the outer rail 1111 of the front component 1110 to improve the wear resistance due to the rolling of the game ball, and the game ball rolls smoothly. ing. Further, the abutting portion 1114 has an elastic body such as rubber or synthetic resin arranged on the surface thereof, and even if the game ball rolls vigorously along the outer rail 1111 and collides with the abutment portion 1114, the impact is alleviated. And the game ball can be repelled inward.

Further, the front component 1110 is vertically separated from the left end of the front view and is vertically separated from the pair of positioning recesses 1119 which are recessed from the front to the rear and opened to the left end. A pair of game board stoppers 1120 arranged, a fixed recess 1121 arranged on the left side of the outer rail 1111 on the left side in the front view and opened downward, and the upper side formed in an arc shape and recessed from the front side, and the lower end in the front view. In the vicinity of the left end portion of the above, a notch portion 1122 for a ball passage, which is notched in a rectangular shape extending upward from the lower end in the left-right direction, is provided. The positioning recess 1119 of the front component 1110 is fitted with the positioning member 956 (see FIG. 5) attached to the inside of the side security plate 950 in the main body frame 3, so that the game board holding port 601 (see FIG. 5) is fitted. ), The left end of the front view of the game board 4 can be restricted from moving in the front-rear direction. Further, the game board stopper 1120 can be detachably locked to the game board locking portion of the main body frame base 600 in the main body frame 3, and the game board stopper 1120 can be locked to the game board clerk. By locking it to the stop portion, it is possible to restrict the right end of the game board 4 inserted into the game board holding port 601 of the main body frame 3 from moving in the front-rear direction.

Further, the fixing recess 1121 of the front component 1110 is a game board fixing tool 690 (FIG. 5) pivotally supported on the front surface of the main body frame 3 in a state where the game board 4 is inserted into the game board holding port 601 of the main body frame 3. When the game board fixture 690 is rotated in the clockwise direction in front view (see), the fixing piece 690a (see FIG. 5) of the game board fixture 690 is inserted, and the game board 4 is inserted by the game board fixture 690. The lower end of the clock is restricted from moving forward. Further, in the ball passage notch 1122 of the front component 1110, a similar ball passage notch 1152 is formed at the same position of the game panel 1150, and the game board 4 is used as the game board holding port 601 of the main body frame 3. In the state of being inserted into, the front end of the full tank branch unit 770 (see FIG. 5) is inserted into the notch portion 1122, 1152 for the ball passage.

A function display unit 1180, which will be described later, is arranged at the lower right of the front view of the front component 1110.

[5-2. Table unit]
Next, the table unit 2000 of the game board 4 will be described. The front unit 200 is an attacker unit 2100 arranged above the out port 1151 at a substantially lower center in the left-right direction in the game area 1100 and supported on the front surface of the game panel 1150, and an outer circumference of the game area 1100 on the left side of the attacker unit 2100. A side winning opening member 2200 arranged along the above and supported on the front surface of the game panel 1150, and a frame-shaped center accessory 2300 arranged along a substantially central portion of the game area 1100 and supported by the game panel 1150. There is.

The table unit 2000 is inserted from the front side into the opening 1158 formed at a position corresponding to the game area 1100 in the game panel 1150, and is attached to the front surface of the game panel 1150. The portion protruding forward from the game panel 1150 is located within the game area 1100. As a result, the front unit 2000 comes into contact with the game ball driven into the game area 1100 at an appropriate position, and with the obstacle nails planted on the front surface of the game panel 1150, with respect to the movement of the game ball. It is possible to give a change. Further, the table unit 2000 can decorate the inside of the game area 1100.

[5-2-1. Attacker unit]
Next, the attacker unit 2100 of the table unit 2000 will be described. The attacker unit 2100 has a plurality of entrances (winning openings) that allow the game balls driven into the game area 1100 to be accepted, and specifically, the attacker unit 2100 is arranged substantially in the center in the left-right direction. A rectangle that is located below the starting port 2101, the lower starting port 2102 located below the upper starting port 2101, and below the lower starting port 2102, and extends significantly in the left-right direction from the upper starting port 2101 and the lower starting port 2102. It is provided with a large winning opening 2103 having a shape and a general winning opening 2104 arranged slightly above the left and right sides of the large winning opening 2103. The game balls accepted by the upper start opening 2101, the lower start opening 2102, the large winning opening 2103, and the general winning opening 2104 are guided from the front side to the rear side of the game panel 1150.

The upper start port 2101 of the attacker unit 2100 is open on the upper side so that a game ball can always be received (winning). On the other hand, in the lower starting port 2102 arranged below the upper starting port 2101, a pair of movable pieces 2106 that can be expanded by the starting port solenoid 2105 (see FIG. 12) are arranged between the lower starting port 2102 and the upper starting port 2101. In a state where the pair of movable pieces 2106 stands up substantially vertically, the upper starting port 2101 and the pair of movable pieces 2106 make the game ball unacceptable to the lower starting port 2102, whereas the pair of movable pieces are movable. When the piece 2106 is expanded in the left-right direction, the game ball can be accepted into the lower starting port 2102. That is, the lower starting port 2102 is a variable winning opening due to the pair of movable pieces 2106. The pair of movable pieces 2106 are drawn according to the result of the normal lottery drawn based on the detection of the passage of the game ball by the gate switch 2352 of the gate portion 2350 in the center accessory 2300 described later (the result of the normal lottery is "hit". ”), It is opened and closed by driving the start port solenoid 2105.

Further, the large winning opening 2103 of the attacker unit 2100 can be opened and closed by a horizontally long rectangular opening and closing member 2107 that can close the opening. The lower side of the opening / closing member 2107 is rotatably supported by the shaft, and in a substantially vertical state, the large winning opening 2103 can be closed to make it difficult to accept the game ball, and the upper side moves to the front side. When it is rotated to, the large winning opening 2103 is opened so that the game ball can be easily accepted. The opening / closing member 2107 is in a state in which the large winning opening 2103 is closed in a normal gaming state, and a special lottery is drawn when a game ball is accepted (starting prize) in the upper starting opening 2101 or the lower starting opening 2102. It opens and closes by driving the attacker solenoid 2108 (see FIG. 12) according to the lottery result (when the result of the special lottery is "big hit" or "small hit").

Further, the general winning opening 2104 of the attacker unit 2100 is opened upward so that the game ball can always be accepted (winning).

Further, although detailed illustration is omitted, the attacker unit 2100 has a lower start port switch 2109 that detects a game ball received by the lower start port 2102 and a count switch that detects a game ball received by the grand prize opening 2103. 2110 is further provided, and the game ball detected by the lower start port switch 2109 and the count switch 2110 is discharged onto the bottom wall portion of the board holder 1160. The upper starting port switch 3022 for detecting the game ball accepted by the upper starting port 2101 and the general winning port switch 3020 for detecting the game ball accepted by the general winning opening 2104 are provided in the back unit 3000. ..

[5-2-2. Side winning opening member]
Next, the side winning opening member 2200 of the table unit 2000 will be described. The side winning opening member 2200 was inserted from the front side into the opening 1158 formed on the left side of the opening 1158 in which the attacker unit 2100 is inserted and fixed at the lower part of the game panel 1150 on the left side from the center in the left-right direction. Above, two are fixed to the front surface of the game panel 1150 and are oriented so as to face each other along the outer periphery of the game area 1100 so as to be aligned with the general winning opening 2104 on the left side of the front view of the attacker unit 2100. It is equipped with a general winning opening 2201. These two general winning openings 2201 are opened upward so that game balls can always be accepted (winning), and the game balls accepted into the general winning opening 2201 are guided from the front side to the rear side of the game panel 1150. After that, it is detected by the general winning opening switch 3020 provided in the back unit 3000, which will be described later.

Further, the side winning opening member 2200 is arranged at a position where the left end portion is substantially in contact with the outer periphery of the game area 1100 at the upper left end portion thereof, and is inclined so as to be lowered toward the right end portion. The shelf portion 2202 and the first shelf portion 2202 are arranged on opposite sides and lower sides of the two general winning openings 2201 and are located on the left-right center side of the game area 1100 (the lower starting opening 2102 and the large winning opening of the attacker unit 2100). It is provided with a second shelf portion 2203 that becomes lower toward the 2103 side), and the game ball that has flowed down along the outer periphery of the game area 1100 by the first shelf portion 2202 can be moved toward the center side of the game area 1100. You can do it.

The two general winning openings 2201 are arranged on the right side of the right end of the first shelf 2202, and even if the game ball is moved to the center side of the game area 1100 by the first shelf 2202, There is a possibility of winning a prize in the general winning opening 2201. Further, a third shelf portion 2204 inclined so as to be lowered toward the center side of the game area 1100 is also provided on the upper side between the two general winning openings 2201.

The side winning opening member 2200 is formed so as to have translucency as a whole, and although detailed illustration is omitted, a side winning opening decorative substrate is provided on the rear side of the second shelf portion 2203. At the same time, the side lamp decorative substrate 3014 in the back unit 3000 described later is arranged behind the side winning opening member 2200, and the side winning opening member 2200 is provided by these side winning opening decorative substrate and the side lamp decorative substrate 3014. Is luminescent and can be decorated.

[5-2-3. Center role]
Next, the center accessory 2300 of the table unit 2000 will be described. The center accessory 2300 is inserted from the front side into an opening 1158 formed large so as to penetrate substantially the center of the game panel 1150, and is fixed to the front surface of the game panel 1150. It is formed in a frame shape with a size that occupies most of the area 1100, and the outer peripheral surface on the right side of the front view is arcuate so as to form a gap slightly larger than the outer diameter of the game ball with the outer circumference of the game area 1100. In addition to being formed, the outer peripheral surface on the left side is formed on a substantially straight line that hangs down so as to form a region having a predetermined width from the outer circumference of the game area 1100.

The center accessory 2300 is an upper shelf portion 2301 that is inclined to the left from a position slightly to the right of the center in the left-right direction on the upper outer peripheral surface of the front wall portion located in front of the game panel 1150 so as to be lowered toward the left. When a game ball driven into the upper part of the game area 1100 flows down to the upper shelf part 2301, it flows down through the left side of the center accessory 2300 and on the right side of the upper shelf part 2301. The game ball that has flowed down (invaded) passes through the right side of the center accessory 2300 and flows down to the lower part of the game area 1100 at once. That is, if the game ball is driven so that the game ball invades to the right side of the upper shelf 2301 in the center accessory 2300, the chance of enjoying the flow of the game ball is reduced, so that the driving force of the game ball is strong. It is possible to adjust the ball as appropriate, and it is possible to maintain a feeling of tension and suppress the game from becoming a vague game.

Further, the center accessory 2300 has invaded the warp entrance 2302 and the warp entrance 2302 in which the game ball flowing down the game area 1100 can enter the outer peripheral surface on the left side of the front wall portion located on the front side of the game panel 1150. A warp outlet (not shown) that discharges the game ball into the frame, and a center accessory that rolls the game ball released from the warp outlet in the left-right direction and then releases it into the game area 1100 above the attacker unit 2100. It mainly includes a stage 2310 formed on the upper surface of the lower side in the frame of the 2300.

Although detailed illustration of the stage 2310 in the center accessory 2300 is omitted, the first stage to which the game balls released from the warp outlet are supplied and the game balls arranged in front of the first stage are arranged from the first stage. It is provided with a second stage, which is supplied and capable of releasing a game ball into the game area 1100. The stage 2310 is formed in a curved surface shape so that the substantially center in the left-right direction is lowered. Further, a chance entrance 2313 through which a game ball can enter is formed on the rear side of the first stage substantially in the center in the left-right direction, and the game ball invading the chance entrance 2313 is a chance at the lowermost front of the center accessory 2300. It is designed to be discharged into the game area 1100 from the exit 2314. The chance exit 2314 is arranged directly above the upper start port 2101 in the attacker unit 2100, and the game ball released from the chance exit 2314 is accepted (wins) in the upper start port 2101 with a high probability. ing.

The stage 2310 in the center accessory 2300 is formed of a transparent member so that the decorative body arranged below the stage 2310 in the back unit 3000 can be visually recognized from the player side through the stage 2310. It has become.

Further, the center accessory 2300 is transparent so as to extend to the left so as to be substantially in contact with the inner rail 1112 on the outer peripheral surface on the left side of the front wall portion located on the front side of the game panel 1150, above the warp entrance 2302. It further includes an arch portion 2315. The arch portion 2315 extends in a thin plate shape from a substantially front end of the front wall portion, and forms a space through which a game ball can pass between the arch portion 2315 and the front surface of the game panel 1150. As a result, the game ball driven into the upper part of the game area 1100 and guided to the left of the center accessory 2300 by the upper shelf portion 2301 flows down to the downstream side through the rear side of the arch portion 2315. ..

Further, the center accessory 2300 is provided with a gate portion 2350 that detects the passage of the game ball near the arch portion 2315 on the outer peripheral surface on the left side of the front wall portion located on the front side of the game panel 1150. The gate portion 2350 detects a gate entrance, which is arranged on the outer peripheral surface on the left side of the front wall portion and above the arch portion 2315 and allows a game ball flowing down the game area 1100 to enter, and a game ball that has entered the gate entrance. The gate switch 2352 and the gate outlet for discharging the game ball detected by the gate switch 2352 from the outer peripheral surface of the front wall portion to the game area 1100 are provided. In the present embodiment, although detailed illustration is omitted, the gate exit of the gate portion 2350 is formed at the same height as the arch portion 2315, and the game ball detected by the gate switch 2352 is an arch. It looks as if you have dived in part 2315.

[5-3. Panel lens member]
Next, the panel lens member 2500 of the game board 4 will be described. The panel lens member 2500 is formed to penetrate in the front-rear direction in a circular or × shape at a position outside the opening 1158 in which the center accessory 2300 is inserted in the game area 1100 of the game panel 1150. The decorative holes are luminescent and decorated. The panel lens member 2500 includes a transparent upper panel lens 2510 corresponding to a plurality of light emitting decorative holes formed on the upper left side on the outer periphery of the center accessory 2300, and a plurality of panels arranged on the rear side of the upper panel lens 2510 on the surface. It is arranged behind the upper panel lens substrate on which the LED is mounted, the transparent lower panel lens 2520 corresponding to a plurality of light emitting decorative holes formed on the lower left side on the outer periphery of the center accessory 2300, and the lower panel lens 2520. It includes a lower panel lens substrate on which a plurality of LEDs are mounted on the surface.

The upper panel lens 2510 and the lower panel lens 2520 in the panel lens member 2500 project forward from the plate-shaped lens base portion and have a plurality of rod-shaped insertion guide guides having substantially the same shape as the shape of the light emitting decorative hole to be inserted. It has a part. When the insertion light guide portion is inserted into the light emitting decorative hole of the game panel 1150 from the rear side, the tip thereof is formed so as to substantially coincide with the front surface of the game panel 1150, and the game flows down the front surface of the game panel 1150. It is designed so that it does not affect the ball as much as possible.

By appropriately emitting the LEDs of the upper panel lens substrate and the lower panel lens substrate, the panel lens member 2500 can illuminate and decorate the area where the gaming ball flows down even if an opaque gaming panel 1150 such as veneer plywood is used. The decoration of the game panel 1150, which has never been seen before, can be shown to the player, and the pachinko game machine 1 can be made to stand out to be differentiated from other pachinko game machines.

[5-4. Back unit]
Next, the back unit 3000 of the game board 4 will be described. The back unit 3000 is attached and fixed to the rear surface of the game panel 1150, and is a 12-inch (image size 800 x 600 dots) liquid crystal display device 1900 (hereinafter, "" It may be described as "the liquid crystal display device 1900 on the game board side") and is arranged at the upper left, lower left, lower right, and upper right of the front side of the liquid crystal display device 1900, 4.3 inches (image size 480 x). The back box 3001 that supports the four movable liquid crystal display devices 1925a to 1925d (272 dots) so that they can move in the vertical and horizontal directions, respectively, and the back box 3001 located above the liquid crystal display device 1900 in the back box 3001 and located on the upper left. The upper unit 3100 arranged on the front side of the movable liquid crystal display device 1925a and the movable liquid crystal display device 1925d arranged on the upper right side, and the upper unit 3100 arranged on the right side and lower right side of the liquid crystal display device 1900 in the back box 3001. The character unit 3400 arranged on the front side of the movable liquid crystal display device 1925c and the movable liquid crystal display device 1925d arranged on the upper right, and the movable movable liquid crystal display device 1900 on the left side and upper left side of the liquid crystal display device 1900 in the back box 3001. It mainly includes a gear decoration unit 3500 arranged on the front side of the liquid crystal display device 1925a and the movable liquid crystal display device 1925b arranged on the lower left side.

Further, the back unit 3000 is arranged at a position corresponding to the side winning opening member 2200 in the front unit 2000 attached to the front surface of the game panel 1150 near the lower left front end of the back box 3001, and a plurality of LEDs are mounted on the surface. A game ball attached to the side lamp decorative substrate 3014 and the lower front end of the back box 3001 and accepted by the general winning opening 2201 of the side winning opening member 2200, and a game accepted by the general winning opening 2104 on the left side of the attacker unit 2100. The left guide member 3016 that guides the ball downward, and the right side that is arranged on the right side of the left guide member 3016 and guides the game ball received downward to the upper start opening 2101 and the general winning opening 2104 on the right side of the attacker unit 2100. The guide member 3018 and the like are provided.

Further, although detailed illustration is omitted, the back unit 3000 is arranged under the rear lower portion of the back box 3001 and accommodates the lamp drive board 4170, and is below the horizontally long rectangular lamp drive board box 3423 and the lamp drive board box 3423. The horizontally long rectangular motor drive board box 3430 arranged on the side and accommodating the motor drive board 4180, and the lamp drive board box 3423 and the motor drive board box 3430 fixed to the rear side of the back box 3001 and arranged on the left side in the rear view. A panel relay terminal board 4161, a horizontally long rectangular upper resistance board arranged on the rear upper side of the back box 3001, and a lock member attached to the rear side of the back box 3001 to hold the liquid crystal display device 1900 detachably. , Is equipped.

Although detailed illustration is omitted, the back unit 3000 has movable liquid crystal display devices 1925a to 1925d in the vertical and horizontal directions on the rear upper left, the rear left lower, the rear right lower, and the rear upper right of the back box 3001, respectively. It is equipped with movable devices 1925aa, 1925ba, 1925ca, 1925da that can be moved. These movable devices 1925aa to 1925da are each provided with two stepping motors and a conversion mechanism for converting the rotational motion of the output shafts of the two stepping motors into linear motion, which are provided in the movable devices 1925aa to 1925da, respectively. By driving two stepping motors, the movable liquid crystal display devices 1925a to 1925d can be independently moved in the vertical and horizontal directions.

In the present embodiment, the back unit 3000 can be visually recognized from the player side through the frame of the center accessory 2300 in the front unit 2000, and the units 3100 and 3400 shaped into a predetermined shape are formed. , 3500, etc. make it possible to characterize the concept of the pachinko gaming machine 1. Further, in the back unit 3000, each unit 3100, 3400, 3500 and the movable liquid crystal display devices 1925a to 1925d are movable independently or in cooperation with each other according to the game state, and the game is performed by the movement. It is possible to suggest changes in the gaming state and the arrival of opportunities to the player, so that the player can be entertained.

[5-4-1. Back box]
Next, the back box 3001 of the back unit 3000 will be described. The back box 3001 is formed in a box shape with the front side open, and is provided with a plurality of flange-shaped fixing portions 3001a protruding outward at the front end, and is provided on the rear side of the game panel 1150 via the fixing portions 3001a. It is designed to be fixed. Further, the back box 3001 has a rectangular opening formed substantially in the center of the rear wall, and the liquid crystal display device 1900 supported on the rear side through the opening can be visually recognized from the player side. Further, the back box 3001 is for attaching and fixing the units 3100, 3400, 3500, the movable liquid crystal display devices 1925a to 1925d, the movable devices 1925aa to 1925da, and the substrates 3014, which can move the movable liquid crystal display devices 1925a to 1925d in the vertical and horizontal directions, respectively. The mounting portion is formed at an appropriate position.

Further, although not shown, the back box 3001 is inserted and locked on the right side of the opening in the rear view by inserting and locking one fixing piece 1902 protruding outward from both the left and right sides of the liquid crystal display device 1900 (the right side in the rear view). A liquid crystal support portion is provided, and a lock member is attached to the left side when viewed from the rear of the opening. The lock member supports the other fixed piece 1902 of the liquid crystal display device 1900 (the left side when viewed from the rear) to form a liquid crystal. The display device 1900 is detachably attached to the rear side of the back box 3001.

[5-4-2. Guidance member]
Next, the left guide member 3016 and the right guide member 3018 will be described. The left guide member 3016 guides and discharges the game ball received into the general winning opening 2201 of the side winning opening member 2200 and the general winning opening 2104 on the left side of the attacker unit 2100 through different flow paths. Each flow path is provided with a general winning opening switch 3020 for detecting the passage of a game ball. On the other hand, the right guiding member 3018 guides and discharges the game balls received by the upper starting port 2101 of the attacker unit 2100 and the general winning opening 2104 on the right side through different flow paths to the vicinity of the lower end. The flow path corresponding to the upper start port 2101 is provided with the upper start port switch 3022, and the flow path corresponding to the general winning port 2104 on the right side is provided with the general winning port switch 3020. Further, the right guiding member 3018 is provided with a magnetic detection switch 3024 capable of detecting magnetism.

The game balls guided downward by the left guide member 3016 and the right guide member 3018 are discharged onto the bottom wall portion of the board holder 1160, and are discharged downward from the out ball discharge portion 1161 of the board holder 1160 to the lower side of the game board 4. It has become so.

[5-4-3. Upper unit]
Next, the upper unit 3100 will be described. The upper unit 3100 is formed horizontally as a whole, and is attached and fixed to the upper side of the opening facing the liquid crystal display device 1900 in the back box 3001. The upper unit 3100 is arranged in the front at substantially the center in the left-right direction and is arranged in a circular shape in front view, and is arranged behind the rotating decoration unit 3200 to raise and lower the rotating decoration unit 3200. Mainly provided with 3250, a swinging decorative unit 3300 arranged substantially in the center in the left-right direction on the rear side of the elevating mechanism 3250, and movable ceiling units 3350 arranged on both left and right sides of the swinging decorative unit 3300. ing.

The rotary decorative unit 3200 can be moved in the vertical direction between the ascending position located at the upper part of the liquid crystal display device 1900 and the descending position located at substantially the center of the liquid crystal display device 1900 by the elevating mechanism 3250. It has become. In the rotating decoration unit 3200, the rotating decoration formed in the shape of a shuriken arranged on the front surface rotates, and the rotation causes the rotational radius of the rotating decoration to increase due to the centrifugal force. It has become like.

Further, in the rotating decoration unit 3200, not only the rotating decoration rotates at the end but also the rotating decoration unit protrudes outward in the radial direction, so that the turning radius of the entire rotating decoration body is expanded and the appearance is greatly changed. It is possible to give a strong impact to the player, entertain the player and suppress the decline in the interest in the game, and strongly attract the interest of the player. This makes it easier to select the pachinko gaming machine 1 as the pachinko gaming machine that plays a game with a large difference from other pachinko gaming machines.

The swinging decoration unit 3300 includes swinging decorations arranged on the left and right sides on the rear side so as to be adjacent to the rotating decoration unit 3200 located at the raised position, and the swinging decorations on the left and right depending on the gaming state. The body can be swung to the left and right all at once.

The movable ceiling unit 3350 is provided with plate-shaped ceiling decorations extending in the horizontal direction at both left and right ends of the upper unit 3100. The ceiling decoration is rotatably formed around an axis extending in the left-right direction around the front end side, and the rear end side of the ceiling decoration rotates in the descending direction according to the game state. It has become.

[5-4-4. Character unit]
Next, the character unit 3400 of the back unit 3000 will be described. The character unit 3400 is provided with a character body that is modeled and three-dimensionally shaped as a ninja, and the character body moves from the rightmost position to the position closer to the center side in the left-right direction according to the game state. Can be done. Further, when the character body of the character unit 3400 moves in the left-right direction, the character body rotates by a predetermined angle around an axis extending in the up-down direction with the movement.

Further, the character body of the character unit 3400 can reciprocate around an axis whose head extends in the left-right direction, and reciprocates around an axis whose right arm extends in the vertical direction. Can be done. As a result, by reciprocating the head, the character can behave as if it were nodding. In addition, by reciprocating the right arm in the horizontal direction, the character can behave as if he were throwing a shuriken.

[5-4-5. Gear decoration unit]
Next, the gear decoration unit 3500 of the back unit 3000 will be described. The gear decoration unit 3500 includes gear-shaped gear decorations that are rotatable around an axis extending in the left-right direction and are arranged in the vertical direction, and the gear decorations are simultaneously arranged according to the gaming state. It is designed to rotate.

[5-4-6. Liquid crystal display device]
Next, the liquid crystal display device 1900 of the game board 4 will be described. The liquid crystal display device 1900 is detachably attached to the rear surface of the back box 3001 of the back unit 3000, and can display a predetermined effect image according to the game state. The liquid crystal display device 1900 includes fixed pieces 1902 protruding outward from both the left and right sides, and can be attached to the back box 3001 via the fixed pieces 1902.

Further, although detailed illustration is omitted, the liquid crystal display device 1900 includes a peripheral board box 1905 that houses a peripheral control board 4140 and a liquid crystal output board 3420, which will be described later, on the rear side thereof.

[5-4-7. Movable liquid crystal display device]
Next, the movable liquid crystal display devices 1925a to 1925d of the game board 4 will be described with reference to FIG. FIG. 10 is a diagram showing an outline of a mode in which the movable liquid crystal display device is movable in the vertical and horizontal directions. The movable liquid crystal display devices 1925a to 1925d are in positions that are difficult to see when the pachinko gaming machine 1 is viewed from the front side in the standby state in the original positions (the movable liquid crystal display devices 1925a and 1925b are decorated with gears. The body unit 3500 is in a standby state with the rear upper left side and the rear left lower side as the original positions, and the movable liquid crystal display devices 1925c and 1925d are in a state of waiting with the rear right lower side and the rear upper right side of the character unit 3400 as the original positions, respectively. ).

As described above, the movable liquid crystal display devices 1925a to 1925d are vertically and horizontally provided by the movable devices 1925aa, 1925ba, 1925ca, 1925da provided on the rear upper left, the rear left lower, the rear right lower, and the rear upper right of the back box 3001. It is configured so that it can be moved independently in each direction. Among a plurality of modes in which the movable liquid crystal display devices 1925a to 1925d are movable, as an example thereof, the front surface of the liquid crystal display device 1900 is moved from each original position toward the center of the display area of the liquid crystal display device 1900. A mode in which the liquid crystal display device 1900 is combined to cover the entire display area of the liquid crystal display device 1900 will be briefly described.

As shown in FIG. 10A, the movable liquid crystal display devices 1925a to 1925d are started to move from their respective original positions toward the center of the display area of the liquid crystal display device 1900 by the movable devices 1925aa, 1925ba, 1925ca, 1925da. As shown in FIG. 10 (b), the liquid crystal display device 1900 appears from the four corners on the front surface of the liquid crystal display device 1900, and as shown in FIG. 10 (c), in the center of the display area of the liquid crystal display device 1900. It is in a state of being united as one liquid crystal display device and covering the entire display area of the liquid crystal display device 1900.

After that, the movable liquid crystal display devices 1925a to 1925d were united as one liquid crystal display device in the center of the display area of the liquid crystal display device 1900 by the movable devices 1925aa, 1925ba, 1925ca, 1925da as shown in FIG. 10 (c). It started to move from the state to each in-situ, passed through the four corners of the liquid crystal display device 1900 as shown in FIG. 10 (b), returned to each in-situ and waited as shown in FIG. 10 (a). It becomes a state.

[6. Function display unit]
Next, the function display unit 1180 in the game board 4 will be described with reference to FIG. The function display unit 1180 is attached and arranged at a predetermined position of the front component member 1110. FIG. 11 is an enlarged front view showing a function display unit on a gaming board in a state of being attached to a pachinko gaming machine.

As shown enlarged in FIG. 11, the function display unit 1180 is a game state display including one LED for displaying a game state changed by a game ball driven into the game area 1100 at the left end portion of the front view. It consists of a device 1183 and two LEDs arranged in the vertical direction on the right side of the game status display 1183. The upper special symbol, which is arranged on the right side of the special symbol storage display 1184 and consists of one 7-segment LED for displaying the result of the first special lottery drawn by accepting the game ball to the upper starting port 2101 as the first special symbol. One 7 for displaying the result of the second special lottery, which is arranged diagonally to the right of the display 1185 and the upper special symbol display 1185 and is drawn by accepting the game ball to the lower starting port 2102, as the second special symbol. The lower special symbol display 1186 consisting of segment LEDs and the lower special symbol display 1186 consisting of two LEDs arranged in the vertical direction on the right side to display the number of holdings related to the acceptance of game balls to the lower starting port 2102. It is equipped with a special symbol memory display 1187.

The display unit 1181 of the function display unit 1180 is arranged in an arc shape substantially along the inner peripheral rail 1113 from directly above the lower special symbol display 1186 to display the number of reservations related to the passage of the gate portion 2350 by the game ball. The normal symbol memory display 1188 consisting of the four LEDs of the above and the normal symbol lottery result arranged under the normal symbol storage display and drawn by passing the game ball through the gate 2350 are displayed as the normal symbol. The normal symbol display 1189 consisting of one LED and the normal symbol storage display 1188 are arranged side by side diagonally to the upper right side, and when the first special lottery result or the second special lottery result is "big hit", the big winning opening 2103 is opened and closed. It includes a round indicator 1190 composed of two LEDs for displaying the number of times the pattern is repeated (the number of rounds).

The game status indicator 1183 is a full-color LED capable of changing the emission color of red, green, and orange, and various gaming states (depending on the combination of the emission color and lighting / blinking). For example, a normal time state, a probability fluctuation state, a time shortening state, a probability change time saving state, a big hit game state, a small hit game state, etc.) can be displayed.

The upper special symbol memory display 1184 suspends the start of the variable display when the game ball is accepted by the upper start opening 2101 when the first special symbol cannot be variablely displayed on the upper special symbol display 1185 ( The number of reserved first special symbols (stored) is displayed. Further, the special symbol storage display 1184 has a first special symbol storage lamp 1184a composed of a predetermined LED and a first special symbol storage lamp 1184b, and the first special symbol storage lamps 1184a and 1184b are lit. The number of holds can be displayed by the blinking pattern. Specifically, for example, when the number of holds is one, the first special symbol storage lamp 1184a is turned on and the first special symbol storage lamp 1184b is turned off, and when the number of holds is two, the first special symbol storage lamps 1184a and 1184b are turned on. 1184a blinks and the first special symbol memory lamp 1184b lights up when the number of holds is three, and the first special symbol memory lamps 1184a and 1184b both light up when the number of holds is four. It is supposed to blink. In this embodiment, up to four are reserved.

The lower special symbol memory display 1187 suspends the start of the variable display when the game ball is accepted by the lower start port 2102 when the lower special symbol display 1186 cannot display the second special symbol in a variable manner (1187). The number of reserved second special symbols (stored) is displayed. The lower special symbol storage display 1187 has a second special symbol storage lamp 1187a and a second special symbol storage lamp 1187b made of predetermined LEDs, and the second special symbol storage lamps 1187a and 1187b are lit. The number of holds can be displayed by the blinking pattern. Specifically, for example, when the number of holdings is one, the second special symbol storage lamp 1187a is turned on and the second special symbol storage lamp 1187b is turned off, and when the number of holdings is two, the second special symbol storage indicator lamp 1187a, When 1187b is lit together, the second special symbol storage lamp 1187a blinks and the second special symbol storage lamp 1187b is lit when the number of holds is three, and when the number of holds is four, the second special symbol storage lamps 1187a and 1187b are lit. Both are designed to blink. In this embodiment, up to four are reserved.

The upper special symbol display 1185 and the lower special symbol display 1186 display the first special lottery result and the second special lottery result drawn by accepting the game ball to the upper start port 2101 and the lower start port 2102. The 7-segment LED is stopped after fluctuating for a predetermined time according to the special lottery result, and the first special lottery result and the second special lottery result are played according to the light emission pattern (special symbol) of the stopped 7-segment LED. It is designed to be recognized by the person.

The ordinary symbol display 1189 is a full-color LED capable of changing the emission color of red, green, and orange, and the gate portion 2350 is played by combining the emission color and lighting / blinking. It is possible to display the result of a normal lottery that is drawn when the ball passes through. As with the special symbol, the display of the normal symbol by the normal symbol display 1189 is also stopped and displayed in a light emitting pattern corresponding to the normal lottery result after the display is changed for a predetermined time.

The normal symbol storage display 1188 holds (stores) the start of the variable display when the game ball passes through the gate portion 2350 when the normal symbol cannot be variablely displayed on the normal symbol display 1189. It displays the number of holds (the number of memories) of. This ordinary symbol storage display 1188 includes four ordinary symbol storage lamps 1188a to 1188d arranged side by side from the bottom, each of which is a predetermined LED, and the ordinary symbol storage lamp 1188a is arranged from the bottom according to the number of holdings. By turning on ~ 1188d in sequence, the number of reserved symbols can be displayed. In this embodiment, up to four variable displays of ordinary symbols are reserved (stored).

The round indicator 1190 includes a 2-round indicator lamp 1190a and a 15-round indicator lamp 1190b composed of predetermined LEDs, and the number of rounds in the "big hit" game can be displayed by turning on each lamp. It has become like.

Further, as shown in FIG. 11, the function display unit 1180 can be visually recognized from the player side through the game window 101 of the door frame 5 in a state where the game board 4 is attached to the pachinko game machine 1. There is. Game status display 1183, upper special symbol storage display 1184, upper special symbol display 1185, lower special symbol display 1186, lower special symbol storage display 1187, normal symbol storage display 1188, normal symbol display 1189, and The round display 1190 is attached to the front surface of the function display board 1191. A connection terminal for connecting the function display board 1191 and the main control board 4100 is attached to the rear end of the rear protruding portion of the function display unit 1180.

In the present embodiment, since the function display unit 1180 is provided in the front component 1110 of the game board 4, it is compared with the case where the front unit 2000 and the back unit 3000 attached to the game panel 1150 are provided. The function display unit 1180 can be diverted as the basic configuration of the gaming board 4, the configuration related to the pachinko gaming machine 1 can be simplified to prevent the cost from increasing, and the model of the pachinko gaming machine 1 (table). Even if the detailed configuration of the gaming board 4 that is embodied by the unit 2000 and the back unit 3000 and can characterize the model of the pachinko gaming machine 1) is different, the position of the function display unit 1180 does not change, so that the player and the game The position of the function display unit 1180 can be recognized by a clerk in the hall without any confusion.

[7. Main control board, payout control board and peripheral control board]
Next, a control board that performs various controls of the pachinko gaming machine 1 will be described with reference to FIGS. 12 to 17. FIG. 12 is a block diagram of a main control board, a payout control board, and a peripheral control board, FIG. 13 is a block diagram showing a continuation of FIG. 12, and FIG. 14 is a payout control board, a CR unit, and a frequency constituting the main board. FIG. 15 is a schematic diagram of various detection signals input / output to / from a game ball rental device connection terminal board that relays an electrical connection with a display board, FIG. 15 is a block diagram showing a continuation of FIG. 12, and FIG. 16 is a block diagram. It is a block diagram which shows the outline of a peripheral control MPU, and FIG. 17 is a block diagram around a VDP with a built-in sound source in a liquid crystal and a sound control unit.

As shown in FIG. 12, the control configuration of the pachinko gaming machine 1 is mainly composed of a main control board 4100, a payout control board 4110, and a peripheral control board 4140, and various controls are shared. First, the main control board will be described, and then the payout control board, the power supply board, and the peripheral control board will be described.

[7-1. Main control board]
As shown in FIG. 12, the main control board 4100 that controls the progress of the game controls the power-on processing executed at the time of power-on, and is executed after a predetermined time has elapsed from the time of power-on, and also performs the game operation. The detection signals from the main control MPU4100a, which is a microprocessor with a built-in various control programs such as the main control program to be controlled, a ROM for storing various commands, and a RAM for temporarily storing data, and various detection switches are input. Main control input circuit 4100b, main control output circuit 4100c for outputting various signals to an external board, etc., main control solenoid drive circuit 4100d for driving various solenoids, and a power failure or momentary voltage of a predetermined voltage. It is mainly equipped with a power failure monitoring circuit 4100e for monitoring signs of stoppage.

In addition to the built-in RAM (hereinafter, referred to as "main control built-in RAM") and the built-in ROM (hereinafter, referred to as "main control built-in ROM") of the main control MPU4100a. It also has a built-in watchdog timer 4100af (hereinafter referred to as "main control built-in WDT4100af") for monitoring its operation (system) and a function for preventing fraud.

Further, the main control MPU4100a has a built-in non-volatile RAM. In this non-volatile RAM, a unique ID code with a unique code (a code that exists only once in the world) for identifying an individual by the manufacturer of the main control MPU4100a is stored in advance. Since the ID code once attached is stored in the non-volatile RAM, it cannot be rewritten even by using an external device. The main control MPU4100a can take out an ID code from the non-volatile RAM and refer to it.

Further, the main control MPU 4100a is a hard random number circuit 4100an (hereinafter, "built-in main control") that updates a big hit determination random number to be used for determining whether or not to generate a big hit game state among various random numbers related to the game by hardware. It is described as "hard random number circuit 4100an"). The main control built-in hard random number circuit 4100an generates a random number within a predetermined numerical range (in the present embodiment, a numerical range of a value 0 to a maximum value of 32767 is preset as a minimum value). The circuit is configured so that a predetermined value is not fixed as the initial value (that is, the initial value is not fixed), and a different value is set each time the main control MPU 4100a is reset. Specifically, in the main control built-in hard random number circuit 4100an, when the main control MPU 4100a is reset, first, a clock signal (1 value within a predetermined numerical range) is set as an initial value and is input to the main control MPU 4100a. Based on the clock signal output from the main control crystal oscillator, which will be described later, other values within the predetermined numerical range are extracted one after another at high speed without duplication, and all the values within the predetermined numerical range are extracted. When this is completed, one value within the predetermined numerical range is extracted again, and the other values within the predetermined numerical range are extracted at high speed based on the clock signal input to the main control MPU4100a without duplication. Extract one after another. The main control built-in hard random number circuit 4100an repeatedly performs such a high-speed lottery, and the main control MPU 4100a hits the value extracted by the main control built-in hard random number circuit 4100an at the time of acquiring the value from the main control built-in hard random number circuit 4100an. It is designed to be set as a random number for judgment.

The main control input circuit 4100b is not provided with a reset terminal for forcibly resetting the information in which the detection signals from the various detection switches are input to the various input terminals, and does not have a reset function. Therefore, the main control input circuit 4100b is configured as a circuit in which the system reset signal from the main control system reset described later is not input. That is, in the main control input circuit 4100b, the information based on the detection signals from the various detection switches input to the various input terminals is not reset by the main control system reset described later, so that the various signals based on the information are various. It is configured as a circuit that is output from the output terminal.

The main control output circuit 4100c is configured as an open collector output type in which the emitter terminal is grounded to the ground (GND), and various signals for outputting various signals to an external board or the like are input to the various input terminals. The main control output circuit 4100ca with a reset function that has a reset function provided with a reset terminal for forcibly resetting the input information, and the main control output circuit 4100cc without a reset function that does not have a reset function without a reset terminal. It is composed of and. The main control output circuit 4100ca with a reset function is configured as a circuit to which a system reset signal from the main control system reset described later is input. That is, the main control output circuit 4100ca with a reset function is reset by the main control system reset described later, so that the information for outputting various signals input to the various input terminals to an external board or the like is reset. It is configured as a circuit in which signals based on the above are not output at all from the various output terminals. On the other hand, the main control output circuit 4100cc without a reset function is configured as a circuit in which a system reset signal from a main control system reset described later is not input. That is, the main control output circuit 4100cc without a reset function is converted to the information because the information for outputting various signals input to the various input terminals to an external board or the like is not reset by the main control system reset described later. It is configured as a circuit in which the based signal is output from its various output terminals.

The upper start port switch 3022 for detecting the game ball entering the upper start port 2101, the lower start port switch 2109 for detecting the game ball entering the lower start port 2102, and the general winning opening 2104 shown in FIG. The detection signal from the general winning port switch 3020 for detecting the entered game ball and the signal from the power failure monitoring circuit 4100e are input to the input terminal of the predetermined input port of the main control MPU 4100a via the main control input circuit 4100b. There is. Further, as shown in FIG. 8, the gate switch 2352 for detecting the game ball passing through the gate portion 2350, the general winning opening switch 3020 for detecting the game ball entering the general winning opening 2201, and the large winning opening 2103 are entered. The detection signals from the count switch 2110 that detects the game ball and the magnetic detection switch 3024 that is attached to the back unit 3000 shown in FIG. 9 and detects fraudulent activity using a magnet are relayed to the panel attached to the game board 4. It is input to the input terminal of a predetermined input port of the main control MPU 4100a via the terminal plate 4161 and the main control input circuit 4100b.

The main control MPU 4100a is a main control output circuit with a reset function by outputting a drive signal from the output terminal of the predetermined output port to the main control output circuit 4100ca with a reset function based on the detection signals from each of these switches. A control signal is output from the 4100ca to the main control solenoid drive circuit 4100d, and a drive signal is output from the main control solenoid drive circuit 4100d to the start port solenoid 2105 and the attacker solenoid 2108 via the panel relay terminal plate 4161, or a predetermined output thereof. By outputting a drive signal from the output terminal of the port to the main control output circuit 4100ca with a reset function, the upper special symbol display is displayed from the main control output circuit 4100ca with a reset function via the panel relay terminal board 4161 and the function display board 1191. 1185, lower special symbol display 1186, upper special symbol storage indicator 1184, lower special symbol storage indicator 1187, ordinary symbol display 1189, ordinary symbol storage indicator 1188, game status indicator 1183, and round indicator 1190 It outputs a drive signal.

Further, the main control MPU 4100a outputs various information (game information) related to the game from the output terminal of the predetermined output port to the main control output circuit 4100ca with a reset function, thereby controlling the payout from the main control output circuit 4100ca with a reset function. By outputting various information (game information) related to the game to the board 4110 and outputting a signal (power failure clear signal) to the main control output circuit 4100ca with a reset function from the output terminal of the predetermined output port, the main with a reset function. A signal (power failure clear signal) is output from the control output circuit 4100ca to the power failure monitoring circuit 4100e.

In the present embodiment, the upper start port switch 3022, the lower start port switch 2109, the gate switch 2352, and the count switch 2110 use a non-contact type electromagnetic proximity switch, whereas they are generally used. A contact type ON / OFF operation type mechanical switch is used for the winning opening switches 3020 and 3020. This is because the game ball frequently enters the upper start port 2101 and the lower start port 2102 and frequently passes through the gate portion 2350, so that the upper start port switch 3022, the lower start port switch 2109, and the gate switch 2352 are used. The detection of game balls also occurs frequently. Therefore, a proximity switch having a long life is used for the upper start port switch 3022, the lower start port switch 2109, and the gate switch 2352. Further, when a big hit game state that is advantageous for the player occurs, the big winning opening 2103 is opened and the game ball frequently enters, so that the count switch 2110 also frequently detects the game ball. Therefore, the count switch 2110 also uses a proximity switch having a long life. On the other hand, in the general winning openings 210 and 2201 in which the game ball does not enter frequently, the detection by the general winning opening switches 3020 and 3020 does not occur frequently. For this reason, mechanical switches having a shorter life than proximity switches are used for the general winning opening switches 3020 and 3020.

Further, the main control MPU 4100a sends various commands related to payout as serial data from the output terminal of the predetermined serial output port to the main control output circuit 4100 kb without a reset function, thereby controlling the payout from the main control output circuit 4100 cc without a reset function. Various commands are transmitted as serial data to the board 4110. When the payout control board 4110 normally completes receiving various commands from the main control board 4100 as serial data, the payout control board 4110 outputs a signal (payer ACK signal) to that effect to the main control board 4100. This signal (payer ACK signal) is input to the input terminal of a predetermined input port of the main control MPU 4100a via the main control input circuit 4100b.

Further, the main control MPU 4100a receives various commands related to the state of the pachinko gaming machine 1 from the payout control board 4110 as serial data in the main control input circuit 4100b, so that the main control input circuit 4100b can be used for the predetermined serial input port. Receive various commands as serial data at the input terminal. When the main control MPU 4100a normally receives various commands from the payout control board 4110 as serial data, the main control MPU 4100a outputs a signal (main payment ACK signal) to that effect from the output terminal of the predetermined output port with a reset function. It is output to the circuit 4100ca, and a signal (main payment ACK signal) is output from the main control output circuit 4100ca with a reset function to the payout control board 4110.

Further, the main control MPU 4100a transmits various commands related to the control of the game effect and various commands related to the state of the pachinko gaming machine 1 as serial data from the output terminal of the predetermined serial output port to the main control output circuit 4100 bc without the reset function. As a result, various commands are transmitted as serial data from the main control output circuit 4100cc without the reset function to the peripheral control board 4140.

Here, the main peripheral serial transmission port that transmits various commands as serial data to the peripheral control board 4140 will be briefly described. The main control MPU 4100a is configured around the main control CPU core 4100aa, and in addition to the main control built-in RAM, the main peripheral serial transmission port 4100ae, which is one of the main control serial I / O ports, provides a bus 4100ah. The circuit is connected via (see FIG. 23). The main peripheral serial transmission port 4100ae transmits various commands to the peripheral control board 4140 as main peripheral serial data, and is mainly composed of a transmission shift register 4100aea, a transmission buffer register 4100aeb, a serial management unit 4100aec, and the like (FIG. 6). 23). When the main control CPU core 4100aa sets a command in the transmission buffer register 4100aeb and outputs a transmission start signal to the serial management unit 4100aec, the serial management unit 4100aec outputs a command set in the transmission buffer register 4100aeb from the transmission buffer register 4100aeb. The data is transferred to the transmission shift register 4100ea and transmission is started to the peripheral control board 4140 as main peripheral serial data. In this embodiment, the transmission buffer register 4100aeb has 32 bytes as a storage capacity. The main control CPU core 4100aa continuously transmits a plurality of commands to the peripheral control board 4140 by outputting a transmission start signal to the serial management unit 4100aec after setting a plurality of commands in the transmission buffer register 4100aeb.

The power supply board 851 that supplies various voltages to the main control board 4100 is an electric double layer as a backup power source for supplying power to the main control board 4100 for a predetermined time (3 hours in this embodiment) even when the power is cut off. It is equipped with a multi-layer capacitor (hereinafter, simply referred to as “capacitor”) BC0 (see FIG. 18). The capacitor BC0 allows the main control MPU4100a to store various information in the main control built-in RAM in the power off processing even when the power is cut off. Various information stored in the main control built-in RAM is an operation signal (RAM clear signal) from the operation switch 860a when the operation switch 860a of the payout control board 4110 described later is operated within a predetermined period from the time when the power is turned on. Is output from the payout control board 4110, is input to the input terminal of the predetermined input port of the main control MPU 4100a via the main control input circuit 4100b, and is completely erased from the main control built-in RAM by the main control MPU 4100a. It is supposed to be (cleared).

[7-2. Payout control board]
As shown in FIG. 13, the payout control board 4110, which performs launch control and ball feed control of the game ball in addition to the payout control of the game ball, performs various controls related to payout and launch control and ball feed control of the game ball. It is provided with a payout control unit 4120, an operation switch 860a that also has various functions, and an error LED display 860b that displays the status of the pachinko gaming machine 1. Further, the operation switch 860a having a function as a RAM clear switch is described as a RAM built in the main control MPU 4100a (hereinafter, referred to as "main control built-in RAM") based on a detection signal output by being operated. .) Outputs a RAM clear signal for completely erasing the information stored in.

[7-2-1. Payout control unit]
As shown in FIG. 13, the payout control unit 4120, which performs various controls related to payout, launch control of the game ball, and ball feed control, controls the power-on processing executed at the time of power-on and is predetermined from the time of power-on. It is a microprocessor with a built-in various control programs including a payout control program that controls the payout operation of the game medium executed after a lapse of time, a ROM that stores various commands, and a RAM that temporarily stores data. The control MPU 4120a, the payout control input circuit 4120b in which the detection signals from various detection switches related to payout and the detection signals from various detection switches related to the launch of the game ball are input, and the payout for outputting various signals to an external board or the like. CR unit input / output for exchanging various signals between the control output circuit 4120c, the payout motor drive circuit 4120d for outputting a drive signal to the payout motor 744 of the prize ball device 740 shown in FIG. 5, and the CR unit 6. The circuit 4120e and the like are provided. The payout control MPU 4120a includes a launch ball feed control circuit 4120ag that controls launch by the launch solenoid 654 of the ball launch device 650 shown in FIG. 5 and ball feed control by the ball feed solenoid 585 of the ball feed unit 580 shown in FIG. , The launch ball feed failure monitoring circuit 4120ah, which monitors whether or not a defect has occurred in the launch ball feed control circuit 4120ag, is built in. Further, the payout control MPU4120a includes a built-in RAM (hereinafter, referred to as "payout control built-in RAM"), a built-in ROM thereof (hereinafter, referred to as "payout control built-in ROM"), and a built-in ROM. It also has a built-in watchdog timer that monitors its operation (system) and a function to prevent fraud.

The launch ball feed control circuit 4120ag built into the payout control MPU 4120a that performs launch control by the launch solenoid 654 and ball feed control by the ball feed solenoid 585 corresponds to the rotation position of the rotation handle main body front 506 shown in FIG. An operation signal from the potentiometer 512 that electrically adjusts the strength (launch strength) of launching the game ball toward the game area 1100, and a touch switch that detects whether or not the palm or finger is touching the front 506 of the rotating handle body. The detection signal from 516 and the detection signal from the launch stop switch 518 that detects whether or not the launch (launch) of the game ball is forcibly stopped by the player's will are the handle relay terminal board 192, the power supply board. It is input via the payout control input circuit 4120b of the payout control board 4110 and 851. Further, in the launch ball feed control circuit 4120ag, when the CR unit 6 and the game ball rental device connection terminal board 869 are electrically connected, a CR connection signal to that effect is sent to the CR unit input / output of the payout control board 4110. It is input via the circuit 4120e.

The launch ball feed control circuit 4120ag adjusts the drive current for launching (launching) the game ball toward the game area 1100 based on the operation signal from the potentiometer 512, and payout control output circuit 4120c (with a reset function described later). It is output to the power supply board 851 (launching solenoid drive circuit 858 described later) via the payout control output circuit 4120ca) to perform firing control by the firing solenoid 654, while the payout control output circuit 4120c (payout control with a reset function described later) is performed. The ball of the ball feed unit 580 is output to the power supply board 851 (ball feed solenoid drive circuit 859 described later) via the output circuit 4120ca) and a constant current is output to the ball feed solenoid 585 via the handle relay terminal plate 192. The feeding member receives one game ball stored in the upper plate 301 of the plate unit 300 shown in FIG. 7, and controls to send the game ball received by the ball feeding member to the hitting ball launching device 650 side.

The launch ball feed control circuit 4120ag operates according to the payout control program, and when the launch operation permission is set, the game ball is moved to the game area 1100 according to the rotation position of the rotation handle main body front 506 shown in FIG. An operation signal from the potentiometer 512 that electrically adjusts the intensity (launching intensity) to be launched toward, and a detection signal from the touch switch 516 that detects whether or not the palm or finger is touching the front 506 of the rotating handle body. The detection signal from the launch stop switch 518 that detects whether or not the launch (launch) of the game ball is forcibly stopped by the player's will, and the CR unit 6 and the game ball rental device connection terminal board 869 are electrically connected. The launch control of the game ball is performed based on the CR connection signal that conveys the fact that the game ball is connected. On the other hand, when the firing operation prohibition is set, the launch control of the game ball described above is forcibly stopped.

The launch control of the game ball by the launch ball feed control circuit 4120ag is such that the number of game balls that can be launched (launched) toward the game area 1100 per minute is 99.93 to 99.95. It is preset so that it does not exceed 100 balls. This is realized by a PWM circuit (not shown) for generating a PWM (Pulse Width Modulation) signal (not shown) built in the payout control MPU4120a. The pulse width of the PWM signal output from this circuit is such that the number of game balls that can be launched (launched) toward the game area 1100 per minute is 99.93 to 99.95. It is set in advance, and the circuit is connected so that this PWM signal is input to the launch ball feed control circuit 4120ag. The launch ball feed control circuit 4120ag measures the launch timing of the game ball based on the input PWM signal.

As described above, the launch ball feed defect monitoring circuit 4120ah monitors whether or not a defect has occurred in the launch ball feed control circuit 4120ag, and stores the monitoring result (whether or not a defect has occurred) as status information. It can be held. When the payout control program acquires status information from the launch ball feed defect monitoring circuit 4120ah and determines that a defect has occurred in the launch ball feed control circuit 4120ag, the payout control program controls the launch of the game ball by the launch ball feed control circuit 4120ag. In order to forcibly stop, the launch operation prohibition is set for the launch ball feed control circuit 4120ag.

In addition to when the power is turned on, the payout control program sets the launch operation prohibition for the launch ball feed control circuit 4120ag as the initial state (default) when a momentary power failure or power failure occurs and then the power is restored. After that, when the status information is acquired from the launch ball feed defect monitoring circuit 4120ah and it is determined that no defect has occurred in the launch ball feed control circuit 4120ag, the launch control of the game ball by the launch ball feed control circuit 4120ag is started. While setting the launch operation permission for the launch ball feed control circuit 4120ag, it fires when it is determined that a defect has occurred in the launch ball feed control circuit 4120ag by acquiring status information from the launch ball feed defect monitoring circuit 4120ah. In order to maintain the state in which the launch control of the game ball by the ball feed control circuit 4120ag is stopped, the launch operation prohibition is set for the launch ball feed control circuit 4120ag.

Here, as a defect in the launch ball feed control circuit 4120ag, it becomes difficult to adjust the drive current for launching (launching) the game ball toward the game area 1100 based on the operation signal from the potentiometer 512. If so, the operation signal from the potentiometer 512 is affected by noise and turns into an extremely disturbed signal, and the drive current for launching (launching) the game ball toward the game area 1100 cannot be specified, and the drive current cannot be specified. If it is difficult to adjust, the detection signal from the touch switch 516 is transformed into an extremely disturbed signal due to the influence of noise, and whether or not the player's palm or finger is touching the 506 in front of the rotating handle body. When it is difficult to identify the signal, the detection signal from the launch stop switch 518 is disguised as an extremely disturbed signal due to the influence of noise, and the player is forced to launch (launch) the game ball. In addition to the case where it is difficult to identify whether or not the signal is stopped, the launch ball feed control circuit 4120ag itself is destroyed for some reason and becomes unusable, or the game area per predetermined time. When the number of game balls launched (launched) toward 1100 exceeds a predetermined number (in the present embodiment, the number of game balls launched (launched) toward the game area 1100 per minute). (When is over 100 balls) and the like.

Under the control of the payout control MPU4120a, the payout control program sends various information (game information) related to the game from the main control board 4100 and various commands related to the payout as payer serial data transmission signals via the payout control I / O port 4120b. Receive serial data in a serial manner. Further, the payout control program generates a frame state 1 command (corresponding to the first error occurrence command) when an error occurs in the payout operation of the game ball, or operates the operation switch 860a as an error canceling unit. A 16-bit (2-byte) error release navigation command (corresponding to the first error release command) is created based on the signal (detection signal), and these error occurrence commands and error release navigation commands are transmitted to the payer serial data, respectively. As a signal, serial data is output to the receiving port of the main control board 4100 via the payout control I / O port 4120b (command transmission means). Further, this payout control program pays out after a predetermined time has elapsed from the time when the power is turned on, that is, after the payout control unit main process is executed or the payout control unit timer interrupt process is executed and the payout control is started. When an error occurs in operation, the error is canceled based on the detection signal generated by the operation of the operation switch 860a, and the output of warning information corresponding to the error is stopped (error cancellation control means).

Further, this payout control program outputs a door frame opening command (first door opening command) when a detection signal (door frame opening detection signal) accompanying the opening operation is input from the door frame opening switch 618. When a detection signal (main body frame opening detection signal) accompanying the opening operation is input from the main body frame opening switch 619, a main body frame opening command (first main body frame opening command) is output. On the other hand, this payout control program also issues a door frame closing command (first door frame closing command) when a detection signal (door frame closing detection signal) accompanying the closing operation is input from the door frame opening switch 618. At the same time, when the detection signal (main body frame closing detection signal) accompanying the closing operation is input from the main body frame opening switch 619, the main body frame closing command (first main body frame closing command) is output.

Further, when this payout control program acquires status information from the launch ball feed failure monitoring circuit 4120ah and determines that no defect has occurred in the launch ball feed control circuit 4120ag, the payout control program uses the launch ball feed control circuit 4120ag to determine that the game ball While setting the launch operation permission for the launch ball feed control circuit 4120ag to start the launch control, when it is determined that a problem has occurred in the launch ball feed control circuit 4120ag, a game by the launch ball feed control circuit 4120ag. In order to forcibly stop the launch control of the ball, the launch operation prohibition is set for the launch ball feed control circuit 4120ag.

The payout control input circuit 4120b is not provided with a reset terminal for forcibly resetting the information in which the detection signals from the various detection switches are input to the various input terminals, and does not have a reset function. Therefore, the payout control input circuit 4120b is configured as a circuit in which the system reset signal from the payout control system reset described later is not input. That is, in the payout control input circuit 4120b, the information based on the detection signals from the various detection switches input to the various input terminals is not reset by the payout control system reset described later, so that the various signals based on the information are various. It is configured as a circuit that is output from the output terminal.

The payout control output circuit 4120c is configured as an open collector output type in which the emitter terminal is grounded to the ground (GND), and various signals for outputting various signals to an external board or the like are input to the various input terminals. A payout control output circuit 4120ca with a reset function having a reset function provided with a reset terminal for forcibly resetting the input information, and a payout control output circuit 4120cc without a reset function having no reset function without a reset terminal. It is composed of and. The payout control output circuit 4120ca with a reset function is configured as a circuit to which a system reset signal from the payout control system reset described later is input. That is, the payout control output circuit 4120ca with a reset function is reset by the payout control system reset described later, so that the information for outputting various signals input to the various input terminals to an external board or the like is reset. It is configured as a circuit in which signals based on the above are not output at all from the various output terminals. On the other hand, the payout control output circuit 4120cc without a reset function is configured as a circuit in which a system reset signal from a payout control system reset, which will be described later, is not input. That is, the payout control output circuit 4120cc without a reset function is converted to the information because the information for outputting various signals input to the various input terminals to an external board or the like is not reset by the payout control system reset described later. It is configured as a circuit in which the based signal is output from its various output terminals.

The detection signals from the ball-out switch 750 that detects the presence or absence of a game ball in the supply passage of the prize ball device 740 and the counting switch 751 that detects the game ball flowing down in the prize ball passage of the prize ball device 740 are first awarded. It is input to the input terminal of a predetermined input port of the payout control MPU 4120a via the board 754 in the prize ball case of the ball device 740 and the payout control input circuit 4120b. The detection signals from the rotation angle switch 752 for detecting the detection slit formed in the rotation detection board of the prize ball device 740 are first, the rotation angle switch board 753 of the prize ball device 740, the board 754 in the prize ball case, and then. It is input to the input terminal of a predetermined input port of the payout control MPU 4120a via the payout control input circuit 4120b.

Further, the detection signal from the door frame opening switch 618 for detecting the opening of the door frame 5 with respect to the main body frame 3 and the main body frame opening switch 619 for detecting the opening of the main body frame 3 with respect to the outer frame 2 is the payout control input circuit 4120b. It is input to the input terminal of a predetermined input port of the payout control MPU4120a via the payout control MPU4120a.

Further, the detection signal from the full tank switch 550 that detects whether or not the game ball in which the accommodation space of the foul cover unit 540 shown in FIG. 1 is full is full is first the handle relay terminal board 192 and the power supply board. It is input to the input terminal of a predetermined input port of the payout control MPU 4120a via the payout control input circuit 4120b and 851.

The payout control MPU 4120a receives various commands related to payout from the main control board 4100 via the payout control input circuit 4120b by the serial data method at the input terminal of the serial input port, or the operation signal (detection) of the operation switch 860a. The signal) is output to the main control board 4100 via the payout control input circuit 4120b. When the payout control MPU4120a normally receives various commands from the main control board 4100 as serial data, a signal (payer ACK signal) to that effect is sent from the output terminal of the predetermined output port to the payout control output with a reset function. By outputting to the circuit 4120ca, a signal (payer ACK signal) is output from the payout control output circuit 4120ca with a reset function to the main control board 4100.

Further, the payout control MPU 4120a sends various commands for indicating the state of the pachinko game machine 1 as serial data from the output terminal of the serial output port to the payout control output circuit 4120 kb without the reset function, thereby paying out without the reset function. Various commands are transmitted as serial data from the control output circuit 4120 kb to the main control board 4100. When the main control board 4100 normally completes receiving various commands from the payout control board 4110 as serial data, the main control board 4100 outputs a signal (main payout ACK signal) to that effect to the payout control board 4110. This signal (main payment ACK signal) is input to the input terminal of a predetermined input port of the payout control MPU 4120a via the payout control input circuit 4120b.

Further, the payout control MPU 4120a outputs a drive signal for driving the payout motor 744 to the payout control output circuit 4120ca with a reset function from the output terminal of the predetermined output port, whereby the payout control output circuit 4120ca with a reset function is output. Outputs the drive signal from the payout motor drive circuit 4120d to the payout motor drive circuit 4120d, and outputs the drive signal from the payout motor drive circuit 4120d to the payout motor 744 via the board 754 in the prize ball case. By outputting the drive signal for displaying the status of the game machine 1 to the error LED display 860b to the payout control output circuit 4120ca with a reset function, the drive signal is output from the payout control output circuit 4120ca with a reset function to the error LED display 860b. Output to.

The error LED display 860b is a segment display, and displays alphanumeric characters, figures, and the like to display the status of the pachinko gaming machine 1. The contents displayed and notified by the error LED display 860b are as follows. For example, when the figure "-" is displayed, it is notified that it is "normal", and when the number "0" is displayed, it means that it is "connection abnormality" (specifically, with the main control board 4100). Notifies that there is an abnormality in the electrical connection between the payout control board 4110 and the board, and when the number "1" is displayed, it means that the ball is out (specifically, the ball is out). Based on the detection signal from the switch 750, it notifies that there is no game ball in the supply passage of the prize ball device 740, and when the number "2" is displayed, it means that it is a "ball" (specifically). Is that the payout rotating body and the game ball mesh with each other near the entrance of the distribution space communicating with the supply passage of the prize ball device 740 based on the detection signal from the rotation angle switch 752, and the payout rotating body is difficult to rotate. When the number "3" is displayed, it means that there is a "counting switch error" (specifically, a problem occurs in the counting switch 751 based on the detection signal from the counting switch 751). When the number "5" is displayed, it notifies that it is a "retry error" (specifically, that the number of retries of the payout operation has reached a preset upper limit). However, when the number "6" is displayed, it means that the tank is "full" (specifically, in a game ball in which the accommodation space of the foul cover unit 540 is stored based on the detection signal from the full tank switch 550. Notifies that the tank is full), and when the number "7" is displayed, it means that "CR is not connected" (the electrical connection is cut off at any of the payout control board 4110 to the CR unit 6). When the number "9" is displayed, it means "in stock (there is a prize ball stock (unpaid))" (specifically, the number of game balls that have not been paid out yet). Has reached a predetermined number of balls).

Further, the payout control MPU 4120a outputs the number of game balls actually paid out as prize balls to the payout control output circuit 4120ca with a reset function from the output terminal of the predetermined output port, thereby payout control with a reset function. The number of game balls actually paid out as prize balls is output from the output circuit 4120ca to the external terminal board 784 via a resistor (not shown).

Further, the payout control board 4110 outputs various information (game information) related to the game from the main control board 4100 to the external terminal board 784 via a resistor (not shown). In addition to the payout control board 4110, various information from the peripheral control board 4140 (the number of game balls to be paid out as prize balls, etc.) is also input to the external terminal board 784. The external terminal board 784 is provided with a plurality of photocouplers (which are configured by incorporating an infrared LED and a photo IC) (not shown), and the playground (hall) is provided through the plurality of photocouplers. ), The number of game balls and various other information (game information, error details related to the payout operation of the game balls, or the fact that there was an error) are transmitted to the hall computer installed in). The external terminal board 784 and the hall computer are electrically insulated by a plurality of photocouplers, and an abnormal voltage is applied to the hall computer via the external terminal board 784 of the pachinko gaming machine 1. The hall computer does not malfunction or break down, and the main control board 4100 that advances the game from the hall computer via the external terminal plate 784 of the pachinko gaming machine 1, the payout control board that controls payout, etc. An abnormal voltage is applied to the 4110 and the peripheral control board 4140 that controls the progress of the effect to prevent malfunction or failure. The hall computer includes the number of game balls actually paid out as prize balls by the pachinko game machine 1, the game information of the pachinko game machine 1, and the number of game balls scheduled to be paid out as prize balls by the pachinko game machine 1. By grasping the above, the game of the player and the payout information (so-called ball payout information) of the game ball by the payout operation of the pachinko gaming machine 1 are monitored.

The ball lending request signal for the game ball from the ball lending switch 365a of the ball lending unit 360 shown in FIG. 2 and the return request signal for the prepaid card from the return switch 365b are, first, the frequency display board 365 and the main door relay terminal board 880. , And the game ball or the like is input to the CR unit 6 via the connection terminal board 869 of the rental device. The CR unit 6 serially transmits a signal specifying the number of game balls to be rented according to the ball lending request signal to the payout control board 4110 via the game ball lending device connection terminal board 869, and this signal is the CR unit. It is input to the input terminal of a predetermined input port of the payout control MPU 4120a via the input / output circuit 4120e. Further, the CR unit 6 updates the remaining amount of the prepaid card inserted according to the number of rented game balls, and sends a signal for displaying the remaining amount on the remaining amount display 365c, such as a game ball. It is output to the rental device connection terminal board 869, the main door relay terminal board 880, and the frequency display board 365, and this signal is input to the residual frequency display 365c. Further, in the CR unit lamp 365d adjacent to the residual power display 365c, the supply voltage from the CR unit 6 is input via the game ball rental device connection terminal board 869 and the main door relay terminal board 880. There is.

The power supply board 851 that supplies various voltages to the payout control board 4110 is a capacitor BC1 as a backup power source for supplying power to the payout control board 4110 for a predetermined time (1 hour in this embodiment) even when the power is cut off. (See FIG. 18). With the capacitor BC1, the payout control MPU4120a can store various information in the payout control built-in RAM (payout storage unit) in the power off processing even when the power is cut off. When the operation switch 860a is operated within a predetermined period from the time when the power is turned on, the various information stored in the payout control built-in RAM is sent to a predetermined payout control MPU 4120a via the payout control input circuit 4120b. The payout control MPU4120a, which is input to the input terminal of the input port, determines as a RAM clear signal for completely erasing the information stored in the payout control built-in RAM. It is designed to be completely erased (cleared). This operation signal (RAM clear signal) is also output to the payout control output circuit 4120 cc without a reset function, and is also output to the main control board 4100 from the payout control output circuit 4120 cc without a reset function.

[7-2-2. Exchange of various signals with the terminal board for renting game balls, etc.]
Here, the exchange of various signals between the payout control unit 4120 and the CR unit 6 and the exchange of various signals between the CR unit 6 and the frequency display board 365 will be described with reference to FIG. As shown in FIG. 14, the game ball rental device connection terminal board 869 relays the electrical connection between the CR unit 6 and the payout control board 4110, and also includes the CR unit 6 and the frequency display board 365. (To be exact, the game ball rental device connection terminal board 869 is electrically connected to the frequency display board 365 via the main door relay terminal board 880. , The CR unit 6 and the game ball rental device connection terminal board 869 are electrically connected, the game ball rental device connection terminal board 869 and the main door relay terminal board 880 are electrically connected, and the main door relay. The terminal board 880 and the frequency display board 365 are electrically connected). Between the boards of the CR unit 6 and the game ball rental device connection terminal board 869, between the boards of the game ball rental device connection terminal board 869 and the payout control board 4110, the game ball rental device connection terminal board 869 and the main door relay The boards of the terminal board 880 and the boards of the game ball rental device connection terminal board 869 and the frequency display board 365 are electrically connected by each wiring (harness). Further, AC24V, which will be described later, from the power supply board 851 is supplied to the CR unit 6 via a game ball or the like rental device connection terminal board 869. The CR unit 6 creates a predetermined voltage VL (in this embodiment, DC + 12V (hereinafter referred to as “+ 12V”)) from the supplied AC24V by a built-in voltage creation circuit (not shown) together with the ground LG. , The game ball rental device connection terminal board 869 is supplied to the payout control board 4110, while the game ball rental device connection terminal board 869 and the main door relay terminal board 880 are supplied to the frequency display board 365. ..

The frequency display board 365 has a ball rental switch 365a, which is a push button switch, mounted on the component surface at a position corresponding to the ball rental button 361 of the ball rental unit 360 shown in FIG. 2, and the ball rental unit 360 is returned. A return switch 365b, which is a push button switch, is mounted at a position corresponding to the button 362, and a residual frequency indicator 365c, which is a segment display, is mounted at a position corresponding to the rental balance display unit 363 of the ball rental unit 360.

In the ball rental switch 365a and the return switch 365b, the ground LG from the CR unit 6 is electrically connected via the game ball rental device connection terminal board 869 and the main door relay terminal board 880. When the ball lending switch 365a is pressed, the ball lending switch 365a is switched on (ON), and the ball lending operation signal TDS from the ball lending switch 365a is sent to the main door relay terminal board 880 and the game. It is designed to be input to the CR unit 6 via the ball rental device connection terminal board 869. When the return button 362 is pressed, the return switch 365b is switched on (ON), and the return operation signal RES from the return switch 365b is connected to the main door relay terminal board 880 and the game ball rental device. It is designed to be input to the CR unit 6 via the terminal board 869.

The residual frequency indicator 365c has three segment indicators arranged side by side in a row, and three digits are driven by a so-called dynamic lighting method in which one digit segment indicator is sequentially driven among these three digit segment indicators. The segment display of is controlled to be lit. By such lighting control, the remaining frequency display 365c displays the remaining amount of the prepaid card inserted in the CR unit 6 and displays the error of the CR unit 6. The residual frequency indicator 365c is a digit signal DG0 to DG2 (three signals in total) for designating a one-digit segment display among the three-digit segment display, and the designated one-digit segment display. Segment drive signals SEG-A to SEG-G (7 signals in total) for designating the contents to be lit and displayed are from the CR unit 6 to the game ball rental device connection terminal board 869 and the main door relay terminal board. When input via 880, the 1-digit segment display is sequentially emitted according to the input digit signals DG0 to DG2 and the segment drive signals SEG-A to SEG-G, and these 3-digit segment indicators are emitted in sequence. The contents of the light emission can be visually recognized through the loan balance display unit 363.

A CR unit lamp 365d is mounted on the frequency display board 365 adjacent to the residual frequency display 365c. In this CR unit lamp 365d, a predetermined voltage VL from the CR unit 6 is input via a game ball or the like rental device connection terminal board 869 and a main door relay terminal board 880. The predetermined voltage VL is input to the CR unit 6 as a ball lending signal TDL through a current limiting resistor mounted on the game ball lending device connection terminal board 869 via the CR unit lamp 365d. When the CR unit 6 creates a predetermined voltage VL from AC24V supplied from the power supply board 851 by the built-in voltage creation circuit, and the ball lending switch 365a and the return switch 365b are in a valid ball lending state. Controls the logic of the ball lending signal TDL to make the CR unit lamp 365d emit light, and this light emission can be visually recognized through the loan remaining display unit 363. Further, the segment drive signals SEG-A to SEG-G are input to the residual power display 365c through the current limiting resistor mounted on the terminal board 869 for renting a game ball or the like.

In the CR unit 6, the ball lending button 361 is pressed and the ball lending operation signal TDS from the ball lending switch 365a is transmitted from the frequency display board 365 via the main door relay terminal board 880 and the game ball lending device connection terminal board 869. When input, BRDY, which is a ball lending request signal, is output to the payout control board 4110 (payout control MPU4120a) via the game ball or the like lending device connection terminal board 869. Then, the CR unit 6 is a single payout operation start request signal for paying out a predetermined number of loaned balls (in this embodiment, 25 balls, which corresponds to an amount of 100 yen) in one payout operation. The BRQ is output to the payout control board 4110 (payout control MPU 4120a) via the game ball or the like rental device connection terminal board 869. The payout control board 4110 (payout control MPU4120a) into which BRDY and BRQ are input sends an EXS, which is a signal for notifying that one payout operation has started or ended, to a game ball or the like rental device connection terminal board 869. PRDY, which is a signal for outputting to the CR unit 6 or for notifying that the payout operation for paying out the ball rental is possible or impossible, is transmitted to the game ball rental device connection terminal board. It is output to the CR unit 6 via 869. For example, if the hall clerk or the like presets the CR unit 6 so that 200 yen worth of game balls are paid out when the ball rental button 361 is pressed, one payout operation is performed. Is to be performed twice in a row, and if 25 balls for 100 yen are paid out, 25 balls for 100 yen will be paid out in succession, and 50 balls for a total of 200 yen will be paid out. Become.

In the CR unit 6, the return button 362 is pressed and the return operation signal RES from the return switch 365b is input from the frequency display board 365 via the main door relay terminal board 880 and the game ball rental device connection terminal board 869. The prepaid card is ejected from an insertion slot (not shown) and returned. The returned prepaid card stores the remaining amount obtained by subtracting the amount corresponding to the number of game balls paid out as a result of pressing the ball lending button 361.

[7-3. Power supply board]
Next, the power supply board 851 will be briefly described. The power supply board 851 includes a power supply switch 852 that is supplied from the Pachinko Island facility and can electrically connect or electrically cut off an AC 24 volt (AC24V), and a power supply control unit 855 that generates various power sources. , The launch solenoid drive circuit 858 for driving the launch solenoid 654 of the ball launching device 650 shown in FIG. 5, and the ball feed solenoid drive circuit for driving the ball feed solenoid 585 of the ball feed unit 580 shown in FIG. It is equipped with 859. The launch solenoid drive circuit 858 is controlled by the launch ball feed control circuit 4120ag built in the payout control MPU 4120a of the payout control board 4110, and launches the game ball toward the game area 1100 based on the operation signal from the potentiometer 512 (launch). The drive current to the firing solenoid 654 is adjusted so that it can be used. The ball feed solenoid drive circuit 859 is controlled by the launch ball feed control circuit 4120ag built in the payout control MPU 4120a of the payout control board 4110, and the ball feed member of the ball feed unit 580 is the upper plate of the dish unit 300 shown in FIG. The drive current to the ball feed solenoid 585 is adjusted to be a constant current so that one game ball stored in 301 can be received and the game ball received by the ball feed member can be sent to the hit ball launcher 650 side. It has become so.

[7-3-1. Power control unit]
The power control unit 855 improves the power factor of the power factor rectified by the synchronous rectifier circuit 855a and the synchronous rectifier circuit 855a in which the power switch 852 is operated to rectify the AC 24 volt (AC24V) supplied from the Pachinko Island facility. The power factor improvement circuit 855b, the smoothing circuit 855c for smoothing the power with the power factor improved by the power factor improvement circuit 855b, and various alternating currents for supplying the power smoothed by the smoothing circuit 855c to various substrates. It includes a power supply creation circuit 855d for creating a power source.

[7-4. Peripheral control board]
As shown in FIG. 15, the peripheral control board 4140 performs effect control based on various commands from the main control board 4100, and covers the display area of the upper plate side liquid crystal display device 470 shown in FIG. Peripheral area that exchanges control commands and various information (various data) with the touch panel drive board 450 that detects and controls the contact state of the capacitance type touch panel 480 provided and draws the display area of the upper plate side liquid crystal display device 470. While the control unit 4150, the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470 perform drawing control, the speaker box 820 shown in FIG. 5 provided on the main body frame 3 is performed. A liquid crystal and sound control unit 4160 that controls sounds such as music and sound effects flowing from the speaker housed in the door frame 5 and the speaker 130 provided in the door frame 5, calendar information for specifying the date, and time for specifying the hour, minute, and second. Music played from a real-time clock (hereinafter referred to as "RTC") control unit 4165 that holds information, a speaker housed in a speaker box 820 provided in the main body frame 3, and a speaker 130 provided in the door frame 5. It is provided with a volume adjusting volume 4140a for adjusting the volume of sound effects and the like by rotating a knob portion.

[7-4-1. Peripheral control unit]
As shown in FIG. 15, the peripheral control unit 4150 that performs the effect control controls the peripheral control MPU 4150a as a microprocessor and the power-on processing executed at the time of power-on, and after a predetermined time has elapsed from the time of power-on. From the peripheral control ROM 4150b that stores various control programs such as sub-control programs that are executed and control the production operation, various data, various control data, and various schedule data, and the VDP 4160a with a built-in sound source of the liquid crystal and sound control unit 4160 described later. Peripheral control unit that is executed each time a V-blank signal is input Various information that is continued across the steady processing (for example, schedule data that defines the screen to be drawn on the game board side liquid crystal display device 1900, light emission of various LEDs, etc. Peripheral control RAM 4150c that stores information for managing schedule data that defines the mode, etc., and various information that continues over days (for example, information for managing the history of occurrence of jackpot game states and special Peripheral control SRAM 4150d that stores information for managing various production flags, and peripheral control external watch dock timer 4150e (hereinafter, "peripheral control external" for monitoring whether peripheral control MPU4150a is operating normally WDT4150e ”) and the value transmitted by the power consumption suppression signal from the power supply board 851 (power consumption suppression stage described later) are sampled at a predetermined cycle via the frame peripheral relay terminal plate 868 (described as WDT4150e). (In the power consumption status history information creation process in the peripheral control unit 1ms timer interrupt processing described later) The power consumption of the power consumption status history RAM 4150f that is sequentially stored and held as the power consumption status history information and the power consumption of the power consumption status history storage unit 4150f when the power is turned off. When the power is turned off based on the battery 4150 g that supplies backup power to the power consumption status history storage unit 4150f so that the status history information is stored and the power consumption status history information stored and stored in the power consumption status history RAM 4150f ( Immediately before the power is turned off), the power status consumed by the pachinko game machine 1 is grasped at the time of power recovery, and the power consumed by the pachinko game machine 1 is suppressed. It is equipped with a notification LED 4150k.

The peripheral control RAM 4150c can hold the stored contents only for a period of time when a momentary power failure occurs and the power is immediately restored, and the power is cut off for a long time (when a long-time power failure occurs). ), The peripheral control SRAM 4150d is supplied with backup power by a large-capacity electrolytic capacitor (hereinafter, referred to as "electrolytic capacitor for SRAM") provided on the power supply board 851. As a result, the stored contents can be retained for about 50 hours. Since the power supply board 851 is provided with the electrolytic capacitor for SRAM, when the game board 4 is removed from the pachinko gaming machine 1, backup power is not supplied to the peripheral control SRAM 4150d. Therefore, the peripheral control SRAM 4150d has stored contents. Can no longer hold and lose its contents.

The peripheral control external WDT4150e is a timer for monitoring whether the system of the peripheral control MPU4150a is out of control, and when the timer is up, it is reset by hardware. That is, if the peripheral control MPU4150a does not output a clear signal for clearing the timer of the peripheral control external WDT4150e to the peripheral control external WDT4150e within a certain period of time (until the timer starts up), the peripheral control MPU4150a is reset. When the peripheral control MPU4150a outputs a clear signal to the peripheral control external WDT4150e within a certain period of time, the timer count of the peripheral control external WDT4150e can be restarted, so that the reset is not applied.

The peripheral control MPU 4150a has a plurality of parallel I / O ports, serial I / O ports, etc. built-in, and when various commands from the main control board 4100 are received, the figure provided on the game board 4 based on these various commands. Of the game balls scheduled to be paid out as prize balls based on the game balls entered in various winning ports such as the upper starting port 2101, the lower starting port 2102, the general winning opening 2104, 2201, and the large winning opening 2103 shown in 8. Every time the number of balls reaches a predetermined number of balls (in this embodiment, it is set to 10 balls), a main prize ball number information output signal for notifying that fact is transmitted from the parallel I / O port to the periphery (not shown). Output to the external terminal board 784 via the control output circuit, or consumed by the pachinko game machine 1 when the power is turned off (immediately before the power is turned off) based on the power consumption status history information stored and held in the power consumption status history RAM 4150f. The power saving mode information output signal for grasping the power status at the time of power recovery and suppressing the power consumed by the pachinko game machine 1 to convey the transition state to the power saving mode at the time of power recovery is not shown from the parallel I / O port. The game board side for outputting to the external terminal board 784 via the peripheral control output circuit, or outputting the lighting signal, blinking signal, or gradation lighting signal to a plurality of LEDs provided on each decorative board of the game board 4. Light emission data is transmitted from the serial I / O port for the lamp drive board to the lamp drive board 4170 via a peripheral control output circuit (not shown), and electrical such as motors and solenoids for operating various movable bodies provided on the game board 4. The game board side motor drive data for outputting the drive signal to the drive source is transmitted from the serial I / O port for the motor drive board to the motor drive board 4180 via the peripheral control output circuit, or is provided on the door frame 5. Door side motor drive data for outputting a drive signal to an electrical drive source such as a dial drive motor 414 is framed from a serial I / O port for a decorative drive amplifier board motor to a peripheral control output circuit, a frame peripheral relay terminal board 868, Then, it is transmitted to the frame decoration drive amplifier board 194 via the peripheral door relay terminal board 882, or outputs a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs provided on each decorative board of the door frame 5. The door side light emission data for the frame is transmitted from the serial I / O port for the frame decoration drive amplifier board LED to the frame decoration drive amplifier board 194 via the peripheral control output circuit, the frame peripheral relay terminal board 868, and the peripheral door relay terminal board 882. To detect and control the contact state of the touch panel 480. Control commands (for example, a detection control start command for starting the detection control of the touch state of the touch panel 480, a contact position data request command for requesting the position where the finger is touching the touch panel 480 (contact position data), power saving. Power saving mode transition command for transition to mode, etc. ) Is transmitted from the serial I / O port for the touch panel drive board to the touch panel drive board 450 via the peripheral control output circuit, the frame peripheral relay terminal board 868, and the peripheral door relay terminal board 882.

Various commands from the main control board 4100 are input to the main control board serial I / O port of the peripheral control MPU 4150a via a peripheral control input circuit (not shown). Further, a detection signal from a rotation detection switch for detecting the rotation (rotation direction) of the dial operation unit 401 and a pressure detection switch for detecting the operation of the pressing operation unit 405 provided on the operation unit 400. The detection signal is serialized by a door-side serial transmission circuit (not shown) provided on the frame decoration drive amplifier board 194, and the serialized operation unit detection data is transmitted from the door-side serial transmission circuit to the peripheral door relay terminal board 882 and the frame. It is input to the operation unit detection serial I / O port of the peripheral control MPU4150a via the peripheral relay terminal board 868 and the peripheral control input circuit. Further, the position where the finger is touching the touch panel 480 from the touch panel drive board 450 that detects and controls the contact state of the touch panel 480 via the peripheral door relay terminal board 882, the frame peripheral relay terminal board 868, and the peripheral control input circuit. (Contact position data) is serialized and input to the serial I / O port for the touch panel drive board of the peripheral control MPU4150a.

Detection signals from various detection switches (for example, a photo sensor) for detecting the original position, movable position, etc. of various movable bodies provided on the game board 4 are on the game board side (not shown) provided on the motor drive board 4180. It is serialized by the serial transmission circuit, and this serialized movable body detection data is input from the game board side serial transmission circuit to the serial I / O port for the motor drive board of the peripheral control MPU4150a via the peripheral control input circuit. There is. The peripheral control MPU 4150a exchanges various data between the peripheral control board 4140 and the motor drive board 4180 by switching the input / output of the serial I / O port for the motor drive board.

The peripheral control MPU4150a has a built-in watchdog timer (hereinafter referred to as "peripheral control built-in WDT"), and its own system runs out of control by using the peripheral control built-in WDT and the peripheral control external WDT4150e together. I am diagnosing whether or not it is.

[7-4-1a. Peripheral control MPU]
Next, the peripheral control MPU4150a, which is a microcomputer, will be described. As shown in FIG. 16, the peripheral control MPU 4150a is centered on the peripheral control CPU core 4150aa, has a peripheral control built-in RAM 4150ab, a peripheral control DMA (abbreviation of Direct Memory Access) controller 4150ac, a peripheral control bus controller 4150ad, and various peripheral control serials I. It is composed of a / O port 4150ae, a WDT4150af with built-in peripheral control, various parallel I / O ports for peripheral control 4150ag, a peripheral control analog / digital converter (hereinafter referred to as a peripheral control A / D converter) 4150ak, and the like.

Peripheral control CPU core 4150aa reads and writes various data to peripheral control built-in RAM 4150ab and peripheral control DMA controller 4150ac via internal bus 4150ah, while peripheral control various serial I / O ports 4150ae, peripheral control built-in WDT4150af, Peripheral control Various data are read and written to the various parallel I / O ports 4150ag and the peripheral control A / D converter 4150ak via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai.

Further, the peripheral control CPU core 4150aa reads various data to the peripheral control ROM 4150b via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the external bus 4150h, while the peripheral control RAM 4150c, the peripheral control SRAM 4150d, and the power supply. Various data are read / written from the consumption status history RAM 4150f via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the external bus 4150h.

The peripheral control DMA controller 4150ac includes storage devices such as peripheral control built-in RAM 4150ab, peripheral control ROM 4150b, peripheral control RAM 4150c, and peripheral control SRAM 4150d, peripheral control various serial I / O ports 4150ae, peripheral control built-in WDT4150af, and peripheral control parallel I. It is a dedicated controller that independently transfers data between the / O port 4150ag and the input / output device such as the peripheral control A / D converter 4150ak without going through the peripheral control CPU core 4150aa, and is DMA0. It has four channels, ~ DMA3.

Specifically, the peripheral control DMA controller 4150ac includes a storage device of the peripheral control built-in RAM 4150ab built in the peripheral control MPU 4150a, various peripheral control serial I / O ports 4150ae built in the peripheral control MPU 4150a, and a peripheral control built-in WDT4150af. , Peripheral control Various parallel I / O ports 4150ag, and input / output devices such as peripheral control A / D converter 4150ak, to perform data transfer independently without going through the peripheral control CPU core 4150aa. In addition, while reading and writing to the storage device of the RAM 4150ab with built-in peripheral control via the internal bus 4150ah, various serial I / O ports 4150ae with peripheral control, WDT4150af with built-in peripheral control, parallel I / O ports 4150ag with peripheral control, and Reads and outputs to / from an input / output device such as a peripheral control A / D converter 4150ak via the peripheral control bus controller 4150ad and the peripheral bus 4150ai.

Further, the peripheral control DMA controller 4150ac includes a storage device such as a peripheral control ROM 4150b, a peripheral control RAM 4150c, and a peripheral control SRAM 4150d externally attached to the peripheral control MPU 4150a, and various peripheral control serial I / Os built in the peripheral control MPU 4150a. Between the O port 4150ae, the WDT4150af with built-in peripheral control, the various parallel I / O ports 4150ag for peripheral control, and the input / output devices such as the peripheral control A / D converter 4150ak, without going through the peripheral control CPU core 4150aa. In order to perform data transfer independently, while reading and outputting to storage devices such as the peripheral control ROM 4150b, the peripheral control RAM 4150c, and the peripheral control SRAM 4150d via the peripheral control bus controller 4150ad and the external bus 4150h, various peripheral controls are performed. For input / output devices such as serial I / O port 4150ae, WDT4150af with built-in peripheral control, various parallel I / O ports for peripheral control, and peripheral control A / D converter 4150ak, via peripheral control bus controller 4150ad and peripheral bus 4150ai. Read and write.

The peripheral control bus controller 4150ad controls the internal bus 4150ah, the peripheral bus 4150ai, and the external bus 4150h to control the central processing device of the peripheral control MPU core 4150aa, the peripheral control built-in RAM 4150ab, the peripheral control ROM 4150b, the peripheral control RAM 4150c, and the peripheral control. Various devices such as a storage device such as SRAM 4150d, various peripheral control serial I / O ports 4150ae, WDT4150af with built-in peripheral control, various parallel I / O ports 4150ag for peripheral control, and input / output devices such as peripheral control A / D converter 4150ak. It is a dedicated controller that exchanges various data between them.

Peripheral control Various serial I / O ports 4150ae are a serial I / O port for a lamp drive board, a serial I / O port for a motor drive board, a serial I / O port for a frame decoration drive amplifier board motor, and a frame decoration drive amplifier board LED. Serial I / O port for frame decoration drive amplifier board Motor serial I / O port, main control board serial I / O port, operation unit information acquisition serial I / O port, touch panel drive board serial I / O Has a port.

The peripheral control built-in watchdog timer (WDT with built-in peripheral control) 4150af is a timer for monitoring whether the system of the peripheral control MPU 4150a is out of control. It has become. That is, the peripheral control CPU core 4150aa is reset when the watchdog timer is started and the clear signal for clearing the timer is not output to the peripheral control built-in WDT4150af within a certain period (until the timer is up). Will be required. When the peripheral control CPU core 4150aa starts the watchdog timer and outputs a clear signal to the peripheral control built-in WDT4150af within a certain period of time, the timer count can be restarted, so that the reset is not applied.

Peripheral control Various parallel I / O ports 4150ag output various latch signals such as a game board side motor drive latch signal and a door side motor drive light emission latch signal, as well as output a clear signal to the peripheral control external WDT4150e, and play games. It is paid out as a prize ball based on the game balls entered in various winning openings such as the upper starting opening 2101, the lower starting opening 2102, the general winning opening 2104, 2201, and the large winning opening 2103 provided on the board 4. Main prize ball number information as main prize ball number information for notifying each time the number of game balls to be played reaches a predetermined number of balls (10 balls are set in this embodiment). The power consumed by the pachinko game machine 1 when the power is turned off (immediately before the power is turned off) based on the power consumption status history information stored in the power consumption status history RAM 4150f and outputting the output signal to the external terminal board 784. The power saving mode information output signal is output to the external terminal board 784 as the power saving mode information for transmitting the transition state to the power saving mode at the time of power recovery by grasping the situation at the time of power recovery and suppressing the power consumed by the pachinko game machine 1. Alternatively, the detection signals from various detection switches for detecting the original position, movable position, etc. of various movable bodies provided on the game board 4 are serialized by a serial transmission circuit on the game board side (not shown) provided on the motor drive board 4180. , Output the movable body information acquisition latch signal for receiving this serialized movable body detection data from the serial transmission circuit on the game board side at the serial I / O port for the motor drive board of the peripheral control MPU4150a, or output the door frame 5 The lighting signal of the LED mounted on the upper decorative substrate of the upper decorative unit 280 in the above is output. This LED is a high-brightness white LED, and is a confirmation lamp for notifying that the occurrence of the big hit game state is confirmed. In the present embodiment, the path between the LED and the peripheral control parallel I / O ports 4150ag is shortened by adopting a configuration in which the LED and the peripheral control various parallel I / O ports 4150ag are directly connected electrically. It is possible to take noise countermeasures for LED lighting control, which has a heavy meaning in terms of games. The output control of the main prize ball number information output signal, the output control of the power saving mode information output signal, and the LED lighting control are executed in the peripheral control unit 1 ms timer interrupt process described later. Further, the lighting control of other LEDs and the like other than the LED that is controlled to be lit in the peripheral control unit 1ms timer interrupt processing, which will be described later, is executed in the peripheral control unit steady processing, which will be described later.

The peripheral control A / D converter 4150ak is electrically connected to the volume adjustment volume 4140a, and the resistance value is changed by rotating the knob portion of the volume adjustment volume 4140a, and the resistance at the rotation position of the knob portion is changed. The voltage divided by the value is converted from an analog value to a digital value and converted into a value in 1024 steps from a value to a value of 1023. In the present embodiment, the value of 1024 steps is divided into seven and managed as the substrate volumes 0 to 6. The board volume 0 is set to mute, the board volume 6 is set to the maximum volume, and the volume is set to increase from the board volume 0 to the board volume 6. The liquid crystal and the sound control unit 4160 (VDP4160a with a built-in sound source, which will be described later) are controlled so that the volume is set to the board volumes 0 to 6, and the speaker and the door frame 5 housed in the speaker box 820 provided in the main body frame 3 Music and sound effects are played from the provided speaker 130. In this way, music and sound effects flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 by adjusting the volume based on the rotation operation of the knob portion. ..

In the present embodiment, in addition to music and sound effects, a notification sound for notifying the clerk of the hall of a malfunction of the pachinko game machine 1 or an illegal act against the pachinko game machine 1, contents related to the game production, etc. (For example, the screen unfolded on the liquid crystal display device 1900 on the game board side is produced as more powerful, or the player is likely to be in a favorable gaming state. The notification sound for) also flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, but the notification sound and the notification sound are adjusted in volume based on the rotation operation of the knob portion. It is a mechanism that flows independently of the sound, and the volume from mute to maximum volume can be adjusted by controlling the liquid crystal and sound control unit 4160 (VDP4160a with built-in sound source, which will be described later) by a program. .. The volume adjusted by this program is different from the substrate volume divided into the above-mentioned seven stages, and can smoothly change from mute to maximum volume. As a result, for example, even when a hall clerk or the like rotates the knob portion of the volume adjustment volume 4140a to set the volume low, the speaker and the door housed in the speaker box 820 provided in the main body frame 3 Although the production sounds such as music and sound effects flowing from the speaker 130 provided in the frame 5 are reduced, the volume is loud when the pachinko gaming machine 1 has a problem or when the player is cheating. In the form, the notification sound set to the maximum volume) can be played. Therefore, even if the volume of the effect sound is reduced, it is possible to prevent the hall clerk and the like from being less likely to notice the occurrence of a problem or the cheating of the player due to the notification sound. In addition, based on the current board volume set by adjusting the volume based on the rotation operation of the knob, the volume at which the advertising sound is played is reduced so as not to interfere with music and sound effects, while the advertising sound is played. In addition to music and sound effects, there is a possibility that the screen unfolded by the liquid crystal display device 1900 on the game board side will be produced as more powerful, or the game will shift to a game state that is advantageous to the player. You can also announce that it is expensive.

[7-4-1b. Peripheral control ROM]
The peripheral control ROM 4150b stores in advance various control programs, various data, various control data, and various schedule data for controlling the peripheral control unit 4150, the liquid crystal and sound control unit 4160, the RTC control unit 4165, and the like. For various schedule data, screen generation schedule data for generating screens to be drawn on the game board side liquid crystal display device 1900, movable liquid crystal display devices 1925a to 1925d, and precision plate side liquid crystal display device 470, and light emission modes of various LEDs are generated. Schedule data for generating light emission modes, schedule data for generating sounds such as music and sound effects, schedule data for electric drive sources that generate drive modes for electric drive sources such as motors and solenoids, and prize balls. The main prize that generates the main prize ball information output signal for transmitting to the hall computer as the main prize ball information that the number of planned game balls has reached a predetermined number (10 balls in this embodiment). There is schedule data for the ball information output signal. The screen generation schedule data is composed of screen data that defines the screen configuration arranged in chronological order. The game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. The order of the screens to be drawn is specified. The light emission mode generation schedule data is configured by arranging light emission data defining the light emission modes of various LEDs in a time series. The sound generation schedule data is composed of sound command data arranged in chronological order, and the order in which music and sound effects are played is defined. The sound command data includes an output channel number for instructing which output channel to use among a plurality of output channels in the built-in sound source of the sound source built-in VDP4160a of the liquid crystal and the sound control unit 4160, which will be described later, and the sound source built-in VDP4160a. Of the plurality of tracks in the built-in sound source of the above, a track number for instructing which track to incorporate sound data such as music and sound effects is specified. The electric drive source schedule data is composed of drive data of electric drive sources such as motors and solenoids arranged in chronological order, and the operation of electric drive sources such as motors and solenoids is specified. The schedule data for the main prize ball information output signal is holed as the main prize ball information that the number of game balls to be paid out as prize balls has reached a predetermined number (10 balls in this embodiment). The output waveform data for generating the main prize ball information output signal to be transmitted to the computer is arranged in chronological order, and the output waveform of the main prize ball information output signal is defined.

Some of the control programs stored in the peripheral control ROM 4150b are directly read from the peripheral control ROM 4150b and executed, and some are copied to the various control program copy areas of the peripheral control RAM 4150c described later when the power is turned on. Some of them are read out and executed. Further, various data, various control data, and various schedule data stored in the peripheral control ROM 4150b may be read directly from the peripheral control ROM 4150b, or when the power is turned on in the various control data copy areas of the peripheral control RAM 4150c described later. In some cases, the copy is read out.

Further, the peripheral control ROM 4150b is used as one of various control programs for controlling the RTC control unit 4165 to correct the brightness of the liquid crystal display device 1900 on the game board side according to the usage time of the liquid crystal display device 1900 on the game board side. A brightness correction program is included. This brightness correction program corrects the decrease in brightness due to aging of the liquid crystal display device 1900 on the game board side when the backlight of the liquid crystal display device 1900 on the game board side is an LED type. , The date and time when the liquid crystal display device 1900 on the game board side was first turned on, the current date and time, the brightness setting information, etc. are acquired from the built-in RAM of the RTC control unit 4165, which will be described later, and the acquired brightness setting information is based on the correction information. To correct. This correction information is stored in advance in the peripheral control ROM 4150b. As will be described later, the brightness setting information includes brightness adjustment information for adjusting the brightness of the LED, which is the backlight of the game board side liquid crystal display device 1900, in 5% increments, and presently. The brightness of the LED that is the backlight of the game board side liquid crystal display device 1900 that has been set is included. For example, the date and time when the game board side liquid crystal display device 1900 is first turned on and the current date and time. Therefore, if six months have already passed since the date and time when the power of the game board side liquid crystal display device 1900 was first turned on, the corresponding correction information (for example, 5%) is acquired from the peripheral control ROM 4150b and the brightness is increased. When the brightness of the LED included in the setting information is 75% and the backlight of the game board side liquid crystal display device 1900 is turned on, the brightness is 80%, which is an additional 5% of the correction information acquired for this 75%. The brightness of the backlight of the game board side liquid crystal display device 1900 is adjusted and turned on based on the brightness adjustment information included in the brightness setting information, and the power is turned on from the date and time when the game board side liquid crystal display device 1900 is first turned on. If December has already passed, the corresponding correction information (for example, 10%) is acquired from the peripheral control ROM 4150b, and the brightness of the LED included in the brightness setting information is 75%, and the liquid crystal display device on the game board side. When the 1900 backlight is turned on, the game board is based on the brightness adjustment information included in the brightness setting information so that the brightness is 85%, which is an additional 10% of the correction information acquired for this 75%. The brightness of the backlight of the side liquid crystal display device 1900 is adjusted and turned on.

[7-4-1c. Peripheral control RAM]
As shown in FIG. 16, the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a is a backup that exclusively stores various information that is updated by executing various control programs and is to be backed up. It is stored in the management target work area 4150ca, the backup first area 4150cc and the backup second area 4150cc, and the peripheral control ROM 4150b, which exclusively store the copy of various information stored in the backup management target work area 4150ca. Various control program copy areas 4150cd that exclusively store copies of various control programs, and various data, various control data, various schedule data, etc. stored in the peripheral control ROM 4150b are copied. Various control data copy areas 4150ce that are exclusively stored, and backup unmanaged work area 4150cf that exclusively stores information that is not backed up among various information that is updated when various control programs are executed. Is provided.

When the power of the pachinko gaming machine 1 is turned on (including when the power is restored due to a momentary power failure or a power failure), a value of 0 is forcibly written to the backup unmanaged work area 4150 cf and cleared to zero. For the backup management target work area 4150ca, backup first area 4150cc, and backup second area 4150cc, the power-on state command (see FIG. 40) from the main control board 4100 clears the RAM when the pachinko gaming machine 1 is powered on. It instructs the start of the effect and the game state (for example, it instructs the start of the effect when the operation switch 860a shown in FIG. 12 is operated within a predetermined period from the time when the power is turned on). When is, it is cleared to zero.

The backup management target work area 4150ca is various information updated in the peripheral control unit steady processing executed every time a V blank signal is input from the sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160, which will be described later. Bank0 (1fr) that exclusively stores 1fr) as a backup target, and effect information (1ms) that is various information updated in the peripheral control unit 1ms timer interrupt processing that is executed every time a 1ms timer interrupt, which will be described later, occurs. It is composed of Bank0 (1 ms), which is exclusively stored as a backup target. Here, to briefly explain the names of Bank0 (1fr) and Bank0 (1ms), "Bank" is a minimum management unit representing the size of a storage area for storing various information, and is referred to as "Bank". The following "0" means that it is a normally used storage area for storing various information updated by executing various control programs. That is, "Bank 0" means that the size of the storage area normally used is set as the minimum management unit. The "Bank1", "Bank2", "Bank3", and "Bank4" provided in the area extending from the backup first area 4150 cc to the backup second area 4150 cc, which will be described later, are the same storage areas as the "Bank0". It means that it has a size. In "(1fr)", as will be described later, the VDP4160a with a built-in sound source displays drawing data for one screen (one frame) of the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device. When it is output to 470, a V blank signal indicating that the screen data from the peripheral control MPU 4150a can be accepted is output to the peripheral control MPU 4150a, so that every time the V blank signal is input, it is output. In other words, since the peripheral control unit routine processing is executed every frame (1 frame), it is added to "Bank0", "Bank1", "Bank2", "Bank3", and "Bank4", respectively ( The effect information (1fr) and the effect backup information (1fr) described later are also used with the same meaning). As described later, "(1ms)" is defined as "Bank0", "Bank1", "Bank2", "Bank3", since the peripheral control unit 1ms timer interrupt processing is executed every time a 1ms timer interrupt is generated. And "Bank 4", respectively (the effect information (1 ms) and the effect backup information (1 ms) described later are also used with the same meaning).

Bank0 (1fr) includes a lamp drive board side transmission data storage area 4150caa, a frame decoration drive amplifier board side LED transmission data storage area 4150cab, a reception command storage area 4150cac, an RTC information acquisition storage area 4150cad, and a schedule data storage area 4150cae. Etc. are provided. The game board side light emission data SL-DAT for outputting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs provided on each decorative board of the game board 4 in the transmission data storage area 4150ca on the lamp drive board side. Is a storage area in which is set, and in the transmission data storage area 4150cab for the LED on the frame decoration drive amplifier board side, a lighting signal, a blinking signal, or a gradation lighting for a plurality of LEDs provided on each decoration board of the door frame 5 is lit. It is a storage area in which the door-side light emission data STL-DAT for outputting a signal is set, and in the reception command storage area 4150cc, various commands transmitted from the main control board 4100 are received and the received various commands are stored. It is a storage area to be set, and the RTC information acquisition storage area 4150cad is a storage area in which various information acquired from the RTC control unit 4165 (RTC built-in RAM4165aa of RTC41654a described later) is set, and is set in the schedule data storage area 4150cae. Is a storage area in which various schedule data corresponding to the received command are set based on the command received from the main control board 4100 (main control MPU 4100a). In the schedule data storage area 4150cae, various schedule data copied from the peripheral control ROM 4150b to the various control data copy areas 4150ce are read and set, and various schedule data are directly read from the peripheral control ROM 4150b. Some are set.

In Bank 0 (1 ms), a frame decoration drive amplifier board side motor transmission data storage area 4150 caf, a motor drive board side transmission data storage area 4150 cag, a movable body information acquisition storage area 4150 cah, an operation unit information acquisition storage area 4150 cai, and drawing. A state information acquisition storage area 4150 kk and the like are provided. In the transmission data storage area 4150 caf for the frame decoration drive amplifier board side motor, the door side motor drive data STM-DAT for outputting a drive signal to an electric drive source such as the dial drive motor 414 provided in the door frame 5 is provided. It is a storage area to be set, and is for outputting a drive signal to an electric drive source such as a motor or a solenoid for operating various movable bodies provided on the game board 4 in the transmission data storage area 4150 cg on the motor drive board side. It is a storage area in which the motor drive data SM-DAT on the game board side is set, and the movable body information acquisition storage area 4150cah is provided in the game board 4 based on the detection signals from various detection switches provided in the game board 4. It is a storage area in which various information acquired such as the original position and the movable position of various movable bodies is set, and the operation unit information acquisition storage area 4150 kai is based on detection signals from various detection switches provided in the operation unit 400. Dial operation unit 401 created based on various information acquired from the rotation (rotation direction) of the dial operation unit 401 and the operation of the pressing operation unit 405 (for example, detection signals from various detection switches provided in the operation unit 400). The rotation (rotation direction) history information and the operation history information of the pressing operation unit 405 are set in the storage area. In the drawing state information acquisition storage area 4150k, the touch panel drive board 450 is used as the peripheral control board 4140. When drawing data from the sound source built-in VDP4160a is received and it is determined that the received drawing data is abnormal data, the peripheral control board 4140 and the touch panel drive board 450 are output based on the LOCKN signal to be described later to convey that fact. It is a storage area in which various information obtained by acquiring the frequency of defects and the occurrence state of defects during connection with is set.

Bank0 (1fr) lamp drive board side transmission data storage area 4150caa, frame decoration drive amplifier board side LED transmission data storage area 4150cab, and Bank0 (1ms) frame decoration drive amplifier board side motor transmission data storage area 4150caf. The transmission data storage area 4150 cg on the motor drive board side is divided into two areas, a first area and a second area, respectively.

In the lamp drive board side transmission data storage area 4150caa, when the peripheral control unit steady processing described later is executed, the game board side light emission data SL-DAT is set in the first area of the lamp drive board side transmission data storage area 4150caa. When the next peripheral control unit steady processing is executed, the game board side light emission data SL-DAT is set in the second area of the lamp drive board side transmission data storage area 4150caa, and the peripheral control unit steady processing. Each time the process is executed, the game board side light emitting data SL-DAT is alternately set in the first area and the second area of the lamp drive board side transmission data storage area 4150caa. Peripheral control unit steady processing is executed. For example, when the game board side light emission data SL-DAT is set in the second area of the lamp drive board side transmission data storage area 4150caa in the current peripheral control unit steady processing, the previous peripheral area is executed. When the control unit steady-state processing is executed, the processing proceeds based on the game board side light emission data SL-DAT set in the first area of the lamp drive board side transmission data storage area 4150caa.

When the peripheral control unit steady processing is executed, the frame decoration drive amplifier board side LED transmission data storage area 4150cab is placed in the first area of the frame decoration drive amplifier board side LED transmission data storage area 4150cab. When -DAT is set and the next peripheral control unit steady processing is executed, the door side light emission data STL-DAT is set in the second area of the transmission data storage area 4150cab for the frame decoration drive amplifier board side LED. The door side emission data STL-DAT is alternately set in the first area and the second area of the frame decoration drive amplifier board side LED transmission data storage area 4150cab every time the peripheral control unit steady processing is executed. NS. Peripheral control unit steady processing is executed, for example, when the door side light emission data STL-DAT is set in the second area of the frame decoration drive amplifier board side LED transmission data storage area 4150cab in the peripheral control unit steady processing this time. When the previous peripheral control unit steady processing is executed, the processing proceeds based on the door side emission data STL-DAT set in the first area of the transmission data storage area 4150cab for the frame decoration drive amplifier board side LED. It has become.

The frame decoration drive amplifier board side motor transmission data storage area 4150 caf is opened to the first area of the frame decoration drive amplifier board side motor transmission data storage area 4150 caf when the peripheral control unit 1 ms timer interrupt process described later is executed. When the side motor drive data STM-DAT is set and the next peripheral control unit 1 ms timer interrupt process is executed, the door side motor drive data STM is stored in the second area of the frame decoration drive amplifier board side motor transmission data storage area 4150 caf. -DAT is set, and each time the peripheral control unit 1ms timer interrupt processing is executed, the door side is in the first and second areas of the transmission data storage area 4150 caf for the frame decoration drive amplifier board side motor. Motor drive data STM-DAT are set alternately. Peripheral control unit 1ms timer interrupt processing is executed. For example, in the peripheral control unit 1ms timer interrupt processing this time, the door side motor drive data STM-DAT is stored in the second area of the frame decoration drive amplifier board side motor transmission data storage area 4150 caf. When set, the door side motor drive data STM-DAT set in the first area of the frame decoration drive amplifier board side motor transmission data storage area 4150 caf when the previous peripheral control unit 1 ms timer interrupt process was executed. The process is to proceed based on this.

When the peripheral control unit 1 ms timer interrupt process is executed, the motor drive board side transmission data storage area 4150 cag sets the game board side motor drive data SM-DAT in the first area of the motor drive board side transmission data storage area 4150 cag. Then, when the next peripheral control unit 1 ms timer interrupt process is executed, the game board side motor drive data SM-DAT is set in the second area of the motor drive board side transmission data storage area 4150 cag. Every time the peripheral control unit 1ms timer interrupt process is executed, the game board side motor drive data SM-DAT is alternately set in the first area and the second area of the motor drive board side transmission data storage area 4150 cag. Peripheral control unit 1ms timer interrupt processing is executed. For example, in the peripheral control unit 1ms timer interrupt processing this time, the game board side motor drive data SM-DAT is set in the second area of the motor drive board side transmission data storage area 4150 cag. Occasionally, when the previous peripheral control unit 1 ms timer interrupt process is executed, the process proceeds based on the game board side motor drive data SM-DAT set in the first area of the motor drive board side transmission data storage area 4150 cg. It has become like.

Next, the backup first area 4150 cc and the backup second area 4150 cc, which exclusively store the copy of the effect information which is various information stored in the backup management target work area 4150ca, will be described. In the backup first area 4150 cc and the backup second area 4150 cc, two pairs with two banks as one pair are managed as one page. The effect information (1fr), which is the content stored in Bank0 (1fr), which is a normally used storage area, is used as the effect backup information (1fr) every time the peripheral control unit steady processing is executed for each frame (1frame). The effect information (1 ms) is copied to the backup first area 4150 cc and the backup second area 4150 cc by the peripheral control DMA controller 4150ac at high speed and is stored in the normally used storage area Bank0 (1 ms). Is used as the effect backup information (1 ms) by the peripheral control DMA controller 4150ac in the backup first area 4150 cc and the backup second area 4150 cc each time the peripheral control unit 1 ms timer interrupt process is executed every time a 1 ms timer interrupt is generated. It is copied at high speed. Consistency of one page is determined by whether or not the contents of the two banks constituting the page match.

Specifically, in the backup first area 4150cc, Bank1 (1fr) and Bank2 (1fr) are set as one pair, and Bank1 (1ms) and Bank2 (1ms) are set as one pair, for a total of two pairs managed as one page. ing. The contents stored in Bank0 (1fr), which is a normally used storage area, are stored in Bank1 (1fr) and Bank2 (1fr) every time the peripheral control unit routine processing is executed for each frame (1frame). The memory that is copied at high speed by the controller 4150ac and stored in Bank0 (1ms), which is a normally used storage area, is stored every time a 1ms timer interrupt is generated and every time the peripheral control unit 1ms timer interrupt processing is executed. It is copied to Bank1 (1ms) and Bank2 (1ms) at high speed by the peripheral control DMA controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank1 (1fr) and Bank2 (1fr) match. This is performed depending on whether or not the contents of Bank 1 (1 ms) and Bank 2 (1 ms) match.

Further, in the backup second area 4150cc, Bank3 (1fr) and Bank4 (1fr) are set as one pair, and Bank3 (1ms) and Bank4 (1ms) are set as one pair, so that a total of two pairs are managed as one page. The content stored in Bank0 (1fr), which is a normally used storage area, is stored in Bank3 (1fr) and Bank4 (1fr) every time the peripheral control unit routine processing is executed for each frame (1frame). The memory that is copied at high speed by the controller 4150ac and stored in Bank0 (1ms), which is a normally used storage area, is stored every time a 1ms timer interrupt is generated and every time the peripheral control unit 1ms timer interrupt processing is executed. It is copied to Bank3 (1ms) and Bank4 (1ms) at high speed by the peripheral control DMA controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank3 (1fr) and Bank4 (1fr) match. This is performed depending on whether or not the contents of Bank 3 (1 ms) and Bank 4 (1 ms) match.

As described above, in the present embodiment, the backup first area 4150 kb has Bank 1 (1 fr) and Bank 2 (1 fr) as one pair, and Bank 1 (1 ms) and Bank 2 (1 ms) as one pair, for a total of two pairs. It is an area for managing as a page, and the backup second area 4150cc has Bank3 (1fr) and Bank4 (1fr) as one pair, and Bank3 (1ms) and Bank4 (1ms) as one pair, for a total of two pairs. This is an area for managing as one page. Different ID coats are stored at the beginning and end of each page, that is, at the beginning and end of the backup first area 4150cc and the backup second area 4150cc.

Further, in the present embodiment, the effect information (1fr), which is the content stored in the normally used storage area Bank0 (1fr), is used as the effect backup information (1fr) in the peripheral control unit for each frame (1frame). Each time a steady process is executed, the contents are copied to the backup first area 4150 cc and the backup second area 4150 cc at high speed by the peripheral control DMA controller 4150ac, and are stored in Bank0 (1 ms), which is a normally used storage area. The effect information (1 ms) is the effect backup information (1 ms), and each time a 1 ms timer interrupt is generated and each time the peripheral control unit 1 ms timer interrupt process is executed, the backup first area 4150 cc and the backup second area 4150 cc The peripheral control DMA controller 4150ac makes a high-speed copy, but the programs that execute the high-speed copy by these peripheral control DMA controllers 4150ac are standardized. That is, in the present embodiment, the effect information (1fr) and the effect information (1 ms) are managed by a common management method (execution of a common program).

[7-4-1d. Peripheral control SRAM]
The peripheral control SRAM 4150d externally attached to the peripheral control MPU 4150a includes a backup management target work area 4150da that exclusively stores the information to be backed up among various information updated by executing various control programs. A backup first area 4150db and a backup second area 4150dc are provided for exclusively storing a copy of various information stored in the backup management target work area 4150da. The contents stored in the peripheral control SRAM 4150d are the power-on state commands from the main control board 4100 when the pachinko gaming machine 1 is turned on (including when the power is restored due to a momentary power failure or a power failure) (see FIG. 40). ) Indicates the start of the RAM clear effect and the gaming state (for example, the start of the effect when the operation switch 860a shown in FIG. 12 is operated within a predetermined period from the time when the power is turned on. Even when it is), it is not cleared to zero. This point is completely different from the above-mentioned point that the backup management target work area 4150ca, the backup first area 4150cc, and the backup second area 4150cc of the peripheral control RAM 4150c are cleared to zero. Further, when the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated within a predetermined time after the power of the pachinko gaming machine 1 is turned on, a screen for performing the setting mode is displayed on the liquid crystal display device 1900 on the game board side. It is supposed to be done. By operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 according to the screen of this setting mode, each content (item) stored in the peripheral control SRAM 4150d (for example, a history of occurrence of a jackpot game state, etc.) On the other hand, the contents (items) stored in the peripheral control RAM 4150c are not displayed at all and cannot be cleared in the setting mode. This point is also completely different between the peripheral control RAM 4150c and the peripheral control SRAM 4150d.

The backup management target work area 4150da is used to manage various information such as effect information (SRAM) (for example, information for managing the history of occurrence of a jackpot game state and special effect flags), which is various information that is continued over days. It is composed of Bank0 (SRAM) that exclusively stores information) as a backup target. Here, briefly explaining the name of Bank0 (SRAM), as described above, "Bank" is a minimum management unit representing the size of a storage area for storing various information, and is referred to as "Bank". The following "0" means that it is a normally used storage area for storing various information updated by executing various control programs. That is, "Bank 0" means that the size of the storage area normally used is set as the minimum management unit. The "Bank1", "Bank2", "Bank3", and "Bank4" provided in the area extending from the backup first area 4150db to the backup second area 4150dc, which will be described later, are the same storage areas as the "Bank0". It means that it has a size. Since various information stored in the peripheral control SRAM 4150d externally attached to the peripheral control SRAM 4150a is backed up in "(SRAM)", "Bank0", "Bank1", "Bank2", and "Bank3" , And "Bank 4", respectively (the effect information (SRAM) and the effect backup information (SRAM) described later are also used with the same meaning).

Next, the backup first area 4150db and the backup second area 4150dc, which exclusively store the copy of the effect information (SRAM) which is various information stored in the backup management target work area 4150da, will be described. The backup first area 4150db and the backup second area 4150dc have two banks as one pair, and this one pair is managed as one page. The effect information (SRAM), which is the content stored in Bank0 (SRAM), which is a normally used storage area, is used as the effect backup information (SRAM) every time the peripheral control unit steady processing is executed for each frame (1 frame). In addition, it is copied to the backup first area 4150db and the backup second area 4150dc at high speed by the peripheral control DMA controller 4150ac. Consistency of one page is determined by whether or not the contents of the two banks constituting the page match.

Specifically, the backup first area 4150db has Bank1 (SRAM) and Bank2 (SRAM) as one pair, and this one pair is managed as one page. The contents stored in Bank0 (SRAM), which is a normally used storage area, are stored in Bank1 (SRAM) and Bank2 (SRAM) every time the peripheral control unit routine processing is executed for each frame (1 frame). It is copied at high speed by the controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank1 (SRAM) and Bank2 (SRAM) match.

Further, in the backup second area 4150dc, Bank3 (SRAM) and Bank4 (SRAM) are set as one pair, and this one pair is managed as one page. The contents stored in Bank0 (SRAM), which is a normally used storage area, are stored in Bank3 (SRAM) and Bank4 (SRAM) every time the peripheral control unit routine processing is executed every frame (1 frame). It is copied at high speed by the controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank3 (SRAM) and Bank4 (SRAM) match.

As described above, in the present embodiment, the backup first area 4150db is an area for managing Bank1 (SRAM) and Bank2 (SRAM) as one pair, and managing this one pair as one page, and the backup second area. 4150dc is an area for managing Bank3 (SRAM) and Bank4 (SRAM) as one pair, and managing this one pair as one page. Different ID coats are stored at the beginning and end of each page, that is, at the beginning and end of the backup first area 4150db and the backup second area 4150dc.

[7-4-1e. Power consumption history RAM]
The power consumption status history RAM 4150f externally attached to the peripheral control MPU 4150a samples the value (power consumption suppression stage) transmitted by the power consumption suppression signal from the power supply board 851 at a predetermined cycle by the peripheral control MPU 4150a (periphery described later). The power consumption status history information is stored and retained as the power consumption status history information (in the power consumption status history information creation process in the control unit 1ms timer interrupt processing). Specifically, the peripheral control MPU4150a executes the peripheral control unit 1ms timer interrupt processing every time a 1ms timer interrupt described later occurs, and in this peripheral control unit 1ms timer interrupt processing, the power consumption suppression signal from the power supply board 851. (Power consumption suppression stage) is sampled and sequentially stored in the power consumption status history RAM 4150f as power consumption status history information. In this embodiment, the power consumption status history information can store and retain the value (power consumption suppression stage) transmitted by the power consumption suppression signal for 3000 times as the number of samplings, and the power consumption suppression signal sampled this time is used. When the transmitted value (power consumption suppression stage) is stored and retained, the value transmitted by the power consumption suppression signal already sampled up to the previous time (power consumption suppression stage) is shifted one by one so that the values are arranged in time series. The value (power consumption suppression stage) that is sampled and transmitted by the power consumption suppression signal is stored and retained, and when the number of samplings reaches 3000, the value that is sampled and transmitted by the power consumption suppression signal (power consumption) is stored. Each time the suppression stage) is stored, the value transmitted by the oldest sampled power consumption suppression signal (power consumption suppression stage) is discarded one by one in order. That is, the power consumption status history information includes the value transmitted by the power consumption suppression signal sampled this time (power consumption suppression stage) for the latest 3000 times (in other words, the peripheral control MPU4150a executes the peripheral control unit 1 ms timer interrupt process). Each time, the value transmitted by the power consumption suppression signal from the power supply board 851 (power consumption suppression stage) is sampled and sequentially stored in the power consumption status history RAM 4150f as power consumption status history information. By executing 3000 times, the values (power consumption suppression stage) transmitted by the power consumption suppression signal for 3 seconds (= 1 ms × 3000 times) are arranged in chronological order.

[7-4-1f. Power saving mode transition notification LED]
The power saving mode transition notification LED 4150k restores the power status consumed by the pachinko game machine 1 when the power is turned off (immediately before the power is turned off) based on the power consumption status history information stored and held in the power consumption status history RAM 4150f. In order to notify the state of transition to the power saving mode at the time of power recovery, which is grasped in the above and the power consumed by the pachinko game machine 1 is suppressed. The power saving mode transition notification LED 4150k is not electrically connected to the peripheral control board 4140 via signal wiring, but is mounted directly on the peripheral control board 4140 and has a circuit configuration such that the light emitting mode is controlled by the peripheral control MPU 4150a. Has been done. In the present embodiment, the power saving mode transition notification LED 4150k is a surface mount type, and a high-brightness single color that emits green light is adopted, and a staff member such as a hall clerk has shown the lock device shown in FIGS. 1 and 5. When the key is inserted into the 1000 cylinder lock 1010 and rotated to release the closed state of the main body frame 3 with respect to the outer frame 2 and the main body frame 3 is opened with respect to the outer frame 2, the open side of the main body frame 3 is opened. The power saving mode transition notification LED 4150k is directly soldered to the peripheral control board 4140 at the position where it becomes, and the main body frame 3 is attached to the back side of the pachinko gaming machine 1 (that is, the back side of the gaming board 4) and the outer frame 2. When the main body frame 3 is opened, a staff member such as a clerk in the hall can visually check the issuance mode of the power saving mode transition notification LED 4150k.

Specifically, the peripheral control MPU4150a is the power consumption status history information stored and held in the power consumption status history RAM 4150f in the power recovery mode transition determination process in the peripheral control unit power-on processing described later, which is executed at the time of power restoration. Based on the above, the power consumption state (power consumption suppression stage described later) consumed by the pachinko game machine 1 at the time of power off (immediately before power off) is specified, and it is determined whether or not to shift to the power saving mode at the time of power recovery. The peripheral control MPU4150a sets the light emitting mode of the power saving mode transition notification LED 4150k to the non-power saving notification mode (lighting state) when the determination result does not shift to the power saving mode at the time of power recovery, while the judgment result is the power saving mode at the time of power recovery. When shifting to, the light emitting mode of the power saving mode transition notification LED 4150k is set to the power saving notification mode (off state). A clerk such as a clerk in the hall inserts a key into the cylinder lock 1010 of the lock device 1000 and rotates whether or not the pachinko gaming machine 1 is in the state of shifting to the power saving mode at the time of power recovery after the power is restored. By releasing the closed state of the main body frame 3 with respect to the outer frame 2 and opening the main body frame 3 with respect to the outer frame 2, it can be confirmed by visually observing the issuing mode of the power saving mode transition notification LED 4150k.

Here, a reason for adopting a surface-mounted type that is directly soldered to the peripheral control board 4140 as the power saving mode transition notification LED 4150k will be briefly described. When the power saving mode transition notification LED 4150k is arranged at a distance from the peripheral control board 4140 and electrically connected to the peripheral control board 4140 via signal wiring, for example, a staff member such as a hall clerk is working. When a finger or a tool is caught in the signal wiring and the connector of the signal wiring is disconnected from the peripheral control board 4140, or when the main body frame 3 is opened to the outer frame 2, the signal wiring enters the gap on the closed side of the main body frame 3. If the gap between the main body frame 3 and the outer frame 2 is narrowed and the signal wiring is broken, it becomes difficult for the peripheral control MPU 4150a to control the light emitting mode of the power saving mode transition notification LED 4150k. Because. In the present embodiment, the power saving mode transition notification LED 4150k is a surface mount type that is directly soldered to the peripheral control board 4140, but is a lead type that can be directly soldered to the peripheral control board 4140. May be good.

[7-4-2. LCD and sound control unit]
Drawing control between the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470, and the speakers and door frame 5 housed in the speaker box 820 provided in the main body frame 3 are provided. As shown in FIG. 15, the liquid crystal and sound control unit 4160 that controls the sound of music and sound effects flowing from the speaker 130 has a built-in sound source for controlling sounds such as music and sound effects (hereinafter, """Built-in sound source") and VDP (abbreviation of Video Display Processor) with built-in sound source that controls drawing between the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. Stores various sound data such as music and sound effects in addition to various character data on the screen displayed on the 4160a, the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. LCD and sound control ROM 4160b, audio data transmission IC 4160c that transmits serialized music, sound effects, etc. as audio data toward the frame decoration drive amplifier board 194, and serialized to the upper plate side liquid crystal display device 470. The upper plate that transmits drawing data to the touch panel drive board 450 that is arranged near the lower side of the upper plate side liquid crystal display device 470 attached to the right side of the plate unit 300 of the door frame 5 and is housed in the plate unit 300. Difference between positive signal and negative signal for LOCKN signal output request data, which is serial data output from the serial I / O port for the touch panel drive board built into the peripheral control MPU 4150a of the peripheral control unit 4150 and the side liquid crystal transmitter IC 4160d. In addition to the signal output from the moving differential circuit 4160e and the upper plate side liquid crystal transmitter IC 4160d, the signal from the differential circuit 4160e is input and the signal from the differential circuit 4160e is input. When this is done, the circuit is connected so as to transmit this signal, while when the signal from the differential circuit 4160e is not input, the circuit is connected so as to transmit the signal output from the upper plate side liquid crystal transmitter IC 4160d. It is provided with a forced switching circuit 4160f to be connected. In the liquid crystal and sound control ROM 4160b, as sprite data used for displaying screens and images described later, for example, ring-shaped image data used for displaying a ring-shaped display object (annular display object), and operation menu background image described later can be displayed. Operation menu background image data to be used, selection display image data used to display at least one selected display object described later, tone adjustment background image data used to display a volume adjustment screen including a volume scale described later, volume adjustment icon described later. Volume setting icon used for display In addition to image data, etc., the position of each part on the back of the main body frame 3 can be visually recognized from the player's point of view. The service mode screen image data used for the above, the break timer setting screen image data used for displaying the break timer setting screen, and the break screen image data used for displaying the break screen are stored. The liquid crystal and the sound control ROM 4160b also store the suggestion display object image data used for displaying the suggestion display object for prompting that the pressing operation unit 405 (operation unit) of the operation unit 400 should be operated.

The peripheral control MPU 4150a of the peripheral control unit 4150 extracts screen generation schedule data corresponding to the command from the main control board 4100 from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c. The screen data at the beginning of the screen generation schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c and set in the schedule data storage area 4150cae is used to control the peripheral control ROM 4150b of the peripheral control unit 4150 or the peripheral control RAM 4150c. After extracting from the data copy area 4150ce and outputting it to the VDP4160a with built-in sound source, when the V blank signal described later is input, the first screen data is set according to the screen generation schedule data set in the schedule data storage area 4150cae. Subsequent next screen data is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP4160a. In this way, the peripheral control MPU 4150a displays the screen data arranged in time series in the screen generation schedule data according to the screen generation schedule data set in the schedule data storage area 4150 cage, each time a V blank signal is input. In addition, the first screen data is output to the built-in sound source VDP4160a one by one.

Further, the peripheral control MPU 4150a transfers the sound command data at the head of the sound generation schedule data corresponding to the command from the main control board 4100 from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c. It is extracted and set in the schedule data storage area 4150cae of the peripheral control RAM 4150c, and the sound command data at the beginning of the sound generation schedule data set in the schedule data storage area 4150cae is set in the peripheral control ROM 4150b or peripheral control of the peripheral control unit 4150. After extracting from various control data copy areas 4150ce of RAM 4150c and outputting to VDP4160a with built-in sound source, when a V blank signal is input, the first sound according to the sound generation schedule data set in the schedule data storage area 4150cae. The next sound command data following the command data is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP 4160a. In this way, the peripheral control MPU4150a inputs the sound command data arranged in time series into the sound generation schedule data according to the sound generation schedule data set in the schedule data storage area 4150cae, and the V blank signal is input. Each time, the first sound command data is output to the built-in sound source VDP4160a one by one.

[7-4-2a. VDP with built-in sound source]
When screen data is input from the peripheral control MPU4150a in addition to the above-mentioned built-in sound source, the VDP4160a with a built-in sound source is a game board from the liquid crystal and the sound control ROM 4160b as shown in FIG. 17 based on the input screen data. One screen worth of side character data and upper plate side character data are extracted to create sprite data and displayed on the game board side liquid crystal display device 1900, movable liquid crystal display devices 1925a to 1925d, and upper plate side liquid crystal display device 470 ( A VRAM for generating drawing data (for one frame) is also built-in (hereinafter, referred to as "built-in VRAM"). Among the drawing data generated on the built-in VRAM, the sound source built-in VDP4160a transmits the drawing data for the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d from the channel CH1 via the liquid crystal output board 3420 on the game board side liquid crystal. In addition to outputting to the display device 1900 and the movable liquid crystal display devices 1925a to 1925d, drawing data for the upper plate side liquid crystal display device 470 is output from channel CH2 to a peripheral control output circuit (not shown), a frame peripheral relay terminal plate 868, and a peripheral door relay terminal. By outputting (transmitting) to the upper plate side liquid crystal display device 470 via the plate 882 and the touch panel drive board 450 housed in the plate unit 300 of the door frame 5, the game board side liquid crystal display device 1900 and the movable liquid crystal The display devices 1925a to 1925d are synchronized with the upper plate side liquid crystal display device 470. The screen data from the peripheral control MPU 4150a is based on the position where the finger is touching the touch panel 480 (contact position data) (that is, the image is reflected in the position where the finger is touching), and the game board side. In some cases, the order of the screens to be drawn on the liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470 is defined.

The drawing data output from the channel CH1 is output from the peripheral control board 4140 to the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d, whereas the drawing data output from the channel CH2 is From the peripheral control board 4140, the plate is arranged near the lower side of the frame peripheral relay terminal plate 868, the peripheral door relay terminal plate 882, and the upper plate side liquid crystal display device 470 attached to the right side of the plate unit 300 of the door frame 5. It is output (transmitted) to the upper plate side liquid crystal display device 470 via the touch panel drive board 450 housed in the unit 300. As described above, the drawing data output from the channel CH1 is output from the peripheral control board 4140 to the game board side liquid crystal display devices 1900 and the movable liquid crystal display devices 1925a to 1925d, so that the peripheral control board 4140 , The game board side liquid crystal display device 1900, and the movable liquid crystal display devices 1925a to 1925d are attached to the game board 4, respectively, from the channel CH1 to the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d. Although the length of the wiring required for the route is short, the drawing data output from the channel CH2 is transmitted from the peripheral control board 4140 via the touch panel drive board 450 housed in the dish unit 300 of the door frame 5 as described above. Since the output is output to the upper plate side liquid crystal display device 470, the peripheral control board 4140 is attached to the game board 4, whereas the touch panel drive board 450 is housed in the plate unit 300 of the door frame 5. As a result, the length of the wiring required for the path from the channel CH2 to the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the touch panel drive board 450 is extremely longer than that of the channel CH1, so that it is extremely susceptible to noise. Become. For this reason, for channel CH2 in which the length of the wiring for sending drawing data is extremely longer than that of channel CH1, "V-by-One (V-by-One) of THine Electronics Inc. is used in the upper plate side liquid crystal transmitter IC4160d. By adopting a differential communication system called "registered trademark)", the system is less susceptible to noise.

Channel CH1 uses a serial differential interface called LVDS (Low Voltage Differential Signaling). In this embodiment, a dual link system is adopted as the LVDS. The single link method uses one signal transmission line, whereas the dual link method uses two signal transmission lines. In the dual link method, when displaying an image with a large image size that cannot be supported by the transmission band of one signal transmission line by the single link method on the display device, the second signal transmission line is used. Data is transmitted simultaneously through the first signal transmission line and the second signal transmission line.

In the present embodiment, the game board side liquid crystal display device 1900 adopts 12 inches having an image size of 800 × 600 dots, and the four movable liquid crystal display devices 1925a to 1925d have an image size of 480 × 272 dots 4.3. Inches are used. That is, since the image size of the liquid crystal display device 1900 on the game board side and the four movable liquid crystal display devices 1925a to 1925d are not large, the image size can be sufficiently displayed by the single link method if used alone. be.

In the present embodiment, the VDP4160a with a built-in sound source has two channels, channels CH1 and CH2, for drawing data generated on the built-in VRAM. Therefore, when the drawing data is transmitted by the single link method, the game board is used. A total of six channels, the side liquid crystal display device 1900, the four movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470, are required, and there are not enough channels for transmitting drawing data by the single link method.

Therefore, in this embodiment, the dual link method is adopted. The first signal transmission line is an even number channel, the signal transmission line on the two sides is an odd number channel, and the drawing data for the game board side liquid crystal display device 1900 is transmitted from the even number channel to the liquid crystal output board 3420, while the odd number channel is 4 Drawing data for the two movable liquid crystal display devices 1925a to 1925d is transmitted to the liquid crystal output board 3420. Drawing data is transmitted simultaneously for even-numbered addresses and odd-numbered addresses by the dual link method.

When the drawing data transmitted to the even address and the odd address at the same time is received by the liquid crystal output board 3420, the drawing data of the even address is transmitted to the liquid crystal display device 1900 on the game board side, and the drawing data of the odd address is four. It is transmitted to the movable liquid crystal display devices 1925a to 1925d.

The channel CH2 uses a parallel interface with respect to the channel CH1. The drawing data output from the channel CH2 is composed of three video signals, a red video signal, a green video signal, and a blue video signal, and three sync signals, a horizontal sync signal, a vertical sync signal, and a clock signal. It is serialized by the upper plate side liquid crystal transmitter IC4610d, and is housed in a peripheral control output circuit (not shown), a frame peripheral relay terminal board 868, a peripheral door relay terminal board 882, and a plate unit 300 of the door frame 5. It is transmitted to the touch panel drive board 450. Then, the various serialized signals are restored to parallel signals on the touch panel drive board 450 and output to the upper plate side liquid crystal display device 470.

In this way, the peripheral control MPU4150a displays the screen data for one screen (one frame) displayed on the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470, and the sound source built-in VDP4160a. The VDP4160a with built-in sound source extracts character data from the liquid crystal and the sound control ROM 4160b based on the input screen data to create sprite data, and the game board side liquid crystal display device 1900 and the movable liquid crystal display device 1925a to Drawing data for one screen (one frame) to be displayed on the 1925d and the upper plate side liquid crystal display device 470 is generated on the built-in VRAM, and among the generated drawing data, the game board side liquid crystal display device 1900 and the movable liquid crystal display The drawing data for the devices 1925a to 1925d is transmitted from the channel CH1 to the liquid crystal output board 3420, and the image data for the upper plate side liquid crystal display device 470 is transmitted from the channel CH2 to the peripheral control output circuit, the frame peripheral relay terminal plate 868, and the periphery. The data is output (transmitted) to the upper plate side liquid crystal display device 470 via the door relay terminal plate 882 and the touch panel drive board 450 housed in the plate unit 300 of the door frame 5. That is, the "screen data for one screen (one frame)" is one screen (1) displayed on the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. This is data for generating drawing data (for frames) on the built-in VRAM.

Further, the VDP4160a with a built-in sound source transmits drawing data for one screen (one frame) from channel CH1 to the liquid crystal output board 3420, and peripheral control (not shown) for image data for the upper plate side liquid crystal display device 470 from channel CH2. When output (transmitted) to the upper plate side liquid crystal display device 470 via the output circuit, the frame peripheral relay terminal plate 868, the peripheral door relay terminal plate 882, and the touch panel drive board 450 housed in the plate unit 300 of the door frame 5. , A V blank signal indicating that the screen data from the peripheral control MPU 4150a can be accepted is output to the peripheral control MPU 4150a. In the present embodiment, the frame frequency (the number of screen updates per second) between the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470 is set to approximately 30 fps per second. Therefore, the interval at which the V blank signal is output is about 33.3 ms (= 1000 ms ÷ 30 fps). The peripheral control MPU4150a is configured to execute the peripheral control unit V blank signal interrupt processing, which will be described later, when the V blank signal is input. Here, the interval at which the V blank signal is output varies slightly depending on the liquid crystal size of the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. Further, the interval at which the V blank signal is output may change slightly even in the manufacturing lot of the peripheral control board 4140 on which the peripheral control MPU 4150a and the sound source built-in VDP 4160a are mounted.

The VDP4160a with a built-in sound source employs a frame buffer method. This "frame buffer method" refers to drawing data for one screen (one frame) drawn on the screens of the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. The drawing data for one screen (one frame) held in the frame buffer (built-in VRAM) and held in this frame buffer (built-in VRAM) is displayed on the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d. This is a method of outputting to the dish side liquid crystal display device 470.

Further, in the sound effect built-in VDP4160a, when the above-mentioned sound command data is input from the peripheral control MPU4150a based on the command from the main control board 4100, the music stored in the liquid crystal and the sound control ROM 4160b as shown in FIG. By extracting sound data such as sound effects and sound effects and controlling the built-in sound source, sound data such as music and sound effects are incorporated into the track according to the track number specified in the sound command data, and used according to the output channel number. The output channel is set, and the music and sound effects flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 are serialized and output as audio data to the audio data transmission IC 4160c. ..

The sound command data also includes a sub-volume value for adjusting the volume of the track that incorporates the sound data, and multiple tracks in the built-in sound source of the built-in sound source VDP4160a include directing sounds such as music and sound effects. In addition to the sound data of the above and the sub-volume value that adjusts the volume, the sound data of the notification sound and its volume for notifying the clerk of the hall of the occurrence of a malfunction of the pachinko game machine 1 or an illegal act against the pachinko game machine 1. A sub-volume value that adjusts is incorporated. Specifically, for the production sound, the substrate volume adjusted by rotating the knob portion of the volume adjustment volume 4140a described above is set as the sub-volume value, and for the notification sound, the volume is adjusted. The maximum volume is set as the sub-volume value without being completely dependent on the volume adjustment based on the rotation operation of the knob portion of the volume 4140a. The sub-volume value of the effect sound can be adjusted by operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 to shift to the setting mode described later.

In addition, the sound command data also includes a master volume value for adjusting the volume of the output channel, and the plurality of output channels in the built-in sound source of the built-in sound source VDP4160a include a plurality of multiple output channels in the built-in sound source of the built-in sound source VDP4160a. Of the tracks, the sound data of the production sound incorporated in the track to be used and the sub-volume value for adjusting the volume of the production sound incorporated in the track to be used are combined, and the volume of the combined production sound is calculated. Actually, the speaker housed in the speaker box 820 provided in the main body frame 3 and the master volume value which is the volume flowing from the speaker 130 provided in the door frame 5 are amplified, and the amplified production sound is serialized as audio data. It is designed to output to the audio data transmission IC 4160c.

In the present embodiment, the master volume value is set to a constant value except for the master volume value for power suppression, and when the volume of the synthesized production sound is the maximum volume, it is amplified to the master volume value. The volume flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 is set to be the maximum allowable volume. Specifically, for the effect sound, as a sub-volume value for adjusting the sound data of the effect sound incorporated in the track to be used and the volume of the effect sound incorporated in the track to be used among a plurality of tracks. The knob portion of the set volume adjustment volume 4140a is rotated to adjust the substrate volume, and the combined production sound volume is actually transmitted to the speaker box 820 provided in the main body frame 3. It is amplified to the master volume value that is the volume that flows from the accommodated speaker and the speaker 130 provided in the door frame 5, and this amplified production sound is serialized and output as audio data to the audio data transmission IC 4160c. Is based on the sound data of the notification sound incorporated in the track to be used and the rotation operation of the knob portion of the volume adjustment volume 4140a set as the sub-volume value for adjusting the volume of the notification sound incorporated in the track to be used. The maximum volume, which is completely independent of the volume adjustment, is combined, and the volume of the combined notification sound is actually combined with the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker provided in the door frame 5. It is amplified from 130 to the master volume value that is the volume that flows, and this amplified notification sound is serialized and output as audio data to the audio data transmission IC 4160c.

Here, when the production sound is flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, a problem occurs in the pachinko game machine 1 or the pachinko game machine 1 is affected. To briefly explain the control of playing a notification sound to notify the clerk of the hall of fraudulent activity, first, the sub-volume value of the track in which the production sound is incorporated is forcibly set to mute, and this production sound is incorporated. The sound data of the track, the sub-volume value set to mute the sound, the sound data of the track with the notification sound incorporated, and the sub-volume value set to the maximum volume of the notification sound are combined and this The volume of the combined production sound and the volume of the notification sound are amplified to the master volume value that is the volume that actually flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. Then, the amplified production sound and notification sound are serialized and output as audio data to the audio data transmission IC 4160c.

That is, as for the sound actually flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, only the maximum volume notification sound flows. At this time, since the effect sound is muted, the effect sound does not flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, but the effect sound is for sound generation described above. It is proceeding according to the schedule data. In the present embodiment, the notification sound flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 for a predetermined period (for example, 90 seconds). When the period elapses, the volume of the effect sound that has been progressing according to the sound generation schedule data forcibly set to mute is subordinated to the board volume adjusted by rotating the knob of the volume adjustment volume 4140a. It is set again as a volume value (at this time, if it is adjusted by operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 to shift to the setting mode, the adjusted production sound sub The volume value is set), and the sound flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5.

In this way, when the production sound is flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, a malfunction occurs in the pachinko game machine 1 or the pachinko game machine 1 occurs. When the notification sound is played to notify the clerk of the hall of the fraudulent act against the above, the volume of the production sound is muted and the notification sound is provided in the speaker and the door frame 5 housed in the speaker box 820 provided in the main body frame 3. Although the sound is played from the speaker 130, the muted production sound is progressing according to the sound generation schedule data. Therefore, the notification sound is a speaker housed in the speaker box 820 provided in the main body frame 3 after a predetermined period of time has passed. When the sound stops flowing from the speaker 130 provided on the door frame 5, the production sound does not start to flow again from the place where the notification sound starts to flow, but follows the sound generation schedule data until the time when the notification sound starts to flow and a predetermined period elapses. It starts to flow again from where it progressed.

[7-4-2b. LCD and sound control ROM]
As shown in FIG. 17, the liquid crystal and sound control ROM 4160b contains the game board side character data for drawing in the display area of the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display. The upper plate side character data for drawing in the display area of the device 470 is stored in advance, and various sound data such as music, sound effects, notification sounds, and notification sounds are also stored in advance.

[7-4-2c. Audio data transmission IC]
When the serialized audio data from the VDP4160a with a built-in sound source is input, the audio data transmission IC 4160c uses the right side audio data as a positive signal and a negative signal as differential serial data, which is not shown in the peripheral control output circuit and the frame peripheral relay. Peripheral control output circuit (not shown) that is transmitted to the frame decoration drive amplifier board 194 via the terminal plate 868 and the peripheral door relay terminal plate 882, and the left side audio data is used as a positive signal and a negative signal as differential serial data. , The frame peripheral relay terminal plate 868, and the peripheral door relay terminal plate 882 are transmitted to the frame decoration drive amplifier board 194. As a result, music, sound effects, and the like that match various effects are reproduced in stereo from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5.

The audio data transmission IC 4160c outputs audio data as serial data of the difference method between the left and right sides of the board extending from the peripheral control board 4140 to the frame decoration drive amplifier board 194, for example, a positive signal of the left side audio data. Even if the negative signal is affected by noise, when combining the noise component on the positive signal and the noise component on the negative signal on the frame decoration drive amplifier board 194 to make one left side audio data, Since the noise components are removed by canceling each other, noise countermeasures can be taken.

[7-4-2d. Transmitter IC for LCD on the upper plate side]
As shown in FIG. 17, the upper plate side liquid crystal transmitter IC 4160d is input with drawing data output from channel CH2 of the sound source built-in VDP4160a. As described above, the channel CH2 uses a parallel interface. The drawing data is composed of three video signals, a red video signal, a green video signal, and a blue video signal, and three sync signals, a horizontal sync signal, a vertical sync signal, and a clock signal, and is a red video signal. , The green video signal, and the blue video signal are each composed of 8 bits, for a total of 24 bits. In the present embodiment, the red video signal, the green video signal, and the blue video signal that can be input to the upper plate side liquid crystal transmitter IC4160d are 6 bits each, for a total of 18 bits, so that the upper 6 bits of each video signal are the upper plate. It is input to the side liquid crystal transmitter IC4160d. Since the lower 2 bits are extremely weak color information that is difficult for the human eye to distinguish, the lower 2 bits including the weak color information are invalidated although they are output from the sound source built-in VDP4160a.

Three video signals, red video signal, green video signal, and blue video signal, which are drawing data output from channel CH2 of VDP4160a with built-in sound source, and three sync signals, horizontal sync signal, vertical sync signal, and clock signal. When is input to the upper plate side liquid crystal transmitter IC 4160d, the upper plate side liquid crystal transmitter IC 4160d has three video signals, a red video signal, a green video signal, and a blue video signal, and a horizontal synchronization signal and a vertical synchronization signal. Three synchronous signals, a signal and a clock signal, are serialized into a differential serial signal (serial data) called "V-by-One (registered trademark)" of Zain Electronics Co., Ltd. with only a differential 1-pair cable. These various signals are transmitted from the peripheral control board 4140 to the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the touch panel drive board 450 housed in the dish unit 300 of the door frame 5.

As described above, the drawing data output from the channel CH1 of the VDP4160a with a built-in sound source is output from the peripheral control board 4140 to the liquid crystal display device 1900 on the game board side, so that the path from the channel CH1 to the liquid crystal display device 1900 on the game board side. Although the length of the wiring required for (first path) is short, the drawing data output from the channel CH2 of the VDP4160a with built-in sound source is obtained from the peripheral control board 4140 to the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the door. Since the data is output (transmitted) to the upper plate side liquid crystal display device 470 via the touch panel drive board 450 housed in the plate unit 300 of the frame 5, the path from channel CH2 to the upper plate side liquid crystal display device 470 (second). Since the length of the wiring required for the path) is extremely longer than the length of the wiring required for the first path, it becomes extremely susceptible to noise.

Specifically, since the door frame 5 is pivotally supported with respect to the main body frame 3 shown in FIG. 1, the opposite of the locking device 1000 shown in FIG. 5 along the open side of the main body frame 3. On the closed side, which is the side, for example, the peripheral control board 4140 provided in the game board 4 mounted on the main body frame 3 to the touch panel drive board 450 housed in the dish unit 300 provided in the door frame 5 are provided on the main body frame 3 side. It is necessary to pass various wirings that electrically connect the various boards and the various boards provided on the door frame 5 side. However, on the closed side of the main body frame 3, as shown in FIG. 3, in addition to the prize ball device 740, the game ball paid out by the prize ball device 740 is shown in FIG. 7, of the plate unit 300. A full-tank branching unit 770 that can guide the upper plate 301 to the lower plate 302 and guide the paid-out game ball to the lower plate 302 side when the upper plate 301 is full is arranged. Further, on the lower side of the main body frame 3, the board unit 800 shown in FIG. 5 in which the power supply board 851 and the like shown in FIG. 6 to which power is supplied from the pachinko island facility is integrated into a unit is arranged. In this way, the various wirings that electrically connect the various boards provided on the main body frame 3 side and the various boards provided on the door frame 5 side are located in the vicinity of the prize ball device 740, the full tank branch unit 770, the power supply board 851, and the like. It will be routed, and in addition to the noise caused by driving the payout motor 744 provided in the prize ball device 740, the noise caused by electrostatic discharge from the gaming ball and the noise caused by the pachinko gaming machine 1 will be supplied from the pachinko island facility where the pachinko gaming machine 1 is installed. The environment is such that it receives noise that has entered the power supply line.

For this reason, for channel CH2 in which the length of the wiring for sending drawing data is extremely longer than that of channel CH1, the upper plate side liquid crystal transmitter IC4160d provided in the peripheral control board 4140 is described by THine Electronics Inc. By adopting a differential type communication called "V-by-One (registered trademark)", the mechanism is less susceptible to noise. In the present embodiment, the upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140 and the upper plate side liquid crystal receiver ICSDIC 0 provided in the touch panel drive board 450 housed in the plate unit 300 of the door frame 5 are provided. As described above, a differential 1-pair cable is used as the wiring for electrically connecting between the connections, that is, between the transmitter and the receiver. However, this differential 1-pair cable has two wires. It is a twisted pair cable, not just parallel wires provided in parallel. This twisted pair cable is a cable in which two wires are twisted together, and is also called a twisted pair wire.

Here, a case where a parallel wire is adopted as a differential paired cable that electrically connects the transmitter and the receiver will be briefly described. Compared to channel CH2 of VDP4160a with built-in sound source, the length of the wiring for sending drawing data is extremely longer than that of channel CH1 of VDP4160a with built-in sound source. Even if the mechanism is less susceptible to noise by adopting a differential type communication called "V-by-One (registered trademark)" of Co., Ltd., the configuration with such hardware alone is due to the electrostatic discharge of the game ball. When the serial data in the parallel lines is affected by noise, noise invading the power supply line supplied from the Pachinko Island facility where the pachinko game machine 1 is installed, etc., the touch panel housed in the dish unit 300 of the door frame 5 Since the noise is not canceled (removed) when the data is received by the upper plate side liquid crystal receiver ICSDIC0 provided in the drive board 450, the serial data is received by the upper plate side liquid crystal receiver ICSDIC0 while being affected. , The drawing data output from the channel CH2 of the VDP4160a with built-in sound source is received by the upper plate side liquid crystal receiver ICSDIC0 as a disordered data different from the normal one, and in the display area of the upper plate side liquid crystal display device 470, it looks like a so-called sandstorm. There is a problem that various images are displayed and it becomes impossible to recognize what kind of image it is.

Therefore, in the present embodiment, the length of the wiring for sending drawing data is extremely longer than the channel CH1 of the VDP4160a with built-in sound source, as opposed to the channel CH2 of the VDP4160a with built-in sound source. The liquid crystal transmitter IC4160d adopts a differential type communication called "V-by-One (registered trademark)" of Zain Electronics Co., Ltd. to make it less susceptible to noise, and in addition to such a hardware configuration. Therefore, even if the serial data by the differential method is affected by the noise that has entered the wiring, a twisted pair cable that can cancel (remove) the noise on the receiving side is electrically connected between the transmitter and the receiver. It was adopted as a differential 1-pair cable. As a result, even if the serial data in the twisted pair cable is affected by noise due to electrostatic discharge of the game ball, noise invading the power supply line supplied from the pachinko island facility where the pachinko game machine 1 is installed, etc., the door Since the noise is canceled (removed) when the upper plate side liquid crystal receiver ICSDIC0 provided in the touch panel drive board 450 housed in the plate unit 300 of the frame 5 receives the noise, the channel of the VDP4160a with a built-in sound source The drawing data output from CH2 is reliably received by the upper plate side liquid crystal receiver ICSDIC0 provided in the touch panel drive board 450 housed in the plate unit 300 of the door frame 5, and is output to the upper plate side liquid crystal display device 470. As a result, the image generated by the liquid crystal and the sound source built-in VDP4160a of the sound control unit 4160 can be reliably displayed on the upper plate side liquid crystal display device 470. By canceling (removing) the noise, it is possible to prevent an image such as a sandstorm that cannot be recognized at all from being displayed on the upper plate side liquid crystal display device 470. Therefore, it is possible to suppress a decrease in the player's motivation to play. Therefore, it is possible to suppress a decrease in the player's willingness to play due to the influence of noise.

In the present embodiment, the upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140 and the upper plate side liquid crystal receiver ICSDIC 0 provided in the touch panel drive board 450 housed in the plate unit 300 of the door frame 5 will be described later. , That is, between the transmitter and the receiver, the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882 are interposed. This is because the main body frame 3 and the door frame 5 are not integrally configured, but a structure in which the door frame 5 is attached to the main body frame 3 after being assembled separately is adopted. After the work of attaching the door frame 5 to the door frame 5, various wirings such as harnesses and twisted cables from various boards provided on the door frame 5 side are electrically connected to the peripheral door relay terminal plate 882 provided on the main body frame 3 side. As a result, various substrates provided on the main body frame 3 side and various substrates provided on the door frame 5 side can be electrically connected. With such a configuration, after opening the door frame 5 from the main body frame 3 and removing various wirings, the door frame 5 is removed from the main body frame 3 to maintain the main body frame 3 and the door frame 5. If the problem that has occurred in the door frame 5 cannot be resolved, another door frame 5'is attached to the main body frame 3 in place of the door frame 5 having the problem, and the door frame 5 is used. By electrically connecting various wirings from various boards provided on the'side to the peripheral door relay terminal plate 882 provided on the main body frame 3 side, various boards provided on the main body frame 3 side and various types provided on the door frame 5'side. It can be electrically connected to the substrate.

Further, in the present embodiment, as described above, in the precision plate side liquid crystal transmitter IC4160d provided in the peripheral control board 4140, differential communication called "V-by-One (registered trademark)" of Zain Electronics Co., Ltd. is adopted. In addition to the hardware configuration, even if the serial data by the differential method is affected by the noise that has entered the wiring, the noise is canceled (removed) on the receiving side. A twisted pair cable that can be used is used as a differential 1-pair cable that electrically connects the transmitter and receiver. Specifically, between the peripheral control board 4140 and the frame peripheral relay terminal board 868, between the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882, and between the peripheral door relay terminal board 882 and the touch panel drive board. The boards with the 450 are electrically connected by twisted pair cables, whereas the power supply wiring and other wirings that transmit various signals are electrically connected by harnesses. As a result, in addition to the video transmission wiring pattern for transmitting the serial data by the differential method transmitted by the precision side liquid crystal transmitter IC4160d, the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882 are Wiring patterns for power supplies and other wiring patterns for various signals for transmitting various signals are mixed. Therefore, the above-mentioned video transmission wiring pattern is formed on the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882, respectively, separated from the power supply wiring pattern and various signal wiring patterns by a predetermined dimension. Since the path from the transmitter to the receiver straddles a plurality of relay terminal boards called a frame peripheral relay terminal board 868 and a peripheral door relay terminal board 882, it is used for video transmission formed on these plurality of relay terminal boards. Between the input and output of the wiring pattern, there is a problem that a part of the signal for transmitting the serial data by the differential method transmitted by the upper plate side liquid crystal transmitter IC4160d is reflected and becomes noise, or the output level of the signal is lowered. Occurs. Therefore, in the present embodiment, impedance matching is applied to the video transmission wiring patterns formed on these plurality of relay terminal boards.

Further, in the present embodiment, as described above, between the boards of the peripheral control board 4140 and the frame peripheral relay terminal board 868, between the boards of the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882, and the peripheral door relay. The terminals 882 and the touch panel drive board 450 are electrically connected by a twisted pair cable, whereas the power supply wiring and other wiring that transmits various signals are electrically connected by a harness. Although they are connected, one of the twisted pair cables is red and the other is gray, and the harness that supplies power is red and the other wires are gray. The wiring for supplying power may be yellow instead of red.

[7-4-2e. Forced switching circuit, differential circuit]
The signal output from the upper plate side liquid crystal transmitter IC 4160d is in the forced switching circuit 4160f, the peripheral control output circuit (not shown), the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the plate unit 300 of the door frame 5. It is designed to be transmitted to the stored touch panel drive board 450. In this forced switching circuit 4160f, in addition to the signal output from the upper plate side liquid crystal transmitter IC 4160d, the serial I / O port for the touch panel drive board built in the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140. The LOCKN signal output request data, which is the serial data output from the above, is input in the differential circuit 4160e after being differentiated into a positive signal and a negative signal. In this differential circuit 4160e, the LOCKN signal output request data is serialized into a differential type serial signal (serial data). This LOCKN signal output request data is demonstrated by the liquid crystal display device 1900 on the game board side while the start screen when the power of the pachinko game machine 1 is turned on is displayed on the liquid crystal display device 1900 on the game board side or in the waiting state for customers. During this period, the upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140 and the upper plate side liquid crystal receiver ICSDIC 0 provided in the touch panel drive board 450 housed in the plate unit 300 of the door frame 5 , That is, it is transmitted as an operation confirmation request of the upper plate side liquid crystal display device 470 in order to confirm whether or not a problem has occurred in the connection between the transmitter and the receiver. When two signals differentiated into a plus signal and a minus signal are input in the differential circuit 4160e, the forced switching circuit 4160f is circuit-connected so as to transmit these two signals, while being differential. When two signals differentiated into a plus signal and a minus signal are not input in the conversion circuit 4160e, the circuit is configured so as to transmit the signal output from the precision side liquid crystal transmitter IC 4160d. Has been done. As a result, when two signals differentiated into a plus signal and a minus signal are input in the differential circuit 4160e, the two signals are connected in a circuit so as to transmit the two signals, so that the two signals are connected. , It is transmitted from the peripheral control board 4140 to the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the touch panel drive board 450 housed in the dish unit 300 of the door frame 5, while being positive in the differential circuit 4160e. When two differential signals, a signal and a negative signal, are not input, the circuit is connected so as to transmit the signal output from the upper plate side liquid crystal transmitter IC 4160d, so that the upper plate side liquid crystal transmitter IC 4160d is connected. The signal output from the peripheral control board 4140 is transmitted from the peripheral control board 4140 to the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the touch panel drive board 450 housed in the dish unit 300 of the door frame 5. The peripheral control MPU4150a demonstrates the period during which the startup screen when the power of the pachinko game machine 1 is turned on is displayed on the game board side liquid crystal display device 1900, and the game board side liquid crystal display device 1900 is in a customer waiting state. The touch panel drive board 450 (actually, the peripheral control board 4140 is provided with the differential) in which the LOCKN signal output request data is stored in the dish unit 300 of the door frame 5 from the serial I / O port for the touch panel drive board during the period. It transmits to the conversion circuit 4160e).

When the touch panel drive board 450 housed in the dish unit 300 of the door frame 5 receives the serial signal (serial data) from the peripheral control board 4140 by the upper dish side liquid crystal receiver ICSDIC0 described later, various serialized signals are received. Is restored to a parallel signal and output to the upper plate side liquid crystal display device 470. The liquid crystal module circuit 450V and the capacitance type touch panel provided so as to cover the display area of the upper plate side liquid crystal display device 470 shown in FIG. It is mainly composed of a touch panel circuit 450W that detects and controls a contact state of 480.

The receiver ICSDIC0 for the liquid crystal on the upper plate side receives the drawing data from the VDP4160a with a built-in sound source, and if it determines that the received drawing data is abnormal data, it transmits a LOCKN signal to that effect, which will be described later, to the peripheral door relay terminal board 882. , And output to the peripheral control board 4140 via the frame peripheral relay terminal board 868. This LOCKN signal is input to the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140 via a peripheral control input circuit (not shown) of the peripheral control board 4140. Peripheral control MPU4150a controls the sound source built-in VDP4160a to generate an image for notifying that a predetermined condition is satisfied based on the input LOCKN signal, and outputs the image to the liquid crystal display device 1900 on the game board side. Is displayed in the display area of the liquid crystal display device 1900 on the game board side to notify the user.

Further, when the precision plate side liquid crystal receiver ICSDIC0 determines that the two received signals are the LOCKN signal output request data from the serial I / O port for the touch panel drive board, the LOCKN signal described later is transmitted to the peripheral door relay terminal. The data is output to the peripheral control board 4140 via the plate 882 and the frame peripheral relay terminal plate 868. This LOCKN signal is input to the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140 via a peripheral control input circuit (not shown) of the peripheral control board 4140. As a result, the peripheral control MPU4150a considers that there is no problem in the connection between the transmitter and the receiver when the LOCKN signal is input as a response signal to the transmission of the LOCKN signal output request data, and the dish unit of the door frame 5 It can be determined that there is no problem with the touch panel drive board 450 housed in the 300, but when the LOCKN signal is not input, it is assumed that there is a problem with the connection between the transmitter and the receiver. It is determined that the touch panel drive board 450 housed in the plate unit 300 of the frame 5 has a problem, and a notification image (for example, "A problem has occurred in the liquid crystal display device on the upper plate side" to convey the problem. "Please call a clerk.") Is output to the game board side liquid crystal display device 1900 by controlling the VDP4160a with a built-in sound source, and a notification sound to that effect (for example, "There is a problem with the upper plate side liquid crystal display device". By controlling the VDP4160a with a built-in sound source and outputting it to the audio data transmission IC 4160c, the notification sound flows from the speakers 130, 222, 262 and the like provided in the door frame 5. As a result, the notification image displayed in the display area of the liquid crystal display device 1900 on the game board side and the notification sound repeatedly flowing from the speakers 130, 222, 262 and the like provided on the door frame 5 can be used for notification. It has become. At this time, all the LEDs for light emitting decoration provided in the door frame 5 and the various LEDs mounted on the various decorative boards provided in the game board 4 may be turned on.

[7-4-3. RTC control unit]
As shown in FIG. 15, the RTC control unit 4165 that holds the calendar information that specifies the date and the time information that specifies the hour, minute, and second is configured around the RTC4165a. The RTC4165a has a built-in RAM4165aa that holds calendar information and time information (hereinafter, referred to as "RTC built-in RAM4165aa"). The RTC4165a is supplied with power from a battery 4165b (a button battery is adopted in this embodiment) as a drive power source and a backup power source for the RTC built-in RAM4165aa. That is, the RTC4165a is not supplied with power from the peripheral control board 4140 (pachinko gaming machine 1) at all, but is supplied with power from the battery 4165b independently of the peripheral control board 4140 (pachinko gaming machine 1). As a result, even if the power of the pachinko gaming machine 1 is cut off, the RTC4165a can update and hold the calendar information and the time information by the power supply from the battery 4165b.

The peripheral control MPU 4150a of the peripheral control unit 4150 acquires calendar information and time information from the RTC built-in RAM4165aa of the RTC4165a, sets them in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c described above, and uses the acquired calendar information and time information as the peripheral control MPU4150a. The effect based on the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470 can be developed. As such an effect, for example, on December 25, the screen of the Christmas tree or the reindeer is unfolded by the liquid crystal display device 1900 on the game board side, the movable liquid crystal display devices 1925a to 1925d, and the liquid crystal display device 470 on the upper plate side. Alternatively, on New Year's Eve, the screen for executing the New Year countdown may be unfolded on the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. Calendar information and time information are set at the time of shipment from the factory.

In addition to the calendar information and the time information, the RTC built-in RAM4165aa stores and holds the LED brightness setting information when the backlight of the liquid crystal display device 1900 on the game board side is of the LED type. There is. When the backlight of the liquid crystal display device 1900 on the game board side is an LED type, the peripheral control MPU4150a acquires the brightness setting information from the RTC built-in RAM4165aa and adjusts the brightness of the backlight by PWM control. .. The brightness setting information includes brightness adjustment information for adjusting the brightness of the LED, which is the backlight of the liquid crystal display device 1900 on the game board side, in a range of 100% to 70% in 5% increments, and the game currently set. The brightness of the LED that is the backlight of the panel-side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470 is included.

Further, in addition to the calendar information, the time information and the brightness setting information, the RTC built-in RAM4165aa also stores the calendar information, the time information and the brightness setting information as the date and hour, minute and second information first stored in the RTC built-in RAM4165aa. The input date and time information is also stored.

The peripheral control MPU4150a is a backlight when the back light of the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470 is a cold cathode tube type. ON / OFF control or ON only.

Various information such as calendar information, time information, brightness setting information, and input date / time information stored in the RTC built-in RAM4165aa are set in the manufacturing line of the game machine manufacturer. In the production line, for example, in order to perform various tests such as a display test of the liquid crystal display device 1900 on the game board side, the year when the input date and time information was input on the production line as the date and time when the liquid crystal display device 1900 on the game board side was first turned on. Set to the manufacturing date and time, which is the month, day, hour, minute, and second.

In this way, in addition to calendar information and time information, the RTC built-in RAM4165aa has brightness setting information, input date and time information, etc. when the backlight of the gaming board side liquid crystal display device 1900 is an LED type. , Information that needs to be maintained can be stored and retained independently of the model information of the pachinko gaming machine 1 (for example, the probability that a big hit gaming state occurs at a low probability or a high probability).

Further, the brightness setting information and the like stored and stored in the RTC built-in RAM4165aa are too bright with the brightness of the backlight of the game board side liquid crystal display device 1900 set at the manufacturing date and time depending on the environment of the hall where the pachinko game machine 1 is installed. Or it may be too dark. Therefore, by operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400, it is possible to shift to the setting mode and adjust the brightness of the backlight to a predetermined brightness. When the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated within a predetermined time after the power of the pachinko game machine 1 is turned on, a screen for performing the setting mode is displayed on the liquid crystal display device 1900 on the game board side. In addition, when the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 are operated during the period during which the customer is waiting and the demonstration by the liquid crystal display device 1900 on the game board side is being performed, the setting mode is performed. The screen is displayed on the liquid crystal display device 1900 on the game board side. By operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 according to the screen of this setting mode, the calendar information and the time information can be reset, and the brightness of the backlight of the liquid crystal display device 1900 on the game board side can be desired. It can be adjusted to brightness. The desired brightness of the backlight of the adjusted liquid crystal display device 1900 on the game board side is overwritten (updated and stored) as the brightness of the LED stored in the brightness setting information.

In the setting mode, the peripheral control MPU4150a executes the above-mentioned luminance correction program, and when the backlight of the game board side liquid crystal display device 1900 is an LED type, the game board side liquid crystal display device 1900 is installed. The decrease in brightness due to the aging of the display device 1900 is corrected. The peripheral control MPU4150a acquires input date and time information from the RTC built-in RAM4165aa of the RTC control unit 4165, specifies the date and time when the liquid crystal display device 1900 on the game board side is first turned on, and specifies the date and time as calendar information and time. The current date and time is specified by acquiring the time information that specifies the minutes and seconds, and the brightness of the LED that is the backlight of the liquid crystal display device 1900 on the game board side is adjusted in 5% increments from 100% to 70%. The brightness setting information having the brightness adjustment information for the purpose and the brightness of the LED which is the backlight of the liquid crystal display device 1900 on the game board side which is currently set is acquired. The acquired luminance setting information is corrected based on the correction information stored in advance in the peripheral control ROM 4150b.

For example, if six months have already passed from the date and time when the liquid crystal display device 1900 on the game board side was first turned on and the current date and time, and from the date and time when the liquid crystal display device 1900 on the game board side was first turned on. When the corresponding correction information (for example, 5%) is acquired from the peripheral control ROM 4150b and the brightness of the LED included in the brightness setting information is 75% and the backlight of the liquid crystal display device 1900 on the game board side is turned on, this 75%. The brightness of the backlight of the liquid crystal display device 1900 on the game board side is adjusted based on the brightness adjustment information included in the brightness setting information so that the brightness is 80%, which is an additional 5% of the correction information acquired for the above. If 12 months have already passed since the date and time when the power of the liquid crystal display device 1900 on the game board side was first turned on, the corresponding correction information (for example, 10%) is acquired from the peripheral control ROM 4150b. When the brightness of the LED included in the brightness setting information is 75% and the backlight of the liquid crystal display device 1900 on the game board side is turned on, the correction information acquired for this 75% is added by 10% to 85%. The brightness of the backlight of the liquid crystal display device 1900 on the game board side is adjusted and turned on based on the brightness adjustment information included in the brightness setting information so as to be the brightness.

The current date and time may be specified by directly acquiring the calendar information for specifying the date and the time information for specifying the hour, minute, and second from the RTC built-in RAM4165aa of the RTC control unit 4165. Current calendar information set in the calendar information storage unit and updated by the system of the peripheral control board 4140 in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c in the current time information acquisition process of step S1002 in the control unit power-on processing. And the current time information set in the time information storage unit and updated by the system of the peripheral control board 4140 may be acquired to specify the current date and time.

[7-4-4. Volume adjustment volume]
As described above, the volume adjusting volume 4140a rotates the knob portion to control the volume of music, sound effects, etc. flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. It can be adjusted by doing. As described above, the resistance value of the volume adjusting volume 4140a is changed by rotating the knob portion, and the electrically connected peripheral control A / D converter 4150ak is used as the knob portion. The voltage divided by the resistance value at the rotation position is converted from an analog value to a digital value and converted into a value in 1024 steps from a value to a value of 1023. In the present embodiment, as described above, the value of 1024 steps is divided into seven and managed as the substrate volumes 0 to 6. The board volume 0 is set to mute, the board volume 6 is set to the maximum volume, and the volume is set to increase from the board volume 0 to the board volume 6. The liquid crystal and sound control unit 4160 (VDP4160a with built-in sound source) are controlled so that the volume is set to the board volumes 0 to 6, and the speaker and the door frame 5 housed in the speaker box 820 provided in the main body frame 3 are provided. Music and sound effects are played from the speaker 130.

In this way, music and sound effects flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 by adjusting the volume based on the rotation operation of the knob portion. .. Further, in the present embodiment, as described above, in addition to the music and sound effects, a notification sound for notifying the clerk of the hall of the occurrence of a malfunction of the pachinko game machine 1 or an illegal act against the pachinko game machine 1 and the like. Announce the contents related to the game production (for example, the screen unfolded on the liquid crystal display device 1900 on the game board side is likely to be produced as more powerful, or the game state is likely to shift to an advantageous state for the player. The notification sound for pachinko and the like also flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, but the notification sound and the notification sound are operated by rotating the knob portion. It is a mechanism that flows without depending on the volume adjustment based on the above, and the volume from mute to maximum volume can be adjusted by controlling the liquid crystal and sound control unit 4160 (VDP4160a with built-in sound source) by a program. ing.

The volume adjusted by this program is different from the substrate volume divided into the above-mentioned seven stages, and can smoothly change from mute to maximum volume. As a result, for example, even when a hall clerk or the like rotates the knob portion of the volume adjustment volume 4140a to set the volume low, the speaker and the door housed in the speaker box 820 provided in the main body frame 3 Although the production sounds such as music and sound effects flowing from the speaker 130 provided in the frame 5 are reduced, the volume is loud when the pachinko gaming machine 1 has a problem or when the player is cheating. In the form, the notification sound set to the maximum volume) can be played. Therefore, even if the volume of the effect sound is reduced, it is possible to prevent the hall clerk and the like from being less likely to notice the occurrence of a problem or the cheating of the player due to the notification sound.

In addition, based on the current board volume set by adjusting the volume based on the rotation operation of the knob, the volume at which the advertisement sound is played is reduced so as not to interfere with music and sound effects, while the advertisement sound is played. In addition to music and sound effects, increase the volume of the sound to make the screen unfolded by the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470 more powerful. It is also possible to direct and announce that there is a high possibility that the gaming state will be favorable to the player.

In the present embodiment, in addition to adjusting the volume of music and sound effects by rotating the knob portion of the volume adjusting volume 4140a, the dial operating portion 401 and pressing of the operation unit 400 By operating the operation unit 405, it is possible to shift to the setting mode and adjust the volume of music and sound effects. When the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated within a predetermined time after the power of the pachinko game machine 1 is turned on, a screen for performing the setting mode is displayed on the liquid crystal display device 1900 on the game board side. In addition, when the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 are operated during the period during which the customer is waiting and the demonstration by the liquid crystal display device 1900 on the game board side is being performed, the setting mode is performed. The screen is displayed on the liquid crystal display device 1900 on the game board side. By operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 according to the screen of this setting mode, the volume of music and sound effects can be adjusted to a desired volume. Specifically, the peripheral control A / D converter 4150ak converts the voltage divided by the resistance value at the rotation position of the knob portion of the volume adjustment volume 4140a from an analog value to a digital value, and the converted value is obtained. Therefore, the value of the board volume can be increased or decreased by adding or subtracting a predetermined value according to the operation of the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400. .. This adjusted volume is set and updated as a sub-volume value for the track in which the sound data of the production sound such as music and sound effects is incorporated among the plurality of tracks in the built-in sound source of the built-in sound source VDP4160a. Although it is reflected in the adjustment of the volume of the above-mentioned notification sound and the notification sound, it is not reflected in the adjustment.

As described above, in the present embodiment, there are cases where the volume of music and sound effects is adjusted by directly rotating the knob portion of the volume adjusting volume 4140a, and cases where the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 are used. There are two methods, one is to adjust the volume of music and sound effects by increasing or decreasing the value of the substrate volume by adding or subtracting a predetermined value according to the operation. Since the volume adjusting volume 4140a is mounted on the peripheral control board 4140, it is necessary to make sure that the main body frame 3 is open from the outer frame 2. Then, it is the clerk in the hall who can rotate the knob portion of the volume adjustment volume 4140a. However, at the volume adjusted by the clerk in the hall, the player may feel small and it may be difficult to hear the music or sound effect, or the player may feel loud and the music or sound effect may be noisy. Therefore, after the power of the pachinko gaming machine 1 is turned on, within a predetermined time, the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 are operated, or the pachinko game machine 1 is in a waiting state and a demonstration is performed by the liquid crystal display device 1900 on the game board side. When the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated within the period during which the operation unit 400 is being performed, a screen for performing the setting mode is displayed on the liquid crystal display device 1900 on the game board side. By operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 according to the screen of the setting mode, the volume of music and sound effects can be adjusted to a desired volume. As a result, the player can adjust the volume of the music or sound effect to a desired volume. Therefore, if the volume adjusted by the hall clerk feels low and it is difficult to hear the music or sound effect, the operation unit 400 can be used. The dial operation unit 401 and the pressing operation unit 405 can be operated to increase the volume to a desired level, and when the volume adjusted by the hall clerk is felt loud and the music or sound effect is noisy, the operation unit 400 can be used. The dial operation unit 401 and the pressing operation unit 405 can be operated to reduce the volume to a desired level.

Further, in the present embodiment, when the pachinko gaming machine 1 is not playing a game for a predetermined time, is in a waiting state for customers, and the demonstration by the liquid crystal display device 1900 on the gaming board side is repeatedly performed (for example, 10 times). ), The volume adjusted by the player who was sitting in front of the pachinko gaming machine 1 and playing the game last time is canceled, and the volume is initialized. In this volume initialization, the volume is adjusted by the hall clerk, that is, the volume adjusted by the hall clerk by directly rotating the knob portion of the volume adjusting volume 4140a. As a result, if the player who was sitting in front of the pachinko machine 1 last time feels that the volume adjusted is low and it is difficult to hear the music or sound effects, this time, the front of the pachinko machine 1 is displayed. A player who sits and plays a game can operate the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 to increase the volume to a desired level. If the player who was playing the game feels the volume adjusted loudly and the music or sound effects are noisy, this time, the player who sits in front of the pachinko machine 1 and plays the game is the dial operation unit of the operation unit 400. The volume can be reduced to a desired level by operating 401 or the pressing operation unit 405.

[8. Power system]
Next, the power supply system of the pachinko gaming machine 1 will be described with reference to FIGS. 18 to 20. FIG. 18 is a block diagram showing a power supply system of a pachinko game machine, FIG. 19 is a block diagram (a) showing a power supply creation circuit, and a diagram showing a relationship between power consumption and a power consumption suppression level associated with the power consumption ( b), FIG. 20 is a block diagram showing the continuation of FIG. First, the power supply board will be described, and then the power supply supplied to each control board and the like will be described. The grounds (GNDs) of the various boards and the grounds (GNDs) of the various terminal boards are electrically connected to the grounds (GNDs) of the power supply board 851 and are the same grounds (GNDs).

[8-1. Power supply board]
The power supply board 851 is electrically connected to the power supply cord, and the plug of the power supply cord is plugged into the power outlet of the pachinko island equipment. When the power switch 852 shown in FIG. 3 is operated, the electric power supplied from the pachinko island equipment is supplied to the power supply board 851, and the pachinko gaming machine 1 can be turned on.

As shown in FIG. 18, the power supply board 851 includes a power supply control unit 855, a firing solenoid drive circuit 858, and a ball feed solenoid drive circuit 859. The power supply control unit 855 is a circuit that creates various DC voltages from AC 24 volt (AC24V) supplied from the Pachinko Island facility and supplies backup power to the main control board 4100 and the payout control board 4110. The drive circuit 858 is a circuit that drives the launching solenoid 654 of the ball-striking launcher 650 shown in FIG. 5, and the ball-feeding solenoid drive circuit 859 drives the ball-feeding solenoid 585 of the ball-feeding unit 580 shown in FIG. It is a circuit.

The power supply control unit 855 includes a synchronous rectifier circuit 855a, a power factor improvement circuit 855b, a smoothing circuit 855c, a power supply creation circuit 855d, and capacitors BC0 and BC1. The AC24V supplied from the pachinko island facility is supplied to the game ball rental device connection terminal plate 869 via the power supply board 851, and is also supplied to the synchronous rectifier circuit 855a. This synchronous commutator circuit 855a is supplied from the pachinko island facility, rectifies AC 24 volts (AC24V), and supplies it to the power factor improving circuit 855b. The power factor improving circuit 855b improves the power factor of the rectified electric power to create DC + 37V (DC + 37V, hereinafter referred to as “+ 37V”) and supplies it to the smoothing circuit 855c. The smoothing circuit 855c removes the supplied + 37V ripple to smooth the + 37V and supplies it to the firing solenoid drive circuit 858, the ball feed solenoid drive circuit 859, and the power supply making circuit 855d, respectively.

The capacitor BC0 supplies backup power to the RAM (main control built-in RAM) built in the main control MPU 4100a of the main control board 4100, and the capacitor BC1 is built in the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110. It supplies backup power to the RAM (RAM with built-in payout control).

The firing solenoid drive circuit 858 uses + 37V supplied from the smoothing circuit 855c as a driving power source, and is controlled by the firing ball feed control circuit 4120ag built in the payout control MPU 4120a of the payout control board 4110 shown in FIG. The drive current to the firing solenoid 654 is adjusted so that the gaming ball can be launched (launched) toward the gaming area 1100 based on the operation signal from. As a result, the game ball can be launched (launched) toward the game area 1100 shown in FIG. 1 with a launch strength (launch intensity) commensurate with the rotation position of the rotary handle main body front 506 shown in FIG. On the other hand, the ball feed solenoid drive circuit 859 is controlled by the launch ball feed control circuit 4120ag built in the payout control MPU 4120a of the payout control board 4110 shown in FIG. 13 using + 37 V supplied from the smoothing circuit 855c as a drive power source. The drive current to the ball feed solenoid 585 is adjusted to be a constant current. As a result, the ball feeding member of the ball feeding unit 580 accepts one game ball stored in the upper plate 301 of the plate unit 300 shown in FIG. 7, and the game ball received by the ball feeding member is sent to the ball launching device 650 side. Can be sent.

The power supply creation circuit 855d includes a power consumption monitoring circuit 855da, a + 5V power supply creation circuit 855db, a + 12V power supply creation circuit 855dc, and a + 24V power supply creation circuit 855dd. The + 37V supplied from the smoothing circuit 855c is supplied to the + 5V power supply creation circuit 855db, the + 12V power supply creation circuit 855dc, and the + 24V power supply creation circuit 855dd, respectively, via the power consumption monitoring circuit 855da.

The power consumption monitoring circuit 855da monitors the power consumption of + 37V supplied from the smoothing circuit 855c. The power consumption monitoring circuit 855da monitors the power consumption of + 37V supplied from the smoothing circuit 855c, and determines the power consumption suppression stage indicating how much the power consumption should be suppressed based on the power consumption. , The determination result is output to the frame peripheral relay terminal plate 868 as a power consumption suppression signal. The power consumption suppression signal output from the power consumption monitoring circuit 855da of the power supply creation circuit 855d is configured as three signal wirings (that is, is configured as three parallel signals), and has a value of 0 to a value of 7. It is possible to transmit eight kinds of values up to, and it is input to the peripheral control board 4140 via the frame peripheral relay terminal board 868, while it is input to the peripheral control board 4140 via the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882. It is designed to be input to the frame decoration drive amplifier board 194 (see FIG. 20B). Then, the power consumption suppression signal from the power consumption monitoring circuit 855da of the power supply creation circuit 855d is input to the decoration board of the door frame or the like via the frame decoration drive amplifier board 194 (FIG. 20 (FIG. 20). b)).

Specifically, as shown in FIG. 19A, the power consumption monitoring circuit 855da includes a power measurement circuit 855da and a power consumption suppression stage determination circuit 855da. The + 37V supplied from the smoothing circuit 855c is supplied to the + 5V power supply creation circuit 855db, the + 12V power supply creation circuit 855dc, and the + 24V power supply creation circuit 855dd via the power measurement circuit 855da, respectively. The power measurement circuit 855da measures the power consumption of + 37V supplied from the smoothing circuit 855c in real time and outputs it to the power consumption suppression stage determination circuit 855da. The power consumption suppression stage determination circuit 855da determines the power consumption suppression stage indicating how much power consumption should be suppressed based on the power consumption measured by the power measurement circuit 855daa, and determines the determination result of three lines. It is set to the value of the power consumption suppression signal configured as the signal wiring and output to the frame peripheral relay terminal board 868.

The relationship between the power consumption suppression stage indicating how much power consumption should be suppressed, the power consumption measured by the power measurement circuit 855da, and the power consumption suppression stage indicating how much power consumption should be suppressed (that is, power consumption). The relationship between the amount of power consumption and the level of power consumption suppression associated with the amount of power consumption) will be briefly explained. In the present embodiment, it is assumed that power (AC24V) is supplied to one pachinko game machine 1 for one transformer (maximum allowable capacity: 250VA) provided in the pachinko island facility, and FIG. 19B is shown. As shown, if the horizontal axis is the power consumption with respect to the maximum allowable capacity of this transformer and the vertical axis is step 0 to step 7 as the power consumption suppression stage, the power consumption suppression stage determination circuit 855dab is a power measurement circuit. When the power consumption of + 37V measured by 855daa is 0% or more and less than 10%, it is determined that the power consumption suppression stage is stage 0, a value 0 is set as the value of the power consumption suppression signal, and the power consumption measurement circuit 855daa measures. When the power consumption of + 37V is 10% or more and less than 20%, it is determined that the power consumption suppression stage is step 1, a value 1 is set as the value of the power consumption suppression signal, and the + 37V measured by the power measurement circuit 855daa. When the power consumption is 20% or more and less than 30%, it is determined that the power consumption suppression stage is stage 2, a value 2 is set as the value of the power consumption suppression signal, and the power consumption of + 37V measured by the power measurement circuit 855daa. When is 30% or more and less than 40%, it is determined that the power consumption suppression stage is stage 3, a value 3 is set as the value of the power consumption suppression signal, and the power consumption of + 37V measured by the power measurement circuit 855daa is 40%. When it is less than 50%, it is determined that it is step 4 as the power consumption suppression step, a value 4 is set as the value of the power consumption suppression signal, and the power consumption of + 37V measured by the power measurement circuit 855daa is 50% or more and 60%. When it is less than, it is determined that the power consumption suppression step is step 5, a value 5 is set as the value of the power consumption suppression signal, and the power consumption of + 37V measured by the power measurement circuit 855daa is 60% or more and less than 70%. Sometimes it is determined that the power consumption suppression stage is stage 6, and the value 6 is set as the value of the power consumption suppression signal, and when the power consumption of + 37V measured by the power measurement circuit 855daa is 70% or more, it is set as the power consumption suppression stage. It is determined that the stage is 7, and the value 7 is set as the value of the power consumption suppression signal.

It should be noted that the pachinko island facility usually employs a system in which, for example, four pachinko gaming machines 1 are supplied as one group to each of the power supplies (AC24V) for one transformer (for example, in one row). In the pachinko island facility where 20 pachinko game machines 1 are installed, four pachinko game machines 1 are managed as five groups, and one transformer is provided for each group (a total of five transformers). ), Power supply (AC24V) is supplied respectively), and a plurality of transformers having a maximum allowable capacity of 1000VA are provided in the pachinko island facility.

The + 5V power supply creation circuit 855db creates DC + 5V (DC + 5V, hereinafter referred to as “+ 5V”) from + 37V supplied from the smoothing circuit 855c via the power consumption monitoring circuit 855da. The + 12V power supply creation circuit 855dc creates DC + 12V (DC + 12V, hereinafter referred to as “+ 12V”) from + 37V supplied from the smoothing circuit 855c via the power consumption monitoring circuit 855da. The + 24V power supply creation circuit 855dd creates DC + 24V (DC + 24V, hereinafter referred to as “+ 24V”) from + 37V supplied from the smoothing circuit 855c via the power consumption monitoring circuit 855da. + 5V, + 12V, and + 24V are supplied to the payout control board 4110 and the frame peripheral relay terminal board 868, respectively. The power supply system to which + 5V is applied and supplied is the + 5V power supply line, the power supply system to which + 12V is applied and supplied is the + 12V power supply line, and the power supply system to which + 24V is applied and supplied is the + 24V power supply line.

+ 5V of the power supply making circuit 855d + 5V created by the power supply making circuit 855db is supplied to the payout control board 4110 as described later. The + 5V supplied to the payout control board 4110 is applied to the power supply terminal of the payout control MPU 4120a via the payout control filter circuit 4110a, and is also applied to the power supply terminal of the payout control built-in RAM via the diode PD0. ing. The + 12V created by the + 12V power supply making circuit 855dc of the power supply making circuit 855d is supplied to the + 5V making circuit 4100g of the main control board 4100 via the payout control board 4110. This + 5V creation circuit 4100g creates + 5V, which is the control reference voltage of the main control MPU 4100a, from + 12V from the payout control board 4110. The + 5V created by the + 5V creation circuit 4100g is supplied to the power supply terminal of the main control MPU 4100a via the main control filter circuit 4100h, and is also supplied to the power supply terminal of the main control built-in RAM via the diode MD0. ing.

The negative terminal of the capacitor BC1 of the power supply board 851 is grounded to the ground (GND), while the positive terminal of the capacitor BC1 is electrically connected to the power supply terminal of the payout control built-in RAM of the payout control board 4110 and is paid out. It is also electrically connected to the cathode terminal of the diode PD0 of the control board 4110. That is, the + 5V created by the + 5V power supply creation circuit 855db of the power supply creation circuit 851 on the power supply board 851 causes a current to flow toward the power supply terminal of the payout control MPU4120a, and the power supply of the discharge control built-in RAM which is forward by the diode PD0. A current flows toward the terminal and the positive terminal of the capacitor BC1. In this way, the capacitor BC1 is electrically such that + 5V created by the + 5V power supply making circuit 855db of the power supply making circuit 855d in the power supply board 851 returns to the payout control board 4110 and again from the payout control board 4110 to the power supply board 851. + 5V can be supplied and charged by various connection methods. As a result, when the + 5V created by the + 5V power supply creation circuit 855db of the power supply creation circuit 855d is no longer supplied to the payout control board 4110, the electric charge charged in the capacitor BC1 is supplied to the payout control board 4110 as the payout VBB. Therefore, although the current is blocked by the diode PD0 and does not flow to the power supply terminal of the payout control MPU4120a and the payout control MPU4120a does not operate, the payout VBB is supplied to the power supply terminal of the payout control built-in RAM. The stored contents are retained by.

The negative terminal of the capacitor BC0 of the power supply board 851 is grounded to the ground (GND), while the positive terminal of the capacitor BC0 is electrically connected to the power supply terminal of the main control built-in RAM of the main control board 4100 via the payout control board 4110. It is also electrically connected to the cathode terminal of the diode MD0 of the main control board 4100. That is, in the + 5V created by the + 5V creation circuit 4100g, a current flows toward the power supply terminal of the main control MPU4100a, and the power supply terminal of the main control built-in RAM in the forward direction by the diode MD0, the positive terminal of the capacitor BC0, and the positive terminal. The current is flowing toward. In this way, the capacitor BC0 is charged by supplying + 5V by an electrical connection method in which + 5V created by the + 5V creation circuit 4100g is supplied from the main control board 4100 and the payout control board 4110 to the power supply board 851. You can do it. As a result, + 12V created by the + 12V power supply creation circuit 855dc of the power supply creation circuit 851 on the power supply board 851 is not supplied to the + 5V creation circuit 4100g of the main control board 4100 via the payout control board 4110, and the + 5V creation circuit 4100g is + 5V. When it becomes impossible to create the main control MPU 4100a, the electric charge charged in the capacitor BC0 is supplied to the main control board 4100 as the main VBB via the payout control board 4110. Although the main control MPU4100a does not operate because the current is obstructed by the diode MD0 at the power supply terminal of the main control built-in RAM, the stored contents are retained by supplying the main VBB to the power supply terminal of the main control built-in RAM. There is.

[8-2. Voltage supplied to each control board, etc.]
Next, the outline of the voltage supplied to each control board and the like will be described, and then the voltage mainly supplied to the payout control board and the voltage supplied to the main control board will be described.

The three types of voltages of + 5V, + 12V, and + 24V created by the + 5V power supply creation circuit 855db, the + 12V power supply creation circuit 855dc, and the + 24V power supply creation circuit 855dd of the power supply board 851 are shown in FIG. Of these three types of voltages, two types of voltages, + 12V and + 24V, are supplied to the payout control board 4110, and are supplied to the main control board 4100 via the payout control board 4110. Further, the three types of voltages of + 5V, + 12V, and + 24V created by the + 5V power supply creation circuit 855db, the + 12V power supply creation circuit 855dc, and the + 24V power supply creation circuit 855dd of the power supply board 851 are the relay terminals around the frame. It is supplied to the plate 868, and is also supplied to the peripheral control board 4140 and the peripheral door relay terminal plate 882 via the frame peripheral relay terminal plate 868, respectively.

As shown in FIG. 20A, the three types of voltages of + 5V, + 12V, and + 24V supplied to the peripheral control board 4140 are the lamp drive circuit 4170a of the lamp drive board 4170 and the drive source drive circuit of the motor drive board 4180. It is supplied to each of the 4180a. The lamp drive circuit 4170a of the lamp drive board 4170 outputs various signals such as a lighting signal, a blinking signal, and a gradation lighting signal to various decorative boards of the game board 4, and the drive source drive circuit 4180a of the motor drive board 4180 is a game. A drive signal is output to an electric drive source such as a motor or a solenoid of the panel 4.

Further, as shown in FIG. 20A, one kind of voltage of + 12V supplied to the peripheral control board 4140 is supplied to the liquid crystal module power supply circuit 3420a on the game board side of the liquid crystal output board 3420. The liquid crystal module power supply circuit 3420a on the game board side creates a direct current 3.3V (DC + 3.3V, hereinafter referred to as "+ 3.3V") from + 12V. The + 3.3V created by the liquid crystal module power supply circuit 3420a on the game board side is supplied to various electronic components mounted on the liquid crystal output board 3420, as well as the liquid crystal module backlight power supply circuit 3420b on the game board side and the game board side. It is supplied to various electronic components mounted on a substrate provided in the liquid crystal display device 1900. The voltage created by the game board side liquid crystal module backlight power supply circuit 3420b is supplied to the backlight provided in the game board side liquid crystal display device 1900.

Further, + 12V is supplied to the movable liquid crystal display devices 1925a to 1925d. In the movable liquid crystal display devices 1925a to 1925d, + 12V from the liquid crystal output board 3420 is supplied to the movable side liquid crystal module power supply circuit, and the movable side liquid crystal module power supply circuit creates + 3.3V from + 12V to create the movable liquid crystal display device 1925a. In addition to being supplied to various electronic components mounted on the substrates provided in each of 1925d, it is supplied to the movable liquid crystal module backlight power supply circuit mounted on the substrates provided in each of the movable liquid crystal display devices 1925a to 1925d. The power supply created by each movable side liquid crystal module backlight power supply circuit is supplied to the movable side backlight provided in the movable liquid crystal display devices 1925a to 1925d.

On the other hand, three types of voltages, + 5V, + 12V, and + 24V, which are supplied to the peripheral door relay terminal board 882, are supplied to the frame decoration drive amplifier board 194 as shown in FIG. 20 (b). The frame decoration drive amplifier board 194 includes a + 9V creation circuit 194a that creates DC + 9V (DC + 9V, hereinafter referred to as “+ 9V”) from + 12V supplied from the peripheral door relay terminal board 882. Along with + 9V created by the + 9V creation circuit 194a, a total of four types of voltages of + 5V, + 12V, and + 24V supplied from the peripheral door relay terminal board 882 are supplied to various decorative substrates of the door frame 5.

Further, the + 5V voltage supplied to the peripheral door relay terminal board 882 is supplied to the touch panel power supply circuit 450a of the touch panel drive board 450. The touch panel power supply circuit 450a creates an analog voltage and a digital voltage from a voltage of + 5V, and the required voltage is supplied to various electronic components constituting the touch panel 450W shown in FIG. At the same time, it is supplied to the touch panel 480. Further, + 12V supplied to the peripheral door relay terminal board 882 is supplied to the upper plate side liquid crystal module power supply circuit 450x. The upper plate side liquid crystal module power supply circuit 450x creates + 12.V to + 3.3V. The + 3.3V created by the upper plate side liquid crystal module power supply circuit 450x is supplied to various electronic components constituting the upper plate side liquid crystal module circuit 450V, respectively, and the upper plate side liquid crystal module backlight power supply circuit 450y. It is supplied to various electronic components mounted on the substrate provided in the liquid crystal display device 470 on the upper plate side. The voltage created by the upper plate side liquid crystal module backlight power supply circuit 450y is supplied to the backlight provided in the upper plate side liquid crystal display device 470.

[8-2-1. Voltage supplied to the payout control board]
As shown in FIG. 18, the payout control board 4110 includes a payout control filter circuit 4110a and the like in addition to the payout control MPU 4120a and the like. The payout control filter circuit 4110a is supplied with + 5V from the power supply board 851, and noise is removed from the + 5V. This + 5V is supplied to the capacitor BC1 of the power supply board 851 via the diode PD0, and is also supplied to, for example, the payout control MPU4120a of the payout control unit 4120. The + 12V from the power supply board 851 is supplied to, for example, the payout control input circuit 4120b of the payout control unit 4120, and is also supplied to the external communication circuit 784a of the external terminal board 784 via the payout control board 4110. The external communication circuit 784a of the external terminal board 784 outputs a signal for transmitting the number of game balls paid out by the pachinko game machine 1 and the game information of the pachinko game machine 1 to the hall computer installed in the game hall. It is a circuit to do. The hall computer monitors the player's game by grasping the number of game balls paid out by the pachinko game machine 1 and the game information of the pachinko game machine 1 from the signal output from the external communication circuit 784a. .. The +24 from the power supply board 851 is supplied to the main control board 4100 via the payout control board 4110 without being used in the payout control board 4110.

[8-2-2. Voltage supplied to the main control board]
As shown in FIG. 18, the main control board 4100 includes a + 5V creation circuit 4100g, a main control filter circuit 4100h, a power failure monitoring circuit 4100e, and the like, in addition to the main control MPU 4100a and the like. In the + 5V creation circuit 4100g, + 12V from the power supply board 851 is supplied via the payout control board 4110, and + 5V, which is the control reference voltage of the main control MPU 4100a, is created from this + 12V. In the main control board 4100, the power supply system to which + 5V created by the + 5V creation circuit 4100g is applied and supplied becomes the + 5V power supply line. In the present embodiment, the + 5V power supply line created by the + 5V power supply creation circuit 855db of the power supply creation circuit 855d on the power supply board 85 and the + 5V power supply line created by the + 5V creation circuit 4100g of the main control board 4100 are electrically connected. Since the circuit is configured so as not to be connected, the + 5V power supply line created by the + 5V power supply creation circuit 855db of the power supply creation circuit 855d on the power supply board 851 is electrically connected to various electronic components of the main control board 4100. The + 5V power supply line created by the + 5V creation circuit 4100g of the main control board 4100 is not electrically connected to various electronic components such as other boards other than the main control board 4100.

The main control filter circuit 4100h is supplied with + 5V created by the + 5V creation circuit 4100g, and noise is removed from this + 5V. This + 5V is supplied to the capacitor BC0 of the power supply board 851 via the diode MD0, and is also supplied to, for example, the main control MPU4100a. The + 12V from the payout control board 4110 is supplied to, for example, the main control input circuit 4100b, and the + 24V from the payout control board 4110 is supplied to, for example, the main control solenoid drive circuit 4100d.

In the power failure monitoring circuit 4100e, + 12V and + 24V from the power supply board 851 are supplied via the payout control board 4110, and the signs of a power failure or momentary power failure of these + 12V and + 24V are monitored. When the power failure monitoring circuit 4100e detects a sign of a power failure or momentary power failure of + 12V and + 24V, it outputs a power failure warning signal to the main control MPU 4100a as a power failure warning. The power failure warning signal is input to the payout control MPU 4120a via the payout control input circuit 4120b of the main control board 4100 and the payout control board 4110. Further, the power failure warning signal is input to the peripheral control board 4140 via the main control board 4100. Further, the power failure warning signal is input to the frame decoration drive amplifier board 194 as shown in FIG. 20B via the peripheral control board 4140, the frame peripheral relay terminal board 868, and the peripheral door relay terminal board 882. At the same time, the input is input to the decorative substrate of the door frame or the like via the frame decorative drive amplifier substrate 194.

In the present embodiment, the power failure monitoring circuit 4100e applies to one of the + 12V power supply line or the + 24V power supply line by monitoring the voltage applied to each of the two power supply lines, the + 12V power supply line and the + 24V power supply line. It is possible to more accurately grasp the signs of power failure such as a power failure or a momentary power failure as compared with the case of monitoring the voltage.

[9. Main control board circuit]
Next, the circuit and the like of the main control board 4100 shown in FIG. 12 will be described with reference to FIGS. 21 to 23. FIG. 21 is a circuit diagram showing a circuit of the main control board, FIG. 22 is a circuit diagram showing a power failure monitoring circuit, and FIG. 23 is a circuit showing a communication interface circuit between the main control board and the peripheral control board. It is a figure. First, the main control filter circuit 4100h shown in FIG. 18 will be described, and then the power supply, main control system reset, main control crystal oscillator, main control input circuit, power failure monitoring circuit, and main control MPU created by the main control board 4100 will be described. Various input / output signals to and from the main control board 4100 and a communication interface circuit between the boards of the main control board 4100 and the peripheral control board 4140 will be described.

The main control board 4100 includes a main control MPU 4100a, a main control input circuit 4100b, a main control output circuit 4100c, a main control solenoid drive circuit 4100d, a power failure monitoring circuit 4100e, a + 5V creation circuit 4100g, and a main control board 4100g shown in FIGS. In addition to the control filter circuit 4100h, as peripheral circuits, as shown in FIG. 21, the main control system reset MIC1 that outputs a reset signal and the main control crystal oscillator MX0 that outputs a clock signal (in this embodiment, 24 megahertz (MHz)). )) Is mainly composed.

[9-1. Main control filter circuit]
As shown in FIG. 21, the main control filter circuit 4100h mainly includes a main control 3-terminal filter MIC0. This main control 3-terminal filter MIC0 is a T-type filter circuit, which is magnetically shielded with ferrite and has excellent attenuation characteristics. In the main control 3-terminal filter MIC0, + 5V created by the + 5V creation circuit 4100g was applied to the 1st terminal, the 2nd terminal was grounded to the ground (GND), and the noise component was removed from the 3rd terminal. + 5V is output. The + 5V applied to the 1st terminal is first electrically removed from the ripple (AC component folded by the voltage) by being electrically connected to the other end of the capacitor MC0 whose one end is grounded to ground (GND). Is smoothed.

The + 5V output from the 3rd terminal is electrically connected to the other end of the capacitor MC1 and the electrolytic capacitor MC2 (capacitance: 470 microfarad (μF) in this embodiment), one end of which is grounded to ground (GND). By connecting to, the ripple is further removed and smoothed. This smoothed + 5V is applied to the power supply terminal of the main control system reset MIC1, the VDD terminal which is the power supply terminal of the main control crystal oscillator MX0, the VDD terminal which is the power supply terminal of the main control MPU4100a, and the like. When a power failure or momentary power failure occurs at the VDD terminal, which is the power supply terminal of the main control MPU4100a, and the power supply from the pachinko island equipment is cut off, the electric charge charged in the electrolytic capacitor MC2 causes a power failure or momentary power failure. It is applied as + 5V over a period of about 7 milliseconds (ms) after it is generated.

The VDD terminal of the main control MPU 4100a is electrically connected to the other end of the capacitor MC3 whose one end is grounded to ground (GND), and the + 5V applied to the VDD terminal is further stripped of ripples and smoothed. The VSS terminal, which is the ground terminal of the main control MPU4100a, is grounded to ground (GND).

Further, the VDD terminal of the main control MPU4100a is electrically connected to the anode terminal of the diode MD0 in addition to being electrically connected to the capacitor MC3. The cathode terminal of the diode MD0 is electrically connected to the VBB terminal, which is the power supply terminal of the RAM (main control built-in RAM) built in the main control MPU4100a, and one end of the capacitor MC4 is grounded to ground (GND). It is electrically connected to the other end of the. The VBB terminal of the main control built-in RAM is electrically connected to the cathode terminal of the diode MD0 and the other end of the capacitor MC4, and is also the plus of the capacitor BC0 of the power supply board 851 shown in FIG. 18 via the resistor MR0. It is electrically connected to the terminal. That is, + 5V smoothed by removing the noise component by the main control filter circuit 4100h is applied to the VDD terminal of the main control MPU4100a, and is applied to the VBB terminal of the main control built-in RAM and the capacitor BC0 via the diode MD0. It is designed to be applied to the positive terminal of. As a result, as described above, + 12V created by the + 12V power supply creation circuit 855dc of the power supply creation circuit 855d of the power supply board 851 shown in FIG. When the + 5V creation circuit 4100g cannot create + 5V because it is no longer supplied, the charge charged in the capacitor BC0 is supplied to the main control board 4100 as the main VBB, so that the main control Although the main control MPU4100a does not operate because the current is obstructed by the diode MD0 at the VDD terminal of the MPU4100a, the stored contents are retained by applying the main VBB to the VBB terminal of the main control built-in RAM. ing.

[9-2. Main control system reset]
As shown in FIG. 21, + 5V smoothed by removing the noise component by the main control filter circuit 4100h is applied to the power supply terminal of the main control system reset MIC1. The main control system reset MIC1 resets the main control MPU 4100a and the main control output circuit 4100ca with a reset function, respectively, and has a built-in delay circuit. One end of the delay capacitance terminal of the main control system reset MIC1 is electrically connected to the other end of the capacitor MC5 which is grounded to ground (GND), and the delay time by the delay circuit is set by the capacitance of this capacitor MC5. You can do it. Specifically, when the + 5V input to the power supply terminal reaches the threshold value (for example, 4.25V), the main control system reset MIC1 outputs a system reset signal from the output terminal after the delay time elapses.

The output terminal of the main control system reset MIC1 is electrically connected to the SRST terminal, which is the reset terminal of the main control MPU 4100a, and the reset terminal of the main control output circuit 4100ca with a reset function. The output terminal is an open collector output type, and is a capacitor whose one end is electrically connected to the other end of the pull-up resistor MR1 which is electrically connected to the + 5V power supply line and one end is grounded to ground (GND). It is electrically connected to the other end of the MC6. Ripple is removed and smoothed by this capacitor MC6. When the voltage input to the power supply terminal is larger than the threshold value, the output terminal is pulled up to the + 5V side by the pull-up resistor MR1 and the logic becomes HI. This logic becomes the SRST terminal of the main control MPU4100a and the main control output with a reset function. While each is input to the reset terminal of the circuit 4100ca, when the voltage input to the power supply terminal is smaller than the threshold value, the logic becomes LOW, and this logic is the SRST terminal of the main control MPU 4100a and the main control output circuit 4100ca with a reset function. It is input to each reset terminal. Since the SRST terminal of the main control MPU 4100a and the reset terminal of the main control output circuit 4100ca with a reset function are negative logic inputs, respectively, when the voltage input to the power supply terminal becomes smaller than the threshold value, the main control MPU 4100a and the reset function The main control output circuit 4100ca is reset. The power supply terminal is electrically connected to the other end of the capacitor MC7 whose one end is grounded to ground (GND), and the + 5V input to the power supply terminal is smoothed by removing ripples. Further, the ground terminal is grounded to the grant (GND), and the NC terminal is in a state of being electrically unconnected to the outside.

[9-3. Main control crystal oscillator]
As shown in FIG. 21, + 5V smoothed by removing the noise component by the main control filter circuit 4100h is applied to the VDD terminal which is the power supply terminal of the main control crystal oscillator MX0. This VDD terminal is electrically connected to the other end of the capacitor MC8 whose one end is grounded to ground (GND), and the + 5V input to the VDD terminal is further stripped of ripples and smoothed. Further, this smoothed + 5V is applied not only to the VDD terminal but also to the A terminal, the B terminal, the C terminal, and the ST terminal, which are output frequency selection terminals, respectively. The main control crystal oscillator MX0 outputs a 24 MHz clock signal from the F terminal, which is an output terminal, by applying + 5 V to these A terminal, B terminal, C terminal, and ST terminal, respectively.

The F terminal of the main control crystal oscillator MX0 is electrically connected to the CLK terminal, which is the clock terminal of the main control MPU4100a, and a 24 MHz clock signal is input. The GND terminal, which is the ground terminal of the main control crystal oscillator MX0, is grounded to ground (GND), and the D terminal, which outputs the frequency division of the F terminal of the main control crystal oscillator MX0, is not electrically connected to the outside. It is in a state.

[9-4. Main control input circuit]
The main control input circuit 4100b is a detection signal from the general winning port switches 3020 and 3020, the upper start port switch 3022, the lower start port switch 2109, the magnetic detection switch 304, the count switch 2110, and the gate switch 2352 shown in FIG. In addition, it is a circuit in which an operation signal (RAM clear signal) or the like from the operation switch 860a provided in the payout control board 4110 shown in FIG. 13 is input. Since the circuit configuration in which the detection signal from each switch is input is the same, a circuit in which the operation signal (RAM clear signal) from the operation switch 860a is input will be described here.

[9-4-1. Circuit to which the operation signal (RAM clear signal) from the operation switch is input]
First, as described above, the operation switch 860a is the RAM (RAM with built-in payout control) built into the payout control MPU 4120a of the payout control board 4110 and the main control of the main control board 4100 within a predetermined period from the time when the power is turned on. It is operated when clearing the RAM (main control built-in RAM) built in the MPU4100a, or when an error is notified after the power is turned on, it is operated to clear the error. A function to clear the RAM within a predetermined period from the time the power is turned on, and an error cancellation after the power is turned on (after the period during which the function as RAM clear is performed, that is, after the predetermined period has passed from the time the power is turned on). It has a function to perform. Since the main control board 4100 does not have the function of canceling the error of the payout control board 4110, the main control is performed when the operation signal from the operation switch 860a is input within a predetermined period from the time when the power is turned on. A process of clearing the main control built-in RAM is performed by judging as a RAM clear signal for clearing the built-in RAM.

When the operation switch 860a is not operated, the operation signal whose logic is LOW is input to the main control board 4100, while when the operation switch 860a is operated, the logic is input from the payout control board 4110. The operation signal in which is HI is input from the payout control board 4110 (a detailed description of this point will be described later).

As shown in FIG. 21, the transmission line for transmitting the operation signal from the operation switch 860a provided on the payout control board 4110 within a predetermined period from the time when the power is turned on is a pull-up in which one end is electrically connected to the + 12V power supply line. It is electrically connected to the other end of the resistor MR2 and is also electrically connected to the base terminal of the transistor MTR0 via the resistor MR3. In addition to being electrically connected to the resistor MR3, the base terminal of the transistor MTR0 is electrically connected to the other end of the resistor MR4 whose one end is grounded to ground (GND). The emitter terminal of the transistor MTR0 is grounded to ground (GND), and the collector terminal of the transistor MTR0 is electrically connected to the other end of the resistor MR5, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Main control via ICMIC10 (non-inverting buffer ICMIC10 includes eight non-inverting buffer circuits, and formats and outputs the logic of the signal waveform input to one of them (MIC10A) without inverting it). It is electrically connected to the input terminal PA0 of the input port PA of the MPU4100a.

The circuit that outputs the operation signal from the operation switch 860a on the payout control board 4110 is configured as an open collector output type in which the emitter terminal is grounded to the ground (GND), and the transmission that transmits the operation signal from the operation switch 860a. The line is pulled up to the + 12V side by the pull-up resistor MR2. In the main control board 4100, when the operation switch 860a is not operated, the operation signal from the payout control board 4110 is pulled down to the ground (GND) side and the logic is input as LOW, while the operation switch 860a is operated. At this time, the operation signal from the payout control board 4110 is pulled up to the + 12V side by the pull-up resistor MR2, and the logic is input as HI.

The circuit composed of the resistors MR3 and MR4 and the transistor MTR0 is a switch circuit that is turned ON / OFF by an operation signal from the operation switch 860a.

When the operation switch 860a is not operated, the operation signal whose logic is LOW is input to the base terminal of the transistor MTR0, so that the transistor MTR0 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor MTR0 is pulled up to the + 5V side by the resistor MR5, and the operation signal from the operation switch 860a whose logic becomes HI is input to the input terminal PA0 of the input port PA of the main control MPU4100a. Will be done. The main control MPU4100a must instruct to clear the RAM that erases the information stored in the main control built-in RAM when the logical value of the operation signal from the operation switch 860a input to the input terminal PA0 is HI. to decide.

On the other hand, when the operation switch 860a is operated, the transistor MTR0 is turned on by inputting the operation signal whose logic is HI by being pulled up to the + 12V side by the pull-up resistor MR2 to the base terminal of the transistor MTR0, and the switch is switched. The circuit will also be turned on. As a result, the voltage applied to the collector terminal of the transistor MTR0 is lowered to the ground (GND) side, and the operation signal from the operation switch 860a whose logic is LOW is input to the input terminal PA0 of the input port PA of the main control MPU4100a. Will be done. The main control MPU4100a instructs to clear the RAM that erases the information stored in the main control built-in RAM when the logical value of the operation signal from the operation switch 860a input to the input terminal PA0 is LOW. Judge.

The operation signal from the operation switch 860a is pulled up to the + 12V side by the pull-up resistor MR2. This is because the operation signal from the operation switch 860a is input via the payout control board 4110. That is, the voltage between the main control board 4100 and the payout control board 4110 is higher than the control reference voltage of + 5V in order to suppress the influence of noise invading the wiring (harness) that electrically connects the boards. The reliability of the signal is enhanced by using + 12V, which is a voltage. Therefore, in the present embodiment, the detection signals from the general winning port switch 3020, the upper starting port switch 3022, and the lower starting port switch 2109, which are directly input to the main control board 4100, are pulled up to the + 5V side by the pull-up resistor. On the other hand, the detection signals from the magnetic detection switch 3024, the count switch 2110, the general winning opening switch 3020, and the gate switch 2352, which are input via the panel relay terminal plate 4161 shown in FIG. 12, are directly sent to the main control board 4100. Since it is not input, it is pulled up to the + 12V side by the pull-up resistor like the operation signal from the operation switch 860a.

[9-5. Power failure monitoring circuit]
As shown in FIG. 18, the main control board 4100 is supplied with two types of voltages, + 12V and + 24V, from the power supply board 851 via the payout control board 4110, and + 12V and + 24V are input to the power failure monitoring circuit 4100e. ing. The power failure monitoring circuit 4100e monitors signs of power failure or momentary power failure of + 12V and + 24V, and when it detects a sign of power failure or momentary power failure, it sends a power failure warning signal as a power failure warning, in addition to the main control MPU4100a, a payout control board. It is output to the payout control MPU 4120a of the 4110 and the peripheral control board 4140. Here, the configuration of the power failure monitoring circuit will be described first, followed by the monitoring of + 24V power failure or momentary power failure, the monitoring of + 12V power failure or momentary power failure, and the output of the power failure warning signal.

[9-5-1. Power failure monitoring circuit configuration]
As shown in FIG. 22, the power failure monitoring circuit 4100e mainly includes a shunt type stabilized power supply circuit MIC20, an open collector output type comparator MIC21, a D type flip-flop MIC22, and transistors MTR20 to MTR23.

The REF terminal, which is the reference voltage input terminal of the shunt-type regulated power supply circuit MIC20, and the K terminal, which is the cathode terminal, are electrically connected to the other end of the resistor MR20, one end of which is electrically connected to the + 5V power supply line. + 5V is applied, and the current input to the REF terminal is limited by the resistor MR20. The K terminal outputs a reference voltage Vref (2.495V is set in this embodiment) which is a comparison reference voltage of the comparator MIC21. The K terminal is electrically connected to the other end of the capacitor MC20 whose one end is grounded to ground (GND), and the reference voltage Vref output from the K terminal is rippled (folded over the voltage) by the capacitor MC20. The AC component) has been removed and smoothed. The A terminal, which is the anode terminal of the shunt-type regulated power supply circuit MIC20, is grounded to ground (GND).

The comparator MIC21 includes two voltage comparison circuits, one of which (MIC21A) is used to compare the + 24V monitoring voltage V1 with the reference voltage Vref, and the remaining one (MIC21B). , + 12V monitoring voltage V2 and reference voltage Vref are used for comparison. A monitoring voltage V1 of + 24V is applied to the positive terminal 3 of the MIC 21A, and a reference voltage Vref is applied to the negative terminal 2 of the MIC 21A. A monitoring voltage V2 of + 12V is applied to the 5th terminal which is a positive terminal of the MIC21B, and a reference voltage Vref is applied to the 6th terminal which is a negative terminal of the MIC21B. The results of these comparisons are input to the D-type flip-flop MIC22. This D-type flip-flop MIC 22 includes two D-type flip-flop circuits, one of which (MIC 22A) is used in the present embodiment. The Vcc terminal, which is the power supply terminal of the comparator MIC21, is electrically connected to the other end of the capacitor MC21 whose one end is grounded to ground (GND), and + 5V applied to the Vcc terminal which is the power supply terminal of the comparator MIC21 is Ripple is removed and smoothed by the capacitor MC21, and the GND terminal, which is the ground terminal of the comparator MIC21, is grounded to the ground (GND).

[9-5-2. + 24V power outage or momentary power failure monitoring]
Monitoring of a + 24V power failure or momentary power failure is performed by comparing the monitoring voltage V1 of + 24V with the reference voltage Vref by the MIC21A of the comparator MIC21, as described above. As shown in FIG. 22, the third terminal, which is the positive terminal of the MIC21A of the comparator MIC21 to which the monitoring voltage V1 of + 24V is applied, has the other end and one end of the resistor MR21 whose one end is electrically connected to the + 24V power supply line. Is electrically connected to the other end of the resistor MR22 which is grounded to the ground (GND), the other end of the resistors MR21 and MR22, and the other end of the capacitor MC23 whose one end is grounded to the ground (GND). Are electrically connected. The + 24V monitoring voltage V1 applied to the 3rd terminal, which is the positive terminal of the MIC21A of the comparator MIC21, is divided by + 24V by the resistance ratio of the resistors MR21 and MR22, and the ripple is removed by the capacitor MC23 and smoothed. .. The values of the resistors MR21 and MR22 are the power failure detection voltage V1pf (set to 21.40V in this embodiment) set in advance when the voltage starts to drop from + 24V when + 24V has a power failure or momentary power failure. At that time, the monitoring voltage V1 of + 24V is set to be the same value as the reference voltage Vref.

The first terminal, which is the output terminal of the MIC21A of the comparator MIC21, has an open collector output, and one end is electrically connected to the other end of the pull-up resistor MR23 which is electrically connected to the + 5V power supply line. One end is electrically connected to the other end of the capacitor MC24 which is grounded to the ground (GND), and is electrically connected to the PR terminal which is a preset terminal of the D type flip flop MIC22. The capacitor MC24 plays a role as a low-pass filter.

When the + 24V voltage is larger than the power failure detection voltage V1pf, the + 24V monitoring voltage V1 becomes larger than the reference voltage Vref, and the voltage applied to the first terminal, which is the output terminal of the MIC21A of the comparator MIC21, is + 5V due to the pull-up resistor MR23. The signal pulled up to the side and the logic becomes HI is input to the PR terminal which is the preset terminal of the D type flip-flop MIC22.

On the other hand, when the voltage of + 24V is smaller than the power failure detection voltage V1pf, the monitoring voltage V1 of + 24V becomes smaller than the reference voltage Vref, and the voltage applied to the first terminal which is the output terminal of the MIC21A of the comparator MIC21 is ground (GND). The signal pulled down to the side and the logic becomes LOW is input to the PR terminal which is the preset terminal of the D type flip-flop MIC22.

[9-5-3. + 12V power outage or momentary power failure monitoring]
Monitoring of a + 12V power failure or momentary power failure is performed by comparing the monitoring voltage V2 of + 12V with the reference voltage Vref by the MIC21B of the comparator MIC21, as described above. As shown in FIG. 22, the fifth terminal, which is the positive terminal of the MIC21B of the comparator MIC21 to which the monitoring voltage V2 of + 12V is applied, has the other end and one end of the resistor MR24 whose one end is electrically connected to the + 12V power supply line. Is electrically connected to the other end of the resistor MR25 which is grounded to the ground (GND), the other end of the resistors MR24 and MR25, and the other end of the capacitor MC25 whose one end is grounded to the ground (GND). Are electrically connected. The + 12V monitoring voltage V2 applied to the 5th terminal, which is the positive terminal of the MIC21B of the comparator MIC21, is divided by the resistance ratio of the resistors MR24 and MR25 to + 12V, and the ripple is removed by the capacitor MC25 and smoothed. .. The values of the resistors MR24 and MR25 become the power failure detection voltage V2pf (set to 10.47V in this embodiment) set in advance when the voltage starts to drop from + 12V when + 12V has a power failure or momentary power failure. At that time, the monitoring voltage V2 of + 12V is set to be the same value as the reference voltage Vref.

The 7th terminal, which is the output terminal of the MIC21B of the comparator MIC21, has an open collector output and is electrically connected to the 1st terminal, which is the output terminal of the MIC21A described above. The preset of the D type flip flop MIC22 is electrically connected to the other end of the pull-up resistor MR23 and is electrically connected to the other end of the capacitor MC24 whose one end is grounded to the ground (GND). It is electrically connected to the PR terminal, which is a terminal. As described above, the capacitor MC24 plays a role as a low-pass filter.

When the + 12V voltage is larger than the power failure detection voltage V2pf, the + 12V monitoring voltage V2 becomes larger than the reference voltage Vref, and the voltage applied to the 7th terminal, which is the output terminal of the MIC21B of the comparator MIC21, is + 5V due to the pull-up resistor MR23. The signal pulled up to the side and the logic becomes HI is input to the PR terminal which is the preset terminal of the D type flip-flop MIC22.

On the other hand, when the + 12V voltage is smaller than the power failure detection voltage V2pf, the + 12V monitoring voltage V2 becomes smaller than the reference voltage Vref, and the voltage applied to the 7th terminal which is the output terminal of the MIC21B of the comparator MIC21 is ground (GND). The signal pulled down to the side and the logic becomes LOW is input to the PR terminal which is the preset terminal of the D type flip-flop MIC22.

[9-5-4. Output of power failure warning signal]
The D-type flip-flop MIC22 stores the value (logic) of the signal input to the 1D terminal, which is the D input terminal, due to the change in the edge of the clock signal input to the 1CK terminal, which is the clock input terminal, and this stored value. (Logic) is output from the 1Q terminal which is an output terminal, and the value obtained by inverting the stored value (logic) is output from the negative logic 1Q terminal which is an output terminal. Further, when a signal whose logic is LOW is input to the CLR terminal which is a clear terminal, the D type flip-flop MIC 22 releases the latch state and transfers the logic of the signal input to the PR terminal which is a preset terminal. The inverted signal is output from the 1Q terminal which is the output terminal (at this time, the logic of the signal output from 1Q is inverted, that is, the same as the logic of the signal input to the PR terminal which is the preset terminal. (The logical signal is output from the negative logic 1Q terminal) On the other hand, when the signal whose logic is HI is input to the CLR terminal which is the clear terminal, the latch state is set. Further, in the D type flip-flop MIC22, when a signal whose logic is HI is input to the CLR terminal which is a clear terminal and the latch state is set, the logic is LOW to the PR terminal which is a preset terminal. When the signal becomes, the state of outputting the signal whose logic is HI from the 1Q terminal which is the output terminal is maintained (at this time, the signal obtained by inverting the logic of the signal output from 1Q is negative logic. Maintain the state of output from the 1Q terminal).

In the D-type flip-flop MIC22, in the present embodiment, the 1D terminal which is the D input terminal and the 1CK terminal which is the clock input terminal are grounded to the ground (GND), respectively, so that the 1CK terminal which is the clock input terminal can be used. The circuit is configured so that the edge of the input clock signal does not change, and the value (logic) of the signal input to the 1D terminal, which is the D input terminal, is not stored and output from the 1Q terminal, which is the output terminal. ing. As described above, the D-type flip-flop MIC22 has a signal from the output terminal 1 of the MIC21A of the comparator MIC21 that monitors a + 24V power failure or a momentary power failure and a + 12V power failure at the PR terminal which is a preset terminal. Alternatively, signals from the 7th terminal, which is the output terminal of the MIC21B of the comparator MIC21 that monitors the momentary power failure, are input, and based on these signals, a signal is output from the 1Q terminal, which is the output terminal. The Vcc terminal, which is a power supply terminal, is electrically connected to the other end of the capacitor MC22 whose one end is grounded to ground (GND), and is applied to the Vcc terminal which is the power supply terminal of the D type flip flop MIC22. + 5V is smoothed by removing ripples by the capacitor MC22, the GND terminal, which is the ground terminal, is grounded to ground (GND), and the negative logic 1Q terminal, which inverts the logic of the 1Q terminal, which is the output terminal, is electrical to the outside. It is in an unconnected state.

In the D-type flip-flop MIC22, in the present embodiment, a power failure clear signal from the main control MPU 4100a is input to the CLR terminal, which is a clear terminal, via the main control output circuit 4100ca with a reset function. This power failure clear signal is output started and stopped after a predetermined time has elapsed in the main control side power-on processing described later performed by the main control MPU 4100a. Since the CLR terminal is a negative logic input, the power failure clear signal from the main control MPU 4100a is input to the CLR terminal with its logic set to LOW via the main control output circuit 4100ca with a reset function. The D-type flip-flop MIC22 is designed to release the latch state when a power failure clear signal is input to the CLR terminal. At this time, the logic input to the PR terminal, which is a preset terminal, is inverted and the output terminal is output. Output from the 1Q terminal.

On the other hand, when the output of the power failure clear signal from the main control MPU 4100a is stopped, the logic becomes HI and is input to the CLR terminal via the main control output circuit 4100ca with a reset function. The D-type flip-flop MIC 22 is designed to set a latch state when a power failure clear signal is not input to the CLR terminal, and latches the state in which the logic is LOW and is input to the PR terminal.

The 1Q terminal, which is the output terminal of the D-type flip flop MIC 22, is electrically connected to the input terminal PA1 of the input port PA of the main control MPU 4100a via the main control input circuit 4100b, and is the output terminal of the D-type flip flop MIC 22. The signal output from the 1Q terminal is input to the input terminal PA1 of the input port PA of the main control MPU4100a as a power failure warning signal. Further, the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is electrically connected to the main control output circuit 4100cc without a reset function, and resets the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22. No function The main control output circuit 4100cc outputs the payout control board 4110 as a payout power failure warning signal, and outputs the peripheral control board 4140 as a peripheral power failure warning signal.

As shown in FIG. 22, the main control input circuit 4100b that electrically connects the 1Q terminal which is the output terminal of the D type flip-flop MIC 22 and the input terminal PA1 of the input port PA of the main control MPU 4100a is a D type flip-flop. The 1Q terminal, which is the output terminal of the MIC22, is electrically connected to the other end of the resistor MR26, one end of which is electrically connected to the + 5V power supply line, and electrically to the base terminal of the transistor MTR20 via the resistor MR27. It is connected. In addition to being electrically connected to the resistor MR27, the base terminal of the transistor MTR20 is electrically connected to the other end of the resistor MR28, one end of which is grounded to ground (GND). The emitter terminal of the transistor MTR20 is grounded to ground (GND), and the collector terminal of the transistor MTR20 is electrically connected to the other end of the resistor MR29, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Main control via ICMIC23 (non-inverting buffer ICMIC23 includes eight non-inverting buffer circuits, and formats and outputs the logic of the signal waveform input to one of them (MIC23A) without inverting it). It is electrically connected to the input terminal PA1 of the input port PA of the MPU4100a.

The circuit composed of the resistors MR27, MR28, and the transistor MTR20 is a switch circuit that is turned ON / OFF by a signal output from the 1Q terminal which is the output terminal of the D type flip-flop MIC22.

When the logic of the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is LOW, the voltage applied to the base terminal of the transistor MTR20 is lowered to the ground (GND) side, and the transistor MTR20 is turned off. , The switch circuit will also be turned off. On the other hand, when the logic of the signal output from the 1Q terminal, which is the output terminal of the D type flip-flop MIC22, is HI, the voltage applied to the base terminal of the transistor MTR20 is raised to the + 5V side, and the transistor MTR20 is turned on. The switch circuit will also be turned on.

When both the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the power failure detection voltage V2pf are satisfied, the signal whose logic is HI is the preset of the D type flip-flop MIC22. Since it is input to the PR terminal, which is a terminal, the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, has its logic as LOW and is input to the base terminal of the transistor MTR20, so that the transistor MTR20 is Turn off. As a result, the voltage applied to the collector terminal of the transistor MTR20 is pulled up to the + 5V side by the resistor MR29, and the power failure warning signal whose logic becomes HI via the non-inverting buffer ICMIC23 is the input terminal of the input port PA of the main control MPU4100a. It is input to PA1.

On the other hand, when either of the condition that the voltage of + 24V is smaller than the power failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is satisfied, the signal whose logic is LOW is D. Since it is input to the PR terminal which is the preset terminal of the type flip-flop MIC22, the signal output from the 1Q terminal which is the output terminal of the D type flip-flop MIC22 becomes HI and is input to the base terminal of the transistor MTR20. As a result, the transistor MTR20 is turned on. As a result, the voltage applied to the collector terminal of the transistor MTR20 is lowered to the ground (GND) side, and the power failure warning signal whose logic becomes LOW via the non-inverting buffer ICMIC23 is the input terminal of the input port PA of the main control MPU4100a. It is input to PA1.

Further, the main control output circuit 4100cc without a reset function that outputs the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, to the payout control board 4110 as a payout failure warning signal is open as shown in FIG. The circuit is configured as a collector output type, and the 1Q terminal, which is the output terminal of the D type flip-flop MIC22, is electrically connected to the resistor MR26 of the main control input circuit 4100b described above, and the transistor MTR21 in the previous stage is connected via the resistor MR30. It is electrically connected to the base terminal. The base terminal of the transistor MTR21 in the previous stage is electrically connected to the resistor MR30, and is also electrically connected to the other end of the resistor MR31 whose one end is grounded to ground (GND). The emitter terminal of the transistor MTR21 in the previous stage is grounded to ground (GND), and the collector terminal of the transistor MTR21 in the previous stage is electrically connected to the other end of the resistor MR32 whose one end is electrically connected to the + 5V power supply line. At the same time, it is electrically connected to the base terminal of the transistor MTR22 in the subsequent stage via the resistor MR33. The base terminal of the transistor MTR22 in the subsequent stage is electrically connected to the resistor MR33, and is also electrically connected to the other end of the resistor MR34 whose one end is grounded to ground (GND). The emitter terminal of the latter transistor MTR22 is grounded to ground (GND), and the collector terminal of the latter transistor MTR22 is electrically connected to the other end of the capacitor MC26, one end of which is grounded to ground (GND), and wiring. It is electrically connected to the payout control board 4110 via (harness). When the collector terminal of the transistor MTR22 in the subsequent stage is electrically connected to the payout control board 4110 via wiring (harness), the payout control input of the payout control unit 4120 shown in FIG. 13 on the payout control board 4110. In circuit 4120b, one end is electrically connected to the other end of a pull-up resistor (not shown) that is electrically connected to the + 12V power supply line, and the input terminal and electricity of a predetermined input port of the payout control MPU 4120a shown in FIG. Is connected.

The circuit composed of the resistors MR30, MR31, and the transistor MTR21 in the front stage is the switch circuit in the front stage, and the circuit composed of the resistors MR33, MR34, and the transistor MTR22 in the rear stage is the switch circuit in the rear stage, and is a D type flip-flop. It is turned ON / OFF by the signal output from the 1Q terminal which is the output terminal of the MIC 22.

When the logic of the signal output from the 1Q terminal, which is the output terminal of the D-type flip flop MIC22, is LOW, the voltage applied to the base terminal of the transistor MTR21 in the previous stage is lowered to the ground (GND) side, and the transistor in the previous stage The MTR21 is turned off, the switch circuit in the front stage is also turned off, and the voltage applied to the collector terminal of the transistor MTR21 in the front stage, which is the voltage applied to the base terminal of the transistor MTR22 in the rear stage, is raised to the + 5V side by the resistor MR32. As a result, the transistor MTR22 in the subsequent stage is turned on, and the switch circuit in the subsequent stage is also turned on. On the other hand, when the logic of the signal output from the 1Q terminal, which is the output terminal of the D type flip flop MIC22, is HI, the voltage applied to the base terminal of the transistor MTR21 is raised to the + 5V side, and the transistor MTR21 is turned on. The switch circuit in the front stage is also turned on, and the voltage applied to the collector terminal of the transistor MTR21 in the front stage, which is the voltage applied to the base terminal of the transistor MTR22 in the rear stage, is lowered to the ground (GND) side, so that the switch circuit in the rear stage The transistor MTR22 is turned off, and the switch circuit in the subsequent stage is also turned off.

When both the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the power failure detection voltage V2pf are satisfied, the signal whose logic is HI is the preset of the D type flip-flop MIC22. Since it is input to the PR terminal, which is a terminal, the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, has its logic set to LOW and is input to the base terminal of the transistor MTR21 in the previous stage. Transistor MTR21 is turned off. As a result, the voltage applied to the collector terminal of the transistor MTR21 in the front stage is pulled up to the + 5V side by the resistor MR32 and applied to the base terminal of the transistor MTR22 in the rear stage, so that the transistor MTR22 in the rear stage is turned on. As a result, the voltage applied to the collector terminal of the transistor MTR22 in the subsequent stage is lowered to the ground (GND) side in the payout control board 4110 via the wiring (harness), so that the payout power failure warning signal whose logic is LOW is paid out. It is input to the control board 4110.

On the other hand, when either of the condition that the voltage of + 24V is smaller than the power failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is satisfied, the signal whose logic is LOW is D. Since it is input to the PR terminal, which is the preset terminal of the type flip-flop MIC22, the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, has its logic as HI and becomes the base terminal of the transistor MTR21 in the previous stage. Upon input, the transistor MTR21 in the previous stage is turned on. As a result, the voltage applied to the collector terminal of the transistor MTR 21 in the previous stage is lowered to ground (GND) and applied to the base terminal of the transistor MTR 22 in the subsequent stage, so that the transistor MTR 22 in the subsequent stage is turned off. As a result, the voltage applied to the collector terminal of the transistor MTR22 in the subsequent stage is pulled up to the + 12V side by the pull-up resistor in the payout control input circuit 4120b of the payout control unit 4120 in the payout control board 4110 via the wiring (harness). The payout power failure warning signal whose logic is HI is input to the payout control board 4110.

Further, the main control output circuit 4100cc without a reset function that outputs the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, to the peripheral control board 4140 as a peripheral power failure warning signal is open as shown in FIG. The circuit is configured as a collector output type, and the 1Q terminal, which is the output terminal of the D type flip-flop MIC22, is electrically connected to the resistor MR26 of the main control input circuit 4100b described above, and is the base terminal of the transistor MTR23 via the resistor MR35. Is electrically connected to. In addition to being electrically connected to the resistor MR35, the base terminal of the transistor MTR23 is electrically connected to the other end of the resistor MR36 whose one end is grounded to ground (GND). The emitter terminal of the transistor MTR23 is grounded to ground (GND), and the collector terminal of the transistor MTR23 is electrically connected to the peripheral control board 4140 via wiring (harness). When the collector terminal of the transistor MTR23 is electrically connected to the peripheral control board 4140 via wiring (harness), a peripheral control input circuit (not shown) of the peripheral control unit 4150 in the peripheral control board 4140 shown in FIG. In the above, one end is electrically connected to the other end of a pull-up resistor (not shown) which is electrically connected to the + 12V power supply line, and is electrically connected to the input terminal of the predetermined input port of the peripheral control MPU 4150a shown in FIG. Be connected.

The circuit composed of the resistors MR35, MR36, and the transistor MTR23 is a switch circuit that turns ON / OFF by a signal output from the 1Q terminal which is the output terminal of the D type flip-flop MIC22.

When the logic of the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is LOW, the voltage applied to the base terminal of the transistor MTR23 is lowered to the ground (GND) side, and the transistor MTR23 is turned off. , The switch circuit will also be turned off. On the other hand, when the logic of the signal output from the 1Q terminal, which is the output terminal of the D type flip-flop MIC22, is HI, the voltage applied to the base terminal of the transistor MTR23 is raised to the + 5V side, and the transistor MTR23 is turned on. The switch circuit will also be turned on.

When both the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the power failure detection voltage V2pf are satisfied, the signal whose logic is HI is the preset of the D type flip-flop MIC22. Since it is input to the PR terminal, which is a terminal, the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, has its logic as LOW and is input to the base terminal of the transistor MTR23, so that the transistor MTR23 becomes Turn off. As a result, the voltage applied to the collector terminal of the transistor MTR23 is pulled up to the + 12V side by the pull-up resistor in the payout control input circuit of the peripheral control unit 4150 on the peripheral control board 4140 via the wiring (harness), so that the logic is HI. The peripheral power failure warning signal is input to the peripheral control board 4140.

On the other hand, when either of the condition that the voltage of + 24V is smaller than the power failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is satisfied, the signal whose logic is LOW is D. Since it is input to the PR terminal which is the preset terminal of the type flip-flop MIC22, the signal output from the 1Q terminal which is the output terminal of the D type flip-flop MIC22 becomes HI and is input to the base terminal of the transistor MTR23. As a result, the transistor MTR23 is turned on. As a result, the voltage applied to the collector terminal of the transistor MTR23 is lowered to the ground (GND) side in the peripheral control board 4140 via the wiring (harness), so that the peripheral power failure warning signal whose logic is LOW is sent to the peripheral control board. It is input to 4140.

In this way, the main control input circuit 4100b that transmits the signal output from the 1Q terminal, which is the output terminal of the D type flip flop MIC22, to the main control MPU 4100a as a power failure warning signal, and the 1Q terminal, which is the output terminal of the D type flip flop MIC22. There is no reset function that outputs the signal output from the peripheral control board 4140 as a peripheral power failure warning signal. The main control output circuit 4100cc has one transistor each, and the power failure warning signal and the peripherals input to the main control MPU 4100a. While the logic is the same as the peripheral power failure warning signal input to the control board 4140, the signal output from the 1Q terminal, which is the output terminal of the D type flip flop MIC22, is paid out to the payout control board 4110. There is no reset function to output as a power failure warning signal. The main control output circuit 4100cc has two transistors, the front stage and the rear stage, and the logic of the payout power failure warning signal is the logic of the power failure warning signal input to the main control MPU 4100a and its surroundings. The logic is the reverse of the logic of the peripheral power failure warning signal input to the control board 4140, which is different from the logic of the power failure warning signal and the logic of the peripheral power failure warning signal.

Further, the collector terminal of the transistor MTR20 of the main control input circuit 4100b is electrically connected to the other end of the resistor MR29 whose one end is electrically connected to the + 5V power supply line, and the main control MPU4100a is electrically connected via the non-inverting buffer ICMIC23. The collector terminal of the transistor MTR22 in the subsequent stage of the main control output circuit 4100cc without the reset function is electrically connected to the input terminal PA1 of the input port PA of the above, and is a payout control board via a wiring (harness). In the payout control input circuit 4120b of the payout control unit 4120 in the 4110, one end is electrically connected to the other end of the pull-up resistor electrically connected to the + 12V power supply line, and the main control output circuit 4100cc without a reset function. The collector terminal of the transistor MTR23 is electrically connected to a + 12V power supply line at one end in the payout control input circuit of the peripheral control unit 4150 on the peripheral control board 4140 via a wiring (harness). It is connected to the. This is because the transistor MTR20 of the main control input circuit 4100b and the main control MPU4100a are the main control boards between the collector terminal of the transistor MTR20 of the main control input circuit 4100b and the input terminal PA1 of the input port PA of the main control MPU4100a. Since it is mounted on the 4100, the power failure warning is given by the logic (ON / OFF signal) of the power failure warning signal using + 5V, which is the control reference voltage of the main control MPU 4100a, whereas the main control board 4100 and the payout control board are used. In order to suppress the influence of noise invading the wiring (harness) that electrically connects the boards between the boards of the 4110 and the boards of the main control board 4100 and the peripheral control board 4140, the main control MPU 4100a, The power failure warning is given by the logic (ON / OFF signal) of the power failure warning signal using + 12V, which is a voltage higher than the control reference voltage of + 5V, which is the control reference voltage of the payout control MPU 4120a and the peripheral control MPU 4150a.

[9-6. Various input / output signals to the main control MPU]
Next, various input / output signals to the main control MPU 4100a will be described with reference to FIG. The RXA terminal, which is the serial data input terminal of the serial input port of the main control MPU 4100a, receives the serial data from the payout control board 4110 shown in FIG. 12 as the payer serial data reception signal via the main control input circuit 4100b. .. On the other hand, the TXA terminal and the TXB terminal, which are the serial data output terminals of the serial output port of the main control MPU4100a, use the serial data transmitted from the TXA terminal to the payout control board 4110 as the main payment serial data transmission signal without the reset function. No reset function by transmitting to circuit 4100cc The main control output circuit 4100cc transmits the main payment serial data transmission signal to the payout control board 4110, and the TXB terminal mainly transmits the serial data to be transmitted to the peripheral control board 4140 shown in FIG. As a peripheral serial data transmission signal, it is transmitted to the main control output circuit 4100cc without a reset function, and a main control output circuit 4100cc without a reset function transmits a main peripheral serial data transmission signal to the peripheral control board 4140.

In addition to the above-mentioned operation signal (RAM clear signal) being input to each input terminal of the predetermined input port of the main control MPU4100a, for example, a payout notifying that the above-mentioned main payment serial data reception signal has been normally received. The payer ACK signal from the control board 4110 is input via the main control input circuit 4100b, and the detection signals from various switches such as the upper start port switch 3022 shown in FIG. 12 are input via the main control input circuit 4100b. It is input and so on.

On the other hand, from each output terminal of the predetermined output port of the main control MPU 4100a, for example, the main payment ACK signal for notifying the completion of normal reception of the above-mentioned payer serial data reception signal is output to the main control output circuit 4100ca with a reset function. Then, the main control output circuit 4100ca with a reset function outputs a main payment ACK signal to the payout control board 4110, or the drive signal is sent to the main control output circuit 4100ca with a reset function with respect to the start port solenoid 2105 shown in FIG. Outputs a drive signal from the main control output circuit 4100ca with a reset function to the start port solenoid 2105 via the main control solenoid drive circuit 4100d, and various indicators such as the upper special symbol display 1185 shown in FIG. On the other hand, the drive signal is output to the main control output circuit 4100ca with a reset function, and the drive signal is output from the main control output circuit 4100ca with a reset function to various indicators, and various information (game information) related to the game is output. It is output to the main control output circuit 4100ca with a reset function, and various information (game information) related to the game is output from the main control output circuit 4100ca with a reset function to the payout control board 4110.

[9-7. Interface circuit for communication between the main control board and the peripheral control board]
Next, the communication interface circuit between the main control board 4100 and the peripheral control board 4140 will be described with reference to FIG. 23. In the main control board 4100, + 12V from the power supply board 851 shown in FIG. 18 is supplied via the payout control board 4110, and the + 5V creation circuit 4100g creates + 5V, which is the control reference voltage of the main control MPU 4100a, from this + 12V. ing. The main peripheral serial data transmission signal transmitted from the main control board 4100 to the peripheral control board 4140 is affected by noise that invades the wiring (harness) that electrically connects the main control board 4100 and the peripheral control board 4140. The reliability is enhanced by transmitting using + 12V, which is a voltage higher than + 5V, which is the control reference voltage of the main control MPU4100a, in order to suppress the above.

Specifically, the main control board 4100 makes the main control output circuit 4100cc without a reset function function as a communication interface circuit, and the communication interface circuit mainly comprises resistors MR50, resistors MR51, MR52, and transistors MTR50. Has been done. On the other hand, the peripheral control board 4140 includes a diode AD10, an electrolytic capacitor AC10 (capacitance: 47 μF in this embodiment), and a photocoupler AIC10 (infrared LED and photoIC) as communication interface circuits. It is mainly composed of.).

+ 12V supplied from the power supply board 851 is applied to the anode terminal of the diode MD50 of the main control board 4100 via the payout control board 4110, and the negative terminal is grounded to the ground (GND) to the cathode terminal of the diode MD50. It is electrically connected to the positive terminal of the electrolytic capacitor MC50 (capacitance: 220 microfarad (μF) in this embodiment). The cathode terminal of the diode MD50 is electrically connected to the positive terminal of the electrolytic capacitor MC50, and is also electrically connected to the anode terminal (terminal 1) of the photocoupler AIC10 of the peripheral control board 4140 via wiring (harness). It is connected to the. As a result, when the power from the power supply board 851 is not supplied to the main control board 4100 via the payout control board 4110 due to, for example, a power failure or a momentary power failure, the charge charged in the electrolytic capacitor MC50 is charged. As + 12V, it can be continuously applied from the main control board 4100 to the anode terminal of the photocoupler AIC10 of the peripheral control board 4140.

As described above, the VDD terminal, which is the power supply terminal of the main control MPU4100a, is charged to the electrolytic capacitor MC2 (capacity: 470 μF in this embodiment) shown in FIG. 21 when a power failure or a momentary power failure occurs. Since the charged charge is applied as + 5V, the main peripheral serial transmission port 4100ae built in the main control MPU 4100a serially manages at least the command set by the main control CPU core 4100aa in the transmission buffer register 4100aeb. The unit 4100aec can transfer the data to the transmission shift register 41aea and complete the transmission as main peripheral serial data from the transmission shift register 4100aea.

As described above, the main peripheral serial data transmission signal transmitted from the main control board 4100 to the peripheral control board 4140 is connected to the wiring (harness) that electrically connects the boards between the main control board 4100 and the peripheral control board 4140. In order to suppress the influence of invading noise, its reliability is enhanced by transmitting using + 12V, which is a voltage higher than + 5V, which is the control reference voltage of the main control MPU4100a.

Therefore, in the present embodiment, when a power failure or a momentary power failure occurs, the charge charged in the electrolytic capacitor MC50 is applied as + 12V from the main control board 4100 to the anode terminal of the photocoupler AIC10 of the peripheral control board 4140. Therefore, the main peripheral serial transmission port 4100ae built in the main control MPU 4100a transfers the command set by the main control CPU core 4100aa to the transmission buffer register 4100aeb to the transmission shift register 41aea by the serial management unit 4100aec and transmits the command. When transmitted as main-circle serial data from the shift register 4100aea, a main-circle serial data transmission signal whose logic is HI can be transmitted from the collector terminal of the transistor MTR50 by + 12V.

In the present embodiment, the storage capacity of the transmission buffer register 4100aeb of the main peripheral serial transmission port 4100ae built in the main control MPU 4100a has 32 bytes, and one packet is composed of 3 bytes of data. Therefore, a maximum of 10 packets of data are stored in the transmission buffer register 4100aeb. Further, in the present embodiment, the transfer bit rate of the main peripheral serial data transmitted from the main control MPU 4100a is set to 19200 bps.

The cathode terminal (terminal No. 3) of the photocoupler AIC10 is electrically connected to the collector terminal of the transistor MTR50 of the main control board 4100 via the resistor AR10 and its wiring (harness). The resistor AR10 of the peripheral control board 4140 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler AIC10.

The TXB terminal that outputs the main peripheral serial data transmission signal from the main control MPU4100a shown in FIG. 21 is electrically connected to the other end of the resistor MR50, one end of which is electrically connected to the + 5V power supply line, and the resistor MR51. It is electrically connected to the base terminal of the transistor MTR50 via. In addition to being electrically connected to the resistor MR51, the base terminal of the transistor MTR50 is electrically connected to the other end of the resistor MR52 whose one end is grounded to ground (GND). The emitter terminal of the transistor MTR50 is grounded to ground (GND).

The circuit composed of the resistors MR51, MR52, and the transistor MTR50 is a switch circuit, and when the logic of the main peripheral serial data transmission signal is HI, the voltage applied to the base terminal of the transistor MTR50 is on the ground (GND) side. When it is pulled down, the transistor MTR50 is turned off, and the switch circuit is also turned off. As a result, no forward current flows through the built-in infrared LED of the photocoupler AIC10 of the peripheral control board 4140, so that the photocoupler AIC10 is turned off. On the other hand, when the logic of the main peripheral serial data transmission signal is LOW, the voltage applied to the base terminal of the transistor MTR50 is pulled up to the + 5V side by the resistor MR50, the transistor MTR50 is turned on, and the switch circuit is also turned on. .. As a result, a forward current flows through the built-in infrared LED of the photocoupler AIC10 of the peripheral control board 4140, so that the photocoupler AIC10 is turned on.

+ 5V supplied from the power supply board 851 is applied to the anode terminal of the diode AD10 of the peripheral control board 4140 via the frame peripheral relay terminal plate 868, and the cathode terminal of the diode AD10 and the negative terminal are grounded (GND). It is electrically connected to the positive terminal of the grounded electrolytic capacitor AC10. The cathode terminal of the diode AD10 is electrically connected to the positive terminal of the electrolytic capacitor AC10, and is also electrically connected to the Vcc terminal (terminal 6) which is the power supply terminal of the photocoupler AIC10. The emitter terminal (terminal 4) of the photocoupler AIC10 is grounded to ground (GND), and the collector terminal (terminal 5) of the photocoupler AIC10 is a pull-up resistor that is electrically connected to the positive terminal of the electrolytic capacitor AC10. It is pulled up to the + 5V side by AR11 and is electrically connected to the input terminal of the serial I / O port for the main control board of the peripheral control MPU4150a. When the photocoupler AIC10 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler AIC10 changes, and the signal is used as the main peripheral serial data transmission signal for the serial I / O port for the main control board of the peripheral control MPU4150a. It is input to the input terminal of.

As a result, as described above, when + 5V supplied from the power supply board 851 is no longer supplied to the peripheral control board 4140 via the frame peripheral relay terminal board 868 due to, for example, a power failure or a momentary power failure. The electric charge charged in the electrolytic capacitor AC10 can be continuously applied to the Vcc terminal of the photocoupler AIC10 as + 5V. When + 5V is applied from the electrolytic capacitor AC10 when an electric power or momentary power failure occurs, the main peripheral serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140 is sent to the main control MPU 4100a. The data set in the transmission buffer register 4100aeb of the built-in main-circle serial transmission port 4100ae can be completed, and the main-circle serial data transmission signal during transmission, that is, the main-circle serial data is cut off. The peripheral control board 4140 ensures reception without any omission or omission.

When the logic of the main peripheral serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140 is HI, the voltage applied to the base terminal of the transistor MTR50 is lowered to the ground (GND) side and the transistor. Since the photocoupler AIC10 is turned off when the MTR50 is turned off, the voltage applied to the collector terminal of the photocoupler AIC10 is pulled up to the + 5V side by the pull-up resistor AR11, and the logic becomes HI. The logic of the main peripheral serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140 while the serial data transmission signal is input to the input terminal of the serial I / O port for the main control board of the peripheral control MPU 4150a. When is LOW, the voltage applied to the base terminal of the transistor MTR50 is pulled up to the + 5V side by the resistor MR50, and the transistor MTR50 is turned on to turn on the photocoupler AIC10. Therefore, the photocoupler AIC10 is turned on. The voltage applied to the collector terminal is lowered to the ground (GND) side, and the main peripheral serial data transmission signal whose logic is LOW is input to the input terminal of the serial I / O port for the main control board of the peripheral control MPU4150a. .. As described above, the logic of the main peripheral serial data transmission signal output from the collector terminal of the photocoupler AIC10 is the same as the logic of the main peripheral serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140. It is the logic of.

As described above, in the present embodiment, the + 5V power supply line to which the control reference voltage of the main control MPU 4100a is applied and the + 12V power supply line to which the communication voltage of + 12V applied via the diode MD50 is applied. However, measures are taken when a power failure or momentary power failure occurs and the control reference voltage and communication voltage drop. That is, for the main peripheral serial transmission port 4100ae built in the main control MPU 4100a, a + 5V power supply line, a positive terminal of the electrolytic capacitor MC2 using the electrolytic capacitor MC2 of the main control filter circuit 4100h as the first auxiliary power supply, and Even if the control reference voltage applied from the + 5V power supply line drops due to a power failure or momentary power failure due to the electrical parallel connection, the electrolytic capacitor of the main control filter circuit 4100h, which is the first auxiliary power supply. By applying the control reference voltage from the positive terminal of the MC2, the state in which the control reference voltage is applied can be maintained, and it is composed of the resistors MR50, the resistors MR51, MR52, and the transistor MTR50. No reset function to function as a communication interface circuit For the main control output circuit 4100cc, + 12V applied to the + 12V power supply line is applied to the anode terminal of the diode MD50 as a communication voltage, and the cathode terminal of this diode MD50. And the positive terminal of the electrolytic capacitor MC50, which is the second auxiliary power supply, are electrically connected in parallel, so that a power failure or momentary power failure occurs and the power is applied from the + 12V power supply line via the diode MD50. Even if the voltage drops, the communication voltage from the positive terminal of the electrolytic capacitor MC50, which is the second auxiliary power source, is applied, so that the state in which the communication voltage is applied can be maintained. There is. As a result, it is possible to prevent the command being transmitted from the main control board 4100 to the peripheral control board 4140 to be interrupted, and it is possible to prevent the command from being missing. Therefore, the peripheral control board 4140 reliably receives the command being transmitted. can do. Therefore, it is possible to eliminate the missing command immediately after the occurrence of a power failure or at the time of a momentary power failure.

Further, a plurality of commands set in the transmission buffer register 4100aeb of the main peripheral serial transmission port 4100ae built in the main control MPU 4100a are all composed of resistors MR50, resistors MR51, MR52, and a transistor MTR50 as main peripheral serial data. No reset function to function as a communication interface circuit 470 μF is set as the capacitance of the electrolytic capacitor MC2 of the main control filter circuit 4100 h so that transmission to the peripheral control board 4140 can be completed via the main control output circuit 4100 cc. Therefore, 220 μF is set as the capacitance of the electrolytic capacitor MC50. As a result, even if a power failure or a momentary power failure occurs during transmission from the main control board 4100 to the peripheral control board 4140, all the commands set in the transmission buffer register 4100aeb are reset to function as an interface circuit as main peripheral serial data. Since transmission to the peripheral control board 4140 can be completed via the main control output circuit 4100 cc without a function, the peripheral control board 4140 does not interrupt a plurality of commands set in the transmission buffer register 4100aeb and is missing. It can be received reliably without any problems.

[10. Payout control board circuit]
Next, the circuit and the like of the payout control board 4110 shown in FIG. 13 will be described with reference to FIGS. 24 to 29. FIG. 24 is a circuit diagram showing a circuit of the payout control unit and the like, FIG. 25 is a circuit diagram showing a payout control input circuit, FIG. 26 is a circuit diagram showing a continuation of FIG. 25, and FIG. 27 is a payout motor drive. FIG. 28 is a circuit diagram showing a circuit, FIG. 28 is a circuit diagram showing a CR unit input / output circuit, and FIG. 29 is an input / output diagram showing various input / output signals to and from the main control board and various output signals to an external terminal board. Is. First, the payout control filter circuit will be described, and then the payout control unit circuit, various input / output signals with the main control board, and various output signals to the external terminal board will be described.

[10-1. Payout control filter circuit]
As shown in FIG. 24, the payout control filter circuit 4110a mainly includes the payout control 3-terminal filter PIC0. The payout control 3-terminal filter PIC0 is a T-type filter circuit, which is magnetically shielded with ferrite and has excellent attenuation characteristics. + 5V from the power supply board 851 shown in FIG. 18 is applied to the 1st terminal of the payout control 3-terminal filter PIC0, and one end is electrically connected to the other end of the capacitor PC0 grounded to the ground (GND). + 5V from the power supply board 851 is first smoothed by removing ripples (AC components folded by the voltage) by the capacitor PC0. The 2nd terminal of the payout control 3 terminal filter PIC0 is grounded to ground (GND), and the 3rd terminal of the payout control 3 terminal filter PIC0 outputs + 5V from which the noise component is removed.

The third terminal of the payout control three-terminal filter PIC0 is the other end of the capacitor PC1 and the electrolytic capacitor PC2 (capacitance: 180 microfarad (μF) in this embodiment) whose one end is grounded to ground (GND). By being electrically connected to each other, ripples are further removed from + 5V output from the 3rd terminal of the payout control 3-terminal filter PIC0 to smooth the filter. This smoothed + 5V is applied to the power supply terminal of the payout control system reset PIC1, the VCS terminal which is the power supply terminal of the payout control crystal oscillator PX0, the VDD terminal which is the power supply terminal of the payout control MPU4120a, and the like, which will be described later. .. If a power failure or momentary power failure occurs at the VDD terminal, which is the power supply terminal of the payout control MPU4120a, and the power supply from the pachinko island facility is cut off, the electric charge charged in the electrolytic capacitor PC2 will cause a power failure or momentary power failure. It is applied as + 5V over a period of about 7 milliseconds (ms) after it is generated.

The VDD terminal of the payout control MPU4120a is electrically connected to the other end of the capacitor PC3 whose one end is grounded to ground (GND), and the + 5V applied to the VDD terminal is further stripped of ripples by the capacitor PC3 and smoothed. ing. The VSS terminal, which is the ground terminal of the payout control MPU4120a, is grounded to the ground (GND).

Further, the DDR terminal of the payout control MPU4120a is electrically connected to the anode terminal of the diode PD0 in addition to being electrically connected to the capacitor PC3. The cathode terminal of the diode PD0 is electrically connected to the VBB terminal, which is the power supply terminal of the RAM (RAM with built-in payout control) built in the payout control MPU4120a, and one end of the capacitor PC4 is grounded to ground (GND). It is electrically connected to the other end of the. The VBB terminal of the RAM with built-in payout control is electrically connected to the cathode terminal of the diode PD0 and the other end of the capacitor PC4, and also via the resistor PR0, the plus of the capacitor BC1 of the power supply board 851 shown in FIG. It is electrically connected to the terminal. That is, + 5V smoothed by removing the noise component by the payout control filter circuit 4110a is applied to the VDD terminal of the payout control MPU4120a, and is applied to the VBB terminal of the payout control built-in RAM and the capacitor BC1 via the diode PD0. It is designed to be applied to the positive terminal of. As a result, as described above, when the + 5V created by the + 5V power supply creation circuit 855db of the power supply creation circuit 855d of the power supply board 851 shown in FIG. 18 is no longer supplied to the payout control board 4110, the capacitor BC1 is charged. Since the charged charge is supplied to the payout control board 4110 as the payout VBB, the current is blocked by the diode PD0 and does not flow to the VDD terminal of the payout control MPU4120a, and the payout control MPU4120a does not operate. The stored contents are retained by applying a pay VBB to the VBB terminal of the built-in RAM.

[10-2. Payout control unit circuit]
In addition to the payout control MPU 4120a, the payout control input circuit 4120b, the payout control output circuit 4120c, the payout motor drive circuit 4120d, and the CR unit input / output circuit 4120e, the payout control unit 4120 resets as peripheral circuits as shown in FIG. It mainly consists of a payout control system reset PIC1 that outputs a signal and a payout control crystal oscillator PX0 (8 megahertz (MHz) in this embodiment) that outputs a clock signal. Here, the payout control system reset will be described first, and then the payout control crystal oscillator, the payout control input circuit, the payout motor drive circuit, the CR unit input / output circuit, and various input / output signals to the payout control MPU will be described.

[10-2-1. Payout control system reset]
As shown in FIG. 24, + 5V smoothed by removing the noise component by the payout control filter circuit 4110a is applied to the power supply terminal of the payout control system reset PIC1. The payout control system reset PIC1 resets the payout control MPU 4120a and the payout control output circuit 4120ca with a reset function, respectively, and has a built-in delay circuit. The delay capacitance terminal of the payout control system reset PIC1 is electrically connected to the other end of the capacitor PC5 whose one end is grounded to ground (GND), and the delay time by the delay circuit is set by the capacitance of this capacitor PC5. You can do it. Specifically, the payout control system reset PIC1 outputs a system reset signal from the output terminal after the delay time elapses when the + 5V input to the power supply terminal reaches a threshold value (for example, 4.25V).

The output terminal of the payout control system reset PIC1 is electrically connected to the SRT0 terminal, which is the reset terminal of the payout control MPU 4120a, and the reset terminal of the payout control output circuit 4120ca with a reset function. The output terminal is an open collector output type, and is a capacitor whose one end is electrically connected to the other end of the pull-up resistor PR1 which is electrically connected to the + 5V power supply line, and one end is grounded to ground (GND). It is electrically connected to the other end of the PC 6. This capacitor PC6 plays a role as a low-pass filter. When the voltage input to the power supply terminal is larger than the threshold value, the output terminal is pulled up to the + 5V side by the pull-up resistor PR1 and the logic becomes HI, and this logic becomes the SRT0 terminal of the payout control MPU4120a and the payout control output with a reset function. While each is input to the reset terminal of the circuit 4120ca, when the voltage input to the power supply terminal is smaller than the threshold value, the logic becomes LOW, and this logic becomes the SRT0 terminal of the payout control MPU 4120a and the payout control output circuit 4120ca with a reset function. It is input to each reset terminal. Since the SRT0 terminal of the payout control MPU4120a and the reset terminal of the payout control output circuit 4120ca with a reset function are each negative logic inputs, when the voltage input to the power supply terminal becomes smaller than the threshold value, the payout control MPU4120a and the reset function The payout control output circuit 4120ca is reset. The power supply terminal is electrically connected to the other end of the capacitor PC7 whose one end is grounded to ground (GND), and the + 5V input to the power supply terminal is smoothed by removing ripples. Further, the ground terminal is grounded to the grant (GND), and the NC terminal is in a state of being electrically unconnected to the outside.

[10-2-2. Payout control crystal oscillator]
As shown in FIG. 24, the + 5V smoothed by removing the noise component by the payout control filter circuit 4110a is input to the VCS terminal which is the power supply terminal of the payout control crystal oscillator PX0. This VCS terminal is electrically connected to the other end of the capacitor PC8 whose one end is grounded to ground (GND), and the + 5V input to the VCS terminal is further stripped of ripples and smoothed. Further, this smoothed + 5V is applied not only to the VCS terminal but also to the OE terminal which is the output enable terminal of the payout control crystal oscillator PX0. The payout control crystal oscillator PX0 outputs an 8 MHz clock signal from the OUT terminal, which is an output terminal, by applying + 5 V to its OE terminal.

The OUT terminal of the payout control crystal oscillator PX0 is electrically connected to the MCLK terminal, which is the clock terminal of the payout control MPU4120a, and an 8 MHz clock signal is input to the payout control MPU4120a. The GND terminal, which is the ground terminal of the payout control crystal oscillator PX0, is grounded to the grant (GND).

[10-2-3. Payout control input circuit]
The payout control input circuit 4120b receives a payout power failure warning signal from the power failure monitoring circuit 4100e provided in the door frame opening switch 618, the main body frame opening switch 619, and the main control board 4100 shown in FIG. The circuit, the handle relay terminal plate 192 shown in FIG. 13, the circuit in which the detection signal from the full tank switch 550 is input via the power supply board 851, the circuit in which the operation signal from the operation switch 860a is input, and the like. First, the circuit in which the detection signal from the door frame opening switch is input will be described, followed by the circuit in which the detection signal from the main body frame opening switch is input, the circuit in which the payout power failure warning signal from the power failure monitoring circuit is input, and the circuit in which the payout power failure warning signal from the power failure monitoring circuit is input. A circuit in which a detection signal from a full switch is input and a circuit in which an operation signal from an operation switch is input will be described. Since the output terminals of various detection switches such as the full tank switch 550, the out-of-ball switch 750, the counting switch 751, and the rotation angle switch 752 shown in FIG. 13 are open collector output types, the various detection switches can be used. Since the circuit configuration in which the detection signal is input is almost the same, a circuit in which the detection signal from the full switch is input will be described here.

[10-2-3 (a). Circuit to which the detection signal from the door frame open switch is input]
The door frame opening switch 618 uses a normally closed type (normally closed (NC)), and the switch is turned on (conducting) when the door frame 5 is opened from the main body frame 3 as shown in FIG. 1, and the door frame is turned on. The switch is turned off (disconnected) when 5 is closed to the main body frame 3. The second terminal of the door frame opening switch 618 is grounded to the ground (GND), while the first terminal of the door frame opening switch 618 has a pull-up resistor PR20 whose one end is electrically connected to the + 5V power supply line. It is electrically connected to the end and is also electrically connected to the base terminal of the transistor PTR20 via a resistor PR21. In addition to being electrically connected to the resistor PR21, the base terminal of the transistor PTR20 is electrically connected to the other end of the resistor PR22 whose one end is grounded to ground (GND). Further, the first terminal of the door frame opening switch 618 is electrically connected to the pull-up resistor PR20, and is also electrically connected to the other end of the capacitor PC20 whose one end is grounded to the ground (GND). .. The emitter terminal of the transistor PTR20 is grounded to ground (GND), and the collector terminal of the transistor PTR20 is electrically connected to the other end of the resistor PR23, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Payout control via ICPIC20 (non-inverting buffer ICPIC20 includes eight non-inverting buffer circuits, and formats and outputs the logic of the signal waveform input to one of them (PIC20A) without inverting it). It is electrically connected to the input terminal PA0 of the input port PA of the MPU4120a. When the transistor PTR 20 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR 20 changes, and the signal is input to the input terminal PA0 of the input port PA of the payout control MPU4120a as a door opening signal.

Further, the first terminal of the door frame opening switch 618 is pulled up to the + 5V side by the pull-up resistor PR20 and electrically connected to the base terminal of the transistor PTR20 via the resistor PR21, and is also connected to the base terminal of the transistor PTR20 by the pull-up resistor PR20 on the + 5V side. It is pulled up to and electrically connected to the base terminal of the transistor PTR21 via a resistor PR24. In addition to being electrically connected to the resistor PR24, the base terminal of the transistor PTR21 is electrically connected to the other end of the resistor PR25, one end of which is grounded to ground (GND). The emitter terminal of the transistor PTR21 is grounded to ground (GND), and the collector terminal of the transistor PTR21 is electrically connected to the external terminal board 784 via wiring (harness). When the collector terminal of the transistor PTR21 is electrically connected to the external terminal board 784 via wiring (harness), one end of the external terminal board 784 is electrically connected to the + 12V power supply line, which is not shown. It is electrically connected to the other end of the up resistor. When the transistor PTR21 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR21 is changed, and the signal is input to the external terminal board 784 as an outer end frame door opening information output signal.

Further, the first terminal of the door frame opening switch 618 is pulled up to the + 5V side by the pull-up resistor PR20 and electrically connected to the base terminal of the transistor PTR20 via the resistor PR21, and is also electrically connected to the + 5V side by the pull-up resistor PR20. In addition to being pulled up to the base terminal of the transistor PTR21 via the resistor PR24, it is pulled up to the + 5V side by the pull-up resistor PR20 and electrically connected to the base terminal of the transistor PTR22 via the resistor PR26. ing. In addition to being electrically connected to the resistor PR26, the base terminal of the transistor PTR22 is electrically connected to the other end of the resistor PR27, one end of which is grounded to ground (GND). The emitter terminal of the transistor PTR22 is grounded to ground (GND), and the collector terminal of the transistor PTR22 is electrically connected to the main control board 4100 shown in FIG. 12 via wiring (harness). When the collector terminal of the transistor PTR22 is electrically connected to the main control board 4100 via wiring (harness), one end of the main control input circuit 4100b of the main control board 4100 shown in FIG. 12 is a + 12V power supply. It is electrically connected to the other end of a pull-up resistor (not shown) that is electrically connected to the line. When the transistor PTR22 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR22 changes, and the signal is input to the main control board 4100 as a main frame door opening signal.

The circuit composed of the pull-up resistor PR20 and the capacitor PC20 is a switch signal generation circuit, and when the door frame 5 is opened from the main body frame 3 or when the door frame 5 is closed by the main body frame 3. It is configured as a circuit having a function of absorbing voltage fluctuations from the door frame opening switch 618 due to a fluttering phenomenon in which the contacts constituting the door frame opening switch 618 are repeatedly turned on and off for a short time.

The circuit composed of the resistors PR21, PR22 and the transistor PTR20, the circuit composed of the resistors PR24, PR25 and the transistor PTR21, and the circuit composed of the resistors PR26, PR27 and the transistor PTR22 are door frame opening switches. It is a switch circuit that turns ON / OFF according to the detection signal from 618.

When the door frame 5 is opened from the main body frame 3, the door frame opening switch 618 is ON, so that the voltage applied to the base terminal of the transistor PTR 20 is lowered to the ground (GND) side, so that the transistor PTR 20 is opened. It turns off, and the switch circuit also turns off. As a result, the voltage applied to the collector terminal of the transistor PTR20 is pulled up to the + 5V side by the pull-up resistor PR23, and the door frame opening signal whose logic is HI is input to the input terminal PA0 of the input port PA of the payout control MPU4120a. NS. Further, in the state where the door frame 5 is opened from the main body frame 3, since the door frame opening switch 618 is ON, the voltage applied to the base terminal of the transistor PTR21 is lowered to the ground (GND) side, so that the transistor The PTR21 is turned off, and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR21 is pulled up to the + 12V side by the pull-up resistance of the external terminal board 784 via the wiring (harness), and the logic becomes HI. Is input to the external terminal board 784. Further, in the state where the door frame 5 is opened from the main body frame 3, since the door frame opening switch 618 is ON, the voltage applied to the base terminal of the transistor PTR22 is lowered to the ground (GND) side, so that the transistor The PTR 22 is turned off, and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR22 is pulled up to the + 12V side by the pull-up resistance of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. The door opening signal is input to the main control board 4100.

On the other hand, when the door frame 5 is closed from the main body frame 3, the door frame opening switch 618 is turned off, so that the voltage applied to the base terminal of the transistor PTR 20 is pulled up to the + 5V side by the pull-up resistor PR20. Then, the transistor PTR20 is turned on, and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR 20 is lowered to the ground (GND) side, and the door frame opening signal whose logic is LOW is input to the input terminal PA0 of the input port PA of the payout control MPU4120a. Further, when the door frame 5 is closed from the main body frame 3, the door frame opening switch 618 is turned off, so that the voltage applied to the base terminal of the transistor PTR 21 is raised to the + 5 V side, so that the transistor PTR 21 is turned on. However, the switch circuit will also be turned on. As a result, the voltage applied to the collector terminal of the transistor PTR21 is lowered to the ground (GND) side, and the outer end frame door opening information output signal whose logic is LOW is input to the external terminal board 784. Further, when the door frame 5 is closed from the main body frame 3, the door frame opening switch 618 is turned off, so that the voltage applied to the base terminal of the transistor PTR 22 is raised to the + 5 V side, so that the transistor PTR 22 is turned on. However, the switch circuit will also be turned on. As a result, the voltage applied to the collector terminal of the transistor PTR22 is lowered to the ground (GND) side, and the main frame door opening signal whose logic is LOW is input to the main control board 4100.

In this way, when the door frame 5 is opened from the main body frame 3, when the door frame opening switch 618 is turned on, the door frame opening signal whose logic is HI is the input terminal of the input port PA of the payout control MPU4120a. The outer end frame door opening information output signal input to PA0 and whose logic is HI is input to the external terminal board 784, and the main frame door opening signal whose logic is HI is input to the main control board 4100. When the door frame 5 is closed to the main body frame 3, the door frame opening switch 618 is turned off, so that the door frame opening signal whose logic is LOW is input to the input terminal PA0 of the input port PA of the payout control MPU4120a. , The outer end frame door opening information output signal whose logic is LOW is input to the external terminal board 784, and the main frame door opening signal whose logic is LOW is input to the main control board 4100.

[10-2-3 (b). Circuit to which the detection signal from the main body frame release switch is input]
The main body frame release switch 619 uses a normally closed type (normally closed (NC)), and the switch is turned on (conducting) with the main body frame 3 released from the outer frame 2 as shown in FIG. 1, and the main body frame is turned on. The switch is turned off (disconnected) when 3 is closed to the outer frame 2. The 2nd terminal of the main body frame opening switch 619 is grounded to the ground (GND), while the 1st terminal of the main body frame opening switch 619 has a pull-up resistor PR28 whose one end is electrically connected to the + 5V power supply line. It is electrically connected to the end and is also electrically connected to the base terminal of the transistor PTR23 via a resistor PR29. The base terminal of the transistor PTR23 is electrically connected to the resistor PR29, and is also electrically connected to the other end of the resistor PR30 whose one end is grounded to ground (GND). In addition to being electrically connected to the pull-up resistor PR28, the first terminal of the main body frame release switch 619 is electrically connected to the other end of the capacitor PC21 whose one end is grounded to ground (GND). .. The emitter terminal of the transistor PTR23 is grounded to ground (GND), and the collector terminal of the transistor PTR23 is electrically connected to the collector terminal of the transistor PTR21 described above, and is connected to the external terminal board 784 via wiring (harness). It is electrically connected. When the collector terminal of the transistor PTR23 is electrically connected to the external terminal board 784 via wiring (harness), one end of the external terminal board 784 is electrically connected to the + 12V power supply line, which is not shown. It is electrically connected to the other end of the up resistor. When the transistor PTR23 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR23 is changed, and the signal is input to the external terminal board 784 as the outer end frame door opening information output signal.

Further, the first terminal of the main body frame opening switch 619 is pulled up to the + 5V side by the pull-up resistor PR28 and electrically connected to the base terminal of the transistor PTR23 via the resistor PR29, and is also connected to the base terminal of the transistor PTR23 by the pull-up resistor PR28 on the + 5V side. It is pulled up to and electrically connected to the base terminal of the transistor PTR24 via a resistor PR31. In addition to being electrically connected to the resistor PR31, the base terminal of the transistor PTR24 is electrically connected to the other end of the resistor PR32, one end of which is grounded to ground (GND). The emitter terminal of the transistor PTR24 is grounded to ground (GND), and the collector terminal of the transistor PTR24 is electrically connected to the collector terminal of the transistor PTR22 described above, and is shown in FIG. 12 via wiring (harness). It is electrically connected to the main control board 4100. When the collector terminal of the transistor PTR24 is electrically connected to the main control board 4100 via wiring (harness), one end of the main control input circuit 4100b of the main control board 4100 shown in FIG. 12 is a + 12V power supply. It is electrically connected to the other end of a pull-up resistor (not shown) that is electrically connected to the line. When the transistor PTR24 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR24 changes, and the signal is input to the main control board 4100 as a main frame door opening signal.

The circuit composed of the pull-up resistor PR28 and the capacitor PC21 is a switch signal generation circuit, and when the main body frame 3 is released from the outer frame 2 or when the main body frame 3 is closed by the outer frame 2. It is configured as a circuit having a function of absorbing voltage fluctuations from the main body frame opening switch 619 due to a fluttering phenomenon in which the contacts constituting the main body frame opening switch 619 are repeatedly turned on and off for a short time.

The circuit composed of the resistors PR29 and PR30 and the transistor PTR23 and the circuit composed of the resistors PR31, PR32 and the transistor PTR24 are switch circuits that are turned ON / OFF by a detection signal from the main body frame opening switch 619.

When the main body frame 3 is released from the outer frame 2, since the main body frame release switch 619 is ON, the voltage applied to the base terminal of the transistor PTR23 is lowered to the ground (GND) side, so that the transistor PTR23 is opened. It turns off, and the switch circuit also turns off. As a result, the voltage applied to the collector terminal of the transistor PTR23 is pulled up to the + 12V side by the pull-up resistance of the external terminal board 784 via the wiring (harness), and the logic becomes HI. Is input to the external terminal board 784. Further, in the state where the main body frame 3 is opened from the outer frame 2, since the main body frame opening switch 619 is ON, the voltage applied to the base terminal of the transistor PTR24 is lowered to the ground (GND) side, so that the transistor The PTR24 is turned off, and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR24 is pulled up to the + 12V side by the pull-up resistance of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. The door opening signal is input to the main control board 4100.

On the other hand, when the main body frame 3 is closed to the outer frame 2, since the main body frame opening switch 619 is OFF, the voltage applied to the base terminal of the transistor PTR23 is pulled up to the + 5V side by the pull-up resistor PR28. Then, the transistor PTR23 is turned on, and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR23 is lowered to the ground (GND) side in the external terminal board 784 via the wiring (harness), and the logic becomes LOW. It is input to the external terminal board 784. Further, in the state where the main body frame 3 is closed to the outer frame 2, since the main body frame opening switch 619 is OFF, the voltage applied to the base terminal of the transistor PTR24 is pulled up to the + 5V side by the pull-up resistor PR28. Then, the transistor PTR24 is turned on, and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR24 is lowered to the ground (GND) side in the main control board 4100 via the wiring (harness), and the main frame door opening signal whose logic becomes LOW is the main control board. It is input to 4100.

In this way, when the main body frame 3 is released from the outer frame 2, the main body frame opening switch 619 is turned on, so that the outer end frame door opening information output signal whose logic is HI is input to the external terminal board 784. The main frame door opening signal whose logic is HI is input to the main control board 4100, while when the main body frame 3 is closed to the outer frame 2, the main frame opening switch 619 is turned off to perform logic. The outer end frame door opening information output signal whose logic is LOW is input to the external terminal board 784, and the main frame door opening signal whose logic is LOW is input to the main control board 4100.

In the present embodiment, as described above, one or both of the state in which the door frame 5 is closed to the main body frame 3 and the state in which the main body frame 3 is opened from the outer frame 2 are in the present embodiment. Even in the case of, since the main frame door opening signal is input to the main control board 4100, the main control MPU 4100a of the main control board 4100 shown in FIG. 12 has the main frame door opening signal. Although it is not possible to determine whether the door frame 5 is open from the main body frame 3 or the main body frame 3 is open from the outer frame 2, the door frame 5 and / or The player can determine that the main body frame 3 is open, which does not occur during the normal game, and the outer end frame door opening information output signal is sent to the external terminal plate 784. Since it is input, this outer end frame door opening information output signal is transmitted to the hall computer via the external terminal plate 784, and the hall computer uses the outer end frame door opening information output signal to transmit the door frame. Although it is not possible to determine whether 5 is in the state of being released from the main body frame 3 or the main body frame 3 is in the state of being released from the outer frame 2, the door frame 5 and / or the main body frame 3 is opened. It is possible to determine that the player who is playing the door has a state that does not occur during the normal game.

Further, in the present embodiment, as described above, by adopting the normally closed switch for the door frame opening switch 618 and the main body frame opening switch 619, the door frame opening switch 618 is short-circuited for some reason and the switch is turned on ( Even if the door frame 5 is released from the main body frame 3 and the main body frame opening switch 619 is short-circuited for some reason and the switch is turned on (conducting), the main body frame is turned on. 3 is released from the outer frame 2. In this way, by adopting the normally closed switch for the door frame opening switch 618 and the main body frame opening switch 619, the main frame door opening signal can be output to the main control board 4100 even at the time of a short circuit, and the outer end can be output. The frame door opening information output signal can be transmitted to the hall computer via the external terminal board 784.

If the door frame opening switch 618 and the main body frame opening switch 619 are changed from the normally closed switch to the normally open type (normally open (NO)) switch (door frame opening switch 618'and main body frame opening switch 619'), , The door frame opening switch 618'turns on (conducts) when the door frame 5 is closed from the main body frame 3, and turns off (disconnects) when the door frame 5 is opened to the main body frame 3. .. The main body frame opening switch 619'turns on (conducts) when the main body frame 3 is closed from the outer frame 2, and turns off (disconnects) when the main body frame 3 is opened to the outer frame 2. Then, even if the door frame opening switch 618'is disconnected for some reason and the switch is turned off (disconnected), the door frame 5 is released from the main body frame 3 and the main body is released for some reason. Even if the frame opening switch 619'is disconnected and the switch is turned off (disconnected), the main body frame 3 is released from the outer frame 2. In this way, even if the door frame opening switch 618'and the main body frame opening switch 619'are adopted as normally open switches, the main frame door opening signal can be output to the main control board 4100 even when the wire is broken. The outer end frame door opening information output signal can be transmitted to the hall computer via the external terminal board 784.

[10-2-3 (c). A circuit to which a power outage warning signal is input from the power outage monitoring circuit]
The transmission line for transmitting the payout power failure warning signal from the power failure monitoring circuit 4100e provided in the main control board 4100 is electrically connected to and resists the other end of the pull-up resistor PR40 whose one end is electrically connected to the + 12V power supply line. It is electrically connected to the base terminal of the transistor PTR40 via PR41. In addition to being electrically connected to the resistor PR41, the base terminal of the transistor PTR40 is electrically connected to the other end of the resistor PR42, one end of which is grounded to ground (GND). The emitter terminal of the transistor PTR40 is grounded to ground (GND), and the collector terminal of the transistor PTR40 is electrically connected to the other end of the resistor PR43, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Payout control via ICPIC40 (non-inverting buffer ICPIC40 includes eight non-inverting buffer circuits, and shapes and outputs the logic of the signal waveform input to one of them (PIC40A) without inverting it). It is electrically connected to the input terminal PA1 of the input port PA of the MPU4120a. When the transistor PTR40 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR40 changes, and the signal is input to the input terminal PA1 of the input port PA of the payout control MPU4120a as a payout power failure warning signal.

The circuit composed of the resistors PR41 and PR42 and the transistor PTR40 is a switch circuit that is turned ON / OFF by a payout power failure warning signal from the power failure monitoring circuit 4100e provided in the main control board 4100.

As described above, the power failure monitoring circuit 4100e monitors the signs of power failure or momentary power failure of two types of voltages, + 12V and + 24V, from the power supply board 851, and when the power failure or momentary power failure sign is detected, there is no reset function. A payout power failure warning signal is output to the payout control board 4110 as a power failure notice via the main control output circuit 4100 cc. The power failure monitoring circuit 4100e monitors signs of power failure or momentary power failure of + 12V and + 24V voltages, and as described above, the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf, and the voltage of + 12V is higher than the power failure detection voltage V2pf. When both of the conditions of being large are satisfied, the voltage applied to the collector terminal of the transistor MTR22 in the subsequent stage is lowered to the ground (GND) side on the payout control board 4110 via the wiring (harness), and the logic becomes LOW. While the payout power failure warning signal is input to the payout control board 4110, one of the conditions that the + 24V voltage is smaller than the power failure detection voltage V1pf and the + 12V voltage is smaller than the power failure detection voltage V2pf. When the condition is satisfied, the voltage applied to the collector terminal of the transistor MTR22 in the subsequent stage is pulled up to the + 12V side by the pull-up resistor PR40 described above via the wiring (harness), and the logic becomes HI. Is input to the payout control board 4110.

When both the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the power failure detection voltage V2pf are satisfied, that is, there is no sign of power failure or momentary power failure of the + 12V and + 24V voltages. Occasionally, a payout power failure warning signal whose logic is LOW is input to the payout control board 4110, so that the voltage applied to the base terminal of the transistor PTR40 is lowered to the ground (GND) side, so that the transistor PTR40 is turned off. The voltage applied to the collector terminal of the transistor PTR40 is raised to the + 5V side by the resistor PR43. As a result, the payout power failure warning signal whose logic is HI is input from the collector terminal of the transistor PTR40 to the input terminal PA1 of the input port PA of the payout control MPU4120a.

On the other hand, when either of the condition that the voltage of + 24V is smaller than the power failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is satisfied, that is, the voltage of + 12V and / or + 24V When there is a sign of power failure or momentary power failure, the payout power failure warning signal whose logic is HI is input to the payout control board 4110, so that the payout power failure warning signal from the power failure monitoring circuit 4100e is applied to the base terminal of the transistor PTR40. When the voltage is pulled up to the + 12V side by the pull-up resistor PR40, the transistor PTR40 is turned on, and the voltage applied to the collector terminal of the transistor PTR40 is lowered to the ground (GND) side. As a result, the payout power failure warning signal in which the logic of the collector terminal of the transistor PTR40 is LOW is input to the input terminal PA1 of the input port PA of the payout control MPU4120a.

In this way, when there is a sign of power failure or momentary power failure of + 12V and / or + 24V voltage, the payout power failure warning signal whose logic is HI is input to the input terminal PA1 of the input port PA of the payout control MPU4120a, while When there is no sign of a power failure or momentary power failure of the + 12V and + 24V voltages, the payout power failure warning signal whose logic is LOW is input to the input terminal PA1 of the input port PA of the payout control MPU4120a. As described above, when there is a sign of a power failure or momentary power failure of + 12V and / or + 24V, a power failure warning signal whose logic is HI is input to the input terminal PA1 of the input port PA of the main control MPU4100a. On the other hand, when there is no sign of power failure or momentary power failure of + 12V and + 24V voltage, the power failure warning signal is input to the input terminal PA1 of the input port PA of the main control MPU4100a, so that the power failure monitoring circuit 4100e The logic of the payout power failure warning signal input to the payout control MPU 4120a and the logic of the power failure notice signal input to the main control MPU 4100a according to the power failure notice are the same logic.

[10-2-3 (d). Circuit to which the detection signal from the full switch is input]
The detection signal from the full tank switch 550 provided in the foul cover unit 540 shown in FIG. 1 is transmitted to the payout control board 4110 via the handle relay terminal board 192 shown in FIG. 1 and the power supply board 851 shown in FIG. It has been entered. The output terminal of the full switch 550 is configured as an open collector output type in which the emitter terminal is grounded to ground (GND), and one end of the payout control board 4110 is electrically connected to the + 12V power supply line. It is electrically connected to the other end of the pull-up resistor PR44a and is also electrically connected to the first terminal of the 3-terminal filter PIC50 for a full tank switch. The 3-terminal filter PIC50 for a full-tan switch is a T-type filter circuit, which is magnetically shielded with ferrite and has excellent attenuation characteristics.

The 2nd terminal of the 3-terminal filter PIC50 for a full-tan switch is grounded to ground (GND), and the 3rd terminal of the 3-terminal filter PIC50 for a full-tan switch is a 3-terminal filter PIC50 for a full-tan switch via a resistor PR44b. It is electrically connected to the first terminal of the transistor PTR41 and is also electrically connected to the base terminal of the transistor PTR41 via the resistor PR45. As a result, the detection signal of the full-tank switch 550 is input to the base terminal of the transistor PTR41 after removing the noise component in the 3-terminal filter PIC50 for the full-tank switch. In addition to being electrically connected to the resistor PR45, the base terminal of the transistor PTR41 is electrically connected to the other end of the resistor PR46, one end of which is grounded to ground (GND), and one end to ground (GND). It is electrically connected to the other end of the electrically connected capacitor PC40. The capacitor PC 40 plays a role as a low-pass filter. The emitter terminal of the transistor PTR41 is grounded to ground (GND), and the collector terminal of the transistor PTR41 is electrically connected to the other end of the resistor PR47, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Payout control via ICPIC40 (non-inverting buffer ICPIC40 includes eight non-inverting buffer circuits, and shapes and outputs the logic of the signal waveform input to one of them (PIC40B) without inverting it). It is electrically connected to the input terminal PA2 of the input port PA of the MPU4120a. When the transistor PTR41 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR41 changes, and the signal is input to the input terminal PA2 of the input port PA of the payout control MPU4120a as a full tank signal.

The circuit composed of the resistors PR45 and PR46 and the transistor PTR41 is a switch circuit that is turned ON / OFF by a detection signal from the full switch 550.

As described above, the full tank switch 550 detects whether or not the game ball in which the accommodation space in the second ball passage of the foul cover unit 540 is stored is full. In the present embodiment, when the accommodation space is not full in the stored game ball, the voltage applied to the output terminal of the full tank switch 550 is discharged via the handle relay terminal plate 192 and the power supply board 851. When the signal that the pull-up resistor 44a pulls up to the + 12V side in the control board 4110 and the logic becomes HI is input to the payout control board 4110, and the accommodation space is filled with the stored game balls, the control board 4110 is filled. The voltage applied to the output terminal of the full switch 550 is lowered to the ground (GND) side on the payout control board 4110 via the handle relay terminal board 192 and the power supply board 851, and a signal whose logic is LOW is paid out. It is input to the control board 4110.

When the accommodation space is not full in the stored game ball, the voltage applied to the output terminal of the full tank switch 550 is pulled by the payout control board 4110 via the handle relay terminal board 192 and the power supply board 851. When the signal pulled up to the + 12V side by the up resistor 44a and the logic becomes HI is input to the base terminal of the above-mentioned transistor PTR41, the transistor PTR41 is turned on and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR41 is lowered to the ground (GND) side, and the full tank signal whose logic is LOW is input to the input terminal PA2 of the input port PA of the payout control MPU4120a.

On the other hand, when the accommodation space is filled with the stored game balls, the voltage applied to the output terminal of the full tank switch 550 is passed through the handle relay terminal board 192 and the power supply board 851 to the payout control board 4110. When the signal pulled down to the ground (GND) side and the logic becomes LOW is input to the base terminal of the transistor PTR41 described above, the transistor PTR41 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR41 is pulled up to the + 5V side by the resistor PR47, and the full tank signal whose logic is HI is input to the input terminal PA2 of the input port PA of the payout control MPU4120a.

In this embodiment, the detection signal from the full switch 550 is input to the switch circuit composed of the resistor PR45, the resistor PR46, and the transistor PTR41 via the 3-terminal filter PIC50 for the full switch. However, the detection signals from various detection switches such as the ball-out switch 750, the counting switch 751, and the rotation angle switch 752 shown in FIG. 13 are T-type filter circuits such as the 3-terminal filter PIC50 for a full tank switch. The circuit configuration is such that it is directly input to each switch circuit without going through. Since the full tank switch 550 is provided in the foul cover unit 540 attached to the door frame 5, the ball out switch 750, the counting switch 751 and the rotation angle switch 752 provided in the prize ball device 740 attached to the main body frame 3 are provided. The path for transmitting the detection signal is extremely long, and it is extremely susceptible to noise.

The full tank switch 550 detects whether or not the game ball in which the accommodation space in the second ball passage of the foul cover unit 540 is stored is full, and the payout control MPU 4120a is from the full tank switch 550. When it is determined that the game ball in which the accommodation space is stored is full based on the detection signal of, the drive control of the payout motor 744 is forcibly stopped to stop the payout of the game ball by the payout rotating body. It is supposed to do. That is, when noise invades the transmission path (transmission line) that transmits the detection signal from the full tank switch 550, the payout control MPU4120a drives the payout motor 744 even though the game ball in which the accommodation space is stored is not full. In some cases, the control is forcibly stopped to stop the payout of the game ball by the payout rotating body, and even though the game ball in which the accommodation space is stored is full, the payout motor 744 is driven and controlled. Then, by rotating the payout rotating body and continuing the payout of the game ball, when the game ball is filled up to the upstream side of the above-mentioned prize ball passage, the payout rotating body itself cannot rotate and the payout motor 744 becomes The load may be abnormally applied, and the payout motor 744 may become overloaded and generate abnormal heat and fail, or the mechanism for transmitting the rotating shaft of the payout motor 744 to the rotational movement of the payout rotating body may break down. .. Therefore, in the present embodiment, in order to prevent such a problem from occurring, a circuit configuration is adopted so that the detection signal from the full tank switch 550 is first removed by the noise component in the 3-terminal filter PIC50 for the full tank switch. ..

[10-2-3 (e). Circuit to which the operation signal from the operation switch is input]
The 1st and 2nd terminals, which are the output terminals of the operation switch 860a, are grounded to the ground (GND), and the 3rd and 4th terminals, which are the output terminals of the operation switch 860a, are moved to the + 5V side by the pull-up resistor PR48. It is pulled up and connected to the base terminal of the transistor PTR42 in the previous stage via a resistor PR49 and electrically. In addition to being electrically connected to the resistor PR49, the base terminal of the transistor PTR42 in the previous stage is electrically connected to the other end of the resistor PR50 whose one end is grounded to ground (GND). In addition to being electrically connected to the pull-up resistor PR48, the fourth terminal, which is the output terminal of the operation switch 860a, is electrically connected to the other end of the capacitor PC41 whose one end is grounded to ground (GND). ing. The emitter terminal of the transistor PTR42 in the previous stage is grounded to ground (GND), and the collector terminal of the transistor PTR42 in the previous stage is electrically connected to the other end of the resistor PR51 whose one end is electrically connected to the + 5V power supply line. At the same time, it is electrically connected to the base terminal of the transistor PTR43 in the subsequent stage via the resistor PR52. The base terminal of the transistor PTR43 in the subsequent stage is electrically connected to the resistor PR52, and is also electrically connected to the other end of the resistor PR53 whose one end is grounded to ground (GND). The emitter terminal of the latter transistor PTR43 is grounded to ground (GND), and the collector terminal of the latter transistor PTR43 is electrically connected to the other end of the resistor PR54, one end of which is electrically connected to the + 5V power supply line. The non-inverting buffer ICPIC40 (the non-inverting buffer ICPIC40 includes eight non-inverting buffer circuits, and formats and outputs the logic of the signal waveform input to one of them (PIC40C) without inverting it). It is electrically connected to the input terminal PA3 of the input port PA of the payout control MPU4120a via. When the first-stage and second-stage transistors PTR42 and PTR43 are turned ON / OFF, the logic of the signal output from the collector terminal of the second-stage transistor PTR43 changes, and the signal becomes the RWMCLR signal as the input terminal PA3 of the input port PA of the payout control MPU4120a. Is entered in.

In addition, the 3rd and 4th terminals, which are the output terminals of the operation switch 860a, are pulled up to the + 5V side by the pull-up resistor PR48 and are electrically connected to the base terminal of the transistor PTR42 in the previous stage via the resistor PR49. It is pulled up to the + 5V side by the pull-up resistor PR48 and is electrically connected to the base terminal of the transistor PTR44 via the resistor PR55. In addition to being electrically connected to the resistor PR55, the base terminal of the transistor PTR44 is electrically connected to the other end of the resistor PR56, one end of which is grounded to ground (GND). The emitter terminal of the transistor PTR44 is grounded to ground (GND), and the collector terminal of the transistor PTR44 is electrically connected to the main control board 4100 via wiring (harness). When the collector terminal of the transistor PTR44 is electrically connected to the main control board 4100 via wiring (harness), one end of the main control input circuit 4100b of the main control board 4100 shown in FIG. 21 is + 12V. It is electrically connected to the other end of the pull-up resistor MR2 that is electrically connected to the power supply line. When the transistor PTR44 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR44 changes, and the signal is input to the input terminal PA0 of the input port PA of the main control MPU4100a as a RAM clear signal.

The circuit composed of the pull-up resistor PR48 and the capacitor PC41 is a switch signal generation circuit, and when the operation switch 860a is pressed, the contacts constituting the operation switch 860a repeatedly turn on and off for a short time. It is configured as a circuit having a function of absorbing the fluctuation of the voltage from the operation switch 860a.

The circuit composed of the resistors PR49, PR50, and the transistor PTR42 is the switch circuit in the front stage, and the circuit composed of the resistors PR52, PR53, and the transistor PTR43 is the switch circuit in the rear stage, and the resistors PR55, PR56, and the transistor PTR44. The circuit composed of the above is a switch circuit, which is turned on / off by an operation signal from the operation switch 860a.

As described above, the operation switch 860a is used in the RAM (RAM with built-in payout control) built in the payout control MPU 4120a of the payout control board 4110 and the main control MPU 4100a of the main control board 4100 within a predetermined period from the time when the power is turned on. It is operated to clear the built-in RAM (main control built-in RAM), or when an error is notified after the power is turned on, it is operated to clear the error, and the power is turned on. The function to clear the RAM within a predetermined period from time and the error cancellation after the power is turned on (after the period during which the function as RAM clear is performed, that is, after the predetermined period has elapsed from the time when the power is turned on). It has a function. The operation signal from the operation switch 860a becomes a RAM clear signal in the function of clearing the RAM within a predetermined period from the time when the power is turned on, while after the power is turned on (after a predetermined period has elapsed from the time when the power is turned on). In the function of canceling the error in), it becomes an error clearing signal.

When the operation switch 860a is not operated, the operation signal whose logic is HI is the transistor in the previous stage because the 3rd and 4th terminals, which are the output terminals of the operation switch 860a, are pulled up to the + 5V side by the pull-up resistor PR48. It is input to the base terminal of the PTR42 to turn on the transistor PTR42 in the previous stage, and the switch circuit in the previous stage is also turned on. When the voltage is lowered to the ground (GND) side, the transistor PTR43 in the subsequent stage is turned off, and the switch circuit in the subsequent stage is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR43 in the subsequent stage is pulled up to the + 5V side by the resistor PR54, and the RWMCLR signal whose logic is HI is input to the input terminal PA3 of the input port PA of the payout control MPU4120a. The payout control MPU4120a performs RAM clearing that erases the information stored in the payout control built-in RAM when the logic of the RWMCLR signal input to the input terminal PA3 is HI within a predetermined period from the time when the power is turned on. It is judged that it is not an instruction, and after the power is turned on (after a predetermined period has passed since the power was turned on), if the logic of the RWMCLR signal input to the input terminal PA3 is HI, the error is cleared. Judge that it is not an instruction.

When the operation switch 860a is not operated, the operation signal whose logic is HI is the transistor PTR44 when the output terminals of the operation switch 860a, the 3rd terminal and the 4th terminal, are pulled up to the + 5V side by the pull-up resistor PR48. The transistor PTR44 is turned on by being input to the base terminal of the above, and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR44 is lowered to the ground (GND) side of the main control board 4100 via the wiring (harness), and the RAM clear signal whose logic is LOW is sent to the main control board 4100. Entered. When the RAM clear signal whose logic is LOW is input to the main control MPU 4100a of the main control board 4100 within a predetermined period from the time when the power is turned on, as described above, this logic is LOW. When the RAM clear signal is input to the base terminal of the transistor MTR0, the transistor MTR0 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor MTR0 is pulled up to the + 5V side by the resistor MR5, and the RAM clear signal whose logic is HI is input to the input terminal PA0 of the input port PA of the main control MPU4100a. The main control MPU4100a determines that when the logic of the RAM clear signal input to the input terminal PA0 is HI, it does not instruct to perform RAM clear for erasing the information stored in the main control built-in RAM.

On the other hand, when the operation switch 860a is being operated, the operation signal whose logic is LOW is the transistor in the previous stage because the 3rd and 4th terminals, which are the output terminals of the operation switch 860a, are pulled down to the ground (GND) side. It is input to the base terminal of the PTR 42, the transistor PTR 42 in the previous stage is turned off, the switch circuit in the previous stage is also turned off, and it is applied to the collector terminal of the transistor PTR 42 in the previous stage, which is the voltage applied to the base of the transistor PTR 43 in the rear stage. When the voltage is raised to the + 5V side by the resistor PR51, the transistor PTR43 in the subsequent stage is turned on, and the switch circuit in the subsequent stage is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR43 in the subsequent stage is lowered to the ground (GND) side, and the RWMCLR signal whose logic is LOW is input to the input terminal PA3 of the input port PA of the payout control MPU4120a. The payout control MPU4120a performs RAM clearing that erases the information stored in the payout control built-in RAM when the logic of the RWMCLR signal input to the input terminal PA3 is LOW within a predetermined period from the time when the power is turned on. It is determined that the signal is to be instructed, and after the power is turned on (after a predetermined period has elapsed from the time the power is turned on), if the logic of the RWMCLR signal input to the input terminal PA3 is LOW, the error is cleared. Judge that it is an instruction.

Further, when the operation switch 860a is operated, the output terminals of the operation switch 860a, the 3rd terminal and the 4th terminal, are pulled down to the ground (GND) side by the pull-up resistor PR48, so that the logic becomes LOW. A signal is input to the base terminal of the transistor PTR44, the transistor PTR44 is turned off, and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR44 is pulled up to the + 12V side by the pull-up resistor MR2 of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. The clear signal is input to the main control board 4100. When the RAM clear signal whose logic is HI is input to the main control MPU 4100a of the main control board 4100 within a predetermined period from the time when the power is turned on, as described above, this logic is HI. When the RAM clear signal is input to the base terminal of the transistor MTR0, the transistor MTR0 is turned on and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor MTR0 is lowered to the ground (GND) side, and the RAM clear signal whose logic is LOW is input to the input terminal PA0 of the input port PA of the main control MPU4100a. The main control MPU4100a determines that when the logic of the RAM clear signal input to the input terminal PA0 is LOW, it is instructed to perform RAM clear that erases the information stored in the main control built-in RAM.

[10-2-4. Payout motor drive circuit]
Next, the payout motor drive circuit 4120d for outputting the drive signal to the payout motor 744 of the prize ball device 740 shown in FIG. 5 will be described. As shown in FIG. 27, the payout motor drive circuit 4120d mainly includes a voltage switching circuit 4120da and a drive ICPIC60. The power input terminals 1 and 2 of the voltage switching circuit 4120da are electrically connected to the + 12V power supply line and the + 5V power supply line, respectively, and +12 and + 5V are applied, respectively. It is grounded. A voltage switching signal is input to the power switching input terminal of the voltage switching circuit 4120da. This voltage switching signal is output from the output terminal of the predetermined output port of the payout control MPU 4120a to the payout control output circuit 4120ca with a reset function, and is output from the payout control output circuit 4120ca with a reset function to the power supply switching input terminal of the voltage switching circuit 4120da. It is supposed to be done. The power output terminal of the voltage switching circuit 4120da is electrically connected to the cathode terminals of the drive ICPIC60, the 3rd terminal and the 10th terminal, respectively, via the Zener diode PZD60, and is also electrically connected to the power supply terminal of the payout motor 744. Based on the voltage switching signal connected to the voltage switching circuit 4120da and input to the voltage switching input terminal, + 12V or + 5V is used as the motor drive voltage via the Zener diode PZD60, and is the cathode terminal of the drive ICPIC60. It is supplied to the terminal and the 10th terminal, respectively, and is also supplied to the discharge motor 744.

The drive ICPIC60 includes four Darlington power transistors. In this embodiment, the emitter terminals 6 and 7 of the drive ICPIC60 are grounded to ground (GND), respectively, and are the base terminals of the drive ICPIC60. A payout motor drive signal is input to a certain terminal 1, terminal 5, terminal 8, and terminal 12 via resistors PR60 to PR63, respectively. The 2nd terminal, 4th terminal, 9th terminal, and 11th terminal, which are the collector terminals of the drive ICPIC60, are the 1st terminal, the 5th terminal, the 8th terminal, and the 12th terminal, which are the base terminals of the drive ICPIC60, respectively. When the payout motor drive signal is input to the 1st terminal, 5th terminal, 8th terminal, and 12th terminal, which are the base terminals of the drive ICPIC60, via the resistors PR60 to PR63, it is an excitation signal. A certain drive pulse is output to each phase (/ B phase, B phase, A phase, / A phase) corresponding to the payout motor 744. This payout motor drive signal is output from the output terminal of the predetermined output port of the payout control MPU 4120a to the payout control output circuit 4120ca with a reset function, and from the payout control output circuit 4120ca with a reset function to the drive ICPIC60 via resistors PR60 to PR63. It is designed to be output to the 1st terminal, 5th terminal, 8th terminal, and 12th terminal, which are the base terminals, respectively. These drive pulses are performed by switching the exciting current flowing through each phase (/ B phase, B phase, A phase, / A phase) of the payout motor 744 to rotate the payout motor 744. When the drive pulse (excitation signal) of each phase (/ B phase, B phase, A phase, / A phase) is cut off by this switching, a counter electromotive force is generated. If this counter electromotive force exceeds the withstand voltage of the drive ICPIC60, the drive ICPIC60 will be damaged. Therefore, as protection, the Zener diode PZD0 described above is electrically connected to the front stages of the 3rd and 10th terminals which are the cathode terminals of the drive ICPIC60. The circuit configuration is adopted.

[10-2-5. CR unit input / output circuit]
Next, the CR unit input / output circuit 4120e for inputting / outputting various signals with the CR unit 6 shown in FIG. 14 will be described. As described above, the payout control board 4110 includes the BRDY, which is a ball lending request signal, and the BRQ, which is a one-time payout operation start request signal, via the game ball lending device connection terminal board 869. , And the predetermined voltage VL (+ 12V) and ground LG created from AC24V supplied from the power supply board 851 shown in FIG. 14 are supplied, while the payout control board 4110 connects to the rental device such as a game ball. An XS signal indicating that one payout operation has started or ended, and a PRDY signal indicating that the payout operation for paying out the rental ball is possible or impossible, via the terminal board 869. And output. As shown in FIG. 28, the input / output circuits for inputting / outputting these various signals and the like are mainly composed of photocouplers PIC70 to PIC74 (infrared LED and phototransistor are built-in).

The predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70 via the resistor PR70. The cathode terminal of the photocoupler PIC70 is electrically connected to the ground LG from the CR unit 6. The resistor PR60 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC70. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned on, while the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70. Occasionally, the photocoupler PIC 70 is turned off. The emitter terminal of the photocoupler PIC70 is grounded to ground (GND), and the collector terminal of the photocoupler PIC70 is electrically connected to the base terminal of the transistor PTR70 via the resistor PR71, and is also connected to the transistor via the resistor PR72. It is electrically connected to the base terminal of the PTR71. In addition to being electrically connected to the resistor PR71, the collector terminal of the photocoupler PIC70 is electrically connected to the other end of the pull-up resistor PR73, one end of which is electrically connected to the + 5V power supply line.

In addition to being electrically connected to the resistor PR71, the base terminal of the transistor PTR70 is electrically connected to the other end of the resistor PR74, one end of which is grounded to ground (GND). The emitter terminal of the transistor PTR70 is grounded to ground (GND), and the collector terminal of the transistor PTR70 is electrically connected to the other end of the resistor PR75, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. FIG. 24 via ICPIC80 (the non-inverting buffer ICPIC80 includes eight non-inverting buffer circuits, and formats and outputs the logic of the signal waveform input to one of them (PIC80A) without inverting it). It is electrically connected to the input terminal of the predetermined input port of the payout control MPU 4120a shown in 1. When the transistor PTR 70 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR 70 is changed, and the signal is input as the CR connection signal 1 to the input terminal of the predetermined input port of the payout control MPU 4120a.

On the other hand, the base terminal of the transistor PTR71 is electrically connected to the resistor PR72 and also electrically connected to the other end of the resistor PR76 whose one end is grounded to ground (GND). The emitter terminal of the transistor PTR71 is grounded to ground (GND), and the collector terminal of the transistor PTR71 is electrically connected to the power supply board 851 via wiring (harness). When the collector terminal of the transistor PTR71 is electrically connected to the power supply board 851 via wiring (harness), one end of the power supply board 851 is electrically connected to the + 12V power supply line. It is electrically connected to the other end of the. When the transistor PTR71 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR71 is changed, and the signal is input to the power supply board 851 as a CR connection signal.

The circuit composed of the resistors PR71 and PR74 and the transistor PTR70 is a switch circuit that is turned ON / OFF by ON / OFF of the photocoupler PIC70.

When the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned off, and the transistor PTR70 is turned on by being pulled up to the + 5V side by the pull-up resistor PR73, and the switch circuit is also turned on. It will be turned on. As a result, the voltage applied to the collector terminal of the transistor PTR70 is lowered to the ground (GND) side, and the CR connection signal 1 whose logic is LOW is input to the input terminal of the predetermined input port of the payout control MPU4120a.

On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned on and the voltage applied to the base terminal of the transistor PTR70 is lowered to the ground (GND) side. As a result, the transistor PTR70 is turned off, and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR70 is pulled up to the + 5V side by the pull-up resistor PTR75, and the CR connection signal 1 whose logic is HI is input to the input terminal of the predetermined input port of the payout control MPU4120a. NS.

The circuit composed of the resistors PR72 and PR76 and the transistor PTR71 is also a switch circuit that is turned ON / OFF by ON / OFF of the photocoupler PIC70.

When the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned off, and the transistor PTR71 is turned on by being pulled up to the + 5V side by the pull-up resistor PR73, and the switch circuit is also turned on. It will be turned on. As a result, the voltage applied to the collector terminal of the transistor PTR71 is lowered to the ground (GND) side of the power supply board 851 via the wiring (harness), and the CR connection signal whose logic is LOW is input to the power supply board 851. NS.

On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned on and the voltage applied to the base terminal of the transistor PTR71 is lowered to the ground (GND) side. As a result, the transistor PTR71 is turned off, and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR71 is pulled up to the + 12V side by the pull-up resistor of the power supply board 851 via the wiring (harness), and the CR connection signal whose logic is HI is input to the power supply board 851. Will be done.

The predetermined voltage VL from the CR unit 6 is applied not only to the anode terminal of the photocoupler PIC70 but also to the anode terminal of the photocoupler PIC71 via the resistor PR77. BRDY from the CR unit 6 is input to the cathode terminal of the photocoupler PIC71. The resistor PR77 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC71. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the logic of BRDY from the CR unit 6 is LOW, the photocoupler PIC71 is turned on while the photo When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the coupler PIC71 and the logic of BRDY from the CR unit 6 is HI, the photocoupler PIC71 is turned off. There is. The emitter terminal of the photocoupler PIC71 is grounded to ground (GND), and the collector terminal of the photocoupler PIC71 is electrically connected to the other end of the pull-up resistor PR78, one end of which is electrically connected to the + 5V power supply line. The non-inverting buffer ICPIC80 (the non-inverting buffer ICPIC80 includes eight non-inverting buffer circuits, and the logic of the signal waveform input to one of them (PIC80B) is formatted and output without being inverted). It is electrically connected to the input terminal of a predetermined input port of the payout control MPU 4120a via the device. When the photocoupler PIC71 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler PIC71 is changed, and the signal is input as a BRDY signal to the input terminal of the predetermined input port of the payout control MPU4120a.

When a predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the logic of BRDY from the CR unit 6 is LOW, the photocoupler PIC71 is turned on and therefore the photo The voltage applied to the collector terminal of the coupler PIC71 is lowered to the ground (GND) side, and the BRDY signal whose logic is LOW is input to the input terminal of the predetermined input port of the payout control MPU4120a. On the other hand, when a predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the logic of BRDY from the CR unit 6 is HI, the photocoupler PIC71 is turned off. The voltage applied to the collector terminal of the photocoupler PIC71 is pulled up to the + 5V side by the pull-up resistor PR78, and the BRDY signal whose logic is HI is input to the input terminal of the predetermined input port of the payout control MPU4120a. As described above, the logic of the BRDY signal output from the collector terminal of the photocoupler PIC71 is the same as the logic of the BRDY from the CR unit 6.

The predetermined voltage VL from the CR unit 6 is applied not only to the anode terminal of the photocoupler PIC70 and the anode terminal of the photocoupler PIC71, but also to the anode terminal of the photocoupler PIC72 via the resistor PR79. The BRQ from the CR unit 6 is input to the cathode terminal of the photocoupler PIC72. The resistor PR79 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC72. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and the logic of the BRQ from the CR unit 6 is LOW, the photocoupler PIC72 is turned on while the photo is taken. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the coupler PIC72 and the logic of the BRQ from the CR unit 6 is HI, the photocoupler PIC72 is turned off. There is. The emitter terminal of the optocoupler PIC72 is grounded to ground (GND), and the collector terminal of the optocoupler PIC72 is electrically connected to the other end of the pull-up resistor PR80, one end of which is electrically connected to the + 5V power supply line. The non-inverting buffer ICPIC80 (the non-inverting buffer ICPIC80 includes eight non-inverting buffer circuits, and the logic of the signal waveform input to one of them (PIC80C) is formatted and output without being inverted). It is electrically connected to the input terminal of a predetermined input port of the payout control MPU 4120a via the device. When the photocoupler PIC72 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler PIC72 is changed, and the signal is input as a BRQ signal to the input terminal of the predetermined input port of the payout control MPU4120a.

When a predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and the logic of the BRQ from the CR unit 6 is LOW, the photocoupler PIC72 is turned on, so that the photocoupler PIC72 is turned on. The voltage applied to the collector terminal of the coupler PIC72 is lowered to the ground (GND) side, and the BRQ signal whose logic is LOW is input to the input terminal of the predetermined input port of the payout control MPU4120a. On the other hand, when a predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and the logic of the BRQ from the CR unit 6 is HI, the photocoupler PIC72 is turned off. The voltage applied to the collector terminal of the photocoupler PIC72 is pulled up to the + 5V side by the pull-up resistor PR80, and the BRQ signal whose logic is HI is input to the input terminal of the predetermined input port of the payout control MPU4120a. As described above, the logic of the BRQ signal output from the collector terminal of the photocoupler PIC72 is the same as the logic of the BRQ from the CR unit 6.

The EXE signal indicating that one payout operation has started or ended from the output terminal of the predetermined output port of the payout control MPU 4120a is output to the payout control output circuit 4120 kb without the reset function, and the payout control output circuit without the reset function. It is input from 4120 kb to the cathode terminal of the photocoupler PIC73 via the resistor PR81. The anode terminal of the photocoupler PIC73 is electrically connected to the other end of the resistor PR82, one end of which is electrically connected to the + 12V power supply line. The resistor PR82 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC73. When + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, the EXS is output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cc without a reset function. When the signal logic is LOW, the photocoupler PIC73 is turned on, while + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, and the predetermined output port of the payout control MPU4120a. When the logic of the EXS signal output from the output terminal of the output terminal without the reset function via the payout control output circuit 4120cc is HI, the photocoupler PIC73 is turned off. The emitter terminal of the photocoupler PIC73 is grounded to the ground LG from the CR unit 6, and the collector terminal of the photocoupler PIC73 is inside the CR unit 6 via a pull-up resistor PR83 via a game ball rental device connection terminal board 869. The voltage is raised to a predetermined voltage VL and is electrically connected to the built-in control device. When the photocoupler PIC73 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler PIC73 is changed, and the signal is input to the built-in control device of the CR unit 6 as EXS.

When + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, the EXS is output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cc without a reset function. When the signal logic is LOW, the photocoupler PIC73 is turned on, so the voltage applied to the collector terminal of the photocoupler PIC73 is lowered to the ground (GND) side, and the EXS whose logic is LOW is the CR unit. It is input to the built-in control device of 6. On the other hand, when + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, it is output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cc without a reset function. When the logic of the EXS signal is HI, the photocoupler PIC73 is turned off, so that the voltage applied to the collector terminal of the photocoupler PIC73 is raised to a predetermined voltage VL by the pull-up resistor PR83, and the logic becomes HI. The EXS is input to the built-in control device of the CR unit 6. As described above, the logic of the EXE output from the collector terminal of the photocoupler PIC73 is the logic of the EXS signal output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cc without the reset function. It has the same logic.

The PRDY signal for notifying that the payout operation for paying out the rental ball from the output terminal of the predetermined output port of the payout control MPU4120a is possible or impossible is the cathode terminal of the photocoupler PIC74 via the resistor PR84. Has been entered in. The anode terminal of the photocoupler PIC74 is electrically connected to the other end of the resistor PR85, one end of which is electrically connected to the + 12V power supply line. The resistor PR85 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC74. When + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, the PRDY is output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cc without a reset function. When the signal logic is LOW, the photocoupler PIC74 is turned on, while + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, and the predetermined output port of the payout control MPU4120a. When the logic of the PRDY signal output from the output terminal of the output terminal without the reset function via the payout control output circuit 4120cc is HI, the photocoupler PIC74 is turned off. The emitter terminal of the photocoupler PIC74 is grounded to the ground LG from the CR unit 6, and the collector terminal of the photocoupler PIC74 is inside the CR unit 6 via a pull-up resistor PR86 via a game ball rental device connection terminal board 869. The voltage is raised to a predetermined voltage VL and is electrically connected to the built-in control device. When the photocoupler PIC74 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler PIC74 changes, and the signal is input to the built-in control device of the CR unit 6 as a PRDY.

When + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, the PRDY is output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cc without a reset function. When the signal logic is LOW, the photocoupler PIC74 is turned on, so the voltage applied to the collector terminal of the photocoupler PIC74 is lowered to the ground (GND) side, and the PRDY whose logic is LOW is the CR unit. It is input to the built-in control device of 6. On the other hand, when + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, it is output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cc without a reset function. When the logic of the PRDY signal is HI, the photocoupler PIC74 is turned off, so that the voltage applied to the collector terminal of the photocoupler PIC74 is raised to a predetermined voltage VL by the pull-up resistor PR86, and the logic becomes HI. The PRDY is input to the built-in control device of the CR unit 6. As described above, the logic of the PRDY output from the collector terminal of the photocoupler PIC74 is the logic of the PRDY signal output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cc without the reset function. It has the same logic.

[10-2-6. Various input / output signals to the payout control MPU]
Next, various input / output signals input / output from the input / output terminals of the various input / output ports of the payout control MPU 4120a will be described.

As shown in FIG. 24, the RXD terminal, which is the serial data input terminal of the serial input port of the payout control MPU 4120a, receives the serial data from the main control board 4100 as the main payout serial data reception signal via the payout control input circuit 4120b. Will be done. On the other hand, from the TXD terminal, which is the serial data output terminal of the serial output port of the payout control MPU4120a, the serial data to be transmitted to the main control board 4100 is transmitted as the payer serial data transmission signal to the payout control output circuit 4120cc without a reset function. No reset function The payer serial data transmission signal is transmitted from the payout control output circuit 4120 kb to the main control board 4100.

Each input terminal of the predetermined input port of the payout control MPU4120a has the above-mentioned RWMCLR signal, payout power failure warning signal, door open signal, full tank signal, and various signals from the CR unit 6 (BRQ signal, BRDY signal, CR connection). In addition to the input of signals 1 and the like), for example, the main payment ACK signal from the main control board 4100 that notifies the completion of normal reception of the above-mentioned payer serial data reception signal is transmitted via the payout control input circuit 4120b. Inputs or detection signals from the ball-out switch 750, the counting switch 751, the rotation angle switch 752, etc. shown in FIG. 13 are input via the payout control input circuit 4120b, respectively, or the potentiometer shown in FIG. The operation signal from the meter 512, the detection signal from the touch switch 516, the launch stop switch 518, the full tank switch 550, etc. shown in FIG. 13 are transmitted via the power supply board 851 and the payout control input circuit 4120b of the payout control board 4100. And so on.

On the other hand, from each output terminal of the predetermined output port of the payout control MPU 4120a, the above-mentioned EXS signal and PRDY signal are output to the payout control output circuit 4120cc without the reset function, respectively, and the EXS signal and the EXS signal from the payout control output circuit 4120cc without the reset function. The PRDY signal is output to the CR unit input / output circuit 4120e, or the above-mentioned voltage switching signal is output to the payout control output circuit 4120ca with a reset function, and the voltage switching signal is output from the payout control output circuit 4120ca with a reset function to the voltage switching circuit 4120da. Output or output the payout motor drive signal to the payout control output circuit 4120ca with a reset function and output the payout motor drive signal from the payout control output circuit 4120ca with a reset function to the payout motor 744 via the payout motor drive circuit 4120d. In addition, for example, the payer ACK signal for notifying the completion of normal reception of the above-mentioned main pay serial data reception signal is output to the payout control output circuit 4120ca with a reset function, and the payer is output from the payout control output circuit 4120ca with a reset function. The ACK signal is output to the main control board 4100, or the drive signal of the error LED display 860b shown in FIG. 13 is output to the payout control output circuit 4120ca with a reset function, and the drive signal is output from the payout control output circuit 4120ca with a reset function. Output to the error LED display 860b or output the control signal for adjusting the drive current to the firing solenoid drive circuit 858 shown in FIG. 13 to the payout control output circuit 4120ca with a reset function, and the payout control output circuit 4120ca with a reset function. The drive current is output to the firing solenoid 654, and the control signal for adjusting the drive current to the ball feed solenoid drive circuit 859 shown in FIG. 13 is output to the payout control output circuit 4120ca with a reset function. The drive current is output from the output circuit 4120ca to the ball feed solenoid 585, and the like.

[10-3. Various input / output signals with the main control board and various output signals to the external terminal board]
Next, various input / output signals between the payout control board 4110 and the main control board 4100 and various output signals from the payout control board 4110 to the external terminal board 784 will be described with reference to FIG. 29.

[10-3-1. Various input / output signals with the main control board]
The payout control board 4110 exchanges various input / output signals with the main control board 4100. Specifically, as shown in FIG. 29A, the payout control board 4110 has the payer serial data transmission signal, payer ACK signal, operation signal (RAM clear signal), main frame door open signal, and the like described above. Is output to the main control board 4100. These output signals are pulled up to the + 12V side by the pull-up resistor of the main control input circuit 4100b of the main control board 4100.

On the other hand, in addition to the above-mentioned main payment serial data reception signal, main payment ACK signal, and operation signal (RAM clear signal), the payout control board 4110 has a 15-round jackpot information output signal, a 2-round jackpot information output signal, and the like. Game information signal related to the game such as jackpot information output signal, probability fluctuation information output signal, special symbol display information output signal, normal symbol display information output signal, time saving medium information output signal, start opening winning information output signal, etc. Signals and the like are input from the main control board 4100. These input signals are pulled up to the + 12V side by the pull-up resistance of the payout control input circuit 4120b of the payout control unit 4120 of the payout control board 4110.

[10-3-2. Various output signals to the external terminal board]
The payout control board 4110 outputs various signals to the external terminal board 784. Specifically, as shown in FIG. 29B, in addition to the above-mentioned outer end frame door opening information output signal, the number of game balls actually paid out by the payout motor 744 as prize balls reaches 10 balls. The prize ball number information output signal output for each, the jackpot information output signal of the 15-round jackpot information output signal and the 2-round jackpot information output signal, and the information output during probability fluctuation via the payout control board 4110 from the main control board 4100. A game information signal such as a signal, a special symbol display information output signal, a normal symbol display information output signal, a time saving / medium information output signal, and a start opening winning information output signal is output to the external terminal board 784. These output signals are pulled up to the + 12V side by the pull-up resistor of the external terminal board 784.

In addition to the various signals described above being input to the external terminal board 784, as shown in FIG. 29 (b), the main prize ball number information output signal from the peripheral control board 4140 and the power saving mode information output signal. Is entered. Briefly explaining the main prize ball number information output signal, the main control board 4100 is provided on the game board 4, and has an upper start port 2101, a lower start port 2102, a general prize opening 2104, 2201, and a general prize opening 2101, 2201 shown in FIG. The number of game balls to be paid out as prize balls based on the game balls entered into various prize openings such as the large prize opening 2103 is set to a predetermined number (10 balls in this embodiment). ) Is transmitted to the peripheral control board 4140, and the peripheral control board 4140 receives the main prize ball number information output command based on the received main prize ball number information output command. The number of game balls scheduled to be paid out as prize balls based on the game balls entered in various winning openings such as the upper starting opening 2101, the lower starting opening 2102, the general winning opening 2104, 2201, and the large winning opening 2103 is determined in advance. Every time the specified number of balls (10 balls are set in this embodiment) is reached, the main prize ball number information output signal is output to the external terminal board 784 as the main prize ball number information to that effect, and the hall computer. I'm telling you. This main prize ball number information output signal is pulled up to the + 12V side by the pull-up resistor of the external terminal board 784.

Next, briefly explaining the power saving mode information output signal, the peripheral control board 4140 is based on the power consumption status history information stored and held in the power consumption status history RAM 4150f shown in FIG. 15 at the time of power recovery. When the power is turned off (immediately before the power is turned off), the power status consumed by the pachinko game machine 1 is grasped at the time of power recovery, and the power consumption by the pachinko game machine 1 is suppressed. It is transmitted to the hall computer via the terminal plate 784. Specifically, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 shown in FIG. 15 is used for power recovery in the power recovery mode transition determination process in the peripheral control unit power-on processing described later. Based on the power consumption status history information stored in the consumption status history RAM 4150f, the power status consumed by the pachinko game machine 1 at the time of power off (immediately before the power off) (power consumption suppression stage described later) is specified. It is determined whether or not to shift to the power saving mode at the time of power recovery. The peripheral control MPU4150a outputs a power saving mode information output signal to the external terminal board 784 as power saving mode information when the judgment result does not shift to the power saving mode at the time of power recovery, and transmits the judgment result to the hall computer. When the mode shifts to the power saving mode at the time of power recovery, the power saving mode information output signal is output to the external terminal board 784 as the power saving mode information and transmitted to the hall computer. This power saving mode information output signal is pulled up to the + 12V side by the pull-up resistor of the external terminal board 784.

That is, two signals, an outer end frame door opening information output signal and a prize ball number information output signal from the payout control board 4110 side, are output to the external terminal board 784, and a 15-round jackpot from the main control board 4100 side. There are seven signals: information output signal, 2-round jackpot information output signal, probability fluctuation information output signal, special symbol display information output signal, normal symbol display information output signal, time saving medium information output signal, and start opening winning information output signal. It is output via (passing through) the payout control board 4110, and two signals, a main prize ball number information output signal and a power saving mode information output signal, are output from the peripheral control board 4140 side.

The signal output from the external terminal board 784 is transmitted to a hall computer installed in a game hall (hall) (not shown), and the hall computer monitors the player's game or the like. When the 15-round jackpot information output signal or the 2-round jackpot information output signal is output to the hall computer as one jackpot information output signal, the hall computer has the number of jackpots in which the round is 2 times (2 round jackpot). The number of big hits in the pachinko gaming machine 1 is the sum of the number of big hits in which the number of rounds is 15 (the number of big hits in 15 rounds). For this reason, the hall computer cannot grasp the number of occurrences of 2 round jackpots and the number of occurrences of 15 land jackpots from the total number of jackpots, so that the number of jackpots actually generated by the pachinko gaming machine 1 is large. However, it is not possible to grasp whether it is a 2-round jackpot or a 15-round jackpot. In addition, a data counter (not shown) is arranged above the pachinko gaming machine 1, and some players can decide whether or not to play the game by referring to the number of occurrences of the jackpot gaming state displayed on the data counter. Some people choose.

However, the number of occurrences of the jackpot game state displayed on the data counter may actually be biased to the number of occurrences of the two-round jackpot, so even if the player starts the game, only two rounds of jackpots occur. In some cases, the 15-round jackpot does not occur easily. In this way, the number of occurrences of the jackpot gaming state displayed on the data counter can give the player a sense of expectation, but may unnecessarily arouse the player's gambling spirit.

Therefore, in the present embodiment, as the jackpot information output signal, the 15-round jackpot information output signal and the 2-round jackpot information output signal are separately output to the hall computer, so that the hall computer can determine the number of occurrences of the 2-round jackpot and the number of occurrences of the 2-round jackpot. It is possible to accurately grasp the number of big hits in 15 rounds. Therefore, the hall computer can grasp whether the number of big hits actually generated in the pachinko game machine 1 is a 2-round big hit or a 15-round big hit, and the data counter has 15 Since the number of round jackpots and the number of 2-round jackpots can be displayed separately or only the number of 15-round jackpots can be displayed as the number of jackpot gaming states, the player's gambling spirit can be stimulated more than necessary. Nor.

In the present embodiment, the 2-round jackpot information output signal is in a state of being output to the hall computer during the period from the occurrence of the 2-round jackpot to the end, and the 15-round jackpot information output signal is also the 15-round jackpot. It is in the state of being output to the hall computer during the period from the occurrence to the end. In addition to the method of outputting the 2-round jackpot information output signal and the 15-round jackpot information output signal to the hall computer as in the present embodiment, for example, when a 2-round jackpot occurs, the 2-round jackpot information output signal is output only for a predetermined period. Such a 2-round jackpot information output signal and 15-round jackpot information are output to the hall computer, and when a 15-round jackpot occurs, the 15-round jackpot information output signal is output to the hall computer for a predetermined period. A method of outputting the output signal to the hall computer for the same predetermined period can also be mentioned.

[11. Arrangement of output terminals on the external terminal board]
Next, the arrangement of the output terminals of the external terminal board 784 that outputs various signals to the hall computer installed in the amusement park (hall) will be described with reference to FIG. The external terminal board 784 is attached to the rear surface of the prize ball base 710 attached to the rear surface of the main body frame base 600 as shown in FIG. 3, and the rear side thereof is covered with the external terminal board cover 786. FIG. 30 is a diagram showing an arrangement of output terminals on the external terminal board.

As described above, the external terminal plate 784 has an outer end frame door opening information output signal, a prize ball number information output signal, a jackpot information output signal of a 15-round jackpot information output signal and a 2-round jackpot information output signal, and a probability fluctuation. The information output signal, the special symbol display information output signal, the normal symbol display information output signal, the time saving medium information output signal, and the start opening winning information output signal are input from the payout control board 4110, and the main prize ball number information output signal, And the power saving mode information output signal is input from the peripheral control board 4140, and these various signals are output to the outside of the pachinko game machine 1. The hall computer is electrically connected to the external terminal board 784 so that signals larger than the minimum detection signal width (for example, a signal width of 60 ms) can be detected as various signals from the external terminal board 784. It has become.

Briefly explaining these various signals, the outer end frame door opening information output signal does not occur during a normal game by a player in which the door frame 5 and / or the main body frame 3 shown in FIG. 1 is open. It is a signal that conveys that a state has occurred, and the prize ball number information output signal is obtained every time the number of game balls actually paid out as prize balls by the payout motor 744 shown in FIG. 5 reaches 10. This is a signal to convey the fact, and the main prize ball number information output signal enters various winning openings such as the upper starting opening 2101, the lower starting opening 2102, the general winning opening 2104, 2201, and the large winning opening 2103 shown in FIG. It is a signal to notify each time the number of game balls to be paid out as prize balls based on the ball has reached 10, and the power saving mode information output signal is when the power is turned off (immediately before the power is turned off). It is a signal that grasps the power status consumed by the pachinko game machine 1 at the time of power recovery and suppresses the power consumed by the pachinko game machine 1 to convey the transition state to the power saving mode at the time of power recovery, and outputs 15 round jackpot information. The signal is a signal indicating that a 15-round jackpot has occurred, and the 2-round jackpot information output signal is a signal indicating that a 2-round jackpot has occurred, and the probability is fluctuating. The information output signal is a signal indicating that a probability fluctuation is occurring, and the special symbol display information output signal is the upper special symbol display 1185 or the lower special symbol of the function display board 1191 shown in FIG. It is a signal indicating that the variable display of the special symbol has been completed (stopped) on the display 1186, and the normal symbol display information output signal is normal on the normal symbol display 1189 of the function display board 1191 shown in FIG. It is a signal that tells that the variation display of the symbol is finished (stopped), the time saving medium information output signal is a signal that tells that the time saving state is occurring, and the start opening winning information output signal is the figure. This is a signal for notifying each time a game ball enters the upper starting port 2101 or the lower starting port 2102 shown in 8.

As shown in FIG. 30, the output terminals PT1 to PT11 are arranged horizontally in a row on the external terminal board 784. The output terminal PT1 is white and outputs a prize ball number information output signal. As described above, the prize ball number information output signal is a signal for notifying each time the number of game balls actually paid out as prize balls by the payout motor 744 shown in FIG. 5 reaches 10. In the embodiment, 0.106 seconds from the output terminal PT1 (because the interrupt cycle is set to 2 ms in the present embodiment as the interrupt cycle when the payout control unit timer interrupt process described later is performed, the output period of 0.106 seconds (that is, that is). The signal width of the prize ball number information output signal output from the output terminal PT1) is output for a period of 53 times during which the payout control unit timer interrupt process is repeated based on the interrupt cycle of 2 ms). ing. When the prize ball number information output signal from the external terminal board 784 is input to the hall computer, the hall computer uses the payout motor 744 of the pachinko gaming machine 1 as a prize ball each time the prize ball number information output signal is input. It is possible to grasp that 10 game balls have been paid out as prize balls, and to count the number of the paid out game balls to grasp the total number of game balls paid out by the pachinko gaming machine 1. can.

The output terminal PT2 is provided in green to output an outer end frame door opening information output signal. As described above, the outer end frame door opening information output signal is in a state in which the player that the door frame 5 and / or the main body frame 3 shown in FIG. 1 is open does not occur during the normal game. This is a signal to convey that, and in the present embodiment, it is output from the output terminal PT2 while the door frame 5 and / or the main body frame 3 is open. When the outer end frame door opening information output signal from the external terminal plate 784 is input to the hall computer, the hall computer performs the door frame 5 of the pachinko gaming machine 1 while the outer end frame door opening information output signal is input. And / or it can be grasped that the main body frame 3 is open.

The output terminal PT3 is grayed out to output a special symbol display information output signal. As described above, the special symbol display information output signal is in a state where the variation display of the special symbol is completed (stopped) by the upper special symbol display 1185 and the lower special symbol display 1186 of the function display board 1191 shown in FIG. It is a signal to convey that, and in the present embodiment, 0.128 at the end (stop) of the variation display of the special symbol on the upper special symbol display 1185 and the lower special symbol display 1186 of the function display board 1191 from the output terminal PT3. It is designed to be output for a second. When the special symbol display information output signal from the external terminal board 784 is input to the hall computer, the hall computer receives the special symbol display information output signal, and when the special symbol display information output signal is input, the hall computer has a special symbol on the functional display board 1191 of the pachinko gaming machine 1. It is possible to grasp that the variable display of the special symbol has ended (stopped) on the display 1185 and the lower special symbol display 1186, and the number of times is counted to count the number of times, and the upper special symbol on the functional display board 1191 of the pachinko game machine 1 is counted. It is possible to grasp the total number of times that the special symbol is variablely displayed on the display 1185 and the lower special symbol display 1186.

The output terminal PT4 is provided in yellow and outputs a start opening winning information output signal. As described above, the start port winning information output signal is a signal for notifying each time a game ball enters the upper start port 2101 or the lower start port 2102 shown in FIG. 8, and is output in the present embodiment. Every time a game ball enters the upper start port 2101 or the lower start port 2102 from the terminal PT4, it is output for 0.128 seconds. When the start port winning information output signal from the external terminal board 784 is input to the hall computer, the hall computer starts the upper start port 2101 or the lower start port 2101 of the pachinko gaming machine 1 each time the start port winning information output signal is input. It is possible to know that the game ball has entered the mouth 2102, and the number of times the start port winning information output signal has been input is counted to enter the upper start port 2101 or the lower start port 2102 of the pachinko gaming machine 1. It is possible to grasp the total number of game balls played.

The output terminal PT5 is black and outputs a 15-round jackpot information output signal. As described above, the 15-round jackpot information output signal is a signal indicating that a 15-round jackpot has occurred. In the present embodiment, while the 15-round jackpot is occurring from the output terminal PT5, the 15-round jackpot information output signal is used. It is designed to be output. When the 15-round jackpot information output signal from the external terminal board 784 is input to the hall computer, the hall computer generates a 15-round jackpot in the pachinko gaming machine 1 while the 15-round jackpot information output signal is input. It is possible to grasp the state of being in the state, and to count the number of times that the 15-round jackpot information output signal is input to grasp the total number of times that the pachinko gaming machine 1 has received a 15-round jackpot.

The output terminal PT6 is colored pink and outputs a 2-round jackpot information output signal. As described above, the two-round jackpot information output signal is a signal indicating that a two-round jackpot is occurring, and in the present embodiment, while the two-round jackpot is occurring from the output terminal PT6, It is designed to be output. When the 2-round jackpot information output signal from the external terminal board 784 is input to the hall computer, the hall computer generates a 2-round jackpot in the pachinko gaming machine 1 while the 2-round jackpot information output signal is input. It is possible to grasp the state of being in the state, and to count the number of times the two-round jackpot information output signal is input to grasp the total number of times the two-round jackpot has occurred in the pachinko gaming machine 1.

The output terminal PT7 is provided in blue to output a normal symbol display information output signal. As described above, the normal symbol display information output signal is a signal indicating that the normal symbol display 1189 of the function display board 1191 shown in FIG. 11 has finished (stopped) the variation display of the normal symbol. In the present embodiment, the output is output from the output terminal PT7 for 0.128 seconds at the end (stop) of the variation display of the normal symbol on the normal symbol display 1189 of the function display board 1191. When the normal symbol display information output signal from the external terminal board 784 is input to the hall computer, the hall computer displays the normal symbol on the function display board 1191 of the pachinko gaming machine 1 when the normal symbol display information output signal is input. It is possible to grasp that the variation display of the normal symbol has ended (stopped) in the device 1189, and the number of times is counted to display the variation display of the normal symbol in the normal symbol display 1189 of the function display board 1191 of the pachinko gaming machine 1. You can grasp the total number of times you have done it.

The output terminal PT8 is red and outputs a time-saving and medium-time information output signal. As described above, the time saving medium information output signal is a signal indicating that the time saving state is occurring, and in the present embodiment, it is output from the output terminal PT8 while the time saving state is occurring. ing. When the time-saving and medium-time information output signal from the external terminal board 784 is input to the hall computer, the hall computer grasps that the pachinko gaming machine 1 is in the time-saving state when the time-saving and medium-time information output signal is input. At the same time, it is possible to count the number of times the information output signal is input during the time saving and to grasp the total number of times the time saving state has occurred in the pachinko gaming machine 1.

The output terminal PT9 is colored orange and outputs an information output signal during probability fluctuation. As described above, the information output signal during the probability fluctuation is a signal indicating that the probability fluctuation is occurring, and is output from the output terminal PT9 while the probability fluctuation is occurring in the present embodiment. It has become so. When the information output signal during probability fluctuation from the external terminal board 784 is input to the hall computer, the hall computer is in a state where the probability fluctuation occurs in the pachinko gaming machine 1 when the information output signal during probability fluctuation is input. It is possible to grasp the total number of times the probability fluctuation has occurred in the pachinko gaming machine 1 by counting the number of times the information output signal is input during the probability fluctuation.

The output terminal PT10 is light blue and outputs a main prize ball number information output signal. As described above, the main prize ball number information output signals are the upper start port 2101 and the lower start port 2102 shown in FIG. 8 based on the command from the main control board 4100 (the main prize ball number information output command described later). , General winning opening 2104, 2201 and large winning opening 2103, etc. Outputs to that effect every time the number of game balls scheduled to be paid out as prize balls reaches 10 based on the game balls entered in various winning openings. In this embodiment, the payout control unit timer interrupt processing described later is performed for 0.128 seconds from the output terminal PT10 (as an interrupt cycle when the peripheral control unit 1ms timer interrupt processing described later is performed). Since the interrupt cycle (2 ms) is set to 1 ms, the output period of 0.128 seconds (that is, the signal width of the main prize ball number information output signal output from the output terminal PT10) is an interrupt of 1 ms. Based on the cycle, the peripheral control unit 1ms timer interrupt processing is repeated 128 times), and is output. When the main prize ball number information output signal from the external terminal board 784 is input to the hall computer, the pachinko game machine 1 uses 10 balls as prize balls each time the main prize ball number information output signal is input. It is possible to grasp that the game balls of the above are to be paid out as prize balls, and the total number of game balls to be paid out by the pachinko game machine 1 by counting the number of the game balls to be paid out. Can be grasped. In addition, based on the command from the main control board 4100 (main prize ball number information output command described later), for example, various types such as the upper start opening 2101, the lower start opening 2102, the general winning opening 2104, 2201, and the large winning opening 2103. When the number of game balls to be paid out as prize balls based on the game balls entered in the winning opening reaches 20 or more and the main prize ball number information output signal is output multiple times, the number of main prize balls The information output signal is output from the peripheral control board 4140 to the external terminal board 784 at intervals of 0.128 seconds so that the information output signal becomes one continuous signal for 0.256 (= 0.128 seconds x 2 times) seconds. It is supposed to be done.

The output terminal PT11 is colored yellowish green to output a power saving mode information output signal. As described above, the power saving mode information output signal is used when the power is turned off (immediately before the power is turned off) based on the power consumption status history information stored and held in the power consumption status history RAM 4150f shown in FIG. 15 at the time of power recovery. The peripheral control MPU4150a shown in FIG. 15 grasps the power state consumed by the pachinko game machine 1 at the time of power recovery, and conveys the transition state to the power saving mode at the time of power recovery, which suppresses the power consumed by the pachinko game machine 1. It is a signal, and in the present embodiment, in the state of shifting to the power saving mode at the time of power recovery, 5 minutes of the power saving mode state maintenance period at the time of power recovery, which is the upper limit time described later from the output terminal PT11 (peripheral control unit 1 ms timer interrupt described later). In this embodiment, the interrupt cycle when the processing is performed is set to 1 ms, which is different from the interrupt cycle (2 ms) when the payout control unit timer interrupt process is performed, which will be described later. Therefore, the output period is 5 minutes (300 seconds). (That is, the signal width of the power saving mode information output signal output from the output terminal PT11) is output so that the peripheral control unit 1 ms timer interrupt process is repeated 300,000 times based on the interrupt cycle of 1 ms). It has become.

Of the output terminals PT1 to PT11 of the external terminal board 784, the output terminals PT1 and PT2 output various signals output on the payout control board 4110 side, and the output terminals PT3 to PT9 are output on the main control board 4100 side. Various signals are output via (passing through) the payout control board 4110, and the output terminals PT10 and PT11 are arranged so that the signals output on the peripheral control board 4140 side are output. The output terminals PT1 to PT11 are each colored, and by electrically connecting the wirings having connectors that are colored in the same color to the output terminals PT1 to PT11, the other wirings are erroneously electrically connected. It is possible to prevent the connection from being targeted. Then, the payout control board 4110 is not mixed with various signals output on the payout control board 4110 side, various signals output on the main control board 4100 side, and signals output on the peripheral control board 4140 side. Output terminals PT1 and PT2 for transmitting various signals output on the side to the hall computer are arranged in a row on the left side of the external terminal board 784, and various signals output on the main control board 4100 side are transmitted to the hall computer. The output terminals PT3 to PT9 are arranged in a row from the center left side to the right side of the external terminal board 784, and the output terminals PT10 and PT11 for transmitting the signal output on the peripheral control board 4140 side to the hall computer are provided on the external terminal board. By arranging the output terminals PT1 to PT11 in a row by arranging them on the right side of 784, also in this respect, wiring for transmitting various signals output on the payout control board 4110 side to the hall computer and Incorrectly electrically connecting the wiring for transmitting various signals output on the main control board 4100 side to the hall computer and the wiring for transmitting the signal output on the peripheral control board 4140 side to the hall computer. Can be prevented.

In the present embodiment, the prize ball number information output signal output on the payout control board 4110 side and the main prize ball number information output signal output on the peripheral control board 4140 side are halled from the external terminal board 784, respectively. It is configured to tell the computer. This is because, for example, the game balls stored in the prize ball tank 720 are stored in the prize ball tank 720 in a state where the game balls from the pachinko island equipment side are not supplied to the prize ball tank 720 shown in FIG. 1 due to some trouble in the pachinko island equipment. If a 15-round jackpot happens to occur in the pachinko game machine 1 when the remaining number is low, the number of game balls stored in the prize ball tank 720 for paying out the game balls as prize balls will be insufficient. (Also, if ball clogging or ball clogging occurs in the prize ball device 740, for example, the game ball cannot be paid out unless this can be resolved). Then, in the prize ball number information output signal output on the payout control board 4110 side, as described above, the number of game balls actually paid out by the payout motor 744 shown in FIG. 5 reaches 10 balls. Since it is a signal to convey that fact for each case, the payout control board 4110 can output a prize ball number information output signal and transmit it to the hall computer via the external terminal board 784 because the game ball cannot be paid out. become unable. When the game ball is not paid out, the player calls a clerk in the hall. The clerk in the hall, for example, checks the hose-shaped replenishment nozzle for supplying the game ball from the pachinko island facility to the prize ball tank 720 and identifies the position of the ball jam (also, in the prize ball device 740, for example). By identifying the position of the ball jam and the position of the ball hose that have occurred) and eliminating it, the game ball will be returned to the state of being paid out.

However, even if the clerk in the hall is working, the game by the main control board 4100 is in progress, so after the 15 rounds of big hits are completed, the game ball is paid out by the clerk in the hall. When the game returns to the above state, the payout control board 4110 pays out the unpaid game balls one after another, and the payout control board 4110 is in the period when the 15-round jackpot is completed and the 15-round jackpot has not occurred. Outputs a prize ball number information output signal to notify each time the number of game balls actually paid out by the payout motor 744 as prize balls reaches 10, and transmits the signal to the hall computer via the external terminal board 784. It will be. Then, even though the 15-round jackpot has not occurred, an extremely large number of gaming balls will be paid out. Therefore, the gaming state of the pachinko gaming machine 1 and the gaming balls paid out by the pachinko gaming machine 1 There arises a problem that the hall computer cannot accurately grasp the relationship between the number of balls and the number of balls.

Therefore, in the present embodiment, regardless of whether or not the payout motor 744 is driven and controlled by the payout control board 4110 and actually paid out as a prize ball, that is, it is different from the prize ball number information output signal output by the payout control board 4110. As a signal of, the main control board 4100 is based on a game ball that has entered various winning openings such as the upper starting opening 2101, the lower starting opening 2102, the general winning opening 2104, 2201, and the large winning opening 2103 shown in FIG. Every time the number of game balls to be paid out as prize balls reaches 10, a command to that effect (main prize ball number information output command described later) is transmitted to the peripheral control board 4140, and the peripheral control board 4140 , Based on this received command (main prize ball number information output command described later), the ball enters various winning openings such as the upper starting opening 2101, the lower starting opening 2102, the general winning opening 2104, 2201, and the large winning opening 2103. Every time the number of game balls scheduled to be paid out as a prize ball based on the game ball reaches 10, the main prize ball number information output signal is output to the external terminal board 784 as the main prize ball number information. We adopted a mechanism to communicate to the hall computer. As a result, even if the above-mentioned troubles (trouble such as ball clogging in the replenishment nozzle or the like, ball clogging in the prize ball device 740, ball clogging, etc.) occur, the gaming state of the pachinko gaming machine 1 and this gaming state It is possible to accurately convey the relationship between the number of game balls to be paid out and the number of game balls to be paid out to the hall computer. Therefore, the hall computer can accurately grasp the relationship between the gaming state of the pachinko gaming machine 1 and the number of gaming balls paid out in the gaming state.

[12. Liquid crystal output board circuit]
Next, four 4.3-inch movable liquid crystal display devices 1925a to 1925d arranged in the upper left, lower left, lower right, and upper right of the front side of the 12-inch game board side liquid crystal display device 1900 shown in FIG. The circuit of the liquid crystal output board 3420 that draws the display area of the above will be described with reference to FIGS. 31 to 34. First, the circuit configuration of the liquid crystal output board will be described, followed by a method of creating drawing data, and an example of the production of the liquid crystal display device on the game board side and the movable liquid crystal display device. FIG. 31 is a block diagram showing a circuit configuration of a liquid crystal output board, FIG. 32 is a diagram showing an example of a drawing data creation method, and FIG. 33 is a production example of a game board side liquid crystal display device and a movable liquid crystal display device. It is a figure which shows an example, and FIG. 34 is a figure which shows the continuation of the example of the effect example of FIG. 33.

[12-1. Liquid crystal output board circuit configuration]
As described above, the liquid crystal and sound source built-in VDP4160a of the sound control unit 4160 in the peripheral control board 4140 receive the input screen data when the screen data is input from the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140. Based on the above, the game board side character data and the precision plate side character data are extracted from the liquid crystal and sound control ROM 4160b of the liquid crystal and sound control unit 4160 to create sprite data, and the game board side liquid crystal display device 1900 and the movable liquid crystal display device are displayed. It also has a built-in VRAM (built-in VRAM) for generating drawing data for one screen (one frame) to be displayed on the 1925a to 1925d and the liquid crystal display device 470 on the upper plate side. Among the drawing data generated on the built-in VRAM, the sound source built-in VDP4160a transmits the drawing data for the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d from the channel CH1 via the liquid crystal output board 3420 on the game board side liquid crystal. In addition to outputting to the display device 1900 and the movable liquid crystal display devices 1925a to 1925d, drawing data for the upper plate side liquid crystal display device 470 is output from channel CH2 to a peripheral control output circuit (not shown), a frame peripheral relay terminal plate 868, and a peripheral door relay terminal. By outputting (transmitting) to the upper plate side liquid crystal display device 470 via the plate 882 and the touch panel drive board 450 housed in the plate unit 300 of the door frame 5, the game board side liquid crystal display device 1900 and the movable liquid crystal The display devices 1925a to 1925d are synchronized with the upper plate side liquid crystal display device 470.

As described above, channel CH1 employs a dual link system as LVDS. The first signal transmission line is an even number channel, the signal transmission line on the two sides is an odd number channel, and the drawing data for the game board side liquid crystal display device 1900 is transmitted from the even number channel to the liquid crystal output board 3420, while the odd number channel is 4 Drawing data for the two movable liquid crystal display devices 1925a to 1925d is transmitted to the liquid crystal output board 3420. Drawing data is transmitted simultaneously for even-numbered addresses and odd-numbered addresses by the dual link method.

As shown in FIG. 31, the liquid crystal output substrate 3420 mainly includes an RGB conversion circuit 3420x and signal division circuits 3420y and 3420z. The RGB conversion circuit 3420x uses the input serial signal as three video signals, a red video signal, a green video signal, and a blue video signal, and three sync signals, a horizontal sync signal, a vertical sync signal, and a clock signal. It is converted into a parallel signal composed of. In the signal division circuits 3420y and 3420z, a control signal as to whether or not to accept the paralleles signal from the RGB conversion circuit 3420x is input from the sound source built-in VDP4160a, and the parallels signal from the RGB conversion circuit 3420x is input based on this control signal. It receives and adjusts the size for drawing in the display area of the movable liquid crystal display devices 1925a to 1925d, and outputs the output to the movable liquid crystal display devices 1925a to 1925d.

Specifically, when drawing data (serial signal) for the movable liquid crystal display devices 1925a to 1925d from an odd address is received (input) by the RGB conversion circuit 3420x, the RGB conversion circuit 3420x receives the received drawing. The data (input serial signal) is composed of three video signals, a red video signal, a green video signal, and a blue video signal, and three sync signals, a horizontal sync signal, a vertical sync signal, and a clock signal. Convert to a parallel signal. Then, the parallel signal converted by the RGB conversion circuit 3420x is input to the signal division circuits 3420y and 3420z.

When the control signal from the sound source built-in VDP4160a conveys that the drawing data for the movable liquid crystal display devices 1925a and 1925b should be received and captured, the signal dividing circuit 3420y captures the drawing data and captures the drawing data. , The size for drawing in the display area of 1925b should be adjusted and output to the movable liquid crystal display devices 1925a and 1925b, while the control signal from the sound source built-in VDP4160a should accept and capture the drawing data for the movable liquid crystal display devices 1925a and 1925b. When it conveys that it is not, the drawing data is not taken in.

When the control signal from the VDP4160a with built-in sound source conveys that the drawing data for the movable liquid crystal display devices 1925c and 1925d should be accepted and captured, the signal dividing circuit 3420z captures the drawing data and captures the drawing data. , The size for drawing in the display area of 1925d should be adjusted and output to the movable liquid crystal display devices 1925c and 1925d, while the control signal from the sound source built-in VDP4160a should accept and capture the drawing data for the movable liquid crystal display devices 1925c and 1925d. When it conveys that it is not, the drawing data is not taken in.

On the other hand, the drawing data (serial signal) for the game board side liquid crystal display device 1900 from even-numbered addresses passes through the liquid crystal output board 3420 and is directly output to the game board side liquid crystal display device 1900.

By the way, as described above, the movable devices 1925a to 1925da, which can independently move the movable liquid crystal display devices 1925a to 1925d in the vertical and horizontal directions, are the output shafts of the two stepping motors and the two stepping motors. Each of them is provided with a conversion mechanism for converting rotary motion into linear motion, and two stepping motors provided in each of the movable devices 1925aa to 1925da are driven and controlled by the peripheral control MPU 4150a of the peripheral control unit 4150 on the peripheral control board 4140. It has become. Further, the movable devices 1925aa to 1925da are provided with photosensors (not shown) for detecting the state in which the movable liquid crystal display devices 1925a to 1925d are in the original position, and the detection signals from these photosensors are peripherally controlled. Each of them is input to the MPU4150a, and the peripheral control MPU4150a determines whether or not the movable liquid crystal display devices 1925a to 1925d are in the in-situ standby state based on the detection signal from the photo sensor. The peripheral control MPU4150a outputs a drive signal (drive pulse) to the stepping motor provided in the movable devices 1925aa to 1925da from the state in which the movable liquid crystal display devices 1925a to 1925d stand by in the original position based on the detection signal from the photo sensor. Since the rotation angle per step of the rotation axis of the stepping motor is determined, the movable positions of the movable liquid crystal display devices 1925a to 1925d are estimated and moved based on the output drive signal (drive pulse). ..

[12-2. How to create drawing data]
Next, drawing data for the liquid crystal display device 1900 on the game board side transmitted from the even-numbered channels to the liquid crystal output board 3420, and drawing data for the four movable liquid crystal display devices 1925a to 1925d transmitted from the odd-numbered channels to the liquid crystal output board 3420. , Will be explained.

The drawing data for the game board side liquid crystal display device 1900 transmitted from the even channel to the liquid crystal output board 3420 and the drawing data for the four movable liquid crystal display devices 1925a to 1925d transmitted from the odd channel to the liquid crystal output board 3420 are: The liquid crystal on the peripheral control board 4140 and the frame buffers MVD and SVD on the built-in VRAM of the sound source built-in VDP4160a of the sound control unit 4160 are created, respectively.

[12-2-1. Drawing data transmitted from even-numbered channels]
The frame buffer MVD for creating drawing data for the liquid crystal display device 1900 on the game board side transmitted from the even channels to the liquid crystal output board 3420 has a frame buffer size (storage capacity) corresponding to an image size of 1600 × 600 dots in advance. Allocated. The frame buffer MVD has twice the size in the horizontal direction as compared with the image size (12 inches) of 800 × 600 dots of the liquid crystal display device 1900 on the game board side. As shown in FIG. 32 (a), the sound source built-in VDP4160a displays the original image MVD0 for drawing in the display area of the liquid crystal display device 1900 on the game board side in the frame buffer MVD in the upper right part of FIG. 32 (b). After creating the origin at 600 dots downward from the origin of FIG. 32 (b) and 800 dots to the left from the origin of FIG. 32 (b), this original image MVD0 is displayed in the horizontal direction (FIG. 32 (b)). A stretched image MVD1 that is stretched twice toward the left side) is created. This extension is a command that creates sprite data by extracting character data from the liquid crystal and sound control ROM 4160b based on the screen data from the peripheral control MPU4150a and enlarging / reducing it when the sound source built-in VDP4160a creates the original image MVD0. Executed by the same command as. In other words, the command used to create various sprite data arranged in the original image MVD0 is used as a command to extend the original image MVD0.

The VDP4160a with a built-in sound source creates a stretched image MVD1 and then removes an image in a portion corresponding to an odd address of the frame buffer MVD (for example, it is painted in black. In FIG. 32 (c), it is white from the viewpoint of easy viewing of the drawing. As shown in FIG. 32 (c), the image corresponding to the odd address is removed in the vertical direction, and only the image corresponding to the even address remains. Create image MVD2.

Since the addresses for specifying the drawing data created in the frame buffer MVD are odd-numbered addresses and even-numbered addresses arranged alternately, the frame buffer MVD has one line in the vertical direction shown in FIG. 32 (c). The image (that is, the image in the vertical direction of one dot) is removed, and the image is in the state of the grid-processed image MVD2. The original image MVD0 shown in FIG. 32 (a) is created at the origin (upper right portion of FIG. 32 (b)), and the original image MVD0 is moved laterally (to the left in FIG. 32 (b)) 2 Even if the above-mentioned grid-like processed image MVD2 is created by stretching it twice, if the image for one vertical line shown in FIG. 32 (c) is omitted and the space between them is shortened, the origin shown in FIG. 32 (a) is reduced. The image is the same as the image MVD0. Note that FIG. 32 (c) shows an image for a plurality of lines (that is, an image for a plurality of lines) in a state in which an image for one vertical line (that is, an image for one dot in the vertical direction) is removed from the viewpoint of easy viewing of the drawing. , Vertical image for multiple dots) is shown as a removed state.

When the drawing data for the game board side liquid crystal display device 1900 created in the frame buffer MVD is transmitted from the even channels of channel CH1 in the sound source built-in VDP4160a to the liquid crystal output board 3420, the game board side liquid crystal display is displayed via the liquid crystal output board 3420. It is output to the device 1900. Since the image size of the original image MVD0 of the drawing data is the same as the image size (12 inches) of 800 x 600 dots of the game board side liquid crystal display device 1900, the image of the same size as the original image MVD0 is the game board side liquid crystal. It is drawn in the display area of the display device 1900.

[12-2-2. Drawing data transmitted from odd-numbered channels]
The frame buffer SVD for creating drawing data for the movable liquid crystal display devices 1925a to 1925d transmitted from the odd channels to the liquid crystal output board 3420 is for the game board side liquid crystal display device 1900 transmitted from the above-mentioned even channels to the liquid crystal output board 3420. It is the same as the frame buffer size of the frame buffer MVD for creating drawing data, and a size (storage capacity) corresponding to an image size of 1600 × 600 dots is allocated in advance as the frame buffer size. As for the drawing data created in the frame buffer SVD, the original image is created in the four frame buffers SVDA to S VDD having a size smaller than the frame buffer size of the frame buffer SVD.

The frame buffer SVDA is an area for creating the original image SVDA0 for drawing in the display area of the movable liquid crystal display device 1925a shown in FIG. 32 (d), and also serves as a temporary area for the image stretching work described later. As a frame buffer size, a size (storage capacity) corresponding to an image size of 720 × 204 dots is allocated in advance. The frame buffer SVDB is an area for creating the original image SVDB0 for drawing in the display area of the movable liquid crystal display device 1925b shown in FIG. 32 (d), and has a frame buffer size corresponding to an image size of 360 × 204 dots. The image (storage capacity) is allocated in advance. The frame buffer SVDC is an area for creating the original image SVDC0 for drawing in the display area of the movable liquid crystal display device 1925c shown in FIG. 32 (d), and has a frame buffer size corresponding to an image size of 360 × 204 dots. The image (storage capacity) is allocated in advance. The frame buffer S VDD is an area for creating the original image S VDD0 for drawing in the display area of the movable liquid crystal display device 1925d shown in FIG. 32 (d), and is a size corresponding to an image size of 360 × 204 dots as a frame buffer size. The image (storage capacity) is allocated in advance.

The original images SVDA0 to S VDD0 are smaller because they have a size of 360 × 204 dots as compared with the image size (4.3 inches) of 480 × 272 dots of the movable liquid crystal display devices 1925a to 1925d. Further, the frame buffer SVDA has twice the size in the horizontal direction as compared with the other frame buffers SVDB to S VDD.

As shown in FIG. 32 (d), the sound source built-in VDP4160a has the original image SVDA0 for drawing in the display area of the movable liquid crystal display device 1925a in the frame buffer SVDA, with the upper right portion as the origin and downward from the origin. After creating 204 dots and 360 dots to the left from the origin, the original image SVDA0 is stretched twice in the horizontal direction (leftward in FIG. 32 (d)) to create a stretched image SVDA1. In this extension, as described above, when the sound source built-in VDP4160a creates the original image MVD0 or the original image SVDA0, the character data is extracted from the liquid crystal and the sound control ROM 4160b based on the screen data from the peripheral control MPU4150a. It is executed by the same command that created the sprite data by scaling. In other words, the command used to create various sprite data arranged in the original image SVDA0 is used as a command to extend the original image SVDA0.

As shown in FIG. 32 (e), the stretched image SVDA1 created by the frame buffer SVDA is transferred to the frame buffer SVD that creates drawing data transmitted from the odd-numbered channels to the liquid crystal output board 3420. In the frame buffer SVD, regions RGNA to RGND for arranging drawing data for the movable liquid crystal display devices 1925a to 1925d are partitioned in advance. As shown in FIG. 32 (e), the area RGND for arranging the drawing data for the movable liquid crystal display device 1925d is located in an area of 204 dots downward from the origin and 720 dots left from the origin, with the upper right portion as the origin. The area RGNC arranged and for arranging the drawing data for the movable liquid crystal display device 1925c is arranged adjacently (continuously) below the area RGND, and 204 dots downward from the lower right point of the area RGND. The area RGNB arranged in the area of 720 dots to the left from the lower right point of the area RGND and for arranging the drawing data for the movable liquid crystal display device 1925b is adjacent (continuously) to the left side of the area RGNC. The area is arranged and has 204 dots downward from the upper left point of the area RGNC (the lower left point of the area RGND) and 720 dots to the left from the upper left point of the area RGNC (the lower left point of the area RGND). The area RGNA for arranging the drawing data for the movable liquid crystal display device 1925a is arranged adjacent to (continuously) to the left of the area RGND and adjacent to (continuously) above the area RGNB. It is arranged in an area of 204 dots downward from the upper left point of the area RGND and 720 dots downward from the upper left point of the area RGND. By arranging the four regions RGNA to RGND adjacent to each other (continuously) in this way, as shown in FIG. 32 (e), 408 dots downward from the origin with the upper right portion as the origin. The area (204 dots + 204 dots) and 1440 (720 dots + 720 dots) from the origin is partitioned by the frame buffer SVD.

When the stretched image SVDA1 is created in the frame buffer SVDA, the sound source built-in VDP4160a transfers the stretched image SVDA1 to the region RGNA as shown in FIG. 32 (e). Then, the sound source built-in VDP4160a transfers the original image SVDB0 for drawing in the display area of the movable liquid crystal display device 1925b created in the frame buffer SVDB to the frame buffer SVDA, and transfers the original image SVDB0 in the horizontal direction (FIG. 32). A stretched image SVDB1 that is stretched twice in the direction (to the left in (d)) is created. In this extension, as described above, when the sound source built-in VDP4160a creates the original image MVD0 or the original image SVDB0, the character data is extracted from the liquid crystal and the sound control ROM 4160b based on the screen data from the peripheral control MPU4150a. It is executed by the same command that created the sprite data by scaling. In other words, the command used to create various sprite data arranged in the original image SVDB0 is used as a command to extend the original image SVDB0. The sound source built-in VDP4160a transfers the stretched image SVDB1 created in the frame buffer SVDA to the region RGNB as shown in FIG. 32 (e).

Then, the sound source built-in VDP4160a transfers the original image SVDC0 for drawing in the display area of the movable liquid crystal display device 1925c created in the frame buffer SVDC to the frame buffer SVDA, and transfers the original image SVDC0 in the horizontal direction (FIG. 32). A stretched image SVDC1 stretched twice in the direction (to the left in (d)) is created. In this extension, as described above, when the sound source built-in VDP4160a creates the original image MVD0 or the original image SVDC0, the character data is extracted from the liquid crystal and the sound control ROM 4160b based on the screen data from the peripheral control MPU4150a. It is executed by the same command that created the sprite data by scaling. In other words, the command used to create various sprite data arranged in the original image SVDC0 is used as a command to extend the original image SVDC0. The sound source built-in VDP4160a transfers the stretched image SVDC1 created in the frame buffer SVDA to the region RGNC as shown in FIG. 32 (e).

Then, the sound source built-in VDP4160a transfers the original image S VDD0 for drawing in the display area of the movable liquid crystal display device 1925d created in the frame buffer S VDD to the frame buffer SVDA, and transfers the original image S VDD0 in the horizontal direction (FIG. 32). A stretched image S VDD1 stretched twice in the direction (to the left in (d)) is created. As described above, this extension extracts character data from the liquid crystal and the sound control ROM 4160b based on the screen data from the peripheral control MPU4150a when the sound source built-in VDP4160a creates the original image MVD0 or the original image S VDD0. It is executed by the same command that created the sprite data by scaling. In other words, the command used to create the various sprite data arranged in the original image S VDD0 is used as the command to extend the original image S VDD0. The sound source built-in VDP4160a transfers the stretched image SVDD1 created in the frame buffer SVDA to the region RGND as shown in FIG. 32 (e).

The sound source built-in VDP4160a completes the transfer of the stretched images SVDA1 to SVDD1 to the regions RGNA to RGND, thereby stretching the stretched images to the frame buffer SVD and completing the creation of the entire image SVD1.

When the VDP4160a with built-in sound source completes the transfer of the stretched images SVDA1 to SVDD1 to the regions RGNA to RGND, the image in the portion corresponding to the even address of the frame buffer SVD is removed (for example, it is painted in black. In FIG. 32 (f), the drawing is shown. It is painted white from the viewpoint of visibility.) As shown in FIG. 32 (f), the image corresponding to the even address is removed in the vertical direction, and only the image corresponding to the odd address remains in a grid pattern. Create a grid-like processed image SVD2 processed into.

Since the addresses for specifying the drawing data created in the frame buffer SVD are odd-numbered addresses and even-numbered addresses arranged alternately, the frame buffer SVD has one line in the vertical direction shown in FIG. 32 (f). (That is, the image in the vertical direction for one dot) is removed, and the image is in the state of the grid-processed image SVD2. The original images SVDA0 to S VDD0 shown in FIG. 32 (d) are created at the origin (upper right part of FIG. 32 (d)), and the original images SVDA0 to S VDD0 are created in the horizontal direction (leftward in FIG. 32 (d)). Even if the above-mentioned grid-like processed image SVD2 is created by stretching the image twice toward and transferring it to the regions RGNA to RGND, the image for one vertical line shown in FIG. 32 (f) is omitted and the interval is shortened. And, it becomes the same image as the whole image in which the four original images SVDA0 to S VDD0 shown in FIG. 32 (d) are arranged adjacently (consecutively). Note that FIG. 32 (f) shows an image for a plurality of lines (that is, an image for a plurality of lines) in a state in which an image for one vertical line (that is, an image for one dot in the vertical direction) is removed from the viewpoint of easy viewing of the drawing. , Vertical image for multiple dots) is shown as a removed state.

In this procedure, among the procedures for creating drawing data for the movable liquid crystal display devices 1925a to 1925d transmitted from the odd channels to the liquid crystal output board 3420, first, the original images SVDA0 to S VDD0 are created in each of the four frame buffers SVDA to SVDD. Then, when the stretched image SVDA1 is created in the frame buffer SVDA and transferred to the area RGNA of the frame buffer SVD, the original images SVDB0 to S VDD0 created in the frame buffers SVDB to S VDD0 are subsequently stretched in the frame buffer SVDA1 to SVDB1 to. Regarding the procedure of creating S VDD1 and transferring it to the areas RGNB to RGND of the frame buffer SVD in order, "after creating the original image MVD0 in the frame buffer MVD, create the stretched image MVD1 in the same frame buffer MVD. This is different from the procedure for creating drawing data for the game board side liquid crystal display device 1900 transmitted from the even channels to the liquid crystal output board 3420.

It should be noted that the image of the frame buffer MVD in which the drawing data for the game board side liquid crystal display device 1900 transmitted from the even channels to the liquid crystal output board 3420 and the movable liquid crystal display device 1925a transmitted from the odd channels to the liquid crystal output board 3420 a. When the image of the frame buffer SVD in which the drawing data for ~ 1925d is created is superimposed, as shown in FIG. 32 (g), the grid-shaped processed images MVD2 and FIG. 32 (c) shown in FIG. 32 (c) ( An image in which the grid-processed image SVD2 shown in f) is alternately arranged without interfering with each other (in other words, the comb teeth of the grid-processed image MVD2 shown in FIG. 32 (c) and FIG. 32 (f). ) Is an image) arranged in a state of being engaged with the comb teeth of the grid-like processed image SVD2 shown in).

When the drawing data for the movable liquid crystal display devices 1925a to 1925d created in the frame buffer SVD is transmitted from the odd channel of the channel CH1 in the sound source built-in VDP4160a to the liquid crystal output board 3420, the liquid crystal output board 3420 is RGB as described above. The conversion circuit 3420x comprises the received drawing data as three video signals, a red video signal, a green video signal, and a blue video signal, and three sync signals, a horizontal sync signal, a vertical sync signal, and a clock signal. It is converted into a parallel signal. Then, the parallel signal converted by the RGB conversion circuit 3420x is input to the signal division circuits 3420y and 3420z.

When the control signal from the sound source built-in VDP4160a conveys that the drawing data for the movable liquid crystal display devices 1925a and 1925b should be received and captured, the signal dividing circuit 3420y captures the drawing data. Since the image size of the captured drawing data is 360 × 204 dots of the original images SVDA0 and SVDB0, it is compared with the image size (4.3 inches) of 480 × 272 dots of the movable liquid crystal display devices 1925a and 1925b. It is small in both the vertical and horizontal directions. Therefore, in the signal dividing circuit 3420y, the size for drawing in the display area of the movable liquid crystal display devices 1925a and 1925b is adjusted and output to the movable liquid crystal display devices 1925a and 1925b. That is, an enlarged image of the original images SVDA0 and SVDB0 is drawn in the display areas of the movable liquid crystal display devices 1925a and 1925b, respectively.

When the control signal from the sound source built-in VDP4160a conveys that the drawing data for the movable liquid crystal display devices 1925c and 1925d should be received and captured, the signal dividing circuit 3420z captures the drawing data. Since the image size of the captured drawing data is 360 × 204 dots of the original images SVDC0 and S VDD0, it is compared with the image size (4.3 inches) of 480 × 272 dots of the movable liquid crystal display devices 1925c and 1925d. It is small in both the vertical and horizontal directions. Therefore, in the signal dividing circuit 3420z, the size for drawing in the display area of the movable liquid crystal display devices 1925c and 1925d is adjusted and output to the movable liquid crystal display devices 1925c and 1925d. That is, an enlarged image of the original images SVDC0 and S VDD0 is drawn in the display areas of the movable liquid crystal display devices 1925c and 1925d, respectively.

[12-3. Production example of the liquid crystal display device on the game board side and the movable liquid crystal display device]
As described above, the channel CH1 in the VDP4160a with a built-in sound source employs a dual link system as the LVDS. The first signal transmission line is an even number channel, the signal transmission line on the two sides is an odd number channel, and drawing data for the game board side liquid crystal display device 1900 is transmitted from the even number channel to the liquid crystal output board 3420, while the odd number channel is 4 Drawing data for the two movable liquid crystal display devices 1925a to 1925d is transmitted to the liquid crystal output board 3420. Drawing data is transmitted simultaneously for even-numbered addresses and odd-numbered addresses by the dual link method. When the drawing data for the game board side liquid crystal display device 1900 created in the frame buffer MVD is transmitted from the even channels of channel CH1 in the sound source built-in VDP4160a to the liquid crystal output board 3420, the game board side liquid crystal display is displayed via the liquid crystal output board 3420. The original image MVD0 output to the device 1900 is drawn in the display area of the liquid crystal display device 1900 on the game board side, and is also drawn for the movable liquid crystal display devices 1925a to 1925d transmitted to the liquid crystal output board 3420 created in the frame buffer SVD. When the data is transmitted from the odd channel of channel CH1 in the sound source built-in VDP4160a to the liquid crystal output board 3420, the data is decomposed and enlarged in the liquid crystal output board 3420 and output to the movable liquid crystal display devices 1925a to 1925d, respectively, and the original image SVDA0. ~ S VDD0 are drawn in the display areas of the movable liquid crystal display devices 1925a to 1925d, respectively.

Here, among a plurality of modes in which the movable liquid crystal display devices 1925a to 1925d are movable, as an example thereof, the movable liquid crystal display devices 1925a to 1925d are moved from their respective original positions toward the center of the display area of the game board side liquid crystal display device 1900. A mode in which the liquid crystal display device 1900 on the game board side appears on the front surface and is united as one display device to cover the entire display area of the liquid crystal display device 1900 on the game board side will be briefly described.

As described above, the movable liquid crystal display devices 1925a to 1925d are in positions that are difficult to see when the pachinko gaming machine 1 is viewed from the front side in the standby state in the original positions (movable liquid crystal display devices 1925a, The 1925b is in a standby state with the rear upper left side and the rear left lower side of the gear decoration unit 3500 shown in FIG. 9 as the original positions, and the movable liquid crystal display devices 1925c and 1925d are in the rear of the character unit 3400 shown in FIG. It is in a state of waiting with the lower right side and the rear upper right side as the original positions.)

As described above, the movable liquid crystal display devices 1925a to 1925d include the movable devices 1925aa, 1925ba, 1925ca, which are provided on the rear upper left, the rear left lower, the rear right lower, and the rear upper right of the back box 3001 shown in FIG. According to 1925da, it is configured to be independently movable in the vertical and horizontal directions.

The movable liquid crystal display devices 1925a to 1925d are drawn by the movable devices 1925aa, 1925ba, 1925ca, 1925da while drawing an enlarged image of the original images SVDA0 to S VDD0 shown in FIG. As shown in (a), the movement is started from each original position toward the center of the display area of the liquid crystal display device 1900 on the game board side. At this time, the original image MVD0 shown in FIG. 32A is drawn in the display area of the liquid crystal display device 1900 on the game board side. Then, as shown in FIG. 34 (b), it appears from the four corners of the game board side liquid crystal display device 1900 to the front surface of the game board side liquid crystal display device 1900, and as shown in FIG. 34 (c), the game board side liquid crystal display device. In the center of the display area of the display device 1900, it is united as one liquid crystal display device and covers the entire display area of the liquid crystal display device 1900 on the game board side.

After that, the movable liquid crystal display devices 1925a to 1925d are moved from the state of being united as one liquid crystal display device in the center of the display area of the game board side liquid crystal display device 1900 to their original positions by the movable devices 1925aa, 1925ba, 1925ca, 1925da. It starts to move, passes through the four corners of the liquid crystal display device 1900 on the game board side, returns to its original position, and stands by.

In the present embodiment, as described above, since the channel CH1 in the VDP4160a with a built-in sound source adopts the dual link method as the LVDS, the drawing data of the even address and the odd address are transmitted at the same time, so that the liquid crystal output is output from the even channel. The drawing data for the substrate 3420 is transmitted, and the drawing data for the four movable liquid crystal display devices 1925a to 1925d are transmitted from the odd-numbered channels. Therefore, regardless of the movable position of the movable liquid crystal display devices 1925a to 1925d, that is, the image drawn in the display area of the movable liquid crystal display devices 1925a to 1925d with the movable liquid crystal display devices 1925a to 1925d standing by at their original positions is displayed. Even when it is difficult for the player to visually recognize the drawing data, the drawing data for drawing in the display area of the movable liquid crystal display devices 1925a to 1925d is transmitted from the odd channel of the channel CH1 in the sound source built-in VDP4160a.

[13. Touch panel drive board circuit]
Next, detection of the contact state of the capacitive touch panel 480 provided so as to cover the display area of the upper plate side liquid crystal display device 470 attached to the right side of the plate unit 300 of the door frame 5 shown in FIG. The circuit of the touch panel drive board 450 that controls and draws the display area of the upper plate side liquid crystal display device 470 will be described with reference to FIGS. 35 to 38. As described above, the touch panel drive board 450 is arranged near the lower side of the upper plate side liquid crystal display device 470 attached to the right side of the plate unit 300 of the door frame 5, and is housed in the plate unit 300. It is mainly composed of a liquid crystal module circuit 450V that draws a display area of the dish-side liquid crystal display device 470 and a touch panel circuit 450W that detects and controls a contact state of the touch panel 480. FIG. 35 is a circuit diagram showing a liquid crystal module circuit that draws a display area of the upper plate side liquid crystal display device, FIG. 36 is a block diagram of a touch panel circuit that detects and controls a contact state of the touch panel, and FIG. 37 is a touch panel. It is a schematic diagram which detects the position which a finger touches, and FIG. 38 is a schematic diagram which shows the continuation of FIG. 37. First, the liquid crystal module circuit will be described, and then the touch panel circuit will be described.

[13-1. Liquid crystal module circuit]
As shown in FIG. 35, the liquid crystal module circuit 450V of the touch panel drive substrate 450 mainly comprises the upper plate side liquid crystal receiver ICSDIC0.

The liquid crystal module circuit 450V is a serial signal (serial data) from the peripheral control board 4140's upper plate side liquid crystal transmitter IC 4160d shown in FIG. 17 by a differential method called "V-by-One (registered trademark)" of Zain Electronics Co., Ltd. Is transmitted as a positive signal and a negative signal, and is input to the common mode choke coil SDL0 via the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882, respectively. Noise can be separated from the negative signal. The positive signal and the negative signal from which noise is separated are input to the RXIN + terminal and the RXIN− terminal of the upper plate side liquid crystal receiver ICSDIC0, respectively. A resistor SDR0 is electrically connected between the RXIN + terminal and the RXIN− terminal. This resistor SDR0 is a terminating resistor (terminator), and prevents the plus signal and the minus signal from being reflected at the RXIN + terminal and the RXIN− terminal, respectively, and prevents the serial signal from being disturbed.

The receiver ICSDIC0 for the liquid crystal on the precision plate side has three video signals, a red video signal, a green video signal, and a blue video signal, based on the serial signals (serial data) input at the RXIN + terminal and the RXIN- terminal, respectively. It is restored to three synchronization signals, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal (that is, it is restored to a parallel signal before being serialized). As for the red video signal, the green video signal, and the blue video signal, as described above, the red video signal, the green video signal, and the blue video signal output from the channel CH2 of the VDP4160a with built-in sound source are each 8 bits. Since the red video signal, the green video signal, and the blue video signal that can be input to the upper plate side liquid crystal transmitter IC 4160d are each 6 bits, a total of 18 bits, they are the upper 6 bits of each video signal.

In addition to the signal from the upper plate side liquid crystal transmitter IC 4160d of the peripheral control board 4140, the liquid crystal module circuit 450V is a touch panel drive board built in the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140 as described above. Two signals in which the LOCKN signal output request data, which is the serial data output from the serial I / O port, is differentiated into a positive signal and a negative signal in the differential circuit 4160e of the peripheral control board 4140 are also input. It has become like. As described above, the forced switching circuit 4160f of the peripheral control board 4140 transmits these two signals when the two signals differentiated into the plus signal and the minus signal are input in the differential circuit 4160e. On the other hand, when the two differential signals, the positive signal and the negative signal, are not input in the differential circuit 4160e, the signal output from the upper plate side liquid crystal transmitter IC 4160d is transmitted. The circuit is configured to connect the circuit so as to do so. As a result, when two signals differentiated into a plus signal and a minus signal are input in the differential circuit 4160e, the two signals are connected in a circuit so as to transmit the two signals, so that the two signals are connected. , Transmitted from the peripheral control board 4140 to the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the liquid crystal module circuit 450V of the touch panel drive board 450 housed in the dish unit 300 of the door frame 5, while being differential. When two signals differentiated into a plus signal and a minus signal are not input in the conversion circuit 4160e, the upper plate is connected so as to transmit the signal output from the upper plate side liquid crystal transmitter IC 4160d. The signal output from the side liquid crystal transmitter IC 4160d is stored in the peripheral control board 4140, the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the liquid crystal of the touch panel drive board 450 housed in the dish unit 300 of the door frame 5. It is transmitted to the module circuit 450V.

The forced switching circuit 4160f is a signal output from the upper plate side liquid crystal transmitter IC 4160d, that is, an upper plate when two signals differentiated into a positive signal and a negative signal are not input in the differential circuit 4160e. From the side liquid crystal transmitter IC4160d, the serial signal (serial data) by the differential method called "V-by-One (registered trademark)" of Zain Electronics Co., Ltd. is used as a positive signal and a negative signal from the peripheral control board 4140 to the frame peripheral relay terminal board. It is input to the common mode choke coil SDL0 via the 868 and the peripheral door relay terminal plate 882, and is input to the RXIN + terminal and the RXIN- terminal of the precision side liquid crystal receiver ICSDIC0, respectively, while the differential circuit 4160e. When two signals differentiated into a positive signal and a negative signal are input from the peripheral control board 4140 via the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882, these two signals are input. It is input to the common mode choke coil SDL0, and is input to the RXIN + terminal and the RXIN- terminal of the upper plate side liquid crystal receiver ICSDIC0, respectively. The receiver ICSDIC0 for the liquid crystal on the upper plate side determines that it is an output request of the LOCKN signal when two signals differentiated into a plus signal and a minus signal are input in the differential circuit 4160e. A LOCKN signal is output from the LOCKN terminal, which will be described later, to the peripheral control board 4140 via the peripheral door relay terminal board 882 and the frame peripheral relay terminal board 868. This LOCKN signal is input to the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140 via a peripheral control input circuit (not shown) of the peripheral control board 4140.

As described above, the LOCKN signal output request data, which is serial data output from the serial I / O port for the touch panel drive board built in the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140, is a pachinko game. Peripheral control board during the period when the startup screen when the power of the machine 1 is turned on is displayed on the liquid crystal display device 1900 on the game board side, or during the period when the player is waiting for customers and the liquid crystal display device 1900 on the game board side is demonstrating. Whether or not there is a problem between the connection between the upper plate side liquid crystal transmitter IC 4160d provided in the 4140 and the upper plate side liquid crystal receiver ICSDIC0 provided in the touch panel drive board 450, that is, whether or not there is a problem in the connection between the transmitter and the receiver. For confirmation, it is transmitted as an operation confirmation request of the upper plate side liquid crystal display device 470. Although the LOCKN signal output request data in the present embodiment is differentiated into a positive signal and a negative signal in the differential circuit 4160e, the signal output from the precision side liquid crystal transmitter IC 4160d, that is, the above-mentioned Zain Electronics stock. The data format is completely different from that of the company's "V-by-One (registered trademark)" differential serial signal (serial data). Therefore, when the LOCKN signal output request data is received by the upper plate side liquid crystal receiver ICSDIC0, it is determined that the upper plate side liquid crystal receiver ICSDIC0 is not a signal output from the upper plate side liquid crystal transmitter IC4160d, which is abnormal. Assuming that it is data, a LOCKN signal will be output from the LOCKN terminal described later. In other words, in the present embodiment, the LOCKN signal is output from the LOCKN terminal described later by utilizing the function of the precision plate side liquid crystal receiver ICSDIC0 that outputs the LOCKN signal when it is determined that the received data is abnormal data. In order to forcibly output the LOCKN signal output request data having a structure different from the signal output from the upper plate side liquid crystal transmitter IC 4160d to the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140. By outputting from the built-in serial I / O port for the touch panel drive board, it is possible to confirm whether or not the device called the receiver ICSDIC0 for the liquid crystal on the upper plate side is operating normally. This makes it possible to check whether or not there is a problem with the connection between the transmitter and the receiver.

+ 3.3V created by the upper plate side liquid crystal module power supply circuit 450x is supplied to the VDD terminal, VDDO terminal, LVDS VDD terminal, PLL VDD terminal, and PDWN terminal of the upper plate side liquid crystal receiver ICSDIC0, respectively. The GND terminal, GNDO terminal, LVDSGND application sheet, PLLGND terminal, EDGE terminal, OE terminal, MODE0, and MODE1 terminal of the dish-side liquid crystal receiver ICSDIC0 are grounded to the ground, respectively.

The VDD terminal is a power supply terminal for a digital circuit, and a capacitor SDC0 is electrically connected between the terminal and the GND terminal which is the ground for the digital circuit, and a + 3.3V power supply supplied to the VDD terminal. High frequency noise is removed from the line.

The VDDO terminal is a power supply terminal for TTL (Transistor-Transistor Logical) output, and a capacitor SDC1 is electrically connected between the terminal and the GNDO terminal which is the ground for this TTL output, and is supplied to the VDDO terminal. High frequency noise is removed from the + 3.3V power supply line.

The LVDS VDD terminal is a power supply terminal for LVDS (Low Voltage Differential Signaling) input, and a capacitor SDC2 is electrically connected between the terminal and the LVDSGND terminal which is the ground for this LVDS input, and is supplied to the LVDS VDD terminal. High frequency noise is removed from the + 3.3V power supply line.

The PLL VDD terminal is a power supply terminal for a PLL (Phase Locked Loop) circuit, and a capacitor SDC3 is electrically connected between the terminal and the PLLGND terminal that serves as a ground for the PLL circuit, and is supplied to the PLL VDD terminal. High frequency noise is removed from the + 3.3V power line.

The PDWN terminal tells that when + 3.3V is supplied (applied), the logic becomes HI and operates normally, while the supply of +3.3 is stopped and the logic becomes LOW and powers down. It is a terminal to transmit. The PDWN terminal is supplied with +3.3 V via the resistor SDR1 and is electrically connected to the other end of the varistor SDZ0 whose one end is grounded to the ground. This varistor SDZ0 suppresses noise and overvoltage of the + 3.3 V electric line supplied via the resistor SDR1.

The EDGE terminal transmits various signals output from various output terminals (DE terminal, SYNC0 terminal to SYNC2 terminal, and D0 terminal to D17 terminal) based on the clock signal DCLK output from the CLKOUT terminal, which will be described later, at the rising edge. It is a terminal for designating either (the logic transitions from LOW to HI) or the falling edge (the logic transitions from HI to LOW), and is described above in the present embodiment. As described above, the falling edge is specified by grounding the EDGE terminal to the ground. By the way, if the EDGE terminal is connected to + 3.3V, the rising edge can be specified.

The OE terminal indicates whether or not to allow output of various output terminals (DE terminal, SYNC0 terminal to SYNC2 terminal, D0 terminal to D17 terminal, and CLKOUT terminal) described later. As described above, by grounding the OE terminal to the ground, the output is always possible. By the way, if the OE terminal is connected to + 3.3V, it will not be possible to output.

The MODE0 terminal and the MODE1 terminal are terminals for selecting an operation mode, and the operation mode can be selected by grounding both of them to the ground. The operation mode includes a normal mode and a shake hand mode. In the normal mode, three video signals (18-bit video signal), a red video signal, a green video signal, and a blue video signal, are based on the serial signals (serial data) input at the RXIN + terminal and the RXIN- terminal, respectively. In the normal operation mode in which the receiver ICSDIC0 for the upper plate side liquid crystal is restored to the parallel signal composed of three synchronization signals (3-bit synchronization signal), that is, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. be. In the shake hand mode, the connection between the upper plate side liquid crystal transmitter IC4160d provided on the peripheral control board 4140 and the upper plate side liquid crystal receiver ICSDIC0 provided on the touch panel drive board 450 is confirmed, that is, the connection between the transmitter and the receiver is confirmed. This mode outputs a LOCKN signal from the LOCKN terminal to request transmission of a predetermined data pattern (SYNC pattern) for (recovery). This shake hand mode is designed to switch automatically.

For example, based on the serial signals (serial data) input at the RXIN + terminal and the RXIN- terminal, three video signals (18-bit video signals), a red video signal, a green video signal, and a blue video signal, For some reason, the precision signal receiver ICSDIC0 restored to the parallel signal composed of three synchronization signals (3-bit synchronization signal), a horizontal synchronization signal, a vertical synchronization signal, and a clock signal, is abnormal. When it is difficult to draw on the upper plate side liquid crystal display device 470 with such data, the normal mode is automatically switched to the shake hand mode and the LOCKN signal is output from the LOCKN terminal. This LOCKN signal is input to the peripheral control board 4140 via the resistor SDR2 which is a damping resistor, the peripheral door relay terminal board 882, and the frame peripheral relay terminal board 868, and the peripheral control input circuit (not shown) of the peripheral control board 4140 is input. It is input to the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140 via the peripheral control board 4140. Peripheral control MPU4150a is a connection confirmation signal to the INIT terminal of the upper plate side liquid crystal transmitter IC 4160d in order to notify the upper plate side liquid crystal transmitter IC 4160d when a predetermined condition is satisfied based on the input LOCKN signal. Is output. When this connection confirmation signal is input to the INIT terminal, the upper plate side liquid crystal transmitter IC4160d connects between the upper plate side liquid crystal receiver ICSDIC0 provided on the touch panel drive board 450, that is, between the transmitter and the receiver. A predetermined data pattern (SYNC pattern) for recovery is provided in the touch panel drive board 450 via the peripheral control board 4140, the frame peripheral relay terminal board 868, and the peripheral door relay terminal board 882. Send to. By receiving such a predetermined data pattern (SYNC pattern) on the upper plate side liquid crystal receiver ICSDIC0, the connection between the transmitter and the receiver can be easily restored. A predetermined data pattern (SYNC pattern) is stored in advance in the upper plate side liquid crystal transmitter IC 4160d. The INIT terminal of the upper plate side liquid crystal transmitter IC 4160d provided on the peripheral control board 4140 and the LOCKN terminal of the upper plate side liquid crystal receiver ICSDIC0 provided on the touch panel drive board 450 are connected to the frame peripheral relay terminal plate 868 and the peripheral door relay. It may be directly connected electrically via the terminal board 882.

As described above, the LOCKN terminal is between the connection between the upper plate side liquid crystal transmitter IC4160d provided on the peripheral control board 4140 and the upper plate side liquid crystal receiver ICSDIC0 provided on the touch panel drive board 450, that is, between the transmitter and the receiver. It is a terminal that outputs a request for transmission of a predetermined data pattern (SYNC pattern) for confirming (recovering) the connection of. The LOCKN signal output from the LOCKN terminal is input to the peripheral control board 4140 via the resistor SDR2 which is the damping resistance of the touch panel drive board 450, the peripheral door relay terminal board 882, and the frame peripheral relay terminal board 868, and is used for peripheral control. It is input to the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140 via a peripheral control input circuit (not shown) of the substrate 4140.

The SYNC0 terminal to SYNC2 terminal output three synchronization signals, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal, which are restored based on the serial signals (serial data) input at the RXIN + terminal and the RXIN- terminal, respectively. It is a terminal. In this embodiment, since the restored horizontal synchronization signal, vertical synchronization signal, and clock signal are not used, the SYNC0 terminal to the SYNC2 terminal are unconnected terminals.

The DE terminal is a terminal that outputs a clock signal output from the CLKOUT terminal and a DE signal that conveys that the data output from the D0 terminals to the D17 terminals, which are data output terminals, is valid or invalid, which will be described later. The DE signal output from the DE terminal is input to the upper plate side liquid crystal display device 470 via the resistor SDR3 which is a damping resistor.

The CLKOUT terminal is a terminal that outputs the clock signal DCLK generated by the PLL circuit built in the upper plate side liquid crystal receiver ICSDIC0. The clock signal DCLK output from the CLKOUT terminal is input to the upper plate side liquid crystal display device 470 via the resistor SDR4 which is a damping resistor.

The D0 terminal to D17 terminal are three video signals (18), which are a red video signal, a green video signal, and a blue video signal restored based on the serial signals (serial data) input at the RXIN + terminal and the RXIN- terminal, respectively. It is a data output terminal that outputs a bit video signal). Blue video signals B0 to B5 (6 bits) are output in synchronization with the clock signal DCLK from the 6-bit data output terminals D0 terminal to D5 terminal, and each signal line of the blue video signals B0 to B5 is a damping resistor. The data is input to the upper plate side liquid crystal display device 470 via the ladder resistor SDRA0. The green video signals G0 to G5 (6 bits) are output in synchronization with the clock signal DCLK from the 6-bit data output terminals D6 terminal to D11 terminal, and each signal line of the green video signals G0 to G5 is a damping resistor. The data is input to the upper plate side liquid crystal display device 470 via the ladder resistor SDRA1. The red video signals R0 to R5 (6 bits) are output in synchronization with the clock signal DCLK from the 6-bit data output terminals D12 to D17, and each signal line of the red video signals R0 to R5 is a damping resistor. It is input to the upper plate side liquid crystal display device 470 via the ladder resistor SDRA2.

The grounds of the peripheral control board 4140, the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, the touch panel drive board 450, and the upper plate side liquid crystal display device 470 are electrically connected and become the same ground. ing.

[13-2. Touch panel circuit]
As shown in FIG. 36, the touch panel circuit 450W of the touch panel drive board 450 includes a touch panel controller in addition to the touch panel power supply circuit 450a that creates and supplies an analog voltage and a digital voltage from a predetermined voltage from the peripheral control board 4140. The oscillator 450c, the sensing IC 450d, and the amplifier circuit 450e are mainly configured around the IC 450b. The touch panel controller IC450b transmits the control command transmitted from the peripheral control board 4140 based on the control command from the peripheral control board 4140 via the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882. (Based on the received control command), the sensing IC 450d is driven and controlled to detect and control the contact state of the touch panel 480, and the position where the finger is touching the touch panel 480 (contact position data) is determined by the peripheral door relay terminal board. It transmits to the peripheral control board 4140 via the 882 and the frame peripheral relay terminal plate 868, and shifts to the power saving mode. The oscillator 450c outputs a reference clock signal to the touch panel controller IC450b. The sensing IC 450d is driven and controlled by the touch panel controller IC 450b, senses the contact state of the touch panel 480, and outputs the value of the capacitance of the touch panel 480 as an analog signal. The amplifier circuit 450e amplifies the analog signal from the sensing IC 450d and outputs it to the touch panel controller IC 450b.

The touch panel controller IC 450b is configured around the controller 450ba, and is an analog-to-digital conversion circuit (hereinafter, "ADC") that converts the contact state of the touch panel 480 sensed by the sensing IC 450d input via the amplifier circuit 450e from an analog signal to a digital signal. () 450bb and various programs (for example, when the power is turned on (including not only when the power is turned on but also when the power is restored due to a power failure or momentary power failure. The same shall apply hereinafter). Power-on program for power-on processing, detection control program for detecting the contact state of the touch panel 480, power-saving mode transition program for shifting to power-saving mode, and activation after canceling power-saving mode The contact positions (X coordinate, Y coordinate) at a maximum of two points among the contact states of the touch panel 480 are stored based on the ROM 450 bc in which the start program for performing the operation, etc.) is stored in advance and the digital signal converted by the ADC 450 db. Based on the two-point contact position storage register 450bd, the phase synchronization circuit (so-called "PLL circuit") 450be that creates a control clock signal from the reference clock signal from the oscillator 450c, and the control clock signal from the PLL circuit 450be. A synchronization signal output circuit 450bf that outputs a synchronization signal for synchronizing the touch panel controller IC450b and the sensing IC450d, a sensing IC serial interface 450bg that outputs serial data for indicating the sensing position of the touch panel 480, and peripherals. Each serialized seed command from the control board 4140 is received via the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882 and transmitted to the controller 450ba, while being stored in the two-point contact position storage register 450bd. Peripheral control board serial that serializes the contact position data that is the existing contact position (up to two contact positions) and transmits it to the peripheral control board 4140 via the peripheral door relay terminal plate 882 and the frame peripheral relay terminal plate 868. It mainly consists of an interface 450bh.

The sensing IC 450d has a serial interface 450da that receives serial data for instructing the sensing position of the touch panel 480 transmitted from the serial interface 450bg for the sensing IC of the touch panel controller IC 450b, and a touch panel 480 that receives the serial data received by the serial interface 450da. By inputting the decoder 450db that restores to the sensing position data that indicates the sensing position of the touch panel and the sensing position data restored by the decoder 450db, the electrical connection to the sensing position in the entire area of the touch panel 480 is opened and closed for sensing. It was restored by an analog multiplexer 450dc that outputs the value of the capacitance of the touch panel 480 at the position as an analog signal, a synchronization signal input circuit 450de that inputs a synchronization signal from the synchronization signal output circuit 450bf of the touch panel controller IC450b, and a decoder 450db. A sensing position data is input, a synchronization signal is input to the synchronization signal input circuit 450de, and a sensing unit 450df that senses an analog signal from the analog multiplexer 450dc and outputs it to the amplification circuit 450e is mainly configured.

Here, the operation of the touch panel controller IC450b and the sensing IC450d will be briefly described. For example, the controller 450ba of the touch panel controller IC450b starts detection control for starting the detection control of the contact state of the touch panel 480 from the peripheral control board 4140. When the command is transmitted via the serial interface 450b for the peripheral control board, the detection control program for detecting the contact state of the touch panel 480 is read from the ROM 450bc (or when the power is turned on to the RAM (not shown) provided in the touch panel controller IC450b). In, when various programs stored in advance in the ROM 450bc are copied (read from this RAM), the read detection control program is started. When this detection control program is started, the controller 450ba transmits serial data for instructing the sensing position of the touch panel 480 from the serial interface 450bg for the sensing IC to the sensing IC 450d.

The sensing IC 450d receives the serial data at the serial interface 450da, outputs the serial data to the decoder 450db, and restores the sensing position data at the decoder 450db. The analog multiplexer 450dc opens and closes an electrical connection to the sensing position in the entire area of the touch panel 480 according to the sensing position data from the decoder 450db, and uses the value of the capacitance of the touch panel 480 at the sensing position as an analog signal in the sensing unit 450df. Output to. The controller 450ba of the touch panel controller IC450b outputs a synchronization signal from the synchronization signal output circuit 450bf to the sensing IC 450d, and when this synchronization signal is input to the synchronization signal input circuit 450de of the sensing IC 450d and transmitted to the sensing unit 450df, this is a trigger. In the sensing unit 450df, the analog signal from the analog multiplexer 450dc opens and closes the electrical connection to the sensing position in the entire area of the touch panel 480 according to the sensing position data from the decoder 450db, and the electrostatic capacity of the touch panel 480 at the sensing position. It is determined that the value is, and the value is output to the amplification circuit 450e. The analog signal amplified via the amplifier circuit 450e is converted into a digital signal by the ADC 450bb of the touch panel controller IC450b and input to the controller 450ba.

The controller 450ba repeatedly controls the serial interface 450bg for the sensing IC to transmit the serial data indicating the sensing position of the touch panel 480 to the sensing IC 450d and the synchronization signal output circuit 450bf to output the synchronization signal to the sensing IC 450d. The entire area of the touch panel 480 is sensed to determine the area of the contact surface among the entire areas of the touch panel 480, and the position where the finger is touching the touch panel is specified.

At this time, when the controller 450ba determines that the touch panel 480 is not touched by a finger, the controller 450ba stores the non-contact information as the contact position data in the two-point contact position storage register 450b, while as shown in FIG. 37 (a), for example. When it is determined that the touch panel 480 is touching only the index finger of the left hand (that is, touching one point), the contact position of one point is as contact position data in the two-point contact position storage register 450bd as shown in FIG. 37 (b). While storing P0 (x0, y0), as shown in FIG. 37 (c), for example, when it is determined that the index finger and the middle finger of the left hand are touching (that is, touching two points) on the touch panel 480, 2 As the contact position data, P0 (x0, y0) and P1 (x1, y1), which are the contact positions of the two points, are stored in the point contact position storage register 450b, respectively, as shown in FIG. 37 (d). The two-point contact position storage register 450b is updated every time the detection control program is started.

This detection control program relays the detection control start command from the peripheral control board 4140 around the frame in the touch panel processing of the peripheral control unit steady processing that is repeatedly performed every 16 ms in the peripheral control unit power-on processing of the peripheral control board 4140, which will be described later. When received via the terminal board 868 and the peripheral door relay terminal board 882, the power supply of the pachinko game machine 1 is cut off, or the power saving mode transition command for shifting to the power mode is not received from the peripheral control board 4140. In this case, it is repeatedly executed, and the sensing of the entire area of the touch panel 480 is completed by the elapse of 16 ms. In the touch panel processing of the peripheral control unit steady processing, the contact position data request command for requesting the position (contact position data) in which the finger is touching the touch panel 480 is issued from the peripheral control board 4140 to the frame peripheral relay terminal plate 868 and the peripheral door. Upon receiving via the relay terminal board 882, that is, the controller 450ba issues a contact position data request command for requesting the position (contact position data) in which the finger is touching the touch panel 480 from the peripheral control board 4140 serially for the peripheral control board. When transmitted via the interface 450b, the contact position data stored in the two-point contact position storage register 450bd is serialized and transmitted from the peripheral control board serial interface 450b to the peripheral control board 4140.

When the controller 450ba determines that the touch panel 480 is touching three or more points, the contact surface determined as the first point and the contact surface determined as the second point in the sensing order by a predetermined algorithm. And, while the contact surface determined as the third point, the contact surface determined as the fourth point, ..., The contact surface determined after the third point is invalidated, and the two-point contact position The contact positions (P0 (x0, y0) and P1 (x1, y1)) of the first point and the second point are stored in the storage register 450b as contact position data, respectively.

Specifically, as shown in FIG. 38 (e), when the touch panel 480 is touched in the order of the index finger, the middle finger, and the ring finger of the left hand, the controller 450ba attaches the index finger, the middle finger, and the ring finger of the left hand to the touch panel 480. When it is determined that is touching (that is, touching three points), as shown in FIG. 38 (f), the position of the contact surface determined as the first point in the sensing order (that is, touching three points) is determined by a predetermined algorithm. That is, the contact position P0 (x0, y0) of the index finger of the left hand and the position of the contact surface determined as the second point (that is, the contact position P1 (x1, y2) of the middle finger of the left hand) are valid (that is,). The contact position P0 (x0, y0) of the index finger of the left hand and the contact position P1 (x1, y2) of the middle finger of the left hand are each enabled points. ), The position of the contact surface determined as the third point (that is, the contact position P2 (x2, y2) of the ring finger of the left hand) is invalid (that is, the contact position P2 (x2, y2) of the ring finger of the left hand is invalid. The point to be converted (the point to be discarded)), and the contact positions of the first and second points (P0 (x0, y0) and P1 (x1,) are stored in the two-point contact position storage register 450db as contact position data. It stores y1))) respectively.

In this way, even if it is determined that the controller 450ba touches the touch panel 480 at three or more points, the contact position detected first and the contact position detected second are detected in the two-point contact position storage register 450b of the touch panel controller IC450b. Since only two contact positions, that is, the contact position, can be stored, three or more contact positions can be invalidated. As a result, the number of fingers required by the player to operate the touch panel 480 can be limited to a maximum of two, so that the operation of the touch panel 480 does not impose a burden on the player.

Here, to briefly explain the effect of using two fingers, when a big hit game state occurs, the big hit effect (for example, of a round) is displayed in the display area of the liquid crystal display device 1900 on the game board side of the game board 4. (Introduction of numbers and various characters, etc.) is progressing, while in the display area of the upper plate side liquid crystal display device 470 attached to the right side of the plate unit 300, a treasure hunting effect is progressing to search for treasure during a big hit. It is supposed to be done. In this treasure hunting production, the treasure is sealed by a bivalve, and the touch panel 480 allows the player to use two fingers (for example, the index finger and middle finger of the left hand) to pry open the upper shell and the lower shell. If you can move while touching and pry open the bivalve to acquire the treasure, you can be promoted to variable probability, but if you can not pry open the bivalve and you can not acquire the treasure, the normal probability remains. .. In this way, it is possible to give a change due to contact with the touch panel 480 to the image displayed in the display area of the upper plate side liquid crystal display device 470 based on the contact state of the finger.

The touch panel provided so as to cover the display area of the display device in a mobile terminal such as a mobile phone can change the posture of the mobile terminal according to the finger operating the touch panel (that is, to make it easy to operate). Therefore, for example, when operating the touch panel using two fingers, it is possible to prevent the other fingers from touching the touch panel. On the other hand, since the touch panel 480 in the present embodiment is provided so as to cover the display area of the upper plate side liquid crystal display device 470 as described above, the touch panel 480 is fixed. Therefore, the posture of the touch panel 480 cannot be changed according to the finger operated by the player (that is, so as to be easy to operate). As a result, for example, even if the player operates the touch panel 480 using two fingers, the touch panel 480 may be touched without being noticed by the other fingers. There is also a method of creating a program that exclusively detects that such another finger is touching the touch panel 480, but the algorithm for distinguishing between the finger required for operation and the finger not required for operation becomes complicated, and the algorithm becomes complicated. There is a problem that the program becomes huge.

[14. Various commands related to transmission and reception of the main control board]
Next, various commands transmitted from the main control board 4100 to the payout control board 4110 and various commands transmitted from the main control board 4100 to the peripheral control board 4140 will be described with reference to FIGS. 39 to 42. FIG. 39 is a table showing an example of various commands transmitted from the main control board to the payout control board, and FIG. 40 is a table showing an example of various commands transmitted from the main control board to the peripheral control board. Is a table showing the continuation of various commands transmitted from the main control board to the peripheral control board of FIG. 40, and FIG. 42 is a table showing an example of various commands received from the payout control board received by the main control board. First, the prize ball command, which is a command related to payout transmitted from the main control board to the payout control board, is described, then various commands transmitted from the main control board to the peripheral control board are described, and the main control board receives the command. Various commands from the payout control board will be described.

[14-1. Various commands sent from the main control board to the payout control board]
The main control MPU 4100a of the main control board 4100 has detection signals from various winning switches such as the general winning port switches 3020 and 3020, the upper starting port switch 3022, the lower starting port switch 2109, and the count switch 2110 shown in FIG. When input, a prize ball command for paying out a predetermined number of game balls as a prize ball is transmitted to the payout control board based on these detection signals. This prize ball command is a command having a storage capacity of 1 byte (8 bits). In the present embodiment, the pachinko gaming machine 1 and the CR unit 6 (communication with the pachinko gaming machine 1 and driving the payout motor 744 of the pachinko gaming machine 1 (prize ball device 740) to drive the payout motor 744, which is a storage tray When the lower plate 302 is electrically connected to a device for paying out game balls as rental balls (such a pachinko gaming machine is referred to as a "CR machine"), as shown in FIG. The prize ball commands transmitted from the main control board 4100 to the payout control board 4110 include commands 10H to 1EH (“H” represents a hexadecimal number), and in command 10H, one prize ball is provided. Designated, command 11H specifies two prize balls, ..., Command 1EH specifies 15 prize balls. The payout control board 4110 controls the payout motor 744 to pay out the game balls by the designated number of prize balls.

In addition, a pachinko game machine 1 and a ball lending machine (a device that directly pays out game balls as lending balls to the upper plate 301 and the lower plate 302, which are storage plates) are installed adjacent to the game hall (hall), and pachinko machines are installed. When the gaming machine 1 and the ball lending machine are electrically connected (such a pachinko gaming machine is referred to as a "general machine"), it is paid out from the main control board 4100 as shown in FIG. 39 (b). Commands 20H to 2EH are prepared for the prize ball command to be transmitted to the control board 4110. One prize ball is specified by the command 20H, two prize balls are specified by the command 21H, and so on. In 2EH, 15 prize balls are designated. The payout control board 4110 controls the payout motor 744 to pay out the game balls by the designated number of prize balls.

As shown in FIG. 39 (c), a command 30H is prepared as a common command for the CR machine and the general machine, and a self-check is specified in this command 30H. After the command is transmitted, the transmitting side transmits the command 30H and checks whether or not the ACK signal is input when the ACK signal to be output as confirmation of receipt of the command is not input from the receiving side for a predetermined period. Check the connection status. In the case of the CR machine in the present embodiment, the payout control board 4110 confirms the connection state with the CR unit 6.

[14-2. Various commands sent from the main control board to the peripheral control board]
Next, various commands transmitted from the main control board 4100 to the peripheral control board 4140 will be described. The main control MPU 4100a of the main control board 4100 transmits various commands to the peripheral control board 4140 based on the progress of the game. These various commands are commands having a storage capacity of 2 bytes (16 bits), and as shown in FIGS. 40 and 41, a status indicating the type of the command having a storage capacity of 1 byte (8 bits) and a status indicating the type of the command have a storage capacity of 1 byte (8 bits). It is composed of a mode showing a variation of an effect having a storage capacity of 1 byte (8 bits).

As shown in FIGS. 40 and 41, the various commands are related to the special figure 1 synchronization effect, the special figure 2 synchronization effect, the jackpot, the power on, the normal electric role effect, the notification display, and the state. It is divided into display and others.

[14-2-1. Special figure 1 Synchronized production related]
The special drawing 1 tuning effect-related is based on the detection signal from the upper start port switch 3022 shown in FIG. 12, and the classification is divided into the function display board 1191 shown in FIG. 12 as shown in FIG. The above special symbol display 1185 is composed of commands named special symbol 1 synchronization effect start, special symbol 1 designation, special diagram 1 synchronization effect end, and change state designation. These various commands are assigned "A * H" as the status and "** H" as the mode ("H" represents a hexadecimal number) ("*" is a specific hexadecimal number. This is determined in advance according to the specifications of the pachinko gaming machine 1).

The special figure 1 synchronization effect start command instructs the start of the special figure synchronization effect with the effect pattern specified in the mode, and the special symbol 1 designation command specifies the loss, the specific jackpot, and the non-specific jackpot. The special figure 1 synchronization effect end command instructs the end of the special figure 1 synchronization effect, and the variable time state designation command indicates the probability and the time saving state. The probabilities and time-saving states include a low-probability time-saving state that indicates a low-probability state and a time-saving state, a high-probability time-saving state that indicates a high-probability state and a time-saving state, and a low-probability state. It is composed of a low-probability non-time-saving state that indicates that it is a state and not a time-saving state, and a high-probability non-time-saving state that indicates that it is a high-probability state and not a time-saving state. Low probability non-time saving state is set). Here, the high probability state is a state in which the probability of a big hit is set higher than that in the low probability state (normal game state), and the time saving state is, for example, the normal symbol display 1189 shown in FIG. By shortening the time for variable display of the symbol compared to the non-time saving state (normal game state) and stopping and displaying the light emission pattern corresponding to the normal lottery result, the result of the normal lottery by the normal lottery described later at a predetermined time can be obtained. The number of stop display times is increased as compared with the non-time saving state, and the period for opening and closing the pair of movable pieces 2106 shown in FIG. 8 is lengthened as compared with the non-time saving state (normal gaming state). By increasing the acceptance rate (entry rate) of game balls to the lower starting port 2102 shown in (1), it is possible to obtain a lottery opportunity for special symbols without reducing the number of balls held (in other words, compared to the non-time saving state). In addition to increasing the number of decisions as to whether or not to open / close the pair of movable pieces 2106, when opening / closing the pair of movable pieces 2106, the period of the opening / closing operation of the pair of movable pieces 2106 is lengthened to start the lower part. It is a state in which the acceptance rate (entrance rate) of the game ball to the mouth 2102 is increased).

As the transmission timing of these various commands, the special symbol 1 synchronization effect start command is transmitted at the start of the special symbol 1 fluctuation, and the special symbol 1 designation command is transmitted immediately after the start of the special diagram 1 synchronization effect. The effect end command is transmitted when the special symbol 1 variation time elapses (when the special symbol 1 is confirmed), and the variation state specification command is transmitted immediately after the special symbol winning information is specified. It should be noted that these various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control side timer interrupt process described later.

[14-2-2. Special Figure 2 Synchronized production related]
The special drawing 2 tuning effect-related is based on the detection signal from the lower start port switch 2109 shown in FIG. 12, and the classification is divided into the function display board 1191 shown in FIG. 12 as shown in FIG. It consists of commands related to the lower special symbol display 1186, which are named special symbol 2 synchronization effect start, special symbol 2 designation, and special diagram 2 synchronization effect end. These various commands are assigned "B * H" as the status and "** H" as the mode ("H" represents a hexadecimal number) ("*" is a specific hexadecimal number. This is determined in advance by the specifications of the pachinko gaming machine 1).

The special figure 2 synchronization effect start command instructs the start of the special figure synchronization effect with the effect pattern specified in the mode, and the special symbol 2 designation command specifies the loss, the specific jackpot, and the non-specific jackpot. , The end of the special figure 2 synchronization effect indicates the end of the special figure 2 synchronization effect.

As the transmission timing of these various commands, the special symbol 2 synchronization effect start command is transmitted at the start of the special symbol 2 fluctuation, and the special symbol 2 designation command is transmitted immediately after the start of the special diagram 2 synchronization effect. The effect end command is transmitted when the special symbol 2 variation time elapses (when the special symbol 2 is confirmed). It should be noted that these various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control side timer interrupt process.

[14-2-3. Big hit related]
As shown in FIG. 40, the categories related to jackpots include jackpot opening, jackpot 1 open Nth display, jackpot 1 closed display, jackpot 1 count display, jackpot ending, jackpot symbol display, and jackpot opening. , Small hit open display, small hit count display, and small hit ending commands. These various commands are assigned "C * H" as the status and "** H" as the mode ("H" represents a hexadecimal number) ("*" is a specific hexadecimal number. This is determined in advance by the specifications of the pachinko gaming machine 1).

The jackpot opening command indicates the start of the jackpot opening, and the Nth display command for opening the jackpot 1 is the start during the opening of the jackpot 1 in the 1st to 16th rounds (the attacker unit 2100 shown in FIG. 8). The opening of the Nth round of the large winning opening 2103 or the opening start) is instructed, and the large winning opening 1 closing display command starts during the closing of the large winning opening 1 between rounds (the large winning opening of the attacker unit 2100). (During closing or starting closing) between 2103 rounds is instructed, and the large winning opening 1 count display command counts the number of game balls with a count of 0 to 10 (count switch shown in FIG. 12). The number of game balls that have entered the jackpot 2103 detected by 2110) is transmitted, the jackpot ending command indicates the start of the jackpot ending, and the jackpot symbol display command is the jackpot symbol information. It instructs the display.

Further, the small hit opening command indicates the start of the small hit opening, and the small hit open display command starts during the small hit opening (at the time of the small hit, the large winning opening 2103 of the attacker unit 2100 is open or open. The small hit count display command indicates (start), and the small hit count display command is used when the small hit medium / large winning opening winning effect (during the small hit, the game ball that has entered the large winning opening 2103 is detected by the count switch 2110). The production) is instructed, and the small hit ending command is instructed to start the small hit ending.

As the transmission timing of these various commands, the jackpot opening command is transmitted at the start of the jackpot opening, and the Nth display command for opening the jackpot 1 is when the jackpot 1 is opened in the 1st to 16th rounds (large attacker unit 2100). It is sent when the Nth round of the winning opening 2103 is opened), and the big winning opening 1 closing display command is sent when the big winning opening 1 is closed (when the large winning opening 2103 of the attacker unit 2100 starts closing), and the big winning opening 1 is closed. The mouth 1 count display command is a count switch when the large winning opening 1 is opened and when the count changes to the large winning opening 1 (when the large winning opening 2103 of the attacker unit 2100 is opened, and the game ball that has entered the large winning opening 2103 is a count switch. (When detected by 2110), the jackpot ending command is transmitted at the start of the jackpot ending, and the jackpot symbol display command is transmitted when the jackpot symbol is opened (when the jackpot 2103 of the attacker unit 2100 is opened). NS.

Further, the small hit opening command is transmitted at the start of the small hit opening, and the small hit open display command is transmitted at the time of opening the small hit (when the large winning opening 2103 of the attacker unit 2100 is opened at the time of the small hit). The hit count display command is transmitted at the time of winning the small hit medium / large winning opening (when the game ball entered in the large winning opening 2103 is detected by the count switch 2110 during the small hit), and the small hit ending command is It is sent at the start of the small hit ending. It should be noted that these various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control side timer interrupt process.

[14-2-4. Power on]
As shown in FIG. 40, the power-on category consists of commands named power-on state, power-on main control return destination, and power-on main prize ball number information output determination counter notification. .. These various commands are assigned "D * H" as the status and "** H" as the mode ("H" represents a hexadecimal number) ("*" is a specific hexadecimal number. This is determined in advance according to the specifications of the pachinko gaming machine 1).

The power-on state command indicates the start of the RAM clear effect and the game state. The power-on state command is used for the payout control board 4110 shown in FIG. 13 when the power is turned on (including not only when the power is turned on but also when the power is restored due to a power failure or a momentary power failure). Includes information instructing that when the operation switch 860a is operated to clear the RAM, and when the power is turned on (in addition to when the power is turned on, when the power is restored due to a power failure or momentary power failure. ) With information indicating which of the above-mentioned low-probability time-saving state, high-probability time-saving state, low-probability non-time-saving state, and high-probability non-time-saving state (probability and time-saving state) is to be restored. , Information indicating the model code of the pachinko machine, and. When creating so-called max type, middle type, and Amadeji type, for example, the model code of this pachinko game machine is for the copyright of which work, and what kind of game specifications (for example, probability fluctuations). When it occurs, in addition to the game specification that the state is continued until the next big hit game state occurs, the game that the probability fluctuation occurs when the number of fluctuations of the special symbol is limited (for example, 30 times or 70 times). It specifies whether it is a specification (so-called ST machine, etc.). In other words, the information on the model code of the pachinko gaming machine specifies the series code for identifying which type is the max type, middle type, or Amadeji type that indicates the model type, and the copyright of the work. In addition to the copyright code for the game specifications and the game specifications (for example, when a probability change occurs, the state is continued until the next big hit game state occurs, the probability is that the number of changes of the special symbol is limited. It is mainly composed of a game specification code for specifying a game specification (ST machine, etc.) in which fluctuations occur.

The main control return destination command at power-on indicates the return destination of the main control board 4100 itself. The main control return destination command at power-on is mainly composed of information indicating the drive state of the start port solenoid 2105 shown in FIG. 12 and information indicating the drive state of the attacker solenoid 2108 shown in FIG. ing.

When the power is turned on, the counter notification command for determining the output of the main prize ball number information is such that the upper starting port 2101, the lower starting port 2102, the general winning opening 2104, 2201, the large winning opening 2103, etc. The value of the main prize ball number information output determination counter that counts the number of game balls to be paid out as prize balls based on the game balls entered in the various winning openings of the main control built-in RAM It is stored (backed up) as one of the game backup information. When the power is turned on The counter notification command for determining the main prize ball number information output is mainly used when the power is turned on (including when the power is turned on and when the power is restored due to a power failure or momentary power failure). It is created by reading the value of the main prize ball number information output determination counter from the game backup information stored (backed up) in the control built-in RAM. When the operation switch 860a of the payout control board 4110 shown in FIG. 13 is operated to clear the RAM, the game backup information stored (backed up) in the main control built-in RAM is initialized to be the main game backup information. When the value of the prize ball number information output determination counter is set to the initial value 0 (zero) (that is, when the operation switch 860a of the payout control board 4110 shown in FIG. 13 is operated to clear the RAM. Is forced to set the number of game balls to be paid out as prize balls to zero).

When the main control board is powered on (in addition to when the power is turned on), the power-on status command, the main control return destination command when the power is turned on, and the counter notification command for determining the main prize ball number information output when the power is turned on are transmitted. It is transmitted at the time of power recovery when power is restored due to a power failure or momentary power failure. Specifically, when the power of the pachinko game machine 1 is turned on, or when the pachinko game machine 1 recovers from a power failure or momentary power failure, the main control side power on time process described later is executed, and the peripheral control board of step S120 in the main control side timer interrupt process In the command transmission process, the power-on state command, the power-on main control return destination command, and the power-on main prize ball count information output determination counter notification command are transmitted.

[14-2-5. Fuzu-tuned production-related]
The normal diagram tuning effect-related is based on the detection signal from the gate switch 2352 shown in FIG. 12, and in the division, as shown in FIG. 40, the normal symbol display of the function display board 1191 shown in FIG. It is composed of commands related to the device 1189, which are named as the start of the normal figure synchronization effect, the designation of the normal symbol, the end of the normal figure synchronization effect, and the specification of the state at the time of fluctuation. These various commands are assigned "E * H" as the status and "** H" as the mode ("H" represents a hexadecimal number) ("*" is a specific hexadecimal number. This is determined in advance according to the specifications of the pachinko gaming machine 1).

The normal figure synchronization effect start command is for instructing the start of the normal figure synchronization effect with the effect pattern specified in the mode, and the normal symbol designation command is for designating the miss, the specific jackpot, and the non-specific jackpot. The figure synchronization effect end command instructs the end of the normal figure synchronization effect, and the variable time state designation command indicates the probability and the time saving state. As described above, the probability and time saving states include a low probability time saving state indicating that the time saving state is a low probability state and a high probability time saving state indicating that the time saving state is a high probability state. It is composed of a state, a low-probability non-time-saving state that indicates that it is a low-probability state and not a time-saving state, and a high-probability non-time-saving state that indicates that it is a high-probability state and not a time-saving state (usually). As the game state, a low probability non-time saving state is set).

As the transmission timing of these various commands, the normal symbol synchronization effect start command is transmitted at the start of the normal symbol 1 fluctuation, the normal symbol designation command is transmitted immediately after the start of the normal symbol synchronization effect, and the normal symbol synchronization effect end command is transmitted. , Ordinary symbol is transmitted when the fluctuation time elapses (when the normal symbol is confirmed), and the change state specification command is transmitted immediately after the normal symbol winning information is specified. It should be noted that these various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control side timer interrupt process.

[14-2-6. Ordinary electric role production related]
The normal electric service effect is related to the pair of movable pieces 2106 shown in FIG. 8 which are opened and closed by the drive of the start port solenoid 2105 shown in FIG. It consists of commands named opening per figure, open display of solenoid, and ending per figure. These various commands are assigned "F * H" as the status and "** H" as the mode ("H" represents a hexadecimal number) ("*" is a specific hexadecimal number. This is determined in advance by the specifications of the pachinko gaming machine 1).

The opening command per normal figure indicates the start of the opening per normal figure, and the open normal power display command starts while the normal power is open (a pair of movable pieces 2106 expands in the left-right direction by driving the starting port solenoid 2105). The ending command per normal figure indicates the start of the ending per normal figure.

As the transmission timing of these various commands, the opening command per normal figure is transmitted at the start of the opening per normal figure, and the open power display command is sent when the normal power is open (a pair of movable pieces 2106 are driven by the start port solenoid 2105). It is transmitted at the time of expanding in the left-right direction), and the ending command per normal figure is transmitted at the start of the ending per normal figure. It should be noted that these various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control side timer interrupt process.

[14-2-7. Notification display]
As shown in FIG. 41, the notification display category is composed of commands named winning abnormality display, connection abnormality display, disconnection / short circuit abnormality display, magnetic detection switch abnormality display, door opening, and door closing. These various commands are assigned a status of "6 * H" and a mode of "** H"("H" represents a hexadecimal number) ("*" is a specific hexadecimal number). This is determined in advance by the specifications of the pachinko gaming machine 1).

The winning abnormality display command is used when a game ball enters the big winning opening 2103 of the attacker unit 2100 even though it is not a big hit (even though it is not a big hit) other than during the big hit (condition device is operating). When the count switch 2110 detects it), the start of the winning abnormality notification is instructed, and the connection abnormality display command is, for example, an electrical connection in the path between the main control board 4100 and the payout control board 4110. When there is an abnormality, the connection abnormality notification is instructed to start, and the disconnection / short-circuit abnormality display command includes, for example, the main control board 4100, the upper start port switch 3022, the lower start port switch 2109, the count switch 2110, and the like. Instructs the start of the disconnection / short-circuit abnormality display when the electrical connection is broken / short-circuited, and the magnetic detection switch abnormality display command causes an abnormality in the magnetic detection switch 3024 shown in FIG. In this case, the magnetic detection switch indicates the start of abnormality notification.

Further, in the door opening command, the door frame 5 is directed to the main body frame 3 based on the detection signal (opening signal) from the door frame opening switch 618 input via the payout control board 4110 shown in FIG. When the door is in the opened state, the door opening notification is instructed, and the door frame closing command closes the door frame 5 with respect to the main body frame 3 based on the detection signal from the door frame opening switch 618. This is to instruct the end of the door opening notification when the state is set. On the other hand, in the main body frame opening command, the main body frame 3 is directed to the outer frame 2 based on the detection signal (opening signal) from the main body frame opening switch 619 input via the payout control board 4110 shown in FIG. In the open state, the main body frame opening notification is instructed, and the main body frame closing command is issued to the main body frame 3 with respect to the outer frame 2 based on the detection signal from the main body frame opening switch 619. When it is in the closed state, it instructs the end of the main body frame opening notification.

As the transmission timing of these various commands, the winning abnormality display command is transmitted when a prize is won in the big winning opening other than during the big hit (condition device is operating), and the connection abnormality display command is sent from the main control board 4100 to the payout control board 4110. It is transmitted when there is no ACK reply (ACK signal) from the payout control board 4110 when the command is transmitted to, and the disconnection / short circuit abnormality display command is among the upper start port switch 3022, the lower start port switch 2109, the count switch 2110, etc. , Which is transmitted when the wire is broken or short-circuited, and the magnetic detection switch abnormality display command is transmitted when an abnormality of the magnetic detection switch 3024 is detected. Further, the door opening command is transmitted when the door opening is detected (when the door frame 5 is in the open state with respect to the main body frame 3 based on the detection signal from the door frame opening switch 618), and the door is opened. The frame closing command is transmitted when the door closing is detected (when the door frame 5 is closed with respect to the main body frame 3 based on the detection signal from the door frame opening switch 618). The main body frame open command is transmitted when the main body frame open is detected (when the main body frame 3 is open to the outer frame 2 based on the detection signal from the main body frame open switch 619), and the main body is sent. The frame closing command is transmitted when the main body frame closing is detected (when the main body frame 3 is closed with respect to the outer frame 2 based on the detection signal from the main body frame opening switch 619). It should be noted that these various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control side timer interrupt process.

[14-2-8. Status display]
As shown in FIG. 41, the status display division consists of commands named frame status 1 command (corresponding to an error occurrence command), error canceling navigation command (corresponding to an error canceling command), and frame status 2 command. There is. These various commands are assigned a status of "7 * H" and a mode of "** H"("H" represents a hexadecimal number) ("*" is a specific hexadecimal number). This is determined in advance by the specifications of the pachinko gaming machine 1).

The frame state 1 command, the error release navigation command, and the frame state 2 command are commands having a storage capacity of 1 byte (8 bits) transmitted from the payout control board 4110, respectively, and detailed description thereof will be described later. .. When the main control MPU 4100a of the main control board 4100 receives the frame state 1 command, the error release navigation command, and the frame state 2 command from the payout control board 4110, it outputs "7 * H" as shown in FIG. 41. Along with setting it as a status, the received command is set as it is as a mode. That is, when the main control MPU4100a receives the frame state 1 command, the error release navigation command, and the frame state 2 command from the payout control board 4110, the main control MPU4100a adds "7 * H" which is additional information to these received commands. Formats the command into a command having a storage capacity of 2 bytes (16 bits).

The formatted frame state 1 command is sent when the power is restored, when the frame state changes, and when the error release navigation is performed, the error release navigation command is sent when the error release navigation is performed, and the frame state 2 command is sent when the power is restored. , And when the frame state changes. The shaped frame state 1 command, error release navigation command, and frame state 2 command are actually transmitted in the peripheral control board command transmission process in step S120 in the main control side timer interrupt process.

[14-2-9. Test related]
As shown in FIG. 41, the test-related division is composed of various commands named test. This test command is assigned a status of "8 * H" and a mode of "** H"("H" represents a hexadecimal number) ("*" is a specific hexadecimal number). Is determined in advance according to the specifications of the pachinko gaming machine 1).

The test command instructs various inspections of the peripheral control board 4140 (for example, the peripheral control unit 4150, the liquid crystal and sound control unit 4160, the lamp drive board 4170, the motor drive board 4180, and the frame shown in FIG. 15). It inspects various boards such as the decorative drive amplifier board 194).

The test command is transmitted at a time other than RAM clear and RAM clear when the main control board is powered on. Specifically, when the power of the pachinko gaming machine 1 is turned on, when the power is restored from a power failure or a momentary power failure, and when the operation switch 860a of the payout control board 4110 is operated, the main control side power-on processing described later Is executed, and a test command is transmitted in the peripheral control board command transmission process in step S120 in the main control side timer interrupt process.

[14-2-10. others]
In other categories, as shown in FIG. 41, start opening prize, fluctuation shortening operation end designation, high probability end designation, special symbol 1 memory, special symbol 2 memory, normal symbol memory, special symbol 1 memory look-ahead effect, special It consists of a command named symbol 2 memory look-ahead effect and main prize ball number information output. These various commands are assigned a status of "9 * H" and a mode of "** H"("H" represents a hexadecimal number) ("*" is a specific hexadecimal number). This is determined in advance by the specifications of the pachinko gaming machine 1).

The start opening winning command instructs the start of the starting opening winning effect, and starts the effect when the game ball enters the upper starting port 2101 based on the detection signal from the upper starting port switch 3022, and lower. Based on the detection signal from the start port switch 2109, it is instructed to start the effect when the game ball enters the lower start port 2102, and the variation shortening operation end specification command is from the variation shortening operation state. The fluctuation shortening inactive state is instructed to shift to the state, the high-probability end designation command is instructed to shift from the high-probability state to the low-probability state, and the special symbol 1 storage command is a special symbol. 1 Hold 0 to 4 (The number of balls that have not yet been used for the variable display of the special symbol on the upper special symbol display 1185 of the function display board 1191 when the game ball enters the upper starting port 2101 shown in FIG. 8 ( The number of holdings)) is transmitted, and the special symbol 2 storage command is a special symbol 2 holding 0 to 4 (the lower special of the function display board 1191 when the game ball enters the lower starting port 2102 shown in FIG. 8). The symbol display 1186 conveys the number of balls (holding number) that have not yet been used for the variable display of the special symbol, and the normal symbol storage command is the normal symbol 1 hold 0 to 4 (gate shown in FIG. 8). The game ball passes through the unit 2350, and the normal symbol display 1189 of the function display board 1191 conveys the number of balls (holding number) that have not yet been used for the variable display of the normal symbol. The command is pre-read and displayed by the upper special symbol display 1185 based on the special symbol 1 hold before the special symbol 1 hold is used for the variable display of the special symbol on the upper special symbol display 1185 of the function display board 1191. The special symbol 2 storage look-ahead effect command is used to indicate the start of the look-ahead effect that notifies the notice of the result, and the special symbol 2 hold is used for the variable display of the special symbol on the special symbol display 1186 under the function display board 1191. Before this, the pre-reading effect is instructed to read ahead and notify the notice of the display result by the lower special symbol display 1186 based on the special symbol 2 hold, and the main prize ball number information output command is the main control board. The number of game balls that the 4100 plans to pay out as prize balls based on the game balls that have entered various winning openings such as the upper starting opening 2101, the lower starting opening 2102, the general winning opening 2104, 2201, and the large winning opening 2103. Every time the number reaches 10 balls, the main prize ball number information output signal is sent to the hole via the external terminal board 784 as the main prize ball number information. It tells the computer to tell.

As the transmission timing of these various commands, the start port winning command is used when the start port is won (when a game ball enters the upper start port 2101 based on the detection signal from the upper start port switch 3022, or when the lower start port switch is used. When the game ball enters the lower starting port 2102 based on the detection signal from 2109), the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and the door frame shown in FIG. The command for specifying the end of the fluctuation shortening operation is transmitted from the speaker 130 provided in No. 5 mainly to notify the fact by voice, and the command for specifying the end of the fluctuation shortening operation is at the end of the stop period after the fluctuation is confirmed after digesting the fluctuation shortening of the specified number of times. The high-probability end designation command is sent at the end of the stop period (after the out-of-order stop period has elapsed) after the fluctuation is confirmed after the high probability number of times in the case of "high probability N times" is exhausted. The memory command is a hold when the number of balls for which the special symbol 1 operation is held changes (a game ball enters the upper start port 2101 and is not yet used for displaying the change of the special symbol on the upper special symbol display 1185 of the function display board 1191. When there is a number, when a game ball enters the upper start port 2101 and the number of holds increases, or from the number of holds, the upper special symbol display 1185 is used to display the fluctuation of the special symbol and the number of holds. The special symbol 2 storage command is sent when the number of special symbol 2 operation pending balls changes (when the game ball enters the lower start port 2102 and the special symbol 2 storage command is displayed on the lower special symbol display 1186 of the function display board 1191). When there is a hold number that has not yet been used for the variable display of the special symbol, and when a game ball enters the lower start port 2102 and the hold number increases, or from the hold number, the lower special symbol display 1186 It is transmitted when the number of reserved balls is reduced by using it for variable display of special symbols), and the normal symbol storage command is sent when the number of reserved balls for normal symbol 1 operation changes (when the game ball passes through the gate 2350 and the number of reserved balls is reduced). When there is a hold number that has not yet been used for the variable display of the normal symbol on the 1191 normal symbol display 1189, and when the game ball passes through the gate 2350 and the hold number increases, or from the hold number, it is normal. It is transmitted on the symbol display 1189 when it is used for variable display of a normal symbol and the number of reserved balls decreases), and the special symbol 1 storage look-ahead effect command is sent when the number of special symbol 1 operation reserved balls increases (at the upper start port 2101). It is transmitted when the game ball enters and the number of reserved balls increases), and the special symbol 2 memory look-ahead effect command is sent when the number of special symbol 2 operation reserved balls increases (the game ball enters the lower start port 2102). The main prize ball number information output command is transmitted when the number of balls is held increases, and the game ball enters the upper start port 2101 based on the detection signal from the upper start port switch 3022 at the time of winning various winning openings. When a game ball enters the lower starting port 2102 based on the detection signal from the lower starting port switch 2109 when the ball hits, the general winning opening 2104, 2201 is entered based on the detection signal from the general winning opening switches 3020 and 3020. It is transmitted when the game ball enters, and when the game ball enters various winning openings such as when the game ball enters the large winning opening 2103 based on the detection signal from the count switch 2110). It should be noted that these various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control side timer interrupt process.

By the way, as described above, the starting port winning command is issued at the time of winning the starting port (when a game ball enters the upper starting port 2101 based on the detection signal from the upper starting port switch 3022, or from the lower starting port switch 2109. When a game ball enters the lower starting port 2102 based on the detection signal of (1), the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 mainly by voice. Although it is transmitted to notify the fact, how the peripheral control board 4140 shown in FIG. 15 uses the start opening winning command may differ depending on the specifications of the pachinko gaming machine. For example, in the pachinko gaming machine 1 of the present embodiment, in addition to notifying by voice from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, the presence or absence of fraudulent activity is monitored. It is a specification that is also used for the purpose. On the other hand, in other pachinko gaming machines, the peripheral control board 4140 simply receives the start opening winning command, and the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker provided in the door frame 5. There is also a specification that does not notify by voice from 130.

[14-3. Various commands from the payout control board received by the main control board]
Next, various commands from the payout control board 4110 received by the main control board 4100 will be described.

As shown in FIG. 42, the classification of various commands from the payout control board 4110 is composed of commands named frame state 1, error release navigation, and frame state 2, frame state 1, error release navigation, and The order of priority is set in the order of frame state 2.

The frame state 1 command (corresponding to the error occurrence command) includes out-of-ball, full tank, stock of 50 or more, connection abnormality and no CR connection, and bit 0 (B0, "B") when the ball is out. Represents a bit.) Is set to a value 1, bit 1 (B1) is set to a value 1 when the tank is full, bit 2 (B2) is set to a value 1 when 50 or more stocks are in stock, and a connection error occurs. The value 1 is set in the bit 3 (B3), and the value 1 is set in the bit 4 (B4) when the CR is not connected. Bits 5 (B5) to 7 (B7) of the frame state 1 command are set to have a value of 1 in B5, a value of 0 in B6, and a value of 0 in B7.

The error release navigation command (corresponding to the error release command) includes a ball, a count switch error, and a retry error. For a ball, bit 2 (B2) is set to a value of 1, and for a count switch error. The value 1 is set in the bit 3 (B3), and the value 1 is set in the bit 4 (B4) in the retry error. Here, the "counting switch error" indicates whether or not the counting switch 751 shown in FIG. 13 has a defect. The "retry error" indicates that the inconsistent game ball is repeatedly paid out by the retry operation. Bits (B0), bits (B1), and bits 5 (B5) to 7 (B7) of the error release navigation command have a value of 0 for B0, a value of 0 for B1, a value of 0 for B5, and a value of 1 for B6. And the value 0 is set in B7.

A launch ball feed control circuit error is prepared for the frame state 2 command, and a value 1 is set to bit 0 (B0) in the launch ball feed control circuit error. Bit 1 (B1) to bit 7 (B7) of the frame state 2 command have a value 0 for B1, a value 0 for B2, a value 0 for B3, a value 0 for B4, a value 1 for B5, a value 1 for B6, and so on. The value 0 is set in B7.

As the transmission timing of these various commands, the frame state 1 command is transmitted at the time of power restoration, the frame state change, and the error release navigation, and the error release navigation command is transmitted at the time of error release navigation, and the frame state 2 command Is transmitted when the power is restored and when the frame state changes. It should be noted that these various commands are actually transmitted in the command transmission process of step S558 in the payout control unit main process of the payout control unit power-on processing described later.

[15. Various control processes on the main control board]
Next, various control processes performed by the main control board 4100 shown in FIG. 12 according to the progress of the game of the pachinko gaming machine 1 will be described with reference to FIGS. 43 to 45. FIG. 43 is a flowchart showing an example of the main control side power-on processing, FIG. 44 is a flowchart showing the continuation of the main control-side power-on processing of FIG. 43, and FIG. 45 is an example of the main control side timer interrupt processing. It is a flowchart which shows. First, various random numbers used for game control will be described, and then the operation of the initial value update type counter, the main control side power-on processing, and the main control side timer interrupt processing will be described.

[15-1. Various random numbers]
As various random numbers used for game control, a random number for determining a big hit to be used for determining whether or not to generate a big hit game state, and whether or not to generate a reach (out of reach) when the big hit game state is not generated. A random number for reach determination to be used for determination, and a variation display pattern to be used for determining the variation display pattern of the special symbol shown in FIG. 12 which is variablely displayed by the upper special symbol display 1185 and the lower special symbol display 1186. Random numbers for big hits, random numbers for big hit symbols to be used to determine the big hit symbols derived and displayed by the upper special symbol display 1185 and the lower special symbol display 1186 when the big hit game state is generated, and the random numbers for the big hit symbols. Random number for determining the initial value for the big hit symbol to be used for determining the initial value, for determining the small hit symbol derived and displayed by the upper special symbol display 1185 and the lower special symbol display 1186 when the small hit game state is generated. A random number for a small hit symbol to be used, a random number for determining an initial value for a small hit symbol to be used for determining the initial value of the random number for the small hit symbol, and the like are prepared. Further, in addition to these random numbers, a random number for determining a normal symbol hit to be used for determining whether or not to open and close the movable piece 2106 shown in FIG. Random numbers for determining the initial value for determining the hit of the normal symbol for use, random numbers for the normal symbol variation display pattern used for determining the variation display pattern of the normal symbol that is variablely displayed by the normal symbol display 1189 shown in FIG. Is prepared.

Among the various random numbers used for such game control, the big hit determination random number is updated by the hardware, while the other various random numbers are updated by the software.

For example, the big hit determination random number is directly updated by the hardware by the main control built-in hard random number circuit 4100an built in the main control MPU 4100a shown in FIG. As described above, in the main control built-in hard random number circuit 4100an, when the main control MPU 4100a is reset, first, the clock signal input to the main control MPU 4100a is set to one value within a predetermined numerical range as an initial value. Based on (the clock signal output from the main control crystal oscillator MX0 shown in FIG. 21), other values within the predetermined numerical range are extracted one after another at high speed, and all the values within the predetermined numerical range are extracted. When the extraction is completed, one value within the predetermined numerical range is extracted again, and other values within the predetermined numerical range are extracted one after another at high speed based on the clock signal input to the main control MPU4100a. do. The main control built-in hard random number circuit 4100an repeatedly performs such a high-speed lottery, and the main control MPU 4100a hits the value extracted by the main control built-in hard random number circuit 4100an at the time of acquiring the value from the main control built-in hard random number circuit 4100an. It is designed to be set as a random number for judgment.

On the other hand, the counter that updates the random number for normal symbol hit determination is updated within a predetermined fixed numerical value range from the minimum value to the maximum value, and the range from the minimum value to the maximum value will be described later. Each time the main control side timer interrupt process is performed, the value is incremented by 1 to count up. This counter counts up from the random number for determining the initial value for determining the normal symbol hit to the maximum value, and then counts up from the minimum value toward the random number for determining the initial value for determining the normal symbol hit. When the counter finishes counting up the range from the minimum value to the maximum value of the normal symbol hit judgment random number, the normal symbol hit judgment initial value determination random number is updated. Such a counter update method is called an "initial value update type counter". The random number for determining the initial value for determining the normal symbol hit can be obtained by executing the initial value lottery process for drawing one value from the fixed numerical value range of the counter that updates the random number for determining the normal symbol hit. ..

In the present embodiment, when the operation switch 860a of the payout control board 4110 shown in FIG. 13 is operated at the time of turning on the power, or in the processing at the time of turning on the power on the main control side, which will be described later, the main control MPU 4100a shown in FIG. The checksum value (sum value) obtained by calculating the total of various information stored in the main control built-in RAM as numerical values is stored in the main control side power off processing (power off). When clearing the entire area of the main control built-in RAM, such as when the checksum value (sum value) does not match, the random number for determining the initial value for normal symbol hit determination is the main control MPU4100a shown in FIG. Extracts the ID code from the built-in non-volatile RAM, and based on the extracted ID code, performs the initial value derivation process that always derives the same fixed value from the fixed numerical range of the counter that updates the normal symbol hit judgment random number. It is a mechanism to execute and set this derived fixed value. That is, the random number for determining the initial value for determining the normal symbol hit is constantly overwritten and updated with the same fixed value derived based on the ID code by executing the initial value derivation process. In this way, the value set in the random number for determining the initial value for normal symbol hit determination is derived using the ID code, and the non-volatile RAM built in the main control MPU4100a by the manufacturer of the main control MPU4100a. The ID code is stored by storing the ID code in the first security measure that the ID code cannot be rewritten even if an external device is used, and by executing the initial value derivation process when clearing the entire area of the main control built-in RAM. It is prevented from being analyzed by taking a second security measure of deriving the same fixed value based on the above and a two-step security measure by.

Here, an advantage of extracting an ID code from the non-volatile RAM built in the main control MPU4100a and using the extracted ID code as a random number for determining an initial value for determining a normal symbol hit will be described. For example, a person who illegally obtains a game ball to be paid out as a prize ball obtains the game board 4 by some method, disassembles it, and inputs an ID code stored in advance in the non-volatile RAM built in the main control MPU 4100a. Even if it is possible to grasp the timing when the value of the counter that illegally acquires and updates the random value for normal symbol hit judgment and the normal symbol hit judgment value match, the ID code is unique for identifying the individual. Since the code is attached, the ID code is completely different from the ID code stored in advance in the non-volatile RAM built in the main control MPU 4100a'provided in the other game board 4'. That is, in the other game board 4', the timing at which the value of the counter for updating the random number for normal symbol hit determination and the normal symbol hit judgment value match is also completely different from that of the obtained game board 4. In other words, the ID code obtained by disassembling and analyzing the obtained game board 4 is completely useless in another game board 4', that is, another pachinko game machine 1', so it is disassembled and analyzed. Even if a momentary power failure is generated at each predetermined interval obtained and the game ball is passed through the gate portion 2350 shown in FIG. 8 at each predetermined interval, the movable piece 2106 shown in FIG. 8 is opened and closed. It is not possible to generate a gaming state in which the gaming ball can be accepted by the lower starting port 2102.

[15-2. Main control side power-on processing]
First, when the power is turned on to the pachinko gaming machine 1, the main control MPU 4100a is configured so that the stack pointer is set at a predetermined address as a default. This stack pointer indicates, for example, the address loaded on the stack for temporarily storing the contents of the storage element (register) in use, or the return address of this routine when the subroutine is terminated and returned to this routine. It indicates the address stacked on the stack for temporary storage, and the stack pointer advances each time the stack is stacked.

Then, the above-mentioned main control program performs the main control side power-on processing as shown in FIGS. 43 and 44 under the control of the main control MPU 4100a of the main control board 4100. When the main control side power-on processing is started, the main control program sets the RAM access permission under the control of the main control MPU4100a (step S10). By setting this RAM access permission, it is possible to update the main control built-in RAM (game storage unit).

Following step S10, the main control program sets the initial value and the start setting of the main control built-in WDT4100af shown in FIG. 12 (step S12). Here, the watchdog timer control register built in the main control MPU 4100a (hereinafter referred to as “) is used to set an initial value in the main control built-in WDT4100af that monitors whether or not the operation (system) of the main control MPU 4100a is operating normally. The timer setting value is set in the WDT control register), the main control built-in WDT4100af is started, and the time counting until the main control MPU4100a is reset is started. When the main control built-in WDT4100af is started, the time counting by the main control built-in WDT4100af is started, and the watchdog timer clear register built in the main control MPU4100a is reached by the time when the timed time reaches the time set by the timer set value. Hereinafter, if the timer clear setting value is not set in the "WDT clear register"), the main control MPU4100a is forcibly reset by the main control built-in WDT4100af. On the other hand, when the WDT4100af with built-in main control is started and the time is started, if the timer clear setting value is set in the WDT clear register before the time is reached by the time set by the timer setting value, the timer clear setting value is set. The timekeeping by the WDT4100af with built-in main control is cleared, and the timekeeping is started again. In this way, the operation (system) of the main control MPU4100a operates normally by repeating the process of clearing the time measurement by the main control built-in WDT4100af until the time set by the timer set value is reached and restarting the time measurement. It is possible to monitor whether or not it is.

Following step S12, the main control program performs a power failure clearing process (step S14). In this electric power clearing process, first, the power failure clear signal is started to be output to the power failure monitoring circuit 4100e shown in FIG. The power failure monitoring circuit 4100e is composed of a comparator MIC21 which is a voltage comparison circuit and a D type flip-flop MIC22. The comparator MIC21, which is a voltage comparison circuit, outputs the comparison result by comparing the voltage between + 24V and the reference voltage or comparing the voltage between + 12V and the reference voltage. This comparison result becomes HI when no power failure or momentary power failure occurs and is input to the PR terminal which is a preset terminal of the D type flip-flop MIC22, while when a power failure or momentary power failure occurs. The logic becomes LOW and is input to the PR terminal which is a preset terminal of the D type flip-flop MIC22.

In the electric power clearing process, the power failure clear signal is first output to the power failure monitoring circuit 4100e to start the output of the power failure clear signal to the CLR terminal which is the clear terminal of the D type flip-flop MIC22. This power failure clear signal is input from the output terminal of the predetermined output port of the main control MPU 4100a to the CLR terminal which is the clear terminal of the D type flip-flop IC via the main control output circuit 4100ca with a reset function with its logic as LOW. Will be done. As a result, the main control MPU4100a can release the latch state of the D-type flip-flop MIC22, and until the latch state is set, the logic input to the PR terminal which is the preset terminal of the D-type flip-flop MIC22 is input. It can be inverted and output from the 1Q terminal, which is an output terminal, and the signal from the 1Q terminal can be monitored.

Subsequently, in the electric power clearing process, a wait timer process is performed to determine whether or not a power failure warning signal is input. The voltage does not rise immediately from the time the power is turned on until the specified voltage is reached. On the other hand, in the event of a power failure or momentary power failure (a phenomenon in which the power supply is temporarily stopped), the voltage drops, and when the voltage becomes smaller than the power failure warning voltage, a power failure warning signal is input from the power failure monitoring circuit 4100e as a power failure warning. Similarly, when the voltage becomes smaller than the power failure warning voltage between the time when the power is turned on and the voltage rises to a predetermined voltage, a power failure warning signal is input from the power failure monitoring circuit 4100e. Therefore, the wait timer process is a process for waiting until the voltage becomes higher than the power failure warning voltage and stabilizes after the power is turned on. In the present embodiment, 200 milliseconds (ms) is set as the waiting time (wait timer). Has been done. The determination of whether or not the power failure warning signal is input is performed based on the signal output from the 1Q terminal, which is the output terminal of the above-mentioned D type flip-flop MIC 22, as the power failure warning signal.

If there is no power failure warning signal input even after waiting until the voltage becomes higher than the power failure warning voltage and stabilizes after the power is turned on, the main control program sends a power failure clear signal to the CLR terminal, which is the clear terminal of the D-type flip-flop MIC22. Stop the output. Here, the power failure clear signal is a CLR terminal which is a clear terminal of the D type flip-flop IC via the main control output circuit 4100ca with a reset function from the output terminal of the predetermined output port of the main control MPU 4100a with its logic as HI. Is entered in. Thereby, the main control MPU4100a can set the D type flip-flop MIC 22 in the latch state. When the D-type flip-flop MIC 22 latches the state in which the logic is LOW and is input to the PR terminal which is the preset terminal, the power failure warning signal is output from the 1Q terminal which is the output terminal.

Following step S14, the main control program is in a state in which the RAM clear process for initializing the main control built-in RAM (game storage unit) can be executed for a predetermined time from the time when the power is turned on (when the power is turned on on the game side). Operation control means). Specifically, the main control program first determines whether or not the operation switch 860a of the payout control board 4110 shown in FIG. 13 is operated (step S16). In this determination, the main control program inputs an error release navigation command (first error release command) based on the operation signal (detection signal) associated with the operation of the operation switch 860a of the payout control board 4110 to the main control MPU 4100a. It depends on whether or not it is done. Based on the logical value of the operation signal, the main control program determines that it does not instruct to clear the RAM when the logical value of the operation signal from the operation switch 860a is HI, and the operation switch 860a operates. On the other hand, when the logical value of the operation signal from the operation switch 860a is LOW, it is determined that the operation switch 860a is not operated, and it is determined that the operation switch 860a is operated.

In step S16, the main control program sets the value 1 in the RAM clear notification flag RCL-FLG when the operation switch 860a is being operated (step S18). On the other hand, when the operation switch 860a is not operated in step S16, the main control program sets the value 0 in the RAM clear notification flag RCL-FLG (step S20). That is, the main control program can execute the RAM clear process that initializes the RAM (that is, the main control built-in RAM (game storage unit)) built in the main control MPU 4100a for a predetermined time from the time when the power is turned on. Set to the state (operation control means when the power is turned on on the game control side). The above-mentioned RAM clear notification flag RCL-FLG is stored in the main control built-in RAM (game storage unit) of the main control MPU4100a, and is stored in the main control built-in RAM (game storage unit). , Information indicating the value of the main prize ball number information output judgment counter, etc.) is a flag indicating whether to delete various information, value 1 when various information is deleted, value 0 when various information is not deleted. Is set to each. The values of the RAM clear notification flags RCL-FLG set in steps S18 and S20 are stored in the general-purpose storage element (general-purpose register) of the main control MPU4100a.

Following step S18 or step S20, the main control program performs a wait time wait process (step S22). In this wait time standby process, the liquid crystal display device 1900 on the game board side, the movable liquid crystal display devices 1925a to 1925d, and the liquid crystal display device 470 on the upper plate side by the liquid crystal and sound control unit 4160 of the peripheral control board 4140 shown in FIG. It waits until the system that controls drawing starts (boots). In the present embodiment, 2.5 seconds (s) is set as a waiting time (boot timer) until booting.

Following step S22, the main control program determines whether or not a power failure warning signal has been input (step S24). As described above, when the power of the pachinko gaming machine 1 is cut off, a power failure or a momentary power failure occurs, when the voltage becomes equal to or lower than the power failure warning voltage, a power failure warning signal is input from the power failure monitoring circuit 4100e as a power failure warning. The determination in step S24 is performed based on this power failure warning signal. When the power failure warning signal is input in the determination in step S24, the main control program returns to the determination in step S24 again, and repeats the determination in step S24 as long as the power failure warning signal is continuously input. As a result, the timer clear setting value is set in the WDT clear register built in the main control MPU 4100a for the main control built-in WDT4100af activated in step S12, the time counting by the main control built-in WDT4100af is cleared, and the time counting is started again. The main control MPU4100a is forcibly reset by the main control built-in WDT4100af. After that, the main control program again performs this main control side power-on processing under the control of the main control MPU 4100a of the main control board 4100. A detailed description of the point that the determination in step S24 is performed following the wait time waiting process in step S22 will be described later.

When the power failure warning signal is not input in the determination in step S24, the main control program determines whether or not the RAM clear notification flag RCL-FLG has a value of 0 (step S26). As described above, the RAM clear notification flag RCL-FLG is set to a value of 1 when various information is erased and a value of 0 when various information is not erased. When the value of the RAM clear notification flag RCL-FLG is 0 in step S26, that is, when various information is not erased, the checksum is calculated (step S28). This checksum considers various information stored in the main control built-in RAM as numerical values and calculates the total.

Following step S28, the main control program sets the calculated checksum value (sum value) as the checksum value (sum value) stored in the main control side power off processing (power off) described later. It is determined whether or not they match (step S30). When they match, the main control program determines whether or not the backup flag BK-FLG has a value of 1 (step S32). This backup flag BK-FLG stores various information, checksum value (sum value), game backup information such as backup flag BK-FLG value, etc. in the main control built-in RAM in the main control side power off processing described later. It is a flag indicating whether or not the operation has been performed, and is set to a value 1 when the main control side power off processing is normally completed, and a value 0 when the main control side power off processing is not normally completed. In the inspection process of the production line of the main control board 4100, the checksum of step S28 is calculated and the determination of step S30 is performed when the main control board 4100 is first turned on after being manufactured for inspection. , Will be described in detail later.

When the backup flag BK-FLG has a value of 1 in step S32, that is, when the main control side power off processing is normally completed, the main control program sets the work area of the main control built-in RAM as the time of power recovery ( Step S34). In this setting, the power recovery information is read from the ROM (that is, the main control built-in ROM) built in the main control MPU4100a, and the power recovery information is set in the work area of the main control built-in RAM. As a result, various information is read from the game backup information, and various commands corresponding to the various information are stored in a predetermined storage area of the main control built-in RAM. In addition to the state where the power is turned on from the state where the power is cut off, the "reset" is the state where the power is restored after the power failure or momentary power failure, and the fraudulent means (for example, the cheating person is on the hem of the arm). The state in which the main control board 4100 is irradiated with the high frequency from the hidden high frequency output device), the main control MPU 4100a itself is reset, and then returned is also included.

Following step S34, the main control program sets the backup flag BK-FLG to a value of 0 (step S36). As a result, various information, checksum value (sum value), etc. are changed by performing various subsequent processes. Therefore, the backup flag BK- is normally terminated when the main control side power is turned off, which will be described later. If the value 1 is not set in FLG, the entire area of the main control built-in RAM will be cleared, as will be described later.

On the other hand, when the RAM clear notification flag RCL-FLG is not a value 0 (value 1) in step S26, that is, when various information is erased, or when the checksum values (sum values) do not match in step S30. Or, when the backup flag BK-FLG is not a value 1 (value 0) in step S32, that is, when the main control side power off processing is not normally completed, the main control program is used for all of the main control internal RAM. Clear the area (step S38). That is, the main control program executes the game control side RAM clear process triggered by the input of the detection signal accompanying the operation of the operation switch 860a described above (the payout control side power-on operation control means). Specifically, the main control program performs by writing the value 0 to the main control built-in RAM. Instead, the main control program may read a predetermined value from the main control built-in ROM as an initial value and set it. Further, the main control MPU4100a performs processing when the logical value of the operation signal from the operation switch 860a indicates RAM clear and various information is erased, when the sum values do not match, or when the main control side power is turned off. When it is not completed normally, the unique ID code stored in advance in the non-volatile RAM of the main control MPU4100a is taken out, and the fixed numerical range of the counter that updates the random number for normal symbol hit judgment based on the taken out ID code. The initial value derivation process that always derives the same fixed value from is performed, and this fixed value is set as the random number for determining the initial value for determining the normal symbol hit to be used for determining the initial value of the above-mentioned random number for determining the normal symbol hit. do.

Following step S38, the main control program sets the work area of the main control built-in RAM as an initial setting (step S40). This setting is performed by reading the initial information from the main control built-in ROM and setting this initial information in the work area of the main control built-in RAM. As a result, the game backup information is initialized, and for example, the value of the main prize ball number information output determination counter is set (set) to the initial value of 0 (zero).

Following step S36 or step S40, the main control program performs interrupt initial setting (step S42). This setting sets the interrupt cycle when the main control side timer interrupt process, which will be described later, is performed. In this embodiment, it is set to 4 milliseconds (ms).

Following step S42, the main control program performs serial communication initial setting (step S44). Here, various serial input / output ports built into the main control MPU 4100a (for example, serial input / output ports (reception channel and transmission channel) for the payout control board 4110, serial input / output ports (reception channel and transmission channel) for the peripheral control board 4140). ), The communication speed is set and the presence / absence of parity is set in the transmission serial port prescaler, and the initialization of the transmission circuit and the transmission permission are set in the transmission serial port control register.

Following step S44, the main control program sets the test signal output port initialization (step S46). Here, in a gaming machine testing institution, a test signal output port (not shown) for outputting various inspection information is initialized (set to OFF data output) when the power is turned on.

Following step S46, the main control program sets the activation of the main control built-in hard random number circuit 4100an shown in FIG. 12 (step S48). Here, among various random numbers related to the game, a hard random number control register built in the main control MPU4100a to update the big hit determination random number used for determining whether or not to generate the big hit game state by hardware. In addition to making settings such as latching and acquiring random numbers, the hardware random number setting register is set to start the main control built-in hard random number circuit 4100an. When the main control built-in hard random number circuit 4100an is activated by these settings, it is determined in advance at high speed based on the clock signal input to the main control MPU 4100a (the clock signal output from the main control crystal oscillator MX0 shown in FIG. 21). Other values in the numerical range are extracted one after another without duplication, and when all the values in the predetermined numerical range have been extracted, one value in the predetermined numerical range is extracted again. Based on the clock signal input to the main control MPU4100a, other values within a predetermined numerical range are extracted one after another at high speed without duplication. When the main control MPU 4100a acquires a random number (random number value) from the main control built-in hard random number circuit 4100an, the main control MPU 4100a outputs a latch signal to the main control built-in hard random number circuit 4100an, and the main control when this latch signal is input. The random number (random number value) extracted by the built-in hard random number circuit 4100an is acquired from the hard random number latch register built in the main control built-in main control MPU 4100a. The main control MPU4100a sets the acquired random number value as a random number for jackpot determination.

Following step S48, the main control program makes reservation settings for commands to be transmitted when the power is turned on (step S50). Here, in order to convey that the power has been turned on (restored) based on the power recovery information set in the main control built-in RAM work area in the setting of the work area of the main control built-in RAM in step S34, FIG. 40 The main control built-in RAM is created as the transmission information by creating the power-on state command, the power-on main control return destination command, and the power-on main prize ball number information output judgment counter notification command, which are classified as power-on. It is stored in the transmission information storage area of. In the transmission information storage area of the main control built-in RAM, in the setting of the work area of the main control built-in RAM in step S34, various information may be read from the game backup information and various commands corresponding to the various information may be stored. be. In such a case, first, after the transmission of various commands according to the game information is completed, the power-on state command, the power-on main control return destination command, and the power-on main prize ball number information The output judgment counter notification command will be sent. These commands are transmitted in the timer interrupt processing on the main control side, which will be described later. A detailed description of the fact that the reservation setting of the command to be transmitted when the power is turned on is set in step S50 will be described later.

Following step S50, the main control program sets interrupt enable setting (step S52). With this setting, the interrupt cycle set in step S42, that is, the main control side timer interrupt process described later is repeatedly performed every 4 ms.

Following step S52, the main control program receives an error release navigation command associated with the operation of the operation switch 860a (operation switch) when a predetermined time elapses from the power-on, that is, when the main control side main process is started. The execution of the game control side RAM clear process triggered by the receipt is restricted (normal operation control means). As described above, the main control program uses the concept of time sharing to input the detection signal input by the operation of the operation switch 860a to the error release navigation command for a predetermined time from the time when the power is turned on as described above. The RAM clear process is executed with the input as an opportunity (operation control means when the power is turned on on the game control side), and the execution of the RAM clear process is restricted even if the error release navigation command is input after the predetermined time has elapsed (the execution of the RAM clear process is restricted). Game control side normal operation control means), it is treated as a release switch for canceling the error notification associated with the generated error. That is, the operation switch 860a (error release unit), which was originally supposed to be used to release the error that occurred in the payout operation, is used as a game storage unit instead of the operation switch 860a (error release unit) for a predetermined time from the time when the power is turned on. It functions as an operation unit for executing RAM clear processing for starting initialization of the main control built-in RAM (and the payout control built-in RAM as a payout storage unit described later), or after a predetermined time has elapsed, a game It can function as an operation unit for canceling an error that occurs in the ball payout operation.

Next, the main control program determines whether or not a power failure warning signal has been input (step S54). As described above, when the power of the pachinko gaming machine 1 is cut off, a power failure or a momentary power failure occurs, when the voltage becomes equal to or lower than the power failure warning voltage, a power failure warning signal is input from the power failure monitoring circuit 4100e as a power failure warning. The determination in step S54 is performed based on this power failure warning signal.

When there is no input of the power failure warning signal in step S54, the main control program performs the non-winning random number update process (step S56). In this non-winning random number update process, the above-mentioned random number for reach determination, random number for variable display pattern, random number for determining initial value for big hit symbol, random number for determining initial value for small hit symbol, and the like are updated. In this way, in the non-winning random number update process, the random numbers that are not related to the winning determination (big hit determination) are updated by the software. It should be noted that the above-mentioned random number for determining the normal symbol hit, the random number for determining the initial value for determining the normal symbol hit, the random number for the normal symbol variation display pattern, and the like are also updated by this non-winning random number update process.

Following step S56, the process returns to step S54 again, the main control program determines whether or not there is a power failure warning signal input, and if there is no power failure warning signal input, the non-winning random number update process is performed in step S56. Then, steps S54 to S56 are repeated. The processes of steps S54 to S56 are referred to as "main control side main process".

On the other hand, when the power failure warning signal is input in step S54, the main control program sets interrupt prohibition (step S58). This setting prevents the main control side timer interrupt processing, which will be described later, from being performed, prevents writing to the main control built-in RAM, and protects the above-mentioned rewriting of various information including game information and other information.

Following step S58, the main control program starts outputting a power failure clear signal (step S60). Here, the same process as the process of starting the output of the power failure clear signal in the power failure clear process of step S14 is performed. As a result, the main control program can release the latch state of the D-type flip-flop MIC22 under the control of the main control MPU4100a.

Following step S60, the main control program includes a start port solenoid 2105, an attacker solenoid 2108, an upper special symbol indicator 1185, a lower special symbol indicator 1186, an upper special symbol memory indicator 1184, and a lower special, as shown in FIG. The drive signal output to the symbol memory display 1187, the normal symbol display 1189, the normal symbol storage display 1188, the game status display 1183, the round display 1190, etc. is stopped (step S62).

Following step S62, the main control program calculates the checksum and stores the calculated value (step S64). This checksum calculates the total of the game information of the work area of the main control built-in RAM, excluding the storage area of the checksum value (sum value) and the backup flag BK-FLG value described above, as numerical values.

Following step S64, the main control program sets the backup flag BK-FLG to a value of 1 (step S66). As a result, the storage of the game backup information is completed.

Following step S66, the main control program sets RAM access prohibition (step S68). This RAM access prohibition setting makes it impossible to access the main control built-in RAM (game storage unit), so that it is possible to prevent the contents of the main control built-in RAM (game storage unit) from being updated.

Following step S68, an infinite loop is entered. In this infinite loop, the timer clear setting value is set in the WDT clear register built in the main control MPU4100a for the main control built-in WDT4100af started in step S12, the time counting by the main control built-in WDT4100af is cleared, and the timekeeping is started again. The main control MPU4100a is forcibly reset by the main control built-in WDT4100af. After that, the main control program again performs this main control side power-on processing under the control of the main control MPU 4100a of the main control board 4100. The processing of steps S58 to S68 and the infinite loop are referred to as "main control side power off processing".

The pachinko gaming machine 1 (main control MPU4100a) is reset when there is a power failure or when there is a momentary power failure, and when the power is restored thereafter, the main control side power-on processing is performed.

In step S30, it is inspected whether or not the game backup information stored in the main control built-in RAM is normal, and then in step S32, whether or not the main control side power off processing is normally completed. Is inspecting. In this way, by double-checking the game backup information stored in the main control built-in RAM, it is inspected whether or not the game backup information is stored by fraudulent activity.

Here, a point will be described in which the presence / absence of the power failure warning signal in step S24 is determined following the wait time standby process in step S22. First, regarding the problem in the case where the presence / absence of the power failure warning signal in step S24 is not determined, that is, the case where the value of the RAM clear flag in step S26 is determined following the wait time standby process in step S22 and the subsequent processing is proceeded. The problem in is explained.

As described above, the VDD terminal, which is the power supply terminal of the main control MPU4100a, is charged to the electrolytic capacitor MC2 shown in FIG. 21 when the power supply from the pachinko island facility is cut off due to a power failure or a momentary power failure. The charged charge is applied as + 5V over a period of about 7 milliseconds (ms) after the occurrence of a power failure or momentary power failure. In other words, even if the power supply from the pachinko island equipment is cut off due to a momentary power failure or power outage, the electric charge charged to the hardware called the electrolytic capacitor MC2 is applied as + 5V, so that the power supply from the pachinko island equipment is supplied. The main control side power off processing can be completed within a period of about 7 ms from the time when the power is cut off. This is because a power failure or momentary power failure occurs when the player is playing a game, that is, when the main control side main process or the main control side timer interrupt process described later is performed, and the pachinko island equipment When the power is cut off, the main control side power off processing can be reliably completed.

However, as an extremely rare phenomenon, in the wait time standby process in step S22 at the time of power recovery, the liquid crystal on the peripheral control board 4140 and the liquid crystal display device 1900 on the game board side and the movable liquid crystal display device by the sound control unit 4160 shown in FIG. The waiting time (boot timer: 2.5 seconds is set in this embodiment) until the system that controls drawing between the 1925a to 1925d and the upper plate side liquid crystal display device 470 starts (boots). If a momentary power failure or power failure occurs just before the timer starts and the standby time is reached, the charge charged in the hardware called the electrolytic capacitor MC2 is applied as + 5V to the VDD terminal which is the power supply terminal of the main control MPU4100a. Within a period of about 7 ms, the interrupt initial setting is performed in step S42, and then the interrupt enable setting is performed in step S52, so that the main control side timer interrupt process, which will be described later, is performed, and the main control built-in RAM Even if the contents are updated, it may not be possible to complete the main control side power off processing in the main control side power on processing. Therefore, the value obtained by calculating the checksum based on the contents of the main control built-in RAM is not stored, and the main control side power-on processing is started again at the time of power recovery.

Then, at the time of this power recovery, the main control side power-on processing is started, the wait time standby processing in step S22 is completed without causing a momentary power failure or a power failure, and then in step S28, the main control built-in RAM is completed. When the value calculated based on the contents of the above and the value stored in the main control built-in RAM immediately before the momentary power failure or power failure occurs are compared and judged in step S30, the checksum values should match. Instead, the entire area of the main control built-in RAM is cleared in step S38. In other words, the above-mentioned game backup information that is forcibly stored in the main control built-in RAM even if the operation switch 860a is operated by the hall clerk or the like at the time of power recovery and there is no manifestation of intention by the hall clerk or the like to clear the RAM. There is a problem that it will be erased (cleared).

Therefore, in the present embodiment, immediately after the wait time standby process in step S22, a process for determining whether or not a power failure warning signal is input is provided as step 24, and when the power failure warning signal is input, The determination in step S24 is returned again, and the determination in step S24 is repeated as long as the power failure warning signal is continuously input. As a result, the timer clear setting value is set in the WDT clear register built in the main control MPU 4100a for the main control built-in WDT4100af activated in step S12, the time counting by the main control built-in WDT4100af is cleared, and the time counting is started again. The main control MPU 4100a can be forcibly reset by the main control built-in WDT4100af. Although the value of the RAM clear notification flag RCL-FLG is set in step S18 or step S20 before the wait time standby process of step S22 is performed, the value of the RAM clear notification flag RCL-FLG is mainly as described above. Since it is stored in the general-purpose storage element (general-purpose register) of the control MPU 4100a, the contents (game information) of the main control built-in RAM are not changed at all even if the RAM access permission is set in step S10.

In this way, immediately after the wait time standby process in step S22, a process for determining whether or not a power failure warning signal is input is provided as step 24, and when the power failure warning signal is input (that is, step). When it is determined by the determination in step S24 that the power to the pachinko gaming machine 1 is cut off after waiting in the wait time standby process in S22), the determination in step S24 is returned again and as long as the power failure warning signal is continuously input. By repeating the determination in step S24, the main control MPU 4100a of the main control board 4100 can be forcibly reset and the main control board 4100 can be restarted. It is possible to prevent various information including game information and other information (for example, information indicating the value of the main prize ball number information output determination counter) from being updated, and the check sum is calculated. The results are designed to be stable. As a result, when the main control MPU4100a of the main control board 4100 is restarted, it is determined that the calculation result of the checksum in step S28 and the calculated and stored value of the checksum in step S64 match. Therefore, the game information immediately before the occurrence of a momentary power failure or a power failure stored in the main control built-in RAM is not initialized. Therefore, it is possible to prevent the game information immediately before the occurrence of a momentary power failure or a power failure from being initialized at the time of power recovery.

Further, immediately after the wait time standby process in step S22, a process for determining whether or not a power failure warning signal is input is provided as step 24, and when the power failure warning signal is not input (that is, in step S22). When it is determined by the determination in step S24 that the power supply to the pachinko gaming machine 1 is not shut off after waiting in the wait time standby process), the pachinko machine is being played while the main control MPU 4100a of the main control board 4100 is proceeding with the game. Even if the power to the game machine 1 is cut off, the power is supplied to the VDD terminal, which is the power terminal of the main control MPU4100a, by the electrolytic capacitor MC2 shown in FIG. The main control side power supply composed of the processes of steps S58 to S68 and the infinite loop, which are backup processes for storing various information including (for example, information indicating the value of the main prize ball number information output determination counter). Since the main control MPU 4100a of the main control board 4100 can complete the disconnection process, when the main control MPU 4100a of the main control MPU 4100a is restarted, the checksum calculation result of step S28 and the checksum calculation result are displayed. In the backup process, it is determined that the checksum calculation result (that is, the value calculated and stored in the checksum in step S64) matches, so that there is a momentary power failure or power failure stored in the main control built-in RAM. The game information immediately before the occurrence of is not initialized. That is, the main control board 4100 can be started by being restored to the game information immediately before the momentary power failure or power failure occurs.

Further, immediately after the wait time standby process in step S22, when it is determined in step S24 that the power failure warning signal is input, the main control built-in RAM is forcibly reset by the main control built-in WDT4100af to reset the contents of the main control built-in RAM. While the main control side power off processing can be started again without updating at all, when it is determined in step S24 that the power failure warning signal has not been input immediately after the wait time standby processing in step S22, it has been so far. As you can see, it is possible to reliably complete the power cutoff process on the main control side within the "power supply securing period in the event of a momentary power failure or power failure" of about 7 ms by the hardware. That is, in the present embodiment, the power supply from the Pachinko Island facility is cut off due to a momentary power failure or a power failure during the processing when the main control side power is turned on at the time of power recovery, and the main control MPU 4100a The charge charged in the electrolytic capacitor MC2 shown in FIG. 21 is applied to the VDD terminal, which is a power supply terminal, as + 5V over a period of about 7 milliseconds (ms) after a power failure or momentary power failure occurs. Therefore, if the main control side power supply cutoff process cannot be completed within the "instantaneous power failure or power supply securing period" of about 7 ms by the hardware of the electrolytic capacitor MC2, the wait time standby process of step S22 is performed. Immediately after, in step 24, it is determined whether or not the power failure warning signal has been input. If the power failure warning signal has been input, the determination returns to step S24 again, and as long as the power failure warning signal continues to be input, step S24 By repeating the determination of, the timer clear setting value is set in the WDT clear register built in the main control MPU4100a for the main control built-in WDT4100af activated in step S12, the time measurement by the main control built-in WDT4100af is cleared again. By making it impossible to start the time measurement, the main control MPU 4100a can be forcibly reset by the main control built-in WDT4100af. The main control MPU4100a is forcibly reset by the main control built-in WDT4100af by such software, so that the steps after step S24 (specifically, the interrupt initial setting is performed in step S42, and then in step S52. The contents of the main control built-in RAM (game information and other information (for example, the number of main prize balls) by blocking the progress to the main control side timer interrupt process (control flow) in which interrupt permission is set and the main control side timer interrupt processing is started, which will be described later. We have adopted a mechanism that can prevent various information) including information indicating the value of the information output judgment counter) from being updated. When the power supply from the pachinko island facility is cut off due to a power outage or momentary power failure in this way, the contents of the main control built-in RAM (game information and other information (for example, a counter for determining the number of main prize balls) are output. Various information including information indicating the value of) is covered by the hardware so that it will not be changed at all, and the contents of the main control built-in RAM (game information and other information) by surely completing the main control side power outage processing. The main part is divided into two parts, one is covered by hardware so that the information (for example, information indicating the value of the main prize ball number information output determination counter) is not changed at all). It is possible to reliably prevent the contents of the control built-in RAM (game information and various information including other information (for example, information indicating the value of the main prize ball number information output determination counter)) from being changed. It has become like.

Next, the point that the reservation setting of the command to be transmitted when the power is turned on is set in step S50 will be described. In step S50, as described above, in the setting of the work area of the main control built-in RAM in step S34, the power is turned on (recovered) based on the power recovery information set in the work area of the main control built-in RAM. In order to convey, a power-on state command, a power-on main control return destination command, and a power-on main prize ball number information output determination counter notification command, which are classified into power-on, are created and transmitted as shown in FIG. Information is stored in the transmission information storage area of the main control built-in RAM. As described above, this power-on main control return destination command is mainly composed of information indicating the driving state of the starting port solenoid 2105 and information indicating the driving state of the attacker solenoid 2108 shown in FIG. There is. Here, first, when the main control return destination command at power-on does not include the information indicating the driving state of the starting port solenoid 2105 and the information indicating the driving state of the attacker solenoid 2108 shown in FIG. In other words, the problem in the case where the main control return destination command at power-on does not set the reservation of the command to be transmitted at power-on in step S50 will be described.

For example, when the peripheral control board 4140 controls the display of the screen of the jackpot game state (for example, the screen of the jackpot game effect) in the display area of the game board side liquid crystal display device 1900 shown in FIG. 8, the main control board 4100 Drives the attacker solenoid 2108, and when the large winning opening 2103 shown in FIG. 8 is opened by the opening / closing member 2107, a momentary power failure or a power failure occurs, and then the power is restored, the main control board 4100 steps. In the setting of the work area of the main control built-in RAM in S34, the attacker is restored to the gaming state immediately before the momentary power failure or power failure based on the power recovery information set in the work area of the main control built-in RAM. The driving of the solenoid 2108 is started, and the large winning opening 2103 shifts from the state of being closed by the opening / closing member 2107 to the state of being opened.

However, when a momentary power failure or power failure occurs, the peripheral control board 4140 receives various commands from the main control board 4100 and recovers when the power is restored, so that a momentary power failure or power failure occurs. After that, when the power is restored, the peripheral control board 4140 can be restored based on the probability and the time saving state indicated by the power-on state command received from the main control board 4100 at the time of power restoration. However, when a momentary power failure or a power failure occurs while the main control board 4100 is generating a big hit gaming state as a gaming state, and then power is restored, the peripheral control board 4140 will be changed to the main control board 4100 at the time of power recovery. Even if the screen can be displayed in the display area of the liquid crystal display device 1900 on the game board side and restored according to the probability and the time saving state based on the probability and the time saving state indicated by the power-on state command received from It is not possible to display at all which round of the jackpot game state. That is, for example, a game ball enters the large winning opening 2103, is detected by the count switch 2110 shown in FIG. 12, and a large winning opening 1 count display command that conveys the number of balls of the game ball entering the large winning opening 2103 is issued. Even if the main control board 4100 transmits to the peripheral control board 4140 and the peripheral control board 4140 receives it, the peripheral control board 4140 is a ball of a game ball that has entered the large winning opening 2103 on the screen according to the probability and the time saving state. Even if the number can be displayed in the display area of the liquid crystal display device 1900 on the game board side, it is not possible to display at all which round (that is, the number of rounds) of the jackpot game state.

In such a situation, when the main control board 4100 ends, for example, the 4th round (fourth round) of the big hit game state, the drive of the attacker solenoid 2108 is stopped and the big winning opening 2103 is opened by the opening / closing member 2107. The main control board 4100 gives the peripheral control board a command to indicate that the attacker unit 2100 shifts from the closed state to the closed state (that is, the closing of the large winning opening 2103 of the attacker unit 2100 is started between rounds). When transmitting to 4140 and the main control board 4100 starts the 5th round (fifth round) of the big hit game state, the attacker solenoid 2108 is started to be driven and the big winning opening 2103 is closed by the opening / closing member 2107. A command to display the 5th round of the opening of the large winning opening 2103 is transmitted from the main control board 4100 to the peripheral control board 4140 instructing the transition from the opening to the open state (that is, the opening of the 5th round of the large winning opening 2103). .. As a result, the peripheral control board 4140 finally switches the screen of starting 5 rounds of the jackpot game state from the screen according to the above-mentioned probability and time saving state and displays it in the display area of the liquid crystal display device 1900 on the game board side. Become.

Further, for example, a screen for notifying the player that the game ball is in a game state in which the game ball can be accepted and the game state is advantageous to the player (for example, a game indicating that the movable piece is expanded) to the lower start port 2102. When the peripheral control board 4140 controls the display in the display area of the liquid crystal display device 1900 on the game board side, the main control board 4100 drives the start port solenoid 2105 to drive the pair of pairs shown in FIG. When a momentary power failure or a power failure occurs while the movable piece 2106 is expanded in the left-right direction, and then the power is restored, the main control board 4100 becomes the work area of the main control built-in RAM in step S34. Based on the power recovery information set in the work area of the main control built-in RAM in the setting, the start port solenoid 2105 is started to be driven by restoring the game state immediately before the momentary power failure or power failure occurs. The movable piece 2106 of the above is shifted from a state in which it stands up substantially vertically to a state in which it is expanded in the left-right direction.

However, when a momentary power failure or power failure occurs, the peripheral control board 4140 receives various commands from the main control board 4100 and recovers when the power is restored, so that a momentary power failure or power failure occurs. After that, when the power is restored, the peripheral control board 4140 can be restored based on the power-on state command received from the main control board 4100 at the time of power restoration. However, when the main control board 4100 is in a game state in which the game ball can be accepted into the lower start port 2102 and a game state advantageous to the player is generated, a momentary power failure or a power failure occurs. After that, when the power is restored, the peripheral control board 4140 plays the screen according to the probability and the time saving state based on the probability and the time saving state indicated by the power-on state command received from the main control board 4100 at the time of power recovery. Even if the display area of the liquid crystal display device 1900 on the board side can be displayed and returned, the game state is such that the game ball can be accepted by the lower start port 2102, which is advantageous to the player. The peripheral control board 4140 cannot display the screen for transmitting the above in the display area of the liquid crystal display device 1900 on the game board side at all. For this reason, the player sitting in front of the pachinko machine is surprised that a momentary power failure or power failure has occurred, and the game ball is received by the lower starting port 2102 immediately before the momentary power failure or power failure occurs at the time of power restoration. In some cases, it may be forgotten that the gaming state is possible, and in such a case, the gaming state is returned to the lower starting port 2102 so that the gaming ball can be accepted as the gaming state at the time of power recovery. Nevertheless, when the power is restored, the screen for instructing the game (that is, the screen for instructing the game to put the game ball into the lower start port 2102) is not displayed in the display area of the liquid crystal display device 1900 on the game board side. There was also the problem that the player would not know what kind of game to play.

As described above, in the above-mentioned two examples, there is a problem that the gaming state immediately before the momentary power failure or the power failure cannot be quickly restored after the power is restored. In other words, a player sitting in front of a pachinko machine suffered a momentary power outage or a power outage, and when the power was restored after that, the pachinko machine's system appeared to be in a frozen state and failed. There was a problem of misunderstanding.

Therefore, in the present embodiment, when the main control board 4100 is turned on (including not only when the power is turned on but also when the power is restored due to a power failure or a momentary power failure), a power-on state command is used. And the power-on main control return destination command to the peripheral control board 4140, in step S50, the power-on state command and the power-on main control return destination command classified into the power-on shown in FIG. 40. Then, when the power is turned on, a counter notification command for determining the output of the main prize ball number information is created and stored as transmission information in the transmission information storage area of the main control built-in RAM. Then, these commands are transmitted in the timer interrupt processing on the main control side, which will be described later.

As a result, the peripheral control board 4140 is based on the power-on state command and the power-on main control return destination command received from the main control board 4100. When a momentary power failure or power failure occurs and then the power is restored, the attacker solenoid 2108 is started to be driven as the return destination of the main control board 4100, and the grand prize opening 2103 is released from the state of being closed by the opening / closing member 2107. Since it is possible to inform the peripheral control board 4140 that the state shifts to the current state, the peripheral control board 4140 is a screen that specifies that it is the 4th round of the jackpot game state (that is, a screen showing how many rounds it is). ) Cannot be displayed in the display area of the liquid crystal display device 1900 on the game board side, but in a big hit game state, the attacker solenoid 2108 is started to be driven and the big winning opening 2103 is opened by the opening / closing member 2107. A screen that tells you that there is a message (for example, a screen that tells the player that "It is a big hit. The big winning opening is open. Please play the game so that the game ball enters the big winning opening.") It is possible to instruct a player who sits in front of the pachinko game machine by displaying it in the display area of the liquid crystal display device 1900 on the game board side to insert the game ball into the large winning opening 2103 after the power is restored. Further, for example, in the above-described example, in a state in which the game ball can be accepted into the lower start port 2102 and the game state is favorable to the player, a momentary power failure or a power failure occurs, and then the game returns. When the power is turned on, a screen telling that the start port solenoid 2105 is started to be driven and the pair of movable pieces 2106 are expanded in the left-right direction as the return destination of the main control board 4100 (for example, "movable pieces"). The peripheral control board 4140 displays the display device 1900 on the game board side on the screen that conveys the message "Please play the game so that the game ball enters the lower start port." It is possible to instruct a player who sits in front of the pachinko game machine by displaying it in the area to play a game in which the game ball is inserted into the lower starting port 2102 after the power is restored. As a result, when a momentary power failure or a power failure occurs and the power is restored after that, the return destination of the peripheral control board 4140 can be finely instructed on the main control board 4100 side. Therefore, it is possible to quickly return to the gaming state immediately before the momentary power failure or power failure after the power is restored. In other words, a player sitting in front of a pachinko machine suffered a momentary power outage or a power outage, and when the power was restored after that, the pachinko machine's system appeared to be in a frozen state and failed. It is possible to prevent misunderstanding.

Next, in the main control board inspection step, which is the inspection step of the production line of the main control board 4100, the checksum of step S28 when the main control board 4100 is first turned on after being manufactured for inspection. The calculation and the determination in step S30 will be described. In the main control board inspection step, when the main control board 4100 is first turned on after being manufactured for inspection, the main control board is composed of the above-mentioned backup processes of steps S58 to S68 and an infinite loop. Since the main control MPU4100a of the main control board 4100 has never executed the control side power off processing, even if the checksum based on the contents of the main control built-in RAM is calculated in step S28, in step S30. In the comparison determination, the checksum values cannot match, and the entire area of the main control built-in RAM is always cleared in step S38. As a result, when the reservation setting of the command to be transmitted at the time of power-on is made in step S50, the power-on state command classified into the power-on, the power-on main control return destination command, and the power-on By creating a counter notification command for determining the output of the main prize ball number information and storing it as transmission information in the transmission information storage area of the main control built-in RAM, the power-on state command, the power-on main control return destination command, and the power supply At the time of insertion, only three commands, the main prize ball number information output determination counter notification command, are stored as transmission information in the transmission information storage area of the main control built-in RAM. Then, in these commands, in the timer interrupt process on the main control side, which will be described later, the power-on state command is first transmitted, then the power-on main control return destination command is transmitted, and then the number of main prize balls at power-on. The information output judgment counter notification command is sent. Utilizing this, in the main control board inspection process, when the main control board 4100 is first powered on after being manufactured for inspection, the power-on state command is issued as the first command from the main control board 4100. It will be transmitted to the inspection device in the main control board inspection process.

By the way, as described above, the power-on state command is shown in FIG. 13 when the power is turned on (including not only when the power is turned on but also when the power is restored due to a power failure or a momentary power failure). Information instructing that when the operation switch 860a of the payout control board 4110 shown is operated to clear the RAM, and when the power is turned on (in addition to the case where the power is turned on, a power failure or a momentary power failure occurs and the power is generated. (Including the time of power recovery to recover), any of the above-mentioned low-probability time-saving state, high-probability time-saving state, low-probability non-time-saving state, and high-probability non-time-saving state (probability and time-saving state) is restored. It is composed of information instructing whether to do so and information indicating the model code of the pachinko gaming machine. Here, a problem will be described when the power-on state command does not include information indicating the model code of the pachinko gaming machine.

As described above, the model code of the pachinko gaming machine is, as described above, which work when creating the so-called max type, middle type, and amadeji type as the pachinko gaming machine 1 (to be exact, the main control board 4100). What kind of game specifications are for copyright? (For example, if a probability change occurs, the state will continue until the next big hit game state occurs, and the number of changes in the special symbol is limited (for example) For example, it is possible to specify whether or not the game specification (so-called ST machine), etc., in which the probability fluctuation occurs after 30 times or 70 times).

In the production line of a manufacturer that manufactures the pachinko gaming machine 1, when the main control board 4100 is manufactured, the main control board 4100 for the copyright of a plurality of types of works may coexist. Then, the worker of the production line is responsible for the copyright of any of the copyrights of a plurality of types of works (for example, the copyrights of the works of movie A, movie B, drama C, movie D, cartoon E, and cartoon F). It is difficult to know whether the main control board 4100 is flowing to the production line in order to manufacture the control board 4100, or the main control board for one copyright (for example, the copyright of the work called movie D) among the copyrights of multiple types of works. Although the main control board 4100 is flowing to the production line to manufacture the 4100, the main control board 4100 is used to manufacture the main control board 4100 for other copyrights (for example, the copyright of the work called Manga F). There are also beliefs and misunderstandings that it is flowing on the production line. For this reason, when the main control board 4100 is manufactured in the manufacturing line of the manufacturer that manufactures the pachinko gaming machine 1, if the main control board 4100 for the copyrights of a plurality of types of works is mixed, the worker of the manufacturing line can use the manufacturing line. It is not possible to confirm which work the main control board 4100 manufactured in is for the copyright of which work, and for the copyright of the same work, which model type (max type, middle type, or Amadeji type) is available. It is also not possible to confirm what kind of game specification (game specification or ST machine that if a probability fluctuation occurs, that state will continue until the next big hit game state occurs). .. As a result, when the main control board 4100 is manufactured on the production line of the manufacturer that manufactures the pachinko gaming machine 1, if the main control boards 4100 for the copyrights of a plurality of types of works are mixed, the main control for the copyrights of the plurality of types of works is performed. With the boards 4100 mixed, they are sent to the game board assembly line for mounting the main control board 4100 on the game board 4. Therefore, the operator of the game board assembly line may attach the main control board 4100, which does not correspond to the game board 4 for the copyright of the work, to the game board 4. As a result, there is a problem that the production efficiency of the game board 4 is lowered.

Therefore, in the present embodiment, when the main control board 4100 is turned on (including not only when the power is turned on but also when the power is restored due to a power failure or a momentary power failure), the model of the pachinko gaming machine. In order to transmit the power-on state command including the information indicating the code to the peripheral control board 4140, in step S50, the power-on state command classified into the power-on shown in FIG. 40 and the power-on main control return destination A command and a counter notification command for determining the output of the main prize ball number information when the power is turned on are created and stored in the transmission information storage area of the main control built-in RAM as transmission information. Then, these commands are transmitted in the timer interrupt processing on the main control side, which will be described later.

As a result, the operator of the production line of the manufacturer that manufactures the pachinko gaming machine 1 turns on the main control board 4100 in the main control board inspection process, which is the inspection process of the production line, so that the inspection device becomes the main control board. Based on the information indicating the model code of the pachinko gaming machine included in the power-on state command received from the 4100, that is, the max type indicating the model type described above, which constitutes the information indicating the model code of the pachinko gaming machine, A series code for specifying which type is the middle type or the Amadeji type, a copyright code for specifying the copyright of the work, and a game specification (for example, when a probability fluctuation occurs, the next big hit In addition to the game specification that the state is continued until the game state occurs, the game specification for specifying the game specification (ST machine) that the probability fluctuation occurs when the number of fluctuations of the special symbol is limited). By visually observing the detailed model information displayed on the inspection monitor based on the code, it is possible to determine which work the main control board 4100 is for the copyright of which work, and for the copyright of the same work. Which model type (max type, middle type, and Amadeji type), and what kind of game specifications (when probability fluctuations occur, that state until the next big hit game state occurs) It is also possible to determine whether the game specification or ST machine) is to be continued. As a result, when manufacturing the main control board 4100 in the manufacturing line of the manufacturer that manufactures the pachinko gaming machine 1, even if the main control board 4100 for the copyright of a plurality of types of works is mixed, the main control board inspection of the manufacturing line is performed. The worker of the process can accurately determine the model type of the main control board 4100, the copyright of the work, and the game specifications by visually observing the inspection monitor, so that the main control board 4100 with respect to the copyright of the work can be sorted and succeeded. Can be sent to the game board assembly line. Then, the worker of the game board assembly line can surely attach the main control board 4100 corresponding to the game board 4 to the copyright of the work to the game board 4, and the main control board not corresponding to the game board 4 to the copyright of the work. It is possible to prevent a decrease in the production efficiency of the game board 4 caused by the work of attaching the 4100 to the game board 4. Therefore, it is possible to contribute to the improvement of the production efficiency of the game board 4.

[15-3. Main control side timer interrupt processing]
Next, the timer interrupt processing on the main control side will be described. This main control side timer interrupt process is repeatedly performed every interrupt cycle (4 ms in this embodiment) set in the main control side power-on process shown in FIGS. 43 and 44.

When the main control side timer interrupt process is started, the main control program on the main control board 4100 switches the register bank under the control of the main control MPU 4100a as shown in FIG. 45 (step S100). The general-purpose storage element (general-purpose register) of the main control MPU 4100a has two register banks composed of a first register bank and a second register bank. The first register bank is used in the main control main processing in the main control side power-on processing described above, while the second register bank is used in the main control side timer interrupt processing which is this routine. In step S100, since the second register bank is used in the main control side timer interrupt processing which is the main control side, the first register bank used in the main control main processing in the main control side power-on processing is the second to the second register bank. Switch the register bank to the register tank of. In this embodiment, it is not necessary to save each register on the stack when the main control side timer interrupt process, which is the routine, is started.

Following step S100, the main control program performs timer subtraction processing (step S102). In this timer subtraction process, for example, the time during which the upper special symbol display 1185 and the lower special symbol display 1186 are lit according to the variable display pattern determined by the special symbol and the special electric accessory control process described later, the normal symbol described later, and the normal symbol In addition to the time when the normal symbol display 1189 lights up according to the normal symbol variation display pattern determined by the normal electric accessory control process, the main control board 4100 (main control MPU4100a) issues various commands and the control board 4110 is normal. When determining whether or not a payer ACK signal for notifying that the signal has been received is input, time management such as the ACK signal input determination time set as the determination condition is performed. Specifically, when the fluctuation time of the fluctuation display pattern or the normal symbol fluctuation display pattern is 5 seconds, the timer interrupt cycle is set to 4 ms, so that the fluctuation time is subtracted by 4 ms each time the timer subtraction process is performed. Then, when the subtraction result becomes a value of 0, the fluctuation time of the fluctuation display pattern or the normal symbol fluctuation display pattern is accurately measured.

In this embodiment, the ACK signal input determination time is set to 100 ms. Each time this timer subtraction process is performed, the ACK signal input determination time is subtracted by 4 ms, and the subtraction result becomes a value of 0, so that the ACK signal input determination time is accurately measured. These various times and the ACK signal input determination time are stored in the time management information storage area of the main control built-in RAM as time management information.

Following step S102, the main control program performs switch input processing (step S104). In this switch input process, various signals input to the input terminals of the various input ports of the main control MPU 4100a are read and stored as input information in the input information storage area of the main control built-in RAM. Specifically, this main control program detects, for example, the detection signals from the general winning opening switches 3020 and 3020 shown in FIG. 12 for detecting the game ball that has entered the general winning opening 2104 and 2201 shown in FIG. The detection signal from the count switch 2110 shown in FIG. 12 for detecting the game ball that has entered the large winning opening 2103 shown in FIG. 8, and the game ball that has entered the upper starting port 2101 shown in FIG. A detection signal from the upper start port switch 3022 shown in FIG. 12, a detection signal from the lower start port switch 2109 shown in FIG. 12 for detecting a game ball entering the lower start port 2102 shown in FIG. 8, FIG. The detection signal from the gate switch 2352 shown in FIG. 12 for detecting the game ball passing through the gate portion 2350 shown, the detection signal from the magnetic detection switch 3024 for detecting fraudulent activity using the magnet shown in FIG. 12, and the detection signal described later. The payer ACK signal from the payout control board 4110 that conveys that the payout control board 4110 shown in FIG. 12 has normally received the prize ball command transmitted in the prize ball control process is read, and the input information is stored as input information. Store in the area. Further, the detection signal from the upper start port switch 3022 that detects the game ball that has entered the upper start port 2101 and the detection signal from the lower start port switch 2109 that detects the game ball that has entered the lower start port 2102 are read. And the corresponding start opening winning command shown in FIG. 41, which is classified into other categories, is stored as transmission information in the transmission information storage area described above. That is, if there is a detection signal from the upper start port switch 3022, the corresponding start port winning command is stored in the transmission information storage area as transmission information, and if there is a detection signal from the lower start port switch 2109, The corresponding start opening winning command is stored in the transmission information storage area as transmission information.

In the present embodiment, the detection signals from the general winning opening switches 3020 and 3020 for detecting the game balls entered in the general winning openings 2104 and 2201, and the count switch 2110 for detecting the game balls entered in the large winning openings 2103. Detection signal from, detection signal from the upper start port switch 3022 that detects the game ball that has entered the upper start port 2101, detection signal from the lower start port switch 2109 that detects the game ball that has entered the lower start port 2102. , And the detection signals from the gate switch 2352 that detects the game ball that has passed through the gate portion 2350 are first read as the first time when the switch input process is started, and after a predetermined time (for example, 10 μs) has elapsed. The second time, each is read again. Then, the result read for the second time and the result read for the first time are compared. It is determined whether or not any of the comparison results has the same result. If the result is not the same, it is read again as the third time, and the result read in the third time is compared with the result read in the second time. It is determined again whether or not any of the comparison results has the same result. If the result is not the same, it is read again as the fourth time, and the result read at the fourth time is compared with the result read at the third time. It is determined again whether or not any of the comparison results has the same result. If the result is the same, it is treated as if there is no entry of the game ball.

As described above, in the switch input process, the main control program first outputs the detection signals from the general winning port switches 3020 and 3020, the count switch 2110, the upper start port switch 3022, the lower start port switch 2109, and the gate switch 2352. False detection due to the effects of chattering, noise, etc. by performing a total of 2 readings, 2 readings for comparison over the 3rd time and 2 readings for comparison over the 2nd to 4th times. The reliability of the detection signals from the general winning port switches 3020 and 3020, the count switch 2110, the upper start port switch 3022, the lower start port switch 2109, and the gate switch 2352 is improved. be able to.

Following step S104, the main control program performs the winning random number update process (step S106). In this winning random number update process, the above-mentioned random number for the big hit symbol and the random number for the small hit symbol are updated. Further, in addition to these random numbers, the random number for determining the initial value for the jackpot symbol, which is updated by the non-winning random number update process in step S56 in the main control side power-on processing (main control side main process) shown in FIG. And the random number for determining the initial value for the small hit symbol is also updated. These random numbers for determining the initial value for the big hit symbol and the random numbers for determining the initial value for the small hit symbol are updated in the main control side main process and the main control side timer interrupt process, respectively, to further enhance the randomness. .. On the other hand, since the big hit symbol random number and the small hit symbol random number are random numbers related to the winning determination (big hit determination), each counter counts up only every time the winning random number update process is performed. The above-mentioned random number for determining the normal symbol hit and the random number for determining the initial value for determining the normal symbol hit are also updated by this winning random number update process.

For example, the counter that updates the random number for normal symbol hit determination is an initial value update type counter as described above, and is updated within a predetermined fixed numerical value range from the minimum value to the maximum value, and this minimum value. The range from to the maximum value is counted up by adding a value of 1 each time the main control side timer interrupt process is performed. The random number for determining the initial value for determining the normal symbol hit is counted up toward the maximum value, and then the random number for determining the initial value for determining the normal symbol hit is counted up from the minimum value. When the counter finishes counting up the range from the minimum value to the maximum value of the normal symbol hit judgment random number, the big hit judgment initial value determination random number is updated by this winning random number update process. The random number for determining the initial value for determining the normal symbol hit can be obtained by executing the initial value lottery process for drawing one value from the fixed numerical value range of the counter that updates the random number for determining the normal symbol hit. ..

In the present embodiment, the random number for determining the initial value for the big hit symbol and the random number for determining the initial value for the small hit symbol are not used in step S56 in the main control side power-on processing (main control side main process) shown in FIG. The winning random number is updated in the winning random number update processing and the winning random number update processing in step S106 in the main control side timer interrupt processing of this routine, but the processing time of this routine becomes uneven every time the interrupt timer occurs. If the number of executions of the non-winning random number update process in step S56 becomes random by repeatedly executing the main control side main process within the remaining time until the interrupt timer is generated, the random number for determining the initial value for the jackpot symbol , And the random number for determining the initial value for the small hit symbol may be updated only in the non-winning random number update process in step S56.

Following step S106, the main control program performs the prize ball control process (step S108). In this prize ball control process, the prize ball command shown in FIG. 39 for reading the input information from the above-mentioned input information storage area and paying out the game ball based on the input information can be created, or with the main control board 4100. The self-check command shown in FIG. 39 for confirming the connection state between the payout control board 4110 and the board is created. Then, the created prize ball command and self-check command are transmitted to the payout control board 4110 as main payment serial data. For example, when one game ball enters the large prize opening 2103 shown in FIG. 8, a prize ball command for paying out 15 balls as a prize ball is created, and the number of game balls to be paid out as a prize ball. Has reached 10 balls, so in order to convey that, the output of the main prize ball number information output signal is set, stored as output information in the output information storage area, and the prize ball command is transmitted to the payout control board 4110. Or, when the payer ACK signal indicating that the payout control board 4110 has normally received the prize ball command is not input within a predetermined time, the connection state between the main control board 4100 and the payout control board 4110 is confirmed. Create a self-check command to send to the payout control board 4110.

Further, in the prize ball control process of step S108, when the number of game balls to be paid out as prize balls has reached 10 based on the input information read from the above-mentioned input information storage area. In order to convey that fact, a main prize ball number information output command, which is classified into other categories shown in FIG. 41, is created and stored in the transmission information storage area as transmission information. The main prize ball number information output command is created based on the value of the main prize ball number information output determination counter. The value of the main prize ball number information output determination counter is based on the input information read from the above-mentioned input information storage area, that is, the upper start port 2101 and the lower start port 2102 provided on the game board 4. The number of game balls to be paid out as prize balls is counted based on the game balls entered in various prize openings such as the general prize openings 2104 and 2201 and the large prize openings 2103, and the prize in step S108. In the ball control process, the memory is updated in the prize ball schedule information storage area of the main control built-in RAM. In the prize ball control process of step S108, the value of the main prize ball number information output determination counter stored in the prize ball schedule information storage area of the main control built-in RAM is read, and the read main prize ball number information output determination counter is read. The input information is read from the above-mentioned input information storage area, the number of game balls to be paid out as prize balls is added to the value of, and the value indicating the added number of balls is the value 10. When the number exceeds (that is, when the number of game balls to be paid out as prize balls has reached 10), a main prize ball number information output command is created to notify that fact, and as transmission information. It is stored in the output information storage area, and the value indicating the excess number of balls is stored and updated in the prize ball schedule information storage area of the main control built-in RAM as the value of the counter for determining the number of main prize balls. It has become.

Following step S108, the main control program performs frame command reception processing (step S110). On the payout control board 4110, the payout control program has various 1-byte (8-bit) commands (for example, a frame state 1 command, an error release navigation command, and a frame state 2 command) classified into the status display shown in FIG. 42. To send. On the other hand, as will be described later, the payout control program outputs an error occurrence command when an error occurs in the payout operation, or outputs an error release navigation command based on the detection signal of the operation switch 860a. In the frame command reception process described above, when the main control program normally receives these various commands as payer serial data, the information that conveys that fact to the payout control board 4110 is stored as output information in the main control built-in RAM. Store in the area. In addition, the main control program formats the command normally received as the payer serial data into a 2-byte (16-bit) command (various commands classified into the status display in FIG. 41 (frame status 1 command, error cancellation). Navi command and frame state 2 command)) are stored in the transmission information storage area described above as transmission information. The frame state 1 command referred to here corresponds to the first error occurrence command, and the error release navigation command corresponds to the first error release command.

Following step S110, the main control program performs fraud detection processing (step S112). In this fraud detection process, an abnormal state related to the prize ball is confirmed. For example, when the input information is read from the above-mentioned input information storage area and the detection signal from the count switch 2110 is input when the game is not in the big hit game state (when the game ball enters the big winning opening 2103). , A winning abnormality display command classified into the notification display shown in FIG. 41 as an abnormal state is created, and stored as transmission information in the transmission information storage area described above.

Following step S112, the main control program performs special symbol and special electric accessory control processing (step S114). In this special symbol and special electric accessory control process, a latch signal is output to the main control built-in hard random number circuit 4100an shown in FIG. 12, and the random number extracted by the main control built-in hard random number circuit 4100an when the latch signal is input. (Random number value) is acquired from the hard random number latch register built in the main control built-in main control MPU4100a, and the acquired random number value is set as a random number for jackpot determination. Then, whether or not the random number for jackpot determination (that is, the random number value acquired from the hard random number latch register built in the main control built-in main control MPU4100a) and the jackpot determination value stored in advance in the main control built-in ROM match. (Determining whether or not to generate a jackpot game state (referred to as "special lottery")), or taking out the value of the counter that updates the random number for the jackpot symbol and storing it in the main control built-in ROM in advance. It is determined whether or not it matches the probability variation hit determination value (determination of whether or not a probability fluctuation is generated). Here, the "probability fluctuation" means that the probability of a big hit changes to a high probability (probability change) set higher than that in the normal time (low probability). In the present embodiment, the value 32668 to the value 32767 are set as the above-mentioned jackpot determination value range (big hit determination range) with a low probability, and are read from the normal judgment table, whereas the value 31768 with a high probability. ~ Value 32767 is set and is read from the probability change determination table. As described above, in the special symbol and special electric accessory control process in step S114, the big hit determination random number (that is, the random number value acquired from the hard random number latch register built in the main control built-in main control MPU4100a) and the main control built-in. When determining whether or not the jackpot determination value stored in the ROM matches, the random number for jackpot determination (that is, the random number value acquired from the hard random number latch register built in the main control built-in main control MPU4100a). Is included in the jackpot judgment range.

When these determination results are based on the upper start port switch 3022, various commands related to the special figure 1 synchronization effect shown in FIG. 40 are created, while the lottery results are based on the lower start port switch 2109. In, various commands related to the special figure 2 synchronization effect shown in FIG. 40 are created and stored as transmission information in the transmission information storage area, and the upper special symbol display 1185 or the lower is stored according to the determined variation display pattern of the special symbol. The output of the lighting signal to the upper special symbol display 1185 or the lower special symbol display 1186 is set so as to light the special symbol display 1186, and the output information is stored in the above-mentioned output information storage area. Further, depending on the game state to be generated, for example, when a big hit game state is reached, various commands classified as related to the big hit shown in FIG. 40 (big hit opening command, big winning opening 1 opening Nth display command, big winning opening 1). A closing display command, a big winning opening 1 count display command, a big hit ending command, and a big hit symbol display command) are created and stored in the transmission information storage area as transmission information, or the opening / closing member 2107 shown in FIG. 8 is opened / closed. When the output of the drive signal to the attacker solenoid 2108 is set and stored as output information in the output information storage area, or when the number of times (round) that the large winning opening 2103 is opened from the closed state is two times, the figure is shown in the figure. The output of the lighting signal to the 2-round indicator lamp 1190a is set so as to light the 2-round indicator lamp 1190a of the round indicator 1190 shown in No. 11, and the output information is stored in the output information storage area, or the round is performed 15 times. At one time, the output of the lighting signal to the 15-round indicator lamp 1190b is set so as to turn on the 15-round indicator lamp 1190b of the round indicator 1190 shown in FIG. 11, and the output information is stored in the output information storage area or the probability. The output of the lighting signal to the game status indicator 1183 is set so that the presence or absence of fluctuation is lit in a predetermined color, and is stored in the output information storage area as output information.

Following step S114, the main control program performs a normal symbol and a normal electric accessory control process (step S116). In this ordinary symbol and ordinary electric accessory control process, input information is read from the above-mentioned input information storage area, and gate winning processing is performed based on this input information. In this gate winning process, it is determined from the input information whether or not the detection signal from the gate switch 2352 has been input to the input terminal. Based on this determination result, when the detection signal is input to the input terminal, the value of the counter that updates the above-mentioned normal symbol hit determination random number is extracted and used as the gate information in the gate information storage area of the main control built-in RAM. Remember in.

The gate information storage area is provided with 0th to 3rd sections (4 sections), and gate information is stored in the order of 0th section, 1st section, 2nd section, and 3rd section. It has become like. For example, when the gate information is stored in the 0th to 2nd sections of the gate information storage, the gate information is stored in the 3rd section of the gate information storage when the detection signal from the gate switch 2352 is input to the input terminal. do.

The gate information stored in the 0th section of the gate information storage is set in the work area of the main control built-in RAM. When this gate information is set, the gate information of the first section of the gate information storage is in the 0th section of the gate information storage, and the gate information of the second section of the gate information storage is in the first section of the gate information storage. The gate information of the third section of the information storage is shifted to the second section of the gate information storage, and the third section of the gate information storage becomes an empty area. For example, when the gate information is stored in the first to second sections of the gate information storage, the gate information of the first section of the gate information storage is stored in the 0th section of the gate information storage, and the gate information storage is the first. The gate information of the two sections is shifted to the first section of the gate information storage, and the second section of the gate information storage and the third section of the gate information storage become free areas. Here, when the gate information is stored in the first to third sections of the gate information storage, the above-mentioned gate information is set so that the normal symbol storage display 1188 is turned on with the total number of the stored gate information as the holding ball. The output of the lighting signal of the normal symbol storage display 1188 is set based on the above, and is stored in the output information storage area described above as output information.

Following the gate winning process, the gate information set in the work area of the main control built-in RAM is read, and the value of the random number for normal symbol hit determination is taken out from the read gate information and stored in advance in the main control built-in ROM. It is judged whether or not it matches the judgment value per normal symbol (referred to as "normal lottery"). Whether or not to open and close the movable piece 2106 is determined based on this determination result (lottery result by ordinary lottery). When the opening / closing operation is performed by this determination, the pair of movable pieces 2106 are in a state of being expanded in the left-right direction, so that the game ball can be accepted into the lower starting port 2102, which is advantageous for the player. It becomes a game state. The variation display pattern of the normal symbol corresponding to this determination is determined based on the above-mentioned random number for the normal symbol variation display pattern, and various commands classified in relation to the normal symbol synchronization effect shown in FIG. 40 are created and used as transmission information. In addition to storing in the transmission information storage area described above, the output of the lighting signal to the normal symbol display 1189 is set so as to light the normal symbol display 1189 according to the determined variation display pattern of the normal symbol, and the output information is described above. It is stored in the output information storage area. Further, for example, when the value of the extracted normal symbol hit determination random number matches the normal symbol hit determination value stored in advance in the main control built-in ROM, various commands related to the normal electric service effect shown in FIG. 40 Is created and stored in the transmission information storage area as transmission information, and the output of the drive signal to the start port solenoid 2105 is set so as to open and close the movable piece 2106, and is stored in the output information storage area described above as output information. On the other hand, when the value of the extracted normal symbol hit judgment random number does not match the normal symbol hit judgment value stored in advance in the main control built-in ROM, the normal symbol is based on the above-mentioned normal symbol variation display pattern random number. A variable display pattern is determined, various commands classified in relation to the normal symbol synchronization effect shown in FIG. 40 are created, stored as transmission information in the above-mentioned transmission information storage area, and according to the determined normal symbol variation display pattern. The output of the lighting signal to the normal symbol display 1189 is set so as to light the normal symbol display 1189, and the output information is stored in the above-mentioned output information storage area.

Following step S116, the main control program performs port output processing (step S118). In this port output process, output information is read from the output information storage area described above from the output terminals of various output ports of the main control MPU 4100a, and various signals are output based on this output information. This main control program, for example, outputs a main payment ACK signal when various commands from the payout control board 4110 are normally received from the output terminal of a predetermined output port of the main control MPU 4100a based on the output information. A drive signal is output to the attacker solenoid 2108 that opens and closes the opening and closing member 2107 of the big winning opening 2103, and a drive signal is output to the starting port solenoid 2105 that opens and closes the movable piece 2106 when the big hit game state is in effect. In addition to outputting, 15 round jackpot information output signal, 2 round jackpot information output signal, probability fluctuation information output signal, special symbol display information output signal, normal symbol display information output signal, time saving medium information output signal, start Various information (game information) signals related to the game, such as a winning information output signal, are output to the payout control board 4110.

Following step S118, the main control program performs peripheral control board command transmission processing (step S120). In this peripheral control board command transmission process, the main control program reads transmission information from the transmission information storage area described above and transmits this transmission information as main peripheral serial data to the peripheral control board 4140. This transmission information includes various commands classified in the special figure 1 synchronization effect-related and various types classified in the special figure 2 synchronization effect-related, as shown in FIG. 40, created by the main control side timer interrupt process of this routine. A big prize is won based on the detection signal from the count switch 2110 (see FIG. 12) when a game ball that has entered the big prize opening 2103 (see FIG. 8) is detected by various commands classified into commands and big hits. Large prize opening 1 count display command equivalent to the mouth count command), various commands classified as power-on, various commands classified as related to the normal electric power production, various commands classified as related to the normal electric role production, Fig. 41 Various commands classified into the notification display (door open command, door frame close command, main body frame open command, main body frame close command, etc.) and various commands classified into the status display (frame state 1 command, error cancellation) shown in Navi command and frame state 2 command), various commands classified as test-related, and various commands classified as others (for example, the main control board 4100 has an upper starting port 2101, a lower starting port 2102, a general winning port 2104, 2201, etc. And every time the number of game balls to be paid out as prize balls based on the game balls entered in various prize openings such as the large prize opening 2103 reaches 10, that fact is used as the main prize ball number information. The main prize ball number information output command, etc., which instructs the hall computer to transmit the number information output signal via the external terminal board 784) is stored. One packet of the main peripheral serial data is composed of 3 bytes. Specifically, the main peripheral serial data has a status indicating the type of command having a storage capacity of 1 byte (8 bits), a mode indicating a variation of an effect having a storage capacity of 1 byte (8 bits), and a status. It is composed of a sum value obtained by regarding the mode as a numerical value and the sum of the sum values, and this sum value is created at the time of transmission.

In this peripheral control board command transmission process, the main control program transmits various commands as main peripheral serial data to the peripheral control board 4140 in the order of status, mode, and sum value. As described above, the charged charge to the electrolytic capacitor MC2 shown in FIG. 21 is applied as + 5V to the VDD terminal, which is the power supply terminal of the main control MPU4100a, in the event of a power failure or a momentary power failure. Therefore, the main peripheral serial transmission port 4100ae built in the main control MPU 4100a shown in FIG. 23 shifts at least the command set by the main control CPU core 4100aa in the transmission buffer register 4100aeb by the serial management unit 4100aec. It can be transferred to the register 41aea and transmitted from the transmission shift register 4100aea as main peripheral serial data. When the power is turned on to the pachinko game machine 1, or when the power is restored due to a power failure or a momentary power failure after the power is turned on, when the power is turned on in step S50 in the main control side power-on processing shown in FIG. In the reservation setting of the command to be transmitted, in order to notify that the power has been restored, the power-on state command, the power-on main control return destination command, and the power-on main prize ball, which are classified into power-on, are shown in FIG. Since a counter notification command for determining the number information output is created and stored as transmission information in the transmission information storage area of the main control built-in RAM, the status, mode, and status command that configure the power-on status command as main circumference serial data Then, it is transmitted to the peripheral control board 4140 in the order of the sum value, then transmitted to the peripheral control board 4140 in the order of the status, mode, and thumb value that configure the main control return destination command when the power is turned on, and then the power is turned on. When the main prize ball number information output determination counter The notification command is transmitted to the peripheral control board 4140 in the order of status, mode, and sum value. In the transmission information storage area of the main control built-in RAM, various information is read from the game backup information and responds to the various information in the setting of the work area of the main control built-in RAM in step S34 in the process when the power is turned on on the main control side. Various commands may be stored. In such a case, first, after the transmission of various commands according to the game information is completed, the power-on state command, the power-on main control return destination command, and the power-on main prize ball number information The output judgment counter notification command will be sent.

In this peripheral control board command transmission process, when the main control program receives the frame state 1 command (first error occurrence command) from the payout control board 4110 through the receiving port of the RXA terminal, the peripheral control board 4140 (effect control unit) ) Is sent a frame state 1 command (second error occurrence command) (error command sending means). In this case, the main control program transfers the frame state 1 command in the form shown in FIG. 42 received from the payout control board 4110 to the peripheral control board 4140 as the frame state 1 command in the form shown in FIG. 41.

On the other hand, in this peripheral control board command transmission process, when the main control program receives an error release navigation command (first error release command) from the payout control board 4110 through the receiving port of the RXA terminal, the peripheral control board 4140 The error release navigation command (second error release command) is transmitted to (error command transmission means). In this case, the main control program transfers the error release navigation command in the form shown in FIG. 42 received from the payout control board 4110 to the peripheral control board 4140 as the error release navigation command in the form shown in FIG. 41.

Furthermore, in this peripheral control board command transmission process, when the main control program receives the main body frame opening command (first main body frame opening command) from the payout control board 4110 through the receiving port of the RXA terminal, the peripheral control board 4140 A main body frame opening command (second main body frame opening command) is transmitted to (effect control unit) (main body frame command sending means, second main body frame sending means). In this case, the main control program transfers the main body frame opening command in the form shown in FIG. 42 received from the payout control board 4110 to the peripheral control board 4140 as the main body frame opening command in the form shown in FIG. 41. On the other hand, in this peripheral control board command transmission process, when the main control program receives the main body frame closing command (first main body frame closing command) from the payout control board 4110 by the receiving port of the RXA terminal, the peripheral control board 4140 (1st main body frame closing command) A main body frame closing command (second main body frame closing command) is transmitted to the effect control unit) (main body frame command sending means, second main body frame command sending means). In this case, the main control program transfers the main body frame closing command in the form shown in FIG. 42 received from the payout control board 4110 to the peripheral control board 4140 as the main body frame closing command in the form shown in FIG. 41.

Further, in this peripheral control board command transmission process, when the main control program receives a door opening command (first door opening command) from the payout control board 4110 through the receiving port of the RXA terminal, the peripheral control board 4140 (effect control) A door opening command (second door frame opening command) is transmitted to (part) (door frame command sending means, second door frame command sending means). In this case, the main control program transfers the door frame closing command in the form shown in FIG. 42 received from the payout control board 4110 to the peripheral control board 4140 as the door closing command in the form shown in FIG. 41. On the other hand, in this peripheral control board command transmission process, when the main control program receives a door closing command (first door closing command) from the payout control board 4110 through the receiving port of the RXA terminal, the peripheral control board 4140 (effect control) A door closing command (second door closing command) is transmitted to (part) (door frame command sending means, second door frame command sending means). In this case, the main control program transfers the door closing command in the form shown in FIG. 42 received from the payout control board 4110 to the peripheral control board 4140 as the door closing command in the form shown in FIG. 41.

Following step S120, the main control program clears the main control built-in WDT4100af shown in FIG. 12 (step S122), and ends this routine. The main control built-in WDT4100af in step S22 is cleared by setting the timer clear set value in the WDT clear register built in the main control MPU4100a. As a result, the timekeeping by the WDT4100af with built-in main control is cleared. Then, by restarting the time counting by the main control built-in WDT4100af, the main control MPU4100a is not forcibly reset by the main control built-in WDT4100af.

As described above, the main control board 4100 is used to store the game information due to the progress of the game before the power to the pachinko gaming machine 1 is cut off during the progress of the game. The backup process can be executed and completed, and at the time of power recovery, the power supply to the pachinko gaming machine 1 is turned on based on the game information on which the backup process is executed as the return destination of the progress of the game by the main control board 4100. Peripheral control of the main control return destination command at power-on in FIG. 40 that indicates the drive state of the start port solenoid 2105 and the attacker solenoid 2108, which are the electrical drive sources by the port output process in step S118 in this routine when the power is cut off. It can be output to the board 4140. That is, the main control board 4100 is mainly used in setting the work area of the main control built-in RAM in step S34 in the reserved setting of the command to be transmitted when the power is turned on in step S50 in the main control side power-on processing in FIG. Based on the power recovery information set in the work area of the control built-in RAM, in order to notify that the power has been turned on (power recovery), the power on state command classified into the power on in FIG. 40, the power on main A control return destination command and a counter notification command for determining the main prize ball number information output when the power is turned on are created and stored as transmission information in the transmission information storage area of the main control built-in RAM, and the peripheral control board command in step S120 in this routine. In the transmission process, as main peripheral serial data, the power-on state command is transmitted to the peripheral control board 4140 in the order of status, mode, and sum value, and then the power-on main control return destination command is configured. , Status, mode, and thumb value are sent to the peripheral control board 4140 in that order, and then the status, mode, and thumb value are used to configure the counter notification command for determining the main prize ball number information output when the power is turned on. It is transmitted to the control board 4140. Therefore, the peripheral control board 4140 sets the return destination of the progress of the game by the main control board 4100 at the time of power restoration to the liquid crystal display device 1900 on the game board side based on the main control return destination command when the power is turned on from the main control board 4100. The effect can be displayed in the display area of. As a result, when a momentary power failure or power failure occurs while the player is playing a game and then the power is restored, the gaming state immediately before the momentary power failure or power failure is quickly restored after the power is restored. In addition, the return destination of the progress of the game by the main control board 4100 can be displayed and notified in the display area of the liquid crystal display device 1900 on the game board side, so that the system of the pachinko game machine 1 is in a solid state, that is, so-called. It is possible to prevent the player from being mistaken for a failure when the player sees the frozen state. Therefore, it is possible to prevent the player from being mistaken for a failure by promptly returning to the gaming state immediately before the momentary power failure or power failure after the power is restored.

Further, in the main control board inspection process, which is the inspection process of the production line of the main control board 4100, when the main control board 4100 is first turned on after being manufactured for inspection, as described above, FIG. 43 shows. In step S38 in the process when the power is turned on on the main control side, the entire area of the main control built-in RAM is surely cleared. As a result, when the reservation setting of the command to be transmitted at the time of power-on is made in the reservation setting of the command to be transmitted at the time of power-on in step S50 in the same process, the power-on state command classified into the power-on shown in FIG. 40 , When the power is turned on, the main control return destination command when the power is turned on, and the counter notification command for determining the main prize ball number information output when the power is turned on are created and stored as transmission information in the transmission information storage area of the main control built-in RAM. A state in which only three commands, a status command, a main control return destination command when the power is turned on, and a counter notification command for determining the main prize ball number information output when the power is turned on, are stored in the transmission information storage area of the main control built-in RAM as transmission information. In the peripheral control board command transmission process in step S120 in this routine, the main control board inspection device is used as the main control board inspection process in the order of status, mode, and sum value that configure the power-on state command as main peripheral serial data. It is transmitted to the inspection device in the main control board inspection process in the order of status, mode, and sum value, which constitutes the main control return destination command when the power is turned on, and then the main prize ball number information is output when the power is turned on. The judgment counter notification command is sent to the inspection device in the main control board inspection process in the order of status, mode, and sum value. The inspection device in the main control board inspection process is based on the information indicating the model code of the pachinko gaming machine included in the power-on state command received from the main control board 4100, that is, the information indicating the model code of the pachinko gaming machine. A series code for specifying which of the above-mentioned max type, middle type, and amadeji type indicating the model type, and a copyright code for specifying the copyright of the work, Game specifications (For example, when a probability fluctuation occurs, in addition to the game specification that the state is continued until the next big hit game state occurs, the game specification that the probability fluctuation occurs in a state where the number of fluctuations of the special symbol is limited. Based on the game specification code for specifying (ST machine), etc.), detailed model information is displayed on the inspection monitor of the main control board inspection process.

[16. Various control processes for payout control boards]
Next, various control processes performed by the payout control board 4110 shown in FIG. 13 will be described with reference to FIGS. 46 to 62. FIG. 46 is a flowchart showing an example of the power-on processing of the payout control unit, FIG. 47 is a flowchart showing the continuation of the power-on processing of the payout control unit, and FIG. 48 shows the payout control unit following FIG. 47. FIG. 49 is a flowchart showing the continuation of the power-on processing, FIG. 49 is a flowchart showing an example of the payout control unit timer interrupt processing, FIG. 50 is a flowchart showing an example of the rotation angle switch history creation processing, and FIG. 51 is a sprocket. FIG. 52 is a flowchart showing an example of the fixed position determination skip process, FIG. 52 is a flowchart showing an example of the ball squeeze determination process, and FIG. 53 is a flowchart showing an example of the prize ball stock number addition process for the prize ball. 54 is a flowchart showing an example of the prize ball stock number addition process for lending, FIG. 55 is a flowchart showing an example of the stock monitoring process, and FIG. 56 is a flowchart showing an example of the payout ball motion determination setting process. FIG. 57 is a flowchart showing an example of the payout setting process, FIG. 58 is a flowchart showing an example of the ball-shaped motion setting process, and FIG. 59 is a flowchart showing an example of the retry operation monitoring process, FIG. 60. Is a flowchart showing an example of the inconsistency counter reset determination process, FIG. 61 is a flowchart showing an example of the error release operation determination process, and FIG. 62 is a signal process (a) at the time of payout operation by ball lending, from the CR unit. It is a timing chart which shows the input signal confirmation processing (a) of.

First, the payout control unit power-on processing will be described, followed by the payout control unit timer interrupt processing, rotation angle switch history creation processing, sprocket fixed position determination skip processing, ball squeeze determination processing, and prize ball stock number addition. Processing, ball rental prize ball stock number addition processing, stock monitoring processing, payout ball movement judgment setting processing, payout setting processing, ball movement setting processing, retry operation monitoring processing, inconsistency counter reset judgment processing, error cancellation The operation determination process will be described. In addition, rotation angle switch history creation processing, sprocket fixed position judgment skip processing, ball shaving judgment processing, prize ball stock number addition processing for prize ball stock number addition processing, stock monitoring processing, payout ball shaving The operation determination setting process, retry operation monitoring process, inconsistency counter reset determination process, and error release operation determination process are performed as one process of the main operation setting process in step S562 in the payout control unit power-on process, which will be described later, and have a rotation angle. Switch history creation processing, sprocket fixed position judgment skip processing, ball bending judgment processing, retry operation monitoring processing, inconsistency counter reset judgment processing, error cancellation operation judgment processing, prize ball stock number addition processing, ball rental prize The priority is set in the order of the ball stock number addition process, the stock monitoring process, and the payout ball motion determination setting process.

[16-1. Discharge control unit power-on processing]
When the power is turned on to the pachinko gaming machine 1, in the payout control unit 4120 on the payout control board 4110, the payout control program controls the payout control MPU 4120a, as shown in FIGS. Performs on-time processing. When the payout control unit power-on processing is started, the payout control program sets the interrupt mode for the payout control MPU4120a (step S500). This interrupt mode sets the priority of the interrupt of the payout control MPU4120a. In the present embodiment, the payout control unit timer interrupt process, which will be described later, is set to have the highest priority, and when an interrupt of the payout control unit timer interrupt process occurs, the process is preferentially performed.

Following step S500, the payout control program performs input / output settings (I / O input / output settings) (step S502). In this I / O input / output setting, various input ports and various output ports of the payout control MPU4120a are set.

Following step S502, the payout control program performs wait timer processing 1 (step S506) and determines whether or not a power failure warning signal has been input (step S508). The voltage does not rise immediately from the time the power is turned on until the specified voltage is reached. On the other hand, when a power failure or a momentary power failure (a phenomenon in which the power supply is temporarily stopped) occurs, the voltage drops, and when the voltage becomes smaller than the power failure warning voltage, the power failure monitoring circuit 4100e of the main control board 4100 shown in FIG. A warning signal (payout power failure warning signal) is input. Similarly, when the voltage becomes smaller than the power failure warning voltage between the time when the power is turned on and the voltage rises to a predetermined voltage, a power failure warning signal (payout power failure warning signal) is input from the power failure monitoring circuit 4100e of the main control board 4100. Therefore, the wait timer process 1 in step S506 is a process for waiting until the voltage becomes larger than the power failure warning voltage and stabilizes after the power is turned on. In the present embodiment, the waiting time (wait timer) is 200 milliseconds (waiting timer). ms) is set. The determination in step S508 is performed based on the power failure warning signal (payout power failure warning signal) from the power failure monitoring circuit 4100e of the main control board 4100.

Following step S508, the payout control program determines whether or not the operation switch 860a is being operated (step S512). This determination is based on the logical value of the operation signal from the operation switch 860a, and it is determined that the operation switch does not instruct to clear the RAM when the logical value of the operation signal from the operation switch 860a is HI. While it is determined that the 860a is not operated, it is determined that when the logical value of the operation signal from the operation switch 860a is LOW, it is determined that the RAM is cleared and the operation switch 860a is operated. judge.

When the operation switch 860a is operated in step S512, the payout control program sets the payout RAM clear notification flag HRCL-FLG to a value of 1 (step S514). That is, the payout control program can execute a RAM clear process that initializes the RAM built in the payout control MPU 4120a (hereinafter, referred to as "payout control built-in RAM") for a predetermined time from the time when the power is turned on. (Delivery control side power-on operation control means). On the other hand, when the operation switch 860a is not operated in step S512, the payout control program sets the payout RAM clear notification flag HRCL-FLG to a value 0 (step S516). The payout RAM clear notification flag HRCL-FLG is stored in the payout control built-in RAM (payout storage unit) of the payout control MPU4120a, for example, various flags, various information stored in various information storage areas (for example, various information). The prize ball stock number PBS, the actual ball count PB, the drive command number DRV, the inconsistency counter INCC, etc. stored in the prize ball information storage area, and the logic of the PRDY signal stored in the CR communication information storage area. It is a flag indicating whether or not to delete the payout information related to the payout of the PRDY signal output setting information whose status is set), and is set to a value of 1 when the payout information is erased and a value of 0 when the payout information is not erased. Will be done. The payout RAM clear notification flag HRCL-FLG set in steps S514 and S516 is stored in the general-purpose storage element (general-purpose register) of the payout control MPU4120a.

Following step S514 or step S516, the payout control program sets to allow access to the payout control built-in RAM (step S518). With this setting, the RAM with built-in payout control can be accessed, and for example, payout information can be written (stored) or read out.

Following step S518, the payout control program sets the stack pointer (step S520). The stack pointer indicates, for example, the address on the stack for temporarily storing the contents of the storage element (register) in use, or temporarily returns the return address of this routine when the subroutine is terminated and returned to this routine. It indicates the address stacked on the stack for storage, and the stack pointer advances each time the stack is stacked. In step S520, the initial address is set in the stack pointer, and the contents of the register, the return address, and the like are pushed onto the stack from this initial address. Then, the stack pointer returns to the initial address by reading in order from the last stacked stack to the first stacked stack.

Following step S520, the payout control program determines whether or not the payout RAM clear notification flag HRCL-FLG has a value of 0 (step S522). As described above, the payout RAM clear notification flag HRCL-FLG is set to a value 1 when the payout information is erased and a value 0 when the payout information is not erased.

When the payout RAM clear notification flag HRCL-FLG has a value of 0 in step S522, that is, when the payout information is not erased, the payout control program calculates the checksum (step S524). This checksum considers the payout information stored in the payout control built-in RAM as a numerical value and calculates the total.

Following step S524, the payout control program determines whether or not the calculated checksum value matches the checksum value stored in the payout control unit power cutoff process (when the power is turned off), which will be described later. (Step S526). When they match, the payout control program determines whether or not the payout backup flag HBK-FLG has a value of 1 (step S528). The payout backup flag HBK-FLG is a flag indicating whether or not the payout backup information such as the payout information and the checksum value is stored and held in the payout control built-in RAM in the payout control unit power cutoff process described later, and is paid out. The value is set to 1 when the control unit power off processing is normally completed, and is set to 0 when the payout control unit power off processing is not normally completed.

When the payout backup flag HBK-FLG has a value of 1 in step S528, that is, when the payout control unit power off processing is normally completed, the payout control program sets the work area of the payout control built-in RAM as the time of power recovery. (Step S530). In this setting, in addition to setting the value 0 to the payout backup flag HBK-FLG, the power recovery information is read from the ROM built in the payout control MPU4120a (hereinafter, referred to as “payout control built-in ROM”). Then, this power recovery information is set in the work area of the payout control built-in RAM. As a result, various flags, various information stored in various information storage areas, etc. (for example, prizes stored in the prize ball information storage area), which are the above-mentioned payout backup information stored in the payout control built-in RAM. Ball stock number PBS, actual ball count PB, drive command number DRV, inconsistency counter INCC, etc., and PRDY signal output setting information in which the logical state of the PRDY signal is set, which is stored in the CR communication information storage area. Information to be used for various processes is set based on the payout information related to the payout of the inconsistency counter reset determination time stored in the time management information storage area. The term "recovery" includes not only the state in which the power is turned on from the state in which the power is cut off, but also the state in which the power is restored after the power failure or momentary power failure.

On the other hand, when the payout RAM clear notification flag HRCL-FLG is not a value 0 (value 1) in step S522, that is, when the payout information is deleted, or when the checksum values do not match in step S526, or step. When the payout backup flag HBK-FLG is not a value 1 (value 0) in S528, that is, when the payout control unit power off processing is not normally completed, the payout control program covers the entire area of the payout control built-in RAM. Clear (step S532). That is, the payout control program executes the payout control side RAM clear process when the operation signal of the operation switch 860a is detected (the payout control side power-on operation control means). As a result, the payout backup information stored in the payout control built-in RAM is cleared.

Following step S532, the payout control program sets the work area of the payout control built-in RAM as an initial setting (step S534). This setting reads the initial information from the payout control built-in ROM and sets this initial information in the work area of the payout control built-in RAM.

Following step S530 or step S534, the payout control program performs interrupt initialization (step S536). This setting sets the interrupt cycle when the payout control unit timer interrupt process, which will be described later, is performed. In this embodiment, it is set to 2 ms.

Following step S536, the payout control program sets the interrupt enable setting (step S538). With this setting, the payout control unit timer interrupt process is repeatedly performed every 2 ms, that is, the interrupt cycle set in step S536.

Following step S538, the payout control program sets the value A in the watchdog timer clear register HWCL (step S539). The watchdog timer is set to clear by setting the value A, the value B, and the value C in order in the watchdog timer clear register HWCL.

Following step S539, the payout control program determines whether or not a power failure warning signal (payout power failure warning signal) has been input (step S540). As described above, when the power supply of the pachinko gaming machine 1 is cut off, or a power failure or momentary power failure occurs, when the voltage becomes equal to or lower than the power failure warning voltage, a power failure warning signal (payout power failure warning signal) is used as the main control board. It is input from the power failure monitoring circuit 4100e of 4100. The determination in step S540 is performed based on this power failure warning signal.

When there is no input of the power failure warning signal in step S540, the payout control program determines whether or not the 2 ms elapsed flag HT-FLG has a value of 1 (step S542). This 2 ms elapsed flag HT-FLG is a flag that clocks 2 ms in the payout control unit timer interrupt process that is processed every 2 ms, which will be described later, and sets a value of 1 when 2 ms has elapsed and a value of 0 when 2 ms has not elapsed. Set.

When the value of the 2 ms elapsed flag HT-FLG is 0 in step S542, that is, when 2 ms has not elapsed, the process returns to step S540, and the payout control program determines whether or not a power failure warning signal (payout power failure warning signal) has been input. To judge.

On the other hand, when the 2 ms elapsed flag HT-FLG has a value of 1 in step S542, that is, when 2 ms has elapsed, the payout control program sets the value 0 to the 2 ms elapsed flag HT-FLG (step S544).

Following step S544, the payout control program sets the value B in the watchdog timer clear register HWCL (step S546). At this time, the value B is set in the watchdog timer clear register HWCL following the value A set in step S539.

Following step S546, the payout control program performs port output processing (step S548). In this port output process, various information is read from the output information storage area of the payout control built-in RAM, and various signals are output from the output terminals of the various output ports of the payout control MPU 4120a based on the various information. In the output information storage area, for example, payer ACK information indicating that various commands related to payout from the main control board 4100 (prize ball command and self-check command shown in FIG. 39) have been normally received, payer ACK information, and payout motor 744 Various information such as drive information for driving control to, prize ball number information for the number of balls actually paid out by the payout motor 744, and LED display information displayed on the error LED display 860b is stored. When various commands related to payout from the main control board 4100 are normally received from the output terminal of the predetermined output port of the payout control MPU 4120a based on the output information, the payer ACK signal is output to the main control board 4100 or the payout motor. A drive signal may be output to the 744, or the number of balls actually paid out by the payout motor 744 may be output to the external terminal board 784 as a prize ball number information output signal (in the present embodiment, the payout motor 744 actually pays out the game balls). A prize ball number information output signal is output to the external terminal board 784 every time 10 game balls are paid out. Specifically, the number of prize balls for determining whether or not to output the prize ball number information. An information output determination counter is provided, and the prize ball number information output determination counter shows the number of game balls actually paid out by the payout motor 744 in the port input process of step S550 described later in FIG. It counts based on the detection signal from the counting switch 751 and is a prize ball of the payout control built-in RAM by a process (program) (not shown) for monitoring the number of game balls actually paid out by the payout motor 744. The memory is updated in the information storage area. In a process (program) (not shown) for monitoring the number of game balls actually paid out by the payout motor 744, the prize ball information is stored in the payout control built-in RAM. The payout motor 744 actually pays out the value of the prize ball number information output determination counter stored in the area based on the detection signal from the counting switch 751 shown in FIG. 13 in the port input process of step S550 described later. The number of game balls is added and stored. In the port output process of step S548, the value of the prize ball number information output determination counter is read from the prize ball information storage area, and the read prize ball number information output determination is made. When the value of the counter is over 10 (that is, when the number of game balls actually paid out by the payout motor 744 reaches 10), the prize ball number information output signal is sent to the external terminal board 784. While outputting, the number of balls that exceeded it Is stored and updated in the prize ball information storage area of the above-mentioned payout control built-in RAM as the value of the prize ball number information output determination counter. ), The display signal is output to the error LED display 860b.

Following step S548, the payout control program performs port input processing (step S550). In this port input process, various signals input to the input terminals of the various input ports of the payout control MPU4120a are read and stored as input information in the input information storage area of the payout control built-in RAM. For example, an operation signal of the operation switch 860a, a detection signal from the rotation angle switch 752, a detection signal from the counting switch 751, a detection signal from the full tank switch 550, a BRQ signal from the CR unit 6, a BRDY signal, and a CR connection signal. The main control board 4100 reads the main payment ACK signal and the like from the main control board 4100, which conveys that the main control board 4100 has normally received various commands transmitted in the command transmission process described later, and stores them in the input information storage area as input information.

Following step S550, the payout control program performs a timer update process (step S552). In this timer update process, the ball squeeze determination set as a determination condition when determining whether or not a sphere squeeze state is generated by the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted is determined. Time, skip determination time set when the fixed position determination of the payout rotating body is not performed, determination of whether or not the game ball in which the accommodation space of the foul cover unit 540 shown in FIG. 1 is stored is full. Whether the number of game balls taken into the supply passage of the prize ball device 740 by the detection signal from the ball burnout switch 750 or the full tank judgment time set as the judgment condition at the time of performing is equal to or more than a predetermined number. In addition to managing the time such as the ball out judgment time set as the judgment condition when judging whether or not it is, the number of game balls received and paid out in the recess of the payout rotating body and the actual number of balls It is determined whether or not to reset the inconsistency counter INCC for monitoring whether or not the number of balls detected by the counting switch 751 and the inconsistent payout of the game balls due to the inconsistency are repeatedly performed. At that time, the judgment condition and the set inconsistency counter reset judgment time are managed. For example, when the ball squeeze judgment time is set to 5005 ms, the timer interrupt cycle is set to 2 ms. Therefore, the sphere squeeze judgment time is subtracted by 2 ms each time the timer update process is performed, and the subtraction result is obtained. When the value becomes 0, the ball squeeze judgment time is accurately measured.

In the present embodiment, the skip determination time is set to 22.75 ms, the full tank determination time is set to 504 ms, the ball out determination time is set to 119 ms, and the inconsistency counter reset determination time is set to 7000 s (about 2 hours). Every time processing is performed, the full tank judgment time, the ball out judgment time, and the inconsistency counter reset judgment time are subtracted by 2 ms, and the subtraction result becomes a value of 0. The full tank judgment time, the ball out judgment time, and the inconsistency counter reset. The judgment time is measured accurately. These various determination times are stored in the time management information storage area of the payout control built-in RAM as time management information.

Following step S552, the payout control program performs CR communication processing (step S554). In this CR communication process, whether or not various signals (BRQ signal, BRDY signal and CR connection signal) from the CR unit 6 are input based on the input information read from the above-mentioned input information storage area. To judge. Based on various signals from the CR unit 6, the payout control MPU4120a exchanges various signals with the CR unit 6. In the process of setting the work area of the payout control built-in RAM in step S530, as described above, various flags and various information stored in the various information storage areas, which are payout backup information stored in the payout control built-in RAM. Etc. (For example, the prize ball stock number PBS, the actual ball count PB, the drive command number DRV, the inconsistency counter INCC, etc. stored in the prize ball information storage area, and the PRDY stored in the CR communication information storage area, etc. Information to be used for various processes is set based on the payout information related to the payout (PRDY signal output setting information, etc. in which the logical state of the signal is set).

By this processing, for example, even if there is a momentary power failure or a power failure, the values such as the prize ball stock number PBS, the actual ball count PB, the drive command number DRV, and the inconsistency counter INCC at the time of power recovery are stored as payout backup information. It can be restored to the values of the prize ball stock number PBS, the actual ball count PB, the drive command number DRV, the inconsistency counter INCC, etc. immediately before the momentary power failure or power failure. As a result, even if the payout operation of the game ball by the prize ball device 740 is being executed and the payout operation cannot be continued due to a momentary power failure or a power failure, the payout operation is continued at the time of power recovery. Therefore, the game ball can be paid out to the upper plate 301 and the lower plate 302 without excess or deficiency. In other words, the payout control MPU4120a momentarily stops or loses power when paying out the game ball to the upper plate 301 or the lower plate 302 while exchanging various signals with the CR unit 6 in the CR communication process. Even if the exchange of various signals with the unit 6 is interrupted and it becomes impossible to continue paying out the game balls, the number of prize balls stock PBS, the actual ball count PB, the drive command number DRV, and the inconsistency counter INCC at the time of power recovery. By restoring the values such as, etc. to the values of the prize ball stock number PBS, the actual ball count PB, the drive command number DRV, the inconsistency counter INCC, etc., which are stored as the payout backup information immediately before the momentary power failure or power failure. , The exchange of various signals between the pachinko gaming machine 1 (payout control MPU4120a) and the CR unit 6 immediately before a momentary power failure or power failure can be continued from the time of power recovery, and the gaming balls can be continuously paid out. You can do it.

In this way, even if the exchange of various signals between the pachinko gaming machine 1 (pain control MPU4120a) and the CR unit 6 is momentarily stopped or stopped, it is restored to the state immediately before the momentary stop or stop at the time of power recovery. The various signals by the pachinko gaming machine 1 (payout control MPU4120a) and the CR unit 6 do not change due to the influence of the momentary power failure or stop. Therefore, the reliability of the exchange of various signals between the pachinko gaming machine 1 (payout control MPU4120a) and the CR unit 6 can be improved.

Further, various information stored in the CR communication information storage area is included in the payout backup information as described above. In the CR communication process, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM, which is set in the process of setting the work area of the payout control built-in RAM in step S530 at the time of power recovery. When the read PRDY signal output setting information is set to the logical state of the PRDY signal that conveys, for example, that the payout operation for paying out the rental ball is impossible, the PRDY signal is paid out. Output to the CR unit 6 from the output terminal of the predetermined output port of the MPU 4120a. Then, in the retry operation monitoring process, which is performed as one of the main operation setting processes, for example, the value of the inconsistency counter INCC of the prize ball information storage area stored in the payout control built-in RAM included in the payout backup information. Based on, it is determined whether or not the value of the inconsistency counter INCC is smaller than the inconsistency threshold value INCTH, and when the value of the inconsistency counter INCC is not smaller than the inconsistency threshold value INCTH, the retry operation is abnormal operation. In other words, it is determined that the payout operation of the game ball by the prize ball device 740 is in an abnormal state, a value 1 is set in the retry error flag RTERR-FLG, and the payout ball movement judgment setting process is performed. In the setting of the output of the error state to the CR unit 6, for example, the logical state (LOW) of the PRDY signal telling that the payout operation for paying out the rental ball is impossible when not communicating with the CR unit 6. Is set in the PRDY signal output setting information and stored in the CR communication information storage area.

As a result, in the CR communication processing, the logical state of this PRDY signal is read from the CR communication information storage area by the next timer interrupt from the time of power recovery, and the PRDY signal is output from the output terminal of the predetermined output port of the MPU4120a. Outputs to the CR unit 6. In this way, for example, if the payout operation of the game ball by the prize ball device 740 is in an abnormal state immediately before the momentary power failure, that state is restored when the power is restored. At an early stage, a PRDY signal indicating that the payout operation for paying out the rental ball is impossible can be output to the CR unit 6 from the output terminal of the predetermined output port of the payout control MPU4120a, and the CR unit 6 can be output. It is possible to convey that the payout operation of the game ball by the prize ball device 740 is in an abnormal state. As a result, it is possible to prevent BRDY, which is a useless ball lending request signal, from being output from the CR unit 6 at an extremely early stage from the time of power recovery.

Further, in the CR communication process, in the port input process of step S550, when the CR connection signal is read from the input information storage area of the payout control built-in RAM and the logic is HI based on the CR connection signal, that is, a pachinko game. When the power of the machine 1 is turned on and the payout control board 4110 and the CR unit 6 are electrically connected via the game ball or the like lending device connection terminal board 869, the lending ball is to be paid out. When the logic state of the PRDY signal is set to HI and output from the output terminal of the predetermined output port of the payout control MPU 4120a to the CR unit 6 in order to convey that the payout operation is possible, the logic is LOW. That is, when the pachinko game machine 1 is turned on and the payout control board 4110 and the CR unit 6 are not electrically connected via the game ball or the like rental device connection terminal board 869, the ball is rented. In order to convey that the payout operation for payout is impossible, the logical state of the PRDY signal is set to LOW and output to the CR unit 6 from the output terminal of the predetermined output port of the payout control MPU4120a. The logical state of the EXE signal for notifying that one payout operation has started or ended is stored in the CR communication information storage area of the payout control built-in RAM as EXS signal output setting information, and is stored in the payout control board 4110. The CR connection signal that conveys whether or not the CR unit 6 is electrically connected is stored in the state information storage area as CR connection information.

Following step S554, the payout control program performs a full tank and out-of-ball check process (step S556). In this full tank and out-of-ball check process, the input information is read from the above-mentioned input information storage area, and based on this input information, the accommodation space of the above-mentioned foul cover unit 540 is stored by the detection signal from the full tank switch 550. It is determined whether or not the game ball is full, and the number of game balls taken into the supply passage of the above-mentioned prize ball device 740 by the detection signal from the ball out switch 750 becomes a predetermined number or more. It is judged whether or not it is. For example, to determine whether or not the game ball in which the accommodation space of the foul cover unit 540 is stored is full, the full tank switch is used in the current full tank and out-of-ball check process using the timer interrupt cycle of 2 ms. When the detection signal from the 550 is ON and the detection signal from the full tank switch 550 is OFF in the previous (2 ms before) full tank and ball out check process, that is, the detection signal from the full tank switch 550 is from OFF to ON. When the transition to, the timer update process in step S552 starts counting the full tank determination time (504 ms) described above. Then, when the full tank determination time becomes 0 in the timer update process, that is, when the full tank determination time is reached, whether or not the detection signal from the full tank switch 550 is ON in this full tank and ball out check process. Is determined. In this determination, when the detection signal from the full tank switch 550 is ON, the full tank information for notifying that the accommodation space of the foul cover unit 540 is full in the stored game ball is stored in the above-mentioned state information storage. Store in the area. On the other hand, when the detection signal from the full tank switch 550 is OFF, the full tank information indicating that the game ball in which the accommodation space of the foul cover unit 540 is stored is not full is stored in the state information storage area. ..

Whether or not the number of game balls taken into the supply passage of the prize ball device 740 is equal to or greater than a predetermined number is also determined by using the timer interrupt cycle of 2 ms to check for full tank and out of balls this time. When the detection signal from the out-of-ball switch is ON, and the detection signal from the out-of-ball switch is OFF in the previous (2 ms before) full tank and out-of-ball check processing, that is, the detection signal from the out-of-ball switch 750 is from OFF to ON. When the transition to, the timer update process in step S552 starts the timing of the ball-out determination time (119 ms) described above. Then, when the value of the ball-out determination time becomes 0 in the timer update process, that is, when the ball-out determination time is reached, whether or not the detection signal from the ball-out switch 750 is ON in this full tank and ball-out check process. Is determined. In this determination, when the detection signal from the ball-out switch 750 is ON, the ball-out information indicating that the number of game balls taken into the supply passage of the prize ball device 740 is equal to or greater than a predetermined number is displayed. While storing in the information storage area, when the detection signal from the ball out switch 750 is OFF, it is assumed that the number of game balls taken into the supply passage of the prize ball device 740 is not equal to or more than a predetermined number, and the ball is out. Information is stored in the state information storage area.

Following step S556, the payout control program performs a launch ball feed control circuit error check process (step S557). In this launch ball feed control circuit error check process, status information is acquired from the launch ball feed defect monitoring circuit 4120ah shown in FIG. 13 to determine whether or not a defect has occurred in the launch ball feed control circuit 4120ag. As described above, the launch ball feed defect monitoring circuit 4120ah determines whether or not a defect has occurred in the launch ball feed control circuit 4120ag that performs launch control by the launch solenoid 654 and ball feed control by the ball feed solenoid 585. It is monitored, and the monitoring result (whether or not a problem has occurred) can be stored and retained as status information. The payout control program acquires status information from the launch ball feed defect monitoring circuit 4120ah and determines whether or not a defect has occurred in the launch ball feed control circuit 4120ag. When the payout control program acquires the status information from the launch ball feed defect monitoring circuit 4120ah and determines that no defect has occurred in the launch ball feed control circuit 4120ag, the payout control program controls the launch of the game ball by the launch ball feed control circuit 4120ag. In order to start the launch ball feed control circuit 4120ag, the launch operation permission is set, and the launch operation permission information indicating that the launch operation permission state is stored is stored in the state information storage area, while the launch ball feed control circuit 4120ag. When it is determined that a problem has occurred in the launch ball feed control circuit 4120ag, a launch operation prohibition is set for the launch ball feed control circuit 4120ag in order to forcibly stop the launch control of the game ball by the launch ball feed control circuit 4120ag, and the launch is performed. The firing operation prohibition information for notifying that the operation is prohibited is stored in the state information storage area.

Following step S557, the payout control program performs a command reception process (step S558). In this command reception process, various commands related to payout from the main control board 4100 (prize ball command and self-check command shown in FIG. 39) are received. When these various commands are normally received, the payer ACK information to that effect is stored in the output information storage area described above. On the other hand, when various commands cannot be received normally, a connection abnormality is transmitted to indicate that an abnormality has occurred in the connection between the main control board 4100 and the payout control board 4110 (an abnormality has occurred in various command signals). Information is stored in the state information storage area described above.

Following step S558, the payout control program performs command analysis processing (step S560). In this command analysis process, the command received in step S558 is analyzed, and the analyzed command is stored in the received command information storage area of the payout control built-in RAM as received command information.

Following step S560, the payout control program performs the main operation setting process (step S562). In this main motion setting process, motion settings such as prize balls, lending balls, ball pulling, and ball scooping are performed, retry operation is determined, and the number of unpaid balls (prize ball stock number) is monitored. do.

Following step S562, the payout control program performs the LED display data creation process (step S564). In this LED display data creation process, various information is read from the state information storage area described above, display data to be displayed on the error LED display 860b of the payout control board 4110 is created, and the output information storage area described above is used as the LED display information. Remember. For example, when the above-mentioned ball-out information is read from the state information storage area and the number of game balls taken into the supply passage of the prize ball device 740 is not equal to or more than a predetermined number based on the ball-out information, the corresponding display data is displayed. (In this embodiment, the display value 1 (number "1")) is created and the LED display information is stored in the output information storage area.

Following step S564, the payout control program performs a command transmission process (step S566). In this command transmission process, various information is read from the above-mentioned state information storage area, and various commands (door open command, door frame close command, main body frame open) classified into the state display shown in FIG. 42 based on the various information. Create a command, a main body frame closing command, a frame state 1 command (corresponding to the first error occurrence command), an error release navigation command (corresponding to the first error release command), and a frame state 2 command) to create the main control board 4100. Send to. For example, when the ball-out information is read from the state information storage area, the frame state 1 command is issued when the number of game balls taken into the supply passage of the prize ball device 740 is not equal to or more than a predetermined number based on the ball-out information. When it is created and transmitted to the main control board 4100 or the launch operation permission information is read from the state information storage area, the frame state 2 command (to convey that there is no launch ball feed control circuit error) based on this launch operation permission information. When a value 0 is set to B0 and transmitted to the main control board 4100 or the firing operation prohibition information is read from the state information storage area, the frame state 2 command (frame state 2 command (based on this firing operation prohibition information) is created. A value of 1 is set in B0 to convey that the launch ball feed control circuit is an error) and transmitted to the main control board 4100. Further, in this command transmission process, when there is a change in the frame state such as an error related to the payout operation of the game ball, the payout control program provides information on the part where the error occurs related to the payout operation (hereinafter, A frame state 1 command (first error release command) including "error occurrence position information") is generated (error occurrence command generation means). On the other hand, in this command transmission process, the above-mentioned error occurs when the payout control program detects that the payout RAM clear notification flag HRCL-FLG has a value of 1, that is, an operation signal corresponding to the operation of the operation switch 860a is detected. Output the release navigation command (first error release command) (command sending means). Further, this payout control program transmits a main body frame opening command (first main body frame opening command) when a main body frame opening detection signal is input from the main body frame opening switch 619 (main body frame command sending means, first 1 main body frame command sending means). B. Ayumu, this payout control program transmits a main body frame closing command (first main body frame closing command) when a main body frame closing detection signal is input from the main body frame opening switch 619 (main body frame command sending means). , First main body frame command sending means). Further, when the door frame opening detection signal from the door frame opening switch 618 is input, this payout control program transmits a door frame opening command (first door frame opening command) (door frame command sending means, first 1 door frame command sending means). On the other hand, when the door frame closing detection signal from the door frame opening switch 618 is input, this payout control program transmits a door frame closing command (first door frame closing command) (door frame command sending means, first 1 door frame command sending means). Further, in the above-mentioned command transmission process (step S566), this payout control program reads error information including error contents from the above-mentioned state information storage area, and has unit number information for distinguishing itself from other pachinko machines. The error information signal based on the error information is output to the hall computer via the external terminal board 784. When the hall computer receives this error information signal, the hall computer provides the above-mentioned unit number information and error information to the wireless device possessed by the hall clerk, and the hall clerk provides the unit number pachinko machine based on the unit number information. In, it is possible to recognize that the error content included in the error information has occurred.

Following step S566, the payout control program sets the value C in the watchdog timer clear register HWCL (step S568). By setting the value C in the watchdog timer clear register HWCL in step S568, the value C is set in the watchdog timer clear register HWCL following the value B set in step S546. As a result, the value A, the value B, and the value C are set in order in the watchdog timer clear register HWCL, and the watchdog timer is set to clear.

Following step S568, the process returns to step S539 again, and the payout control program sets the value A in the watch dock timer clear register HWCL, and determines whether or not a power failure warning signal (payout power failure warning signal) has been input in step S540. If the determination is made and there is no input of this power failure warning signal (payout power failure warning signal), it is determined in step S542 whether or not the 2ms elapsed flag HT-FLG has a value of 1, and the 2ms elapsed flag HT-FLG has a value of 1. In other words, when 2 ms has elapsed, the value 0 is set in the 2 ms elapsed flag HT-FLG in step S544, the value B is set in the watch dock timer clear register HWCL in step S546, and the port output process is performed in step S548. , Step S550 performs port input processing, step S552 performs timer update processing, step S554 performs CR communication processing, step S556 performs full tank and ball out check processing, and step S558 performs command reception processing. Command analysis processing is performed in step S560, main operation setting processing is performed in step S562, LED display data creation processing is performed in step S564, command transmission processing is performed in step S566, and a value is set in the watch dock timer clear register HWCL in step S568. C is set, and steps S539 to S568 are repeated. The processes of steps S539 to S568 are referred to as "payout control unit main process".

The processing content of the payout control unit main processing differs according to the progress of the game by the main control board 4100. Therefore, the time required for the processing of the payout control MPU4120a fluctuates. Therefore, in the port output process of step S548, the payout control MPU 4120a preferentially outputs a payer ACK signal indicating that various commands related to payout from the main control board 4100 have been normally received to the main control board 4100. There is. As a result, the payout control MPU4120a secures the processing time so that other fluctuating processing can be sufficiently performed.

On the other hand, when the power failure warning signal (payout power failure warning signal) is input in step S540, the interrupt prohibition setting is performed (step S570). With this setting, the timer interrupt process of the payout control unit, which will be described later, is not performed, writing to the payout control built-in RAM is prevented, and the above-mentioned rewriting of the payout information is protected.

Following step S570, the payout control program stops the output of the drive signal to the payout motor 744 (step S574). As a result, the payout of the game ball is stopped.

Following step S574, the payout control program sets the watchdog timer to clear (step S576). As described above, this clear setting is performed by setting the value A, the value B, and the value C in order in the watchdog timer clear register HWCL.

Following step S576, the payout control program calculates the checksum and stores the calculated value (step S578). For this checksum, the payout information of the work area of the payout control built-in RAM excluding the storage area of the checksum value calculated in step S524 and the value of the payout backup flag HBK-FLG is regarded as a numerical value, and the total is calculated.

Following step S578, the payout control program sets the payout backup flag HBK-FLG to a value of 1 (step S580). As a result, the storage of the payout backup information is completed.

Following step S580, the payout control program sets the prohibition of access to the payout control built-in RAM (step S582). By this setting, access to the payout control built-in RAM is prohibited, writing and reading become impossible, and the payout backup information stored in the payout control built-in RAM is protected.

Following step S582, the payout control program enters an infinite loop. In this infinite loop, the watchdog timer is not set to clear because the value A, the value B, and the value C are not set in order in the watchdog timer clear register HWCL. Therefore, the payout control MPU4120a is reset, and then the payout control program performs the payout control unit power-on processing again under the control of the payout control MPU4120a. The process of steps S570 to S582 and the infinite loop are referred to as "payout control unit power cutoff process".

The pachinko gaming machine 1 (pain control MPU4120a) is reset when there is a power failure or when there is a momentary power failure, and when the power is restored thereafter, the payout control unit power-on processing is performed.

In step S526, it is inspected whether or not the payout backup information stored in the payout control built-in RAM is normal, and then in step S528, whether or not the payout control unit power off processing is normally completed. Is inspecting. In this way, by double-checking the payout backup information stored in the payout control built-in RAM, it is inspected whether or not the payout backup information is stored by fraudulent activity.

[16-2. Payout control unit timer interrupt processing]
Next, the payout control unit timer interrupt processing will be described. This payout control unit timer interrupt process is repeatedly performed every interrupt cycle (2 ms in this embodiment) set in the payout control unit power-on process shown in FIGS. 46 to 48.

When the payout control unit timer interrupt process is started, the payout control unit 4120 of the payout control board 4110 sets the payout control program to disable the timer interrupt as shown in FIG. 49 under the control of the payout control MPU4120a. To switch (save) the register (step S590). Here, the general-purpose storage element (general-purpose register) used in the above-mentioned payout control unit main processing is switched to the auxiliary register. By using this auxiliary register in the timer interrupt processing of the payout control unit, the value of the general-purpose register is not overwritten. This prevents the contents of the general-purpose register used in the main processing of the payout control unit from being destroyed.

Following step S590, the payout control program sets the 2ms elapsed flag HT-FLG to a value of 1 (step S592). The 2 ms elapsed flag HT-FLG is a flag that clocks 2 ms every time the payout control unit timer interrupt process is performed, that is, every 2 ms, and becomes a value of 1 when 2 ms has elapsed and a value of 0 when 2 ms has not elapsed. Each is set.

Following step S592, the payout control program switches (returns) registers (step S594). This return switches from the auxiliary register used in the payout control unit timer interrupt processing to the general-purpose storage element (general-purpose register). By using this general-purpose register in the main processing of the payout control unit, the value of the auxiliary register is not overwritten. This prevents the contents of the auxiliary register used in the payout control unit timer interrupt processing from being destroyed.

Following step S594, the payout control program sets interrupt enable (step S596) and ends this routine.

[16-3. Rotation angle switch history creation process]
Next, the rotation angle switch history creation process will be described. In this rotation angle switch history creation process, the history of the detection signal from the rotation angle switch 752 shown in FIG. 13 is created.

When the rotation angle switch history creation process is started, in the payout control unit 4120 on the payout control board 4110, the payout control program controls the payout control MPU4120a, and as shown in FIG. 50, the rotation angle is rotated from the payout control built-in RAM. The switch detection history information RSW-HIST is read (step S610). This rotation angle switch detection history information RSW-HIST is 1 byte (8 bits: most significant bit B7, B6, B5, B4, B3, B2, B1, least significant bit B0, "B" represents a bit). It has a storage capacity, and the history of the detection signal from the rotation angle switch 752 is stored in the rotation angle switch history information storage area of the payout control built-in RAM as the rotation angle switch detection history information LSB-HIST. In step S610, the rotation angle switch detection history information RSW-HIST is read from the rotation angle switch history information storage area.

Following step S610, the payout control program determines whether or not there is a detection signal from the rotation angle switch 752 (step S612). This determination is performed based on the detection signal from the rotation angle switch 752 in the port input process of step S550 in the power-on processing of the payout control unit (main process of the payout control unit) shown in FIG. 48. Specifically, the detection signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S612, the input information is read from the input information storage area, and it is determined whether or not there is a detection signal from the rotation angle switch 752. When there is a detection signal from the rotation angle switch 752 in the input information, the payout control program detects the rotation position of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. It is determined that the axis has transitioned from the blocked state to the non-blocked state. On the other hand, when there is no detection signal from the rotation angle switch 752 in the input information, the payout control program determines that the detection slit has transitioned the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state.

When the detection slit has transitioned the optical axis of the rotation angle switch 752 from the cutoff state to the non-cutoff state in step S612, the payout control program shifts the rotation angle switch detection history information (step S614). In this shift process of the rotation angle switch detection history information, the rotation angle switch detection history information RSW-HIST read in step S610 is converted to the most significant bit B7 ← B6, B6 ← B5, B5 ← B4, B4 ← B3, B3 ← B2. , B2 ← B1, B1 ← least significant bit B0, and so on, shifting from the least significant bit B0 to the most significant bit B7 one bit at a time.

Following step S614, the payout control program sets the least significant bit B0 of the rotation angle switch detection history information RSW-HIST to a value 1 (step S616), and ends this routine.

On the other hand, when the detection slit has transitioned the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state in step S612, the payout control program shifts the rotation angle switch detection history information (step S618). .. In the shift processing of the rotation angle switch detection history information, the payout control program performs the same processing as the shift processing of the rotation angle switch detection history information in step S614, and the rotation angle switch detection history information LSB-HIST read in step S610. From the least significant bit B0 to the most significant bit B7, such as the most significant bit B7 ← B6, B6 ← B5, B5 ← B4, B4 ← B3, B3 ← B2, B2 ← B1, B1 ← least significant bit B0. Shifts bit by bit.

Following step S618, the payout control program sets the least significant bit B0 of the rotation angle switch detection history information RSW-HIST to a value 0 (step S620), and ends this routine.

In this way, each time the rotation angle switch history creation process is performed, the rotation angle switch detection history information RSW-HIST is shifted by 1 bit from the least significant bit B0 to the most significant bit B7, and then the detection slit rotates. The least significant bit B0 has a value of 1 or a value of 1 depending on the state in which the optical axis of the angle switch 752 is transitioned from the cutoff state to the non-blocking state or the detection slit is in the state in which the optical axis of the rotation angle switch 752 is changed from the non-blocking state to the blocking state. Since the value 0 is set, the history of the detection signal from the rotation angle switch 752 can be created.

[16-4. Sprocket fixed position judgment skip processing]
Next, the sprocket fixed position determination skip process will be described. This sprocket fixed position determination skip process skips the determination of whether or not the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted is in the fixed position when a predetermined condition is satisfied. It should be noted that the fixed position determination of the payout rotating body is also performed when the payout of the game ball by the prize ball device 740 is completed. As a result, the rotation of the rotation shaft of the payout motor 744 can be reliably started in a state where the ball is not squeezed.

When the sprocket fixed position determination skip process is started, in the payout control unit 4120 on the payout control board 4110, the payout control program controls the payout control MPU4120a, and as shown in FIG. 51, the fixed position determination skip flag SKP- It is determined whether or not the FLG has a value of 0 (step S630). This fixed position determination skip flag SKP-FLG is a flag indicating whether or not to perform the fixed position determination of the payout rotating body, and when the fixed position determination of the payout rotating body is not performed (when skipping), the value is 1, and the payout rotation The value is set to 0 when the fixed position of the body is determined (when not skipped).

When the fixed position determination skip flag SKP-FLG has a value of 0 (not skipped) in step S630, that is, when the fixed position determination of the payout rotating body is performed, the payout control program uses the rotation angle switch history information of the payout control built-in RAM. The rotation angle switch detection history information RSW-HIST is read from the storage area (step S632), and it is determined whether or not the value matches the fixed position determination value (step S634). This fixed position determination value is stored in the payout built-in ROM, and in the present embodiment, it is "000011111B (" B "represents a bit)", and the upper 4 bits B7 to B4 have a value of 0 and a lower 4 bits. Bits B3 to B0 have a value of 1. In the determination in step S634, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST and the lower 4 bits B3 to B0 of the fixed position determination value match.

Here, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST have a value of 1, the detection slit described above is the optical axis of the rotation angle switch 752 in succession in four timer interrupt cycles. It means that the state has changed from the blocked state to the non-blocked state. In the generation of the four timer interrupt cycles, the payout motor 744 shown in FIG. 13 is rotated by four steps. The rotation of the payout motor 744 is the rotation of the payout rotating body of the rotation detection panel via the first gear, the second gear, and the third gear. Since the first gear, the second gear, and the third gear have play (backlash), the payout rotating body rotates clockwise or counterclockwise, but the payout rotating body due to this backlash Since the rotation is designed to correspond to the rotation of about two steps of the payout motor 744, in the present embodiment, when determining the fixed position of the payout rotating body, the rotation angle switch 752 is used. The rotation angle switch detection history information RSW-HIST is created by the rotation angle switch history creation process shown in the history of the detection signal and FIG. 50, and the lower 4 bits B3 to B0 of the created rotation angle switch detection history information RSW-HIST, that is, This is performed based on the detection signal from the rotation angle switch 752 due to the occurrence of the latest four timer interrupt cycles. As a result, in the four timer interrupt cycles, the payout motor 744 rotates four steps, so that it rotates more than the rotation of the payout rotating body due to backlash, and absorbs the rotation of the payout rotating body due to backlash. Can be done. Therefore, since it is possible to prevent erroneous detection of the fixed position of the payout rotating body due to backlash, the rotation position of the payout rotating body can be correctly managed by the rotation position of the payout motor 744. In the present embodiment, the four timer interrupt cycles are 8 ms (= 2 ms × 4 times), which is set as the backlash absorption time.

In step S634, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S632 and the lower 4 bits B3 to B0 of the fixed position determination value match, the payout control program determines. A value of 1 is set in the fixed position determination skip flag SKP-FLG (step S636). As a result, it is possible to set not to perform (skip) the fixed position determination of the payout rotating body. The payout control MPU4120a sets the rotation position of the payout rotating body in step S636 to a fixed position of the payout rotating body.

Following step S636, the payout control program effectively sets the skip determination time (step S638) and ends this routine. Here, the number of detection slits is three, which is the same as the number of recesses of the payout rotating body, and is formed in equal parts (every 120 degrees) on the outer circumference of the rotation detection plate. Further, as described above, the rotation of the payout motor 744 is the rotation of the payout rotating body of the rotation detection panel via the first gear, the second gear, and the third gear. In the present embodiment, the rotation between each detection slit (120 degrees) of the rotation detection board (delivery rotating body) is designed to correspond to the rotation of 18 steps of the payout motor 744.

The payout control program manages the rotation position of the payout rotating body based on the number of steps of the payout motor 744 under the control of the payout control MPU4120a. Specifically, (1) a transient state in which the detection slit shifts the optical axis of the rotation angle switch 752 from a blocking state to a non-blocking state (referred to as “edge detection state”), and (2) the detection slit rotates at an angle of rotation. The state in which the optical axis of the switch 752 is transitioned from the blocked state to the non-blocked state (referred to as "fixed position fixed state") and (3) the detection slit shifts the optical axis of the rotation angle switch 752 from the non-blocked state to the blocked state. It is managed in three states: the state in which it is set (“fixed position determination skip state”). The edge detection state of (1) corresponds to the rotation of one step of the payout motor 744, the fixed position determination state of (2) corresponds to the rotation of four steps of the payout motor 744, and the fixed position determination skip state of (3). This corresponds to the rotation of the payout motor 744 in 13 steps, and the rotation position between the detection slits (120 degrees) of the rotation detection panel, that is, the rotation position of the payout rotating body is managed by a total of 18 steps of rotation.

In the fixed position determination skip state of (3), since the detection slit is in a state in which the optical axis of the rotation angle switch 752 is changed from the non-blocking state to the blocking state, the skip determination time is the time for 13 steps of rotation of the payout motor 744. Is set. As described above, since the timer interrupt cycle is set to 2 ms, the skip determination time is 26 ms (= 2 ms × 13 steps).

When the skip determination time becomes effective in step S638, the skip determination time is subtracted in the timer update process of step S552 in the payout control unit power-on time process (payout control unit main process) shown in FIG. 48. The payout control MPU4120a subtracts the skip determination time, and when the subtraction result reaches a value of 0, the fixed position determination skip flag SKP-FLG is set to an initial value of 0.

On the other hand, when the fixed position determination skip flag SKP-FLG is not a value 0 (value 1) (when skipping) in step S630, that is, when the fixed position determination of the payout rotating body is not performed, or in step S634, step S632. When the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step 1 and the lower 4 bits B3 to B0 of the fixed position determination value do not match, the payout control program terminates this routine as it is. .. The fixed position determination skip flag SKP-FLG set in step S636 is stored in the general-purpose storage element (general-purpose register) of the payout control MPU4120a.

The game balls supplied from the pachinko island facility are stored in the prize ball tank 720 and the tank rail 731, taken into the supply passage of the prize ball device 740, and guided to the prize ball device 740. When the game balls rub against each other and become charged, they are electrostatically discharged to generate noise. Therefore, the prize ball device 740 is easily affected by noise and is in an environment. The rotation angle switch board 753 of the prize ball device 740 shown in FIG. 3 is provided with a rotation angle switch 752, and the detection signal from the rotation angle switch 752 is affected by noise due to electrostatic discharge of the game ball. Cheap. Further, the wiring (harness) connecting the payout control board 4110 and the board 754 in the prize ball case in the prize ball device 740 shown in FIG. 3 is also affected by noise due to electrostatic discharge of the game ball. Cheap.

Therefore, in the present embodiment, in order to suppress erroneous detection due to the influence of noise, the above-mentioned fixed position determination skip state (3), that is, the detection slit changes the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state. In the transitional state, the fixed position determination of the payout rotating body is not performed. As a result, the accuracy of the fixed position determination of the payout rotating body is improved. As described above, the period and period required to detect the fixed position of the payout rotating body can be calculated in advance, so that the skip determination time can be easily set and adjusted.

[16-5. Ball shaving judgment processing]
Next, the ball bending determination process will be described. This ball squeeze determination process determines whether or not a ball squeeze state is generated by the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted.

When the ball squeeze determination process is started, the payout control MPU4120a of the payout control unit 4120 on the payout control board 4110 has a rotation angle from the rotation angle switch history information storage area of the above-mentioned payout control built-in RAM, as shown in FIG. The switch detection history information RSW-HIST is read (step S640).

Following step S640, the payout control program determines whether or not there is a detection signal from the rotation angle switch 752 described above (step S642). This determination determines whether or not the rotation angle switch detection history information RSW-HIST read in step S640 matches the fixed position determination value. As described above, this fixed position determination value is stored in the payout built-in ROM, and in the present embodiment, it is "00001111B (" B "represents a bit)", and the upper 4 bits B7 to B4 are The value 0 and the lower 4 bits B3 to B0 are the values 1. In the determination in step S642, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST and the lower 4 bits B3 to B0 of the fixed position determination value match.

In step S642, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S640 and the lower 4 bits B3 to B0 of the fixed position determination value match, the payout control program determines. This routine is terminated as it is, assuming that the detection slit has changed the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state, that is, the payout rotating body is rotating and the ball is not squeezed. do.

On the other hand, in step S642, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S640 and the lower 4 bits B3 to B0 of the fixed position determination value do not match, the ball is flagged. The value 1 is set in the middle flag PBE-FLG (step S644). This ball-squeezing flag PBE-FLG is a flag indicating whether or not a ball-squatting state is generated by the payout rotating body, and has a value of 1 when the payout motor 744 is performing a ball-sucking operation. The value is set to 0 when no operation is performed.

Following step S644, the payout control program effectively sets the ball squeeze determination time (step S646) and ends this routine. When the ball squeeze determination time becomes effective, the sphere squeeze determination time is subtracted in the timer update process of step S552 in the payout control unit power-on processing (payout control unit main process) shown in FIG. ..

[16-6. Various prize ball stock number addition processing]
Next, various prize ball stock number addition processes will be described. The various prize ball stock number addition processes include a prize ball stock number addition process for prize balls and a prize ball stock number addition process for rental balls, and the prize ball stock number addition process for prize balls is performed from the main control board 4100. It is a process of adding the number of balls to be paid out based on the prize ball command described later, and the process of adding the number of prize balls stock for lending is a process of adding the number of balls to be paid out based on the ball lending request signal from the CR unit 6. be. First, the prize ball stock number addition process for prize balls will be described, and then the prize ball stock number addition process for rental balls will be described. In this embodiment, the prize ball stock number addition process is set to be preferentially performed, and the prize ball stock number added in the prize ball stock number addition process is set according to the prize ball stock number. After the game balls are paid out by the prize ball device 740, it is set to perform the process of adding the number of prize ball stocks for rental balls.

[16-6-1. Prize ball stock number addition processing for prize balls]
When the prize ball stock number addition process for prize balls is started, in the payout control unit 4120 on the payout control board 4110, the payout control program issues a prize ball command as shown in FIG. 53 under the control of the payout control MPU4120a. It is determined whether or not there is (step S650). This determination is performed based on the command analyzed in the command analysis process of step S560 in the power-on processing of the payout control unit (main process of the payout control unit) shown in FIG. 48. Specifically, the analyzed command is stored as the received command information in the received command information storage area of the payout control built-in RAM. In step S650, the payout control program reads the received command information from the received command information storage area and determines whether or not it is a prize ball command.

When the received command information is not a prize ball command in step S650, the payout control program terminates this routine as it is, while when the received command information is a prize ball command in step S650, the payout control program sends this prize ball command. The corresponding prize ball number PBV is read out from the prize ball number information table (step S652). The prize ball number information table, which will be described in detail later, is an information table that is stored in advance in the payout built-in ROM in association with the prize ball command and the prize ball number PBV.

Following step S652, the payout control program reads the prize ball stock number PBS from the payout control built-in RAM (step S654). The prize ball stock number PBS represents the number of game balls that have not yet been paid out by the prize ball device 740, that is, the number of unpaid balls, and in the present embodiment, it has a storage capacity of 2 bytes (16 bits). ing. As a result, the prize ball stock number PBS can store the number of unpaid balls from a value of 0 to a value of 32767. The prize ball stock number PBS is stored in the prize ball information storage area of the RAM with built-in payout control. In step S652, the prize ball stock number PBS is read out from this prize ball information storage area.

The payout control program adds the number of prize balls PBV read in step S652 to the number of prize ball stocks PBS read in step S654 (step S656), and ends this routine. After adding in step S656, the prize ball command read in step S650 is deleted from the received command information storage area.

[16-6-2. Prize ball stock number addition processing for ball rental]
Next, the process of adding the number of prize balls stock for lending will be described. When the process of adding the number of prize balls for ball rental is started, in the payout control unit 4120 on the payout control board 4110, the payout control program requests the ball rental as shown in FIG. 54 under the control of the payout control MPU4120a. It is determined whether or not there is a signal (step S660). This determination is performed based on the ball lending request signal from the CR unit 6 in the port input process of step S550 in the payout control unit power-on time process (payout control unit main process) shown in FIG. Specifically, the ball rental request signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S660, the payout control program reads the input information from the input information storage area and determines whether or not there is a ball lending request signal.

When there is no ball lending request signal in step S660, the payout control program terminates this routine as it is, while when there is a ball lending request signal in step S660, the payout control program receives the prize ball information of the above-mentioned payout control built-in RAM. The prize ball stock number PBS is read from the storage area (step S662), the number of rented balls RBV is added to the prize ball stock number PBS (step S664), and this routine is terminated. The number of rented balls RBV is a fixed value and is stored in advance in the payout built-in ROM. In this embodiment, a value of 25 is set as the number of rented balls RBV. After the addition in step S664, the payout control program erases the ball lending request signal read in step S660 from the input information storage area. Further, in the present embodiment, since the prize ball is prioritized (the prize ball and the ball lending are managed separately), the ball lending request signal is held even when there is a ball lending request signal. , The loan ball will be paid out when the prize ball is paid out. Therefore, in the present embodiment, the ball loan is paid out after the prize ball stock number PBS reaches a value of 0.

[16-7. Stock monitoring process]
Next, the stock monitoring process will be described. In this stock monitoring process, the player monitors whether or not the player continues the game in a state (stocked state) in which the accommodation space of the foul cover unit 540 shown in FIG. 1 is filled with the stored game balls during the game. It is a process to do.

When the stock monitoring process is started, in the payout control unit 4120 on the payout control board 4110, the payout control program controls the payout control MPU4120a, and as shown in FIG. 55, the prize ball information of the above-mentioned payout control built-in RAM. The prize ball stock number PBS is read from the storage area (step S670), and it is determined whether or not the read prize ball stock number PBS is equal to or higher than the caution threshold TH (step S672). The caution threshold TH is a fixed value and is stored in advance in the payout built-in ROM. In this embodiment, a value of 50 is set as the caution threshold TH.

When the prize ball stock number PBS is equal to or higher than the caution threshold value TH in step S672, the payout control program sets the caution flag CA-FLG to a value of 1 (step S674) and ends this routine. With this caution flag CA-FLG, the player starts stocking the game balls in the accommodation space of the foul cover unit 540, and the number of unpaid game balls (the number of prize balls stock described above) becomes equal to or higher than the caution threshold TH. It is a flag indicating that the value has been reached, and is set to a value 1 when the caution threshold value TH or higher is reached, and a value 0 when the caution threshold value TH or higher is not reached.

On the other hand, when the prize ball stock number PBS is less than the caution threshold TH in step S672, the payout control program sets the caution flag CA-FLG to a value 0 (step S676) and ends this routine.

The game state became a big hit, and the player relaxed and watched the production unfolded by the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470 as shown in FIG. If so, the player may not inadvertently pull out the game ball paid out as a prize ball from the lower plate 302 by operating the lower plate ball removal button 354 for one round. be. If the game is continued in this state, the lower plate 302 is filled with the game balls, and the game balls start to accumulate in the accommodation space of the foul cover unit 540. When the accommodation space of the foul cover unit 540 is filled with game balls, as described above, the value of the prize ball stock number PBS increases to be equal to or higher than the caution threshold TH, and the door frame 5 is provided as a caution effect. Multiple LEDs on various decorative boards flash. By this blinking, for example, it is possible to inform the clerk of the hall to pay attention to the player's game. As a result, the clerk in the hall can inform the player that the game ball will be pulled out from the lower plate 302, and the player can fill the lower plate 302 (the accommodation space of the foul cover unit 540) with the game ball. It is possible to prevent the game from continuing.

In the present embodiment, the caution threshold TH is set to a value 50 corresponding to about one-fifth of the upper limit value 255 that can be represented by 1 byte (8 bits). As a result, it is possible to inform the clerk of the hall to call attention to the player's game at the earliest possible stage.

[16-8. Payout ball movement judgment setting process]
Next, the payout ball motion determination setting process will be described. In the payout ball operation determination setting process, the game ball is paid out to the upper plate 301 or the lower plate 302 shown in FIG. 7, the ball is made to perform the ball-to-ball operation, or such a payout is performed. It is a process to set either or not to discharge.

When the payout ball operation determination setting process is started, in the payout control unit 4120 on the payout control board 4110, the payout control program has a built-in payout control as shown in FIG. 56 under the control of the payout control MPU4120a. The rotation angle switch detection history information RSW-HIST is read from the rotation angle switch history information storage area of the RAM (step S680).

Following step S680, the payout control program determines whether or not there is a detection signal from the rotation angle switch 752 shown in FIG. 13 (step S682). This determination determines whether or not the rotation angle switch detection history information RSW-HIST read in step S680 matches the fixed position determination value. As described above, this fixed position determination value is stored in the payout built-in ROM, and in the present embodiment, it is "00001111B (" B "represents a bit)", and the upper 4 bits B7 to B4 are The value 0 and the lower 4 bits B3 to B0 are the values 1. In the determination in step S682, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST and the lower 4 bits B3 to B0 of the fixed position determination value match.

In step S682, when the payout control program matches the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S680 and the lower 4 bits B3 to B0 of the fixed position determination value, It is determined whether or not the retry error flag RTERR-FLG has a value of 1 (step S684). This retry error flag RTERR-FLG is a flag indicating whether or not the retry operation described later is abnormally operating. The value is 1 when the retry operation is abnormally operating, and when the retrying operation is not abnormally operating (retry). When the operation is normal), the value is set to 0, respectively.

When the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S682 and the lower 4 bits B3 to B0 of the fixed position determination value do not match in step S682, or in step S684. , When the retry error flag RTERR-FLG is not a value 1 (value is 0), that is, when the retry operation is not abnormally operating, the payout control program determines whether or not the ball-filled flag PBE-FLG is a value 1. (Step S686). The ball squeezing flag PBE-FLG is a flag indicating whether or not a sphere is squeezed by the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. The value is set to 1 when the motion is performed, and the value is set to 0 when the ball is not performing the motion.

When the ball-squeezing flag PEB-FLG is not a value 1 (value is 0) in step S686, that is, when the ball-squeezing operation is not performed, the payout control program stores the prize ball information of the above-mentioned payout control built-in RAM. The prize ball stock number PBS is read from the region (step S688), and it is determined whether or not the read prize ball stock number PBS is greater than the value 0 (step S690). In this determination, it is determined whether or not there is an unpaid number of balls in the payout of the game balls by the payout motor 744.

When the prize ball stock number PBS is greater than 0 in step S690, that is, when there is an unpaid number of balls, the payout control program determines whether or not the accommodation space of the foul cover unit 540 is full of stored game balls. (Step S692). This determination is performed based on the full tank information stored in the full tank and out-of-ball check processing in step S556 in the power-on processing of the payout control unit (main process of the payout control unit) shown in FIG. Specifically, the full tank information is stored in the state information storage area of the above-mentioned payout control built-in RAM. In step S692, the full tank information is read from the state information storage area, and it is determined whether or not the game ball in which the accommodation space of the foul cover unit 540 is stored is full.

When the accommodation space of the foul cover unit 540 is not full in the game ball stored in step S692, the payout control program performs the payout setting process described later (step S694), and ends this routine. In this payout setting process, a payout operation is performed in which the game ball is paid out to the upper plate 301 and the lower plate 302.

On the other hand, when the accommodation space of the foul cover unit 540 is full with the stored game balls in step S692, the payout control program ends this routine as it is. In the pachinko gaming machine 1 of the present embodiment, when the accommodation space of the foul cover unit 540 is filled with the stored game balls, the payout motor 744 is forcibly stopped. When a prize ball is generated while the payout motor 744 is forcibly stopped, the number of unpaid balls by the payout motor 744 increases, and the prize ball stock number PBS is added by the prize ball stock number addition process for prize balls shown in FIG. 53. Will increase.

On the other hand, when the prize ball stock number PBS is not larger than the value 0 (value 0) in step S690, that is, when there is no unpaid number of balls, the payout control program ends this routine as it is. As a result, the game ball is not paid out.

On the other hand, when the ball-grinding flag PBE-FLG has a value of 1, that is, the ball-grinding operation is performed in step S686, the payout control program performs the ball-grinding motion setting process described later (step S700), and this routine To finish. In this ball-grinding motion setting process, a ball-grinding motion is performed to eliminate the ball-grinding state by the payout rotating body of the prize ball device 740.

On the other hand, in step S684, when the retry error flag RTERR-FLG has a value of 1, that is, when the retry operation is abnormally operating, the payout control program sets the output stop (stop) of the drive signal to the payout motor 744. (Step S702). In this setting, the drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the above-mentioned payout control built-in RAM.

Following step S702, the payout control program sets the output of the error state to the CR unit 6 (step S704) and ends this routine. In step S704, when the payout control program is not communicating with the CR unit 6 under the control of the payout control MPU4120a in order to inform the CR unit 6 that the ball cannot be lent (CR unit 6). When the logic of BRDY from is LOW, that is, when it is held down), the logic of the PRDY signal is LOW, that is, the state of being down is held, and the logic state of the PRDY signal is set in the PRDY signal output setting information. And store it in the CR communication information storage area. As a result, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control section main process of the payout control section power-on process of FIG. 48. The read PRDY signal output setting information, that is, the PRDY signal whose logic is LOW, is CRed from the output terminal of the predetermined output port of the payout control MPU 4120a of the payout control unit 4120 via the game ball rental device connection terminal board 869. Output to unit 6. On the other hand, when communicating with the CR unit 6 (when the logic of BRDY from the CR unit 6 is HI, that is, when it stands up and is held), the logic state of the EXS signal is maintained, and the logic state of the EXS signal is maintained. Is set in the EXS signal output setting information and stored in the CR communication information storage area. As a result, the EXS signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control section main process of the payout control section power-on process of FIG. 48. The read out EXS signal output setting information, that is, the EXS signal whose logic is maintained is output from the output terminal of the predetermined output port of the payout control MPU 4120a to the CR unit 6 via the game ball rental device connection terminal board 869. .. In addition, "maintaining the logical state of the EXS signal" means that when the logic of the EXS signal is LOW (the EXS signal is held down), the logical LOW is maintained, and the logic of the EXS signal is HI. At some point (holding the XS signal up and running) is to maintain its logical HI.

[16-8-1. Payout setting process]
Next, the payout setting process will be described. In this payout setting process, the payout motor 744 is driven to set the game ball to be paid out.

When the payout setting process is started, in the payout control unit 4120 on the payout control board 4110, the payout control program outputs the drive command number DRV from the payout control built-in RAM as shown in FIG. 57 under the control of the payout control MPU4120a. Read (step S710). This drive command number DRV commands the number of game balls to be paid out by the payout motor 744, and is equivalent to the prize ball stock number PBS. The drive command number DRV is stored in the prize ball information storage area of the payout control built-in RAM. In step S710, the drive command number DRV is read from the prize ball information storage area.

Following step S710, the payout control program determines whether or not the drive command number DRV has a value of 0 (step S712). This determination is determined based on the drive command number DRV whether or not the number of game balls to be paid out by the payout motor 744 remains.

When the drive command number DRV is 0 in step S712, that is, when the number of game balls to be paid out by the payout motor 744 is zero, the payout control program stops (stops) the output of the drive signal to the payout motor 744. ) Is set (step S714). In this setting, the drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the above-mentioned payout control built-in RAM.

Following step S714, the payout control program reads out the prize ball stock number PBS from the prize ball information storage area of the payout control built-in RAM (step S716), and reads out the actual ball count PB (step S718). This actual ball count PB is a count of the number of game balls actually paid out by the payout motor 744. The count will be described in detail later, but the count is from the count switch 751 shown in FIG. 13 in the port input process of step S550 in the payout control unit power-on processing (payout control unit main process) shown in FIG. Perform based on the detection signal. The actual ball count PB is stored in the prize ball information storage area of the payout control built-in RAM. In step S718, the actual ball count PB is read from the prize ball information storage area.

Following step S718, the payout control program sets the value obtained by subtracting the actual ball count PB read in step S718 from the prize ball stock number PBS read in step S716 to the prize ball stock number PBS and the drive command number DRV. (Step S720), the value 0 is set in the actual ball count PB (step S722), and this routine is terminated. When the drive command number DRV and the actual ball count PB are values 0, in step S722, the value of the prize ball stock number PBS read in step S716 is set to the drive command number DRV as it is.

On the other hand, when the drive command number DRV is not a value 0 in step S712, that is, when there is a number of game balls to be paid out by the payout motor 744, the payout control program sets the output of the drive signal to the payout motor 744. (Step S724). In this setting, the drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM.

Following step S724, the payout control program subtracts a value of 1 from the drive command number DRV (decrements, step S726), and determines whether or not there is a detection signal from the counting switch 751 (step S728). This determination is performed based on the detection signal from the counting switch 751 in the port input process of step S550 in the power-on processing of the payout control unit (main process of the payout control unit) shown in FIG. 48. Specifically, the detection signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S728, the payout control program reads the input information from the input information storage area and determines whether or not there is a detection signal from the counting switch 751.

When there is a detection signal from the counting switch 751 in step S728, the payout control program adds a value of 1 to the actual ball counting PB (increments, step S730), and ends this routine. By incrementing the actual ball count PB in step S730, the actual ball count PB is counted up.

On the other hand, when there is no detection signal from the counting switch 751 in step S728, the payout control program ends this routine as it is. As described above, the payout control program is in the case of decrementing the drive command number DRV in step S726 under the control of the payout control MPU4120a, and when there is no detection signal from the counting switch 751 in the determination in step S728, that is, in fact. If it is not incremented to the ball count PB, it is said that one ball could not be paid out because the game ball was not received in the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. to decide. Therefore, the payout control program sets the value obtained by subtracting the actual ball count PB from the prize ball stock number PBS in the above-mentioned step S720 to the drive command number DRV in order to pay out the one ball to be paid out again. As a result, when there is no detection signal from the counting switch 751 in the determination of step S728, that is, when the actual ball counting PB is not incremented, the value 1 which is one ball to be paid out can be included in the prize ball stock number PBS. In other words, since the value 1 which is one ball to be paid out can be rounded into the prize ball stock number PBS, the retry operation to pay out the one ball to be paid out can be performed again. By performing this retry operation, it is possible to extremely reduce the possibility that the game ball is not paid out to the player, and it is possible to prevent the player from being disadvantaged due to the unpaid game ball.

[16-8-2. Ball motion setting process]
Next, the ball-shaped motion setting process will be described. In this ball squeezing operation setting process, it is a process of setting to eliminate the ball squeezing state by the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 of the prize ball device 740 is transmitted.

When the ball squeeze operation setting process is started, in the payout control unit 4120 on the payout control board 4110, the payout control program elapses the ball squeeze determination time as shown in FIG. 58 under the control of the payout control MPU 4120a. It is determined whether or not this has been done (step S750). This determination is made based on the ball squeeze determination time subtracted in the timer update process of step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the ball bending determination time is stored in the time management information storage area of the above-mentioned payout control built-in RAM as time management information. In step S750, the time management information is read from the time management information storage area, and it is determined whether or not the ball squeezing determination time has elapsed.

When the ball squeeze determination time has not elapsed in step S750, the payout control program reads the rotation angle switch detection history information RSW-HIST from the rotation angle switch history information storage area of the above-mentioned payout control built-in RAM (step S752). ..

Following step S752, the payout control program determines whether or not there is a detection signal from the rotation angle switch 752 described above (step S754). In this determination, it is determined whether or not the rotation angle switch detection history information RSW-HIST read in step S752 matches the fixed position determination value. As described above, this fixed position determination value is stored in the payout built-in ROM, and in the present embodiment, it is "00001111B (" B "represents a bit)", and the upper 4 bits B7 to B4 are The value 0 and the lower 4 bits B3 to B0 are the values 1. In the determination in step S754, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST and the lower 4 bits B3 to B0 of the fixed position determination value match.

In step S754, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S752 and the lower 4 bits B3 to B0 of the fixed position determination value do not match, the payout control program determines. The output of the drive signal to the payout motor 744 is set so as to perform the ball-sucking operation (step S756), and this routine is terminated. In this setting, the drive information for outputting the drive signal to the payout motor 744 is set and stored in the output information storage area of the above-mentioned payout control built-in RAM.

On the other hand, in step S754, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S752 and the lower 4 bits B3 to B0 of the fixed position determination value match, the payout control program Sets the stop of the drive signal to the payout motor 744 (step S758). In this setting, the drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM.

Following step S758, the payout control program sets the value 0 in the ball-grinding flag PBE-FLG as the end of the ball-grinding operation (step S760), and ends this routine. This ball-squeezing flag PBE-FLG is a flag indicating whether or not a ball-squashing state is generated by the payout rotating body, and has a value of 1 when the payout motor 744 is performing a ball-sucking operation. When no operation is performed (end of ball-sliding operation), the values are set to 0, respectively.

On the other hand, when the ball squeeze determination time has elapsed in step S750, the payout control program sets the stop of the drive signal to the payout motor 744 (step S762). In this setting, the drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM.

Following step S762, the payout control program sets the output of the error state to the CR unit 6 (step S764). Here, in order to inform the CR unit 6 that the ball cannot be lent at present, the payout control MPU4120a is not communicating with the CR unit 6 (the logic of BRDY from the CR unit 6 is LOW, that is, When it is down and held), the logic of the PRDY signal is LOW, that is, the down state is held, and the logic state of the PRDY signal is set in the PRDY signal output setting information and stored in the CR communication information storage area. do. As a result, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control section main process of the payout control section power-on process of FIG. 48. The read PRDY signal output setting information, that is, the PRDY signal whose logic is LOW, is CRed from the output terminal of the predetermined output port of the payout control MPU 4120a of the payout control unit 4120 via the game ball rental device connection terminal board 869. Output to unit 6. On the other hand, when communicating with the CR unit 6 (when the logic of BRDY from the CR unit 6 is HI, that is, when it stands up and is held), the logic state of the EXS signal is maintained, and the logic state of the EXS signal is maintained. Is set in the EXS signal output setting information and stored in the CR communication information storage area. As a result, the EXS signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control section main process of the payout control section power-on process of FIG. 48. The read out EXS signal output setting information, that is, the EXS signal whose logic is maintained is output from the output terminal of the predetermined output port of the payout control MPU 4120a to the CR unit 6 via the game ball rental device connection terminal board 869. .. As described above, "maintaining the logical state of the EXS signal" means that when the logic of the EXS signal is LOW (the EXS signal is held down), the logical LOW is maintained and the EXS signal is maintained. When the logic of is HI (the XS signal is held up), that logic HI is maintained.

Following step S764, the payout control program sets the value 0 in the ball-grinding flag PBE-FLG as the end of the ball-grinding operation (step S766), and ends this routine.

[16-9. Retry operation monitoring process]
Next, the retry operation monitoring process will be described. In this retry operation monitoring process, it is a process of monitoring whether or not the retry operation of paying out the game ball to be paid out again is normally performed.

When the retry operation monitoring process is started, in the payout control unit 4120 on the payout control board 4110, the payout control program controls the payout control MPU4120a, and as shown in FIG. 59, the rotation angle of the above-mentioned payout control built-in RAM. The rotation angle switch detection history information RSW-HIST is read from the switch history information storage area (step S770).

Following step S770, the payout control program determines whether or not there is a detection signal from the rotation angle switch 752 described above (step S772). This determination determines whether or not the rotation angle switch detection history information RSW-HIST read in step S770 matches the fixed position determination value. As described above, this fixed position determination value is stored in the ROM with built-in payout control, and in the present embodiment, it is "00001111B (" B "represents a bit)", and the upper 4 bits B7 to B4. Is a value 0, and B3 to B0 of the lower 4 bits are a value 1. In the determination in step S772, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST and the lower 4 bits B3 to B0 of the fixed position determination value match.

In step S772, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S770 and the lower 4 bits B3 to B0 of the fixed position determination value match, the payout control program determines. The value 1 is added to the inconsistency counter INCC (increment, step S774). This mismatch counter INCC includes the number of game balls that are received and discharged in the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted, the number of balls detected by the counting switch 751 and the number of balls. This is a counter for calculating the difference between the two, and usually, the number of game balls received and paid out in the recess of the payout rotating body matches the number of balls detected by the counting switch 751. , The value is 0. Since the payout control program performs a retry operation in the payout installation process shown in FIG. 57, the number of game balls received and paid out in the recess of the payout rotating body by this retry operation and the actual counting switch. The inconsistency counter INCC monitors and determines whether or not the number of balls detected in 751 and the inconsistent payout of game balls due to the inconsistency are repeated. The inconsistency counter INCC is stored in the prize ball information storage area of the payout control built-in RAM. In step S774, the payout control program increments the inconsistency counter INCC stored in the prize ball information storage area.

Following step S774 or in step S772, the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S770 and the lower 4 bits B3 to B0 of the fixed position determination value do not match. Occasionally, the payout control program determines if there is a detection signal from the counting switch 751 (step S776). This determination is performed based on the detection signal from the counting switch 751 in the port input process of step S550 in the power-on processing of the payout control unit (main process of the payout control unit) shown in FIG. Specifically, as described above, the detection signal is stored as input information in the input information storage area of the above-mentioned payout control built-in RAM. In step S776, the payout control program reads the input information from the input information storage area and determines whether or not there is a detection signal from the counting switch 751.

When there is a detection signal from the counting switch 751 in step S776, the payout control program subtracts a value of 1 from the mismatch counter INCC stored in the prize ball information storage area of the payout control built-in RAM (decrement, step S778). ..

Following step S778, or when there is no detection signal from the counting switch 751 in step S776, the payout control program determines whether the value of the mismatch counter INCC is less than the mismatch threshold INCTH (step S780). ). In the pachinko gaming machine 1, it has been experimentally obtained that the probability that one inconsistent gaming ball is paid out due to the retry operation is about 1 in millions, and in the present embodiment, the inconsistency threshold value is obtained. A value of 5 is set as INCTH.

As described above, in the process of setting the work area of the payout control built-in RAM in step S530 in the payout control unit power-on process of FIG. 48, the payout backup information stored in the payout control built-in RAM at the time of power recovery. , Information used for this retry operation monitoring process is set based on the inconsistency counter INCC stored in the prize ball information storage area. By this processing, for example, even if there is a momentary power failure or a power failure, the value of the inconsistent counter INCC or the like at the time of power recovery is restored to the value of the mismatch counter INCC or the like immediately before the momentary power failure or the power failure stored as the payout backup information. You can do it. As a result, in the determination of step S780, the monitoring of the game ball payout operation (retry operation) by the prize ball device 740, which was performed until immediately before the momentary power failure or power failure, can be continued from the time of power recovery. ing. Therefore, for example, when the value of the inconsistency counter INCC is smaller than the inconsistency threshold value INCTH in the determination of step S780 immediately before the momentary power failure or power failure, it is determined that the retry operation is operating normally, that is, the prize ball. It can be determined that the payout operation of the game ball by the device 740 is in the normal state, and even at the time of power recovery, it can be determined that the payout operation of the game ball by the prize ball device 740 is in the normal state by the determination in step S780. On the other hand, when the value of the inconsistency counter INCC is not smaller than the inconsistency threshold value INCTH in the determination in step S780, it is determined that the retry operation is abnormal, that is, the game ball payout operation by the prize ball device 740 is abnormal. It can be determined that the state is in the state, and even at the time of power recovery, it can be determined in the determination in step S780 that the payout operation of the game ball by the prize ball device 740 is in an abnormal state.

When the value of the inconsistency counter INCC is smaller than the inconsistency threshold value INCTH in step S780, this routine is terminated as it is. On the other hand, when the value of the inconsistency counter INCC is not smaller than the inconsistency threshold value INCTH in step S780, that is, when the value of the inconsistency counter INCH is equal to or more than the inconsistency threshold value INCTH, the payout control program determines the "retry error". In order to notify that, the error LED display 860b, which is a segment display mounted on the payout control board 4110, is set with retry error information for displaying the number “5”, and the above-mentioned payout control built-in RAM is set. Is set (stored) in the state information storage area of (step S782). On the other hand, in the case of notifying that "the prize ball is in stock", the payout control program sets the information in the prize ball stock that displays the number "9" on the error LED display 860b and has the above-mentioned built-in payout control. It is set (stored) in the state information storage area of the RAM (step S782).

Following step S782, the payout control program sets a value 0 (initial value 0) in the mismatch counter INCC stored in the prize ball information storage area of the payout control built-in RAM (step S784). In step S784, the inconsistent counter INCC is determined in step S780 when the value of the inconsistent counter INCC is not smaller than the inconsistent threshold value INCTH, that is, when the value of the inconsistent counter INCC is equal to or greater than the inconsistent threshold value INCTH. It is initialized when this internal factor occurs. The inconsistency counter INCC is initialized when the operation switch 860a is operated to clear the RAM when the power is turned on, triggered by the occurrence of this external factor. When the operation switch 860a is operated when the power is turned on, as described above, the operation signal corresponding to the operation is input to the main control MPU 4100a of the main control board 4100 shown in FIG. 12 as a RAM clear signal. Under the control of the main control MPU4100a, the above-mentioned main control program erases all the various information stored in the main control built-in RAM, and issues a RAM clear notification command to the peripheral control board shown in FIG. Output to 4140. As a result, the RAM clear notification sound flows from the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and the speaker 130 provided in the door frame 5 shown in FIG.

Following step S784, the retry error flag RTERR-FLG is set to a value of 1 (step S786), and this routine ends. This retry error flag RTERR-FLG is a flag indicating whether or not the retry operation is abnormally operating, and has a value of 1 when the retry operation is abnormally operating and when the retrying operation is not abnormally operating (retrying operation is). It is set to 0 when it is operating normally).

Note that the payout control program shows retry error information (or information in prize ball stock) set (stored) in the output information storage area of the payout control built-in RAM in step S782 under the control of the payout control MPU4120a. In the command transmission process of step S566 in the power-on processing of the payout control unit (main process of the payout control unit), a retry error status command is created and transmitted to the main control board 4100, and the LED display data of step S564 in the same process is created. In the process, display data to be displayed on the error LED display 860b is created and stored as LED display information in the output information storage area, and the LED display information stored in the output information storage area in the port output process of step S548 in the same process. Based on this, a drive signal is output to the error LED display 860b, and the number "5" is displayed on the error LED display 860b. In the main control board 4100 that has received the state command, the main control program transmits the peripheral control board command transmission process in step S120 in the main control side timer interrupt process shown in FIG. 45 to the peripheral control board 4140. FIG. 15 shows a door frame side lighting / blinking command for outputting a lighting signal, in which the peripheral control board 4140 causes a plurality of LEDs of various decorative boards provided on the door frame 5 to emit light in a predetermined color (red in this embodiment). It is output to the frame decoration drive amplifier board 194 shown in 1 and a plurality of LEDs are made to emit light in a predetermined color. As described above, the clerk in the hall who noticed the light emission of the plurality of LEDs displayed the number "" on the error LED display 860b mounted on the payout control board 4110 by opening the main body frame 3 with respect to the outer frame 2. It can be confirmed that the "retry error" has occurred by visually observing that "5" is displayed. As a result, the clerk in the hall, etc., in order to investigate the cause of the occurrence, confirms the malfunction of the counting switch 751, the disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, the contact failure of various connectors, and the like. This can be performed extremely quickly as compared with the case where the light emission of a plurality of LEDs and the display content of the error LED display 860b are not notified.

Further, by intentionally deactivating the counter switch 751, it is difficult to detect the game ball that is received and paid out by the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. Even if a retry operation is forcibly generated and a fraudulent act of illegally acquiring the game ball paid out by this retry operation is performed, the value of the inconsistency counter INCC described above becomes equal to or higher than the inconsistency threshold INCTH. Since a plurality of LEDs of various decorative boards provided on the door frame 5 emit light, a clerk in the hall or the like rushes to check the state of the pachinko gaming machine 1. Then, the player who commits the fraudulent act has no choice but to interrupt the act so that the act is not discovered, and cannot continuously acquire the fraudulent game ball due to the fraudulent act. Even if the value of the inconsistency counter INCC matches the inconsistency threshold value INCTH, the number of game balls that can be acquired by the cheating player is the same as the inconsistency threshold value INCTH, that is, 5 balls. Therefore, the damage to the hall due to the act of intentionally deactivating the counting switch 751 can be suppressed to an extremely small level.

Further, as described above, when the value of the inconsistent counter INCC is not smaller than the inconsistent threshold value INCTH in step S780, that is, the value of the inconsistent counter INCC is equal to or more than the inconsistent threshold value INCTH. It has come to be initialized when an internal factor such as the fact that it has become is generated. As a result, the inconsistency counter INCC is not initialized when, for example, an external factor such as operating the operation switch 860a to clear the error occurs. Therefore, even if the operation switch 860a or the like is illegally modified so that the operation signal is input to the payout control MPU4120a, the inconsistency counter INCC may be forcibly initialized by such an illegal act. do not have.

[16-10. Inconsistency counter reset judgment process]
Next, the inconsistency counter reset process will be described. In this inconsistency counter reset process, the number of game balls received and paid out in the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted, and the number of balls detected by the counting switch 751. This is a process of determining whether or not to reset the inconsistency counter INCC that calculates the difference between.

When the inconsistency counter reset determination process is started, in the payout control unit 4120 on the payout control board 4110, the payout control program controls the inconsistency counter reset determination time as shown in FIG. 60 under the control of the payout control MPU4120a. It is determined whether or not the elapse has passed (step S790). This determination is made based on the inconsistency counter reset determination time updated in the timer update process of step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG. 48. Specifically, the inconsistency counter reset determination time is stored in the time management information storage area of the above-mentioned payout control built-in RAM as time management information. In step S790, the time management information is read from the time management information storage area, and it is determined whether or not the inconsistency counter reset determination time has elapsed.

When the inconsistency counter reset determination time has not elapsed in step S790, the payout control program ends this routine as it is. On the other hand, when the inconsistency counter reset determination time has elapsed in step S790, the payout control program initializes the inconsistency counter reset determination time (step S792). By this initialization, the inconsistency counter reset determination time is set to the initial value of 7000s (about 2 hours).

Following step S792, the payout control program sets the inconsistency counter INCC stored in the prize ball information storage area of the payout control built-in RAM to a value 0 (initial value 0) (step S794), and this routine To finish. As described above, the mismatch counter INCC was detected by the counting switch 751 and the number of game balls that were received and paid out in the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. It is a counter for calculating the difference between the number of balls and the number of game balls that are usually received and paid out in the recess of the payout rotating body, and the number of balls detected by the counting switch 751 is one. The value is 0 because it is done. Since the payout control program performs a retry operation in the payout installation process shown in FIG. 57 under the control of the payout control MPU4120a, the ball of the game ball received and paid out in the recess of the payout rotating body by this retry operation. The inconsistency counter INCC monitors and determines whether or not the number and the number of balls actually detected by the counting switch 751 are inconsistent with each other and the game balls are paid out repeatedly. In the pachinko gaming machine 1 of the present invention, it has been experimentally obtained that the probability that one inconsistent gaming ball is paid out due to a retry operation is about 1 in millions.

Here, as described above, the pachinko game machine 1 is composed of a game board 4 and a frame body such as a main body frame 3 on which the game board 4 is mounted, and by exchanging the game board 4 (replacement of a new machine). Since the game specifications can be changed, the payout control board 4110 that controls the prize ball device 740, and the power supply board 851 that generates the drive power supply for the prize ball device 740 and the control power supply for the payout control board 4110 are common. It is equipped on the frame side as a function. In the payout control unit 4120 of the payout control board 4110, it is abnormal whether or not the payout control program repeatedly performs the retry operation by monitoring the inconsistency counter INCC as described above under the control of the payout control MPU4120a. The operation can be determined, and in the payout control unit power-off processing in the payout control unit power-on processing shown in FIG. 48, the inconsistency counter INCC immediately before the power-off is stored when the power is turned off, while FIG. In the process of step S530 (setting at the time of power recovery of the RAM work area) in the process at the time of power-on of the payout control unit shown in 47, the process is restarted from the stored inconsistency counter INCC at the time of power-on.

Then, when the power is cut off and the game board 4 mounted on the pachinko game machine 1 is replaced with a game board 4'of another game specification different from the game board 4, the payout control is performed. The payout control MPU4120a of the payout control unit 4120 on the board 4110 starts processing again from the inconsistency counter INCC stored when the game board 4 is mounted on the pachinko gaming machine 1. That is, when the player plays the pachinko gaming machine 1 equipped with the gaming board 4', the inconsistency counter INCC in the pachinko gaming machine 1 equipped with the gaming board 4 before replacement is inherited as it is. For this reason, the player plays the pachinko game machine 1 equipped with the game board 4', and there is a probability of 1 in millions that the number of inconsistent game balls is generated, and the inconsistency counter INCC. When the inconsistency counter INCC becomes equal to or higher than the above-mentioned inconsistency value INCTH, the game board 4 is replaced with the game board 4', and in a short period of time, the payout control MPU4120a determines that the retry operation is abnormal. There is a risk of That is, in the short period after the game board 4 is replaced with the game board 4', the counting switch 751 is defective, the various harnesses extending from the counting switch 751 to the payout control board 4110 are broken, and the various connectors are poorly contacted. There is a possibility that it is suddenly determined as an abnormal operation of the retry operation even though the above has not occurred.

In this way, when the game board 4 is replaced with the game board 4'and judged as an abnormal operation of the retry operation in a short period of time, the replaced game board 4'is new, but the impression is that it is easy to break down. It may be given to the player. The probability that one inconsistent game ball will be paid out due to the retry operation is 1 in millions when the pachinko game machine 1 is installed in the hall and continuously operated for one week during the hall's business hours. , Since it is the same as the probability that one inconsistent game ball due to the retry operation is paid out, the probability of one millionth from the inconsistency counter INCC in the process of step S778 in the retry operation monitoring process shown in FIG. 59. In the state where only the value 1 is not subtracted. Then, in one week, the value 1 is incremented to the inconsistent counter INCC and the inconsistent counter INCC becomes the value 1, and in two weeks, the value 1 is further incremented to the inconsistent counter INCC and the inconsistent counter INCC becomes the value 2. In the week, the value 1 is further incremented to the inconsistent counter INCC and the inconsistent counter INCC becomes the value 3, and in the 4th week, the value 1 is further incremented to the inconsistent counter INCC and the inconsistent counter INCC becomes the value 4. The value 1 is further incremented by the inconsistency counter INCC, and the inconsistency counter INCC becomes a value of 5, which coincides with the above-mentioned inconsistency threshold INCTH. That is, after 5 weeks have passed, since the inconsistency counter INCC matches the inconsistency threshold INCTH, the payout control program controls the payout control MPU4120a, and in step S776 in the retry operation monitoring process shown in FIG. 59. In the judgment, it is judged that there is no detection signal from the counting switch 751, and a malfunction of the counting switch 751, disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, poor contact of various connectors, etc. occur. This is a segment display mounted on the payout control board 4110 in order to notify that a “retry error” has occurred in the process of step S782 in the retry operation monitoring process shown in FIG. 59. Retry error information for displaying the number "5" is set on the error LED display 860b and set (stored) in the state information storage area of the payout control built-in RAM.

Therefore, when the payout control MPU4120a determines that the inconsistency counter reset determination time has elapsed in the determination in step S790 in this inconsistency counter reset determination process, that is, every 7000s (about 2 hours), the inconsistency counter reset is repeated. By forcibly setting the value 0 to the inconsistency counter INCC in the process of step S794 in the determination process, that is, forcibly resetting it, the increment of the inconsistency counter INCC that occurs with a probability of 1 in millions described above is incremented. It has been disabled. As a result, an error has occurred in the retry operation even though there is no malfunction of the counting switch 751, disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, poor contact of various connectors, and the like. It is possible to prevent the retry error information for transmitting the above from being set (stored) in the state information storage area of the payout control built-in RAM.

It should be noted that by intentionally deactivating the counting switch 751, it is difficult to detect the game ball that is received and paid out by the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. Even if a retry operation is forcibly generated and a fraudulent act of illegally acquiring the game ball paid out by this retry operation is performed, the counting switch 751 is intentionally repeatedly inactive for a short time as described above. As described above, when the value of the inconsistency counter INCC becomes equal to or higher than the inconsistency threshold INCTH, a plurality of LEDs of various decorative boards provided on the door frame 5 emit light, so that the clerk in the hall or the like can check the state of the pachinko gaming machine 1. I will rush to confirm. Then, the player who commits the fraudulent act has no choice but to interrupt the act so that the act is not discovered, and cannot continuously acquire the fraudulent game ball due to the fraudulent act. On the other hand, when the counting switch 751 is intentionally repeatedly inactive for a long time so that the value of the inconsistency counter INCC does not exceed the inconsistency threshold value INCTH, the inconsistency counter INCC is set every 7000s (about 2 hours). Although it is reset, the number of game balls that can be acquired by the cheating player during this period is, as described above, the inconsistency counter INCC up to the inconsistency threshold value INCTH, and the counting switch 751 is intentionally set. Even if the player is repeatedly inactive for a long time, the number of game balls that can be acquired by a player who cheats can be extremely reduced.

[16-11. Error release operation judgment processing]
Next, the error release operation determination process will be described. In this error release operation determination process, it is determined whether or not the operation switch 860a shown in FIG. 13 is operated.

When the error release operation determination process is started, in the payout control unit 4120 on the payout control board 4110, the payout control program releases the error by the operation switch 860a under the control of the payout control MPU4120a as shown in FIG. It is determined whether or not the operation is performed (step S800). This determination is performed based on the operation signal from the operation switch 860a in the port input process of step S550 in the power-on processing of the payout control unit (main process of the payout control unit) shown in FIG. 48. Specifically, the operation signal is stored as input information in the input information storage area of the above-mentioned payout control built-in RAM. In step S800, it is determined that the payout control program does not read the input information from the input information storage area and instruct to cancel the error when the logical value of the operation signal from the operation switch 860a is HI. While it is determined that the operation switch 860a is not operated, it is determined that when the logical value of the operation signal from the operation switch 860a is LOW, it is determined that the error is cleared and the operation switch 860a is operated. It is determined that it is.

When the operation switch 860a is not operated in step S800, the payout control program terminates this routine as it is, while when the operation switch 860a is operated in step S800, the payout control program performs an error flag status confirmation process. (Step S802). In this error flag state determination process, the state of the error flag corresponding to various error information related to the prize ball device 740 is confirmed. For example, the state of the retry error flag RTERR-FLG indicating whether or not the retry operation is abnormal is confirmed. As described above, the retry error flag RTERR-FLG has a value of 1 when the retry operation is abnormally operating and a value of 0 when the retry operation is not abnormally operating (the retry operation is operating normally). Since it is set, the payout control program confirms whether the value of the retry error flag RTERR-FLG is a value 0 or a value 1 under the control of the payout control MPU4120a.

Following step S802, the payout control program performs the state information setting process (step S804). In this state information setting process, if the state of the error flag indicates that an error has occurred based on the error flag confirmed in step S802, the state information corresponding to the error flag is described above. Set (store) in the status information storage area of the dispensed control built-in RAM. As a result, various information (state information) is read from the state information storage area in the command transmission process of step S566 in the power-on processing of the payout control unit (main process of the payout control unit) shown in FIG. 48, and the read state is read. A state command is created based on the information and transmitted to the main control board 4100. For example, when the retry error flag RTERR-FLG indicating whether or not the above-mentioned retry operation is abnormally operating has a value of 1, that is, when the retrying operation is abnormally operating, an error has occurred in the retrying operation. When the retry error information to be transmitted is set (stored) in the state information storage area of the payout control built-in RAM, the command transmission process in step S566 in the payout control unit power-on processing (payout control unit main process) shown in FIG. 48 A retry error status command is created and sent to the main control board 4100.

The main control board 4100 that has received the retry error information is transmitted by the main control program to the peripheral control board 4140 in the peripheral control board command transmission process of step S120 in the main control side timer interrupt process shown in FIG. 45. On the control board 4140, the sub-control program performs a retry operation error notification process for notifying that an error has occurred in the retry operation. In this retry operation error notification process, the error notification announcement of the retry operation of "Please check the prize ball unit" and "Check the harness of the payout control board" is made a predetermined number of times (in this embodiment). 2 times.) Repeatedly, the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and the speaker 130 provided in the door frame 5 shown in FIG. It is designed to do. The clerk in the hall who heard the error notification announcement of this retry operation had a malfunction of the counting switch 751 shown in FIG. 13, disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, poor contact of various connectors, etc. This can be confirmed extremely quickly as compared with the case where the error notification announcement of the retry operation does not flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. Further, in the retry operation error notification process, a plurality of LEDs of various decorative substrates provided on the door frame 5 are made to emit light in a predetermined color (red in the present embodiment).

Following step S804, the payout control program performs the release setting process (step S806). In this release setting process, based on the error flags corresponding to the various error information confirmed in step S802, if the state of the error flag indicates that an error has occurred, it corresponds to the error flag. The CR unit 6 indicates that the content displayed by the error LED display 860b, which is a segment display already mounted on the payout control board 4110, can be forcibly stopped or the ball can be rented. In order to convey the above-mentioned logic of the PRDY signal to HI, that is, the state in which it is started up is maintained, and the game ball or the like lending device connection terminal plate 869 is connected from the output terminal of the predetermined output port of the payout control MPU 4120a of the payout control unit 4120. It is output to the CR unit 6 via. For example, when the retry error flag RTERR-FLG indicating whether or not the above-mentioned retry operation is abnormally operating has a value of 1, that is, when the retry operation is abnormally operating, the error LED display 860b has already displayed the error. The retry error information stored in the state information storage area of the above-mentioned payout control built-in RAM is "normal" in order to forcibly stop the number "5" that notifies that the "retry error" is present. Forcibly overwrite the information in which the figure "-" that notifies the effect is displayed. Further, in order to inform the CR unit 6 that the ball can be rented, the logic of the PRDY signal is kept in the HI, that is, the rising state, and the game ball is played from the output terminal of the predetermined output port of the payout control MPU4120a. It is output to the CR unit 6 via the equal rental device connection terminal board 869.

Following step S806, the payout control program performs error flag initialization processing (step S808), and ends this routine. In this error flag initialization process, if the state of the error flag indicates that an error has occurred based on the error flag corresponding to the various error information confirmed in step S802, the error flag is set. initialize. For example, when the retry error flag RTERR-FLG indicating whether or not the above-mentioned retry operation is abnormally operating has a value of 1, that is, when the retry operation is abnormally operating, a value 0 is set to the retry error flag RTERR-FLG. Set and initialize. At this time, the logic of the PRDY signal described above is held in the HI, that is, the rising state, and the logic state of the PRDY signal is set in the PRDY signal output setting information and stored in the CR communication information storage area. As a result, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control section main process of the payout control section power-on process of FIG. 48. The read PRDY signal output setting information, that is, the PRDY signal whose logic is LOW is output from the output terminal of the predetermined output port of the payout control MPU 4120a to the CR unit 6 via the game ball rental device connection terminal board 869. ..

As described above, the retry error flag RTERR-FLG is an internal factor when the value of the inconsistency counter INCC is equal to or more than the inconsistency threshold value INCTH in the determination of step S780 in the retry operation monitoring process shown in FIG. 59. Is set to the retry error flag RTERR-FLG in the process of step S786 of the same process, but when the operation switch 860a is operated, this is an opportunity, that is, this external factor is caused. When it occurs, the retry error flag RTERR-FLG is set to a value of 0 and initialized. When the operation switch 860a is operated to clear the RAM when the power is turned on, the retry error flag RTERR-FLG is operated to clear the RAM in order to clear the RAM, that is, the operation switch 860a is operated to clear the RAM. Similar to the case where the switch 860a is operated, it is initialized when this external factor occurs.

As described above, in the pachinko gaming machine 1, the main control side main processing executes the operation switch 860a (operation switch), which was originally supposed to be used to clear the error that occurred in the payout operation, from the time when the power is turned on. An operation for demonstrating the RAM clear function for starting the initialization of the main control built-in RAM (game storage unit) and the payout control built-in RAM (payout storage unit) for a predetermined time until the error is performed. It is functioning as a department. Further, the pachinko gaming machine 1 causes the operation switch 860a to function as an operation unit for canceling an error generated in the payout operation of the game ball after the lapse of the predetermined time. Here, even if the hall clerk is not accustomed to operating the pachinko machine, as long as he / she remembers the position of the operation switch 860a on the back of the gaming machine, he / she can operate the operation switch 860a according to the timing of operating the operation switch 860a. If a predetermined time has passed from the time when the power is turned on, the function of canceling the error generated in the payout operation of the game ball is exerted, while the predetermined time is determined from the time when the power is turned on according to the timing when the operation switch 860a is operated. Within the time, the function of initializing the storage unit can be exerted. Therefore, even if an error occurs in such a gaming machine, the hall clerk can improve the efficiency of the switch operation when dealing with the error and can appropriately deal with the switch operation without hesitation, so that the game is interrupted. The game can be restarted before the player is discouraged from playing the game.

[16-12. Exchange of various signals with the CR unit]
Next, the CR communication process in step S554 in the payout control section main process of the payout control section power-on process of FIG. 48 will be described using a timing chart. In this CR communication process, various signals are exchanged between the payout control board 4110 and the CR unit 6 shown in FIG. First, the signal processing at the time of payout operation by ball lending will be described, and then the input signal confirmation processing from the CR unit 6 will be described. Here, the number of game balls for 200 yen as the amount of money (in this embodiment, 50 balls, and the payout operation of 25 balls for 100 yen as the amount of money is performed twice) is used as the number of balls to be rented. A case of paying out to the upper plate 301 and the lower plate 302 shown in FIG. 7 will be described. The BRQ signal, BRDY signal, and CR connection signal from the CR unit 6 read input information from the input information storage area of the payout control built-in RAM and store it in the read input information, and perform CR communication processing. Checks the logical state of the BRQ signal, BRDY signal, and CR connection signal from the input information every 2 ms, which is the interrupt timer cycle.

[16-12-1. Signal processing during payout operation by lending a ball]
The payout control MPU4120a of the payout control unit 4120 on the payout control board 4110 reads out the PRDY signal output setting information from the CR communication information storage area of the payout control built-in RAM, and the read out PRDY signal output setting information pays out the rental ball. When it is set to the logical state of the PRDY signal that conveys that the payout operation is possible, as shown in FIG. 62 (d), the payout operation for paying out the rental ball is possible. The logic of the PRDY signal is HI, that is, it is started up and held, and is output from the output terminal of the predetermined output port of the payout control MPU4120a of the payout control unit 4120. It is output to the CR unit 6 via the plate 869 (timing H0). In this state, for example, when the player presses the ball lending button 361 of the ball lending unit 360 shown in FIG. 2, the ball lending switch 365b is switched on (turned on). The operation signal is input to the CR unit 6 from the frequency display board 365 as the TDS shown in FIG. 14 via the game ball rental device connection terminal board 869. The CR unit 6 into which the TDS is input pays out the number of game balls worth 200 yen as the number of balls to be rented to the upper plate 301 and the lower plate 302, as shown in FIG. 62 (a). BRDY, which is a ball request signal, is output from the CR unit 6 to the payout control board 4110 (payout control MPU4120a) via the game ball rental device connection terminal board 869, and the signal is started up and held (timing H1). .. This BRDY is input as a BRDY signal to the input terminal of a predetermined input port of the payout control MPU4120a.

In the payout control MPU4120a to which the BRDY signal is input, the payout control program sets the lending request monitoring time HA (in the present embodiment, 20 milliseconds (ms) to 58 ms) from the timing H1 as shown in FIG. 62 (b). By the time the set number has elapsed, the number of balls rented from the CR unit 6 via the game ball renting device connection terminal board 869 (25 balls in the present embodiment) in one payout operation. , Equivalent to 100 yen as the amount of money.) It is monitored whether or not BRQ, which is a signal for requesting the start of one payout operation for paying out, is started.

Of the number of game balls worth 200 yen, the CR unit 6 first pays out the number of game balls worth 100 yen to the upper plate 301 and the lower plate 302 as the number of rented balls, so FIG. 62 (b) ), The BRQ is output from the CR unit 6 to the CR unit 6 via the game ball rental device connection terminal board 869 from the timing H1 until the rental request monitoring time HA elapses, and the signal is output. Start up and hold (timing H2). This BRQ is input as a BRQ signal to the input terminal of a predetermined input port of the payout control MPU4120a.

As shown in FIG. 62 (c), when the BRQ signal rises from the timing H1 until the lending request monitoring time HA elapses, the payout control MPU4120a starts from the timing H2 to the BRQ request approval ACK monitoring time HB (in the present embodiment, (It is set to 20 ms ± 1 ms.) In order to convey that one payout operation has started by the time, the logic of the EXS signal is set to HI, that is, the payout control MPU4120a is held in the started state. It is output from the output terminal of the predetermined output port of the above, and is output to the CR unit 6 as EXS via the game ball or the like rental device connection terminal board 869 (timing H3).

As shown in FIG. 62 (b), the CR unit 6 to which the XS is input has a lending instruction monitoring time HC (set to 20 ms to 58 ms in this embodiment) from timing H3 to elapse. The BRQ that has been started up and held from the timing H2 is output from the CR unit 6 to the payout control board 4110 via the game ball rental device connection terminal board 869, and the signal is lowered and held (timing H4).

As shown in FIG. 62 (c), the payout control MPU4120a performs one payout operation from the timing H4 until the payout monitoring time HD (in the present embodiment, the ball payout time is set) elapses. Go and pay out the predetermined number of balls to be rented, that is, the number of game balls for 100 yen to the upper plate 301 and the lower plate 302 as the number of rented balls. Then, when the payout monitoring time HD elapses, the XS signal that is started up and held from the timing H3 is held as LOW, that is, in the downed state, and is output from the output terminal of the predetermined output port of the payout control MPU4120a. , EXS is output to the CR unit 6 via the game ball rental device connection terminal board 869 (timing H5).

Since the CR unit 6 pays out the remaining 100 yen worth of game balls out of the 200 yen worth of game balls to the upper plate 301 and the lower plate 302 as the number of rented balls, FIG. 62 (b) ), The BRQ is transferred from the CR unit 6 to the game ball rental device connection terminal board by the time when the next request confirmation timing HE (in this embodiment, the maximum is set to 268 ms) elapses from the timing H5. It is output to the payout control board 4110 (payout control MPU4120a) via the 869, and the signal is started up and held (timing H6).

Similarly, when the payout control MPU4120a pays out the remaining 100 yen worth of game balls to the upper plate 301 and the lower plate 302 as the number of rented balls by using the method described above, as shown in FIG. 62 (c). , The logic of the XS signal that has been started up and held is held as LOW, that is, in the lowered state, and is output from the output terminal of the predetermined output port of the payout control MPU4120a. It is output to the CR unit 6 via the plate 869 (timing H7).

As shown in FIG. 62 (a), the CR unit 6 stands up from the timing H1 until the CR unit lending completion monitoring time HF (in the present embodiment, the maximum is set to 268 ms) elapses from the timing H7. The raised and held BRDY is output from the CR unit 6 to the payout control board 4110 (payout control MPU4120a) via the game ball rental device connection terminal board 869, and the signal is lowered and held (timing H8).

The above-mentioned lending request monitoring time HA, BRQ request approval ACK monitoring time HB, lending instruction monitoring time HC, payout monitoring time HD, next request confirmation timing HE, and CR unit lending completion monitoring time HF are the payout control shown in FIG. The time is measured in the timer update process of step S552 in the process when the power is turned on (main process of the payout control unit).

The payout control MPU4120a is not communicating with the CR unit 6 when the ball is out, the ball is flat, a counting switch error, a retry error, a full tank, etc. (the logic of BRDY from the CR unit 6). Is LOW, that is, when it is held down), as shown in FIG. 62 (d), the PRDY signal that is started up and held from the timing H1 is set to the logic of LOW, that is, in the state of being held down. It is held and output from the output terminal of the predetermined output port of the payout control MPU4120a, and is output as a PRDY to the CR unit 6 via the game ball or the like rental device connection terminal board 869 (timing H9). On the other hand, when communicating with the CR unit 6 (when the logic of BRDY from the CR unit 6 is HI, that is, when it stands up and is held), although not shown, the logic state of the EXS signal is maintained and dispensed. It outputs from the output terminal of the predetermined output port of the control MPU 4120a, and outputs as EXS to the CR unit 6 via the game ball or the like rental device connection terminal board 869. "Maintaining the logic state of the EXS signal" means that when the logic of the EXS signal is LOW (the EXS signal is held down), the logic LOW is maintained, and the logic of the EXS signal is HI (maintaining the logic state of the EXS signal). It is to maintain its logical HI when the EXS signal is up and held).

In this way, the CR unit 6 exchanges various signals with the payout control MPU 4120a of the payout control unit 4120 on the payout control board 4110, and the payout control MPU 4120a uses the number of game balls for 200 yen as the amount of money and 100 as the amount of money. By performing the payout operation of 25 balls for a yen twice, the game balls having a loan number of 50 balls are paid out to the upper plate 301 and the lower plate 302. A clerk in the hall or the like operates a setting unit (not shown) provided on the front side of the CR unit 6, for example, the upper plate 301 or the number of balls rented for 100 yen as the amount of money. When it is set to pay out to the lower plate 302, the payout control MPU4120a performs a payout operation of 25 balls for 100 yen as the amount of money once, and the number of game balls for 500 yen as the amount of money is used as the number of rented balls. When it is set to pay out to the upper plate 301 or the lower plate 302, the payout control MPU4120a performs the payout operation of 25 balls for 100 yen as the amount of money five times, and the number of game balls for 1000 yen as the amount of money is calculated. When the number of balls to be rented is set to be paid out to the upper plate 301 or the lower plate 302, the payout control MPU4120a will perform the payout operation of 25 balls for 100 yen as the amount of money 10 times.

[16-12-2. Input signal confirmation processing from CR unit]
In the payout control MPU4120a of the payout control unit 4120 on the payout control board 4110, the CR unit 6 passes the BRQ from the CR unit 6 via the game ball or the like lending device connection terminal board 869 even after the above-mentioned lending request monitoring time HA elapses. Therefore, even if the signal is output to the payout control board 4110 and the signal is not started, or even if the above-mentioned rental instruction monitoring time HC has elapsed, the CR unit 6 connects the BRDY to the game ball rental device from the CR unit 6. The CR unit 6 plays the BRQ from the CR unit 6 even when the signal is output to the payout control board 4110 via the terminal board 869 and the signal is not shut down or the above-mentioned next request confirmation timing HE has passed. Even if the signal is output to the payout control board 4110 via the ball rental device connection terminal board 869 and the signal is not started, or even if the above-mentioned CR unit rental completion monitoring time HF has elapsed, the CR unit 6 is BRDY. Is output from the CR unit 6 to the payout control board 4110 via the game ball rental device connection terminal board 869, and when the signal is not shut down, the BRQ and the BRQ and the XS described above are used. Check whether BRDY is normal or not. Specifically, as shown in FIGS. 62 (e) and 62 (f), the payout control MPU4120a determines that the BRQ and BRDY are not normal (timing J0), and from this timing J0 to a predetermined period JA (in the present embodiment). , 200 ms ± 1 ms), the logic of the PRDY signal is set to LOW, that is, the output is held from the output terminal of the predetermined output port of the payout control MPU 4120a of the payout control unit 4120 while maintaining the lowered state. Then, as a PRDY, it is output to the CR unit 6 via the game ball rental device connection terminal board 869, and the logic of the EXS signal is set as LOW, that is, the predetermined output port of the payout control MPU4120a is held in the down state. It is output from the output terminal of the above, and is output to the CR unit 6 as EXS via the game ball rental device connection terminal board 869 (timing J1).

Subsequently, the payout control MPU4120a uses the logic of the PRDY signal, which is held down from the timing J1 after the lapse of the predetermined period JB (set to 200 ms ± 1 ms in the present embodiment) from the timing J1, as HI. That is, it is held in the started-up state and output from the output terminal of the predetermined output port of the payout control MPU4120a, and is output to the CR unit 6 as a PRDY via the game ball rental device connection terminal board 869 (timing J2). ).

Subsequently, the payout control MPU4120a uses the PRDY signal that is started up and held from the timing J2 after the elapse of the predetermined period JC (in this embodiment, 100 ms ± 1 ms) from the timing J2, and its logic is set to LOW. That is, it is held in the down state and output from the output terminal of the predetermined output port of the payout control MPU4120a, and is output to the CR unit 6 as a PRDY via the game ball rental device connection terminal board 869 (timing J3). ).

Subsequently, the payout control MPU4120a uses the logic of the PRDY signal that is held down from the timing J3 as HI after the elapse of the predetermined period JD (in this embodiment, 100 ms ± 1 ms) from the timing J3. That is, it is held in the started-up state and output from the output terminal of the predetermined output port of the payout control MPU4120a, and is output as a PRDY to the CR unit 6 via the game ball rental device connection terminal board 869 (timing J4). ).

Subsequently, the payout control MPU4120a uses the PRDY signal that is started up and held from the timing J4 after the lapse of a predetermined period JE (set to 100 ms ± 1 ms in this embodiment) from the timing J4, and its logic is set to LOW. That is, it is held in the down state and output from the output terminal of the predetermined output port of the payout control MPU4120a, and is output to the CR unit 6 as a PRDY via the game ball rental device connection terminal board 869 (timing J5). ).

Subsequently, the payout control MPU4120a uses the logic of the PRDY signal that is stopped and held from the timing J5 as HI after the elapse of the predetermined period JF (in this embodiment, 10000 ms ± 1 ms) from the timing J5. That is, it is held in the started-up state and output from the output terminal of the predetermined output port of the payout control MPU4120a, and is output to the CR unit 6 as a PRDY via the game ball rental device connection terminal board 869 (timing J6). ).

The predetermined period JA to the predetermined period JF described above are timed by the timer update process in step S552 in the payout control unit power-on time process (payout control unit main process) shown in FIG. 48.

[17. Various control processes for peripheral control boards]
Next, various processes of the peripheral control board 4140 for receiving various commands from the main control board 4100 (main control MPU 4100a) shown in FIG. 12 will be described with reference to FIGS. 63 to 74. FIG. 63 is a flowchart showing an example of the peripheral control unit power-on processing, FIG. 64 is a flowchart showing an example of the peripheral control unit V blank interrupt processing, and FIG. 65 shows an example of the peripheral control unit 1ms timer interrupt processing. FIG. 66 is a flowchart showing an example of peripheral control unit command reception interrupt processing, FIG. 67 is a flowchart showing an example of peripheral control unit power failure warning signal interrupt processing, and FIG. 68 is a transition to a power saving mode at the time of power recovery. FIG. 69 is a flowchart showing an example of the determination process, FIG. 69 is a flowchart showing an example of the power consumption monitoring process, and FIG. 70 shows the relationship between the value set as the master volume value for power suppression and the power consumption suppression stage. FIG. 6A is a diagram showing the relationship between the brightness set as the brightness for power suppression and the power consumption suppression stage, and FIG. 71 is a flowchart showing an example of the LOCKN signal history creation process. 72 is a flowchart showing an example of the connection failure determination process, FIG. 73 is a flowchart showing an example of the connection recovery process, and FIG. 74 outputs a connection confirmation signal to the INIT terminal of the upper plate side liquid crystal transmitter IC. It is a timing chart explaining the timing.

As shown in FIG. 15, the peripheral control board 4140 is composed of a peripheral control unit 4150, a liquid crystal display, and a sound control unit 4160. Here, various control processes of the peripheral control unit 4150 will be described. First, the peripheral control unit power-on processing will be described, followed by peripheral control unit V blank interrupt processing, peripheral control unit 1ms timer interrupt processing, peripheral control unit command reception interrupt processing, peripheral control unit power failure warning signal interrupt processing, and power recovery. The time-saving mode transition determination process, power consumption monitoring process, LOCKN signal history creation process, connection failure determination process, and connection recovery process will be described. The power saving mode transition determination process at the time of power recovery is the process of step S1004 in the peripheral control unit power-on process described later, and the power consumption monitoring process is the peripheral control unit steady process of the peripheral control unit power-on process described later. The process of step S1027, the LOCKN signal history creation process is executed as one process of the drawing state information acquisition process of step S1110 in the peripheral control unit 1 ms timer interrupt process described later, and the connection failure determination process and the connection recovery process are described later. The peripheral control unit is executed as one of the warning processing of step S1024 in the peripheral control unit steady processing of the power-on processing, and the connection recovery processing is executed following the connection failure determination processing. In the present embodiment, the peripheral control unit power failure warning signal interrupt processing is set to the highest priority as the interrupt processing, followed by the power consumption suppression signal interrupt processing, the peripheral control unit 1ms timer interrupt processing, and the peripheral control unit command reception. The interrupt processing and the peripheral control unit V blank interrupt processing are set in this order.

[17-1. Various control processes of the peripheral control unit]
[17-1-1. Peripheral control unit power-on processing]
First, the peripheral control unit power-on processing will be described with reference to FIG. 63. When the power is turned on to the pachinko gaming machine 1, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 15 performs a power-on processing of the peripheral control unit as shown in FIG. 63. When the peripheral control unit power-on processing is started, the effect control program performs the initial setting processing under the control of the peripheral control MPU4150a (step S1000). In this initial setting process, the effect control program performs a process of initializing the peripheral control MPU4150a itself, a process of determining hot start / cold start, a process of setting a wait timer after reset, and the like. The peripheral control MPU4150a first performs a process of initializing itself, and the time required for the process of initializing the peripheral control MPU4150a is on the order of microseconds (μs), and the peripheral control MPU4150a is initialized in an extremely short time. be able to. As a result, the peripheral control MPU 4150a is output from the main control board 4100 in the peripheral control unit command reception interrupt processing, which will be described later, when the interrupt enable is set, as shown in FIGS. 40 and 41. , It becomes possible to receive various commands such as a command related to the control of the game effect and a command related to the state of the pachinko gaming machine 1.

In the hot start / cold start determination process, the peripheral control RAM 4150c shown in FIG. 16 is backed up in Bank1 (1fr) and Bank2 (1fr) in the backup first area 4150cc. ), And the effect backup information (1 ms), which is the content backed up in Bank 1 (1 ms) and Bank 2 (1 ms), are compared, and Bank 3 (1 fr) and Bank 4 (1 fr) in the backup second area 4150 cc. The production backup information (1fr), which is the content backed up in, is compared, and the production backup information (1ms), which is the content backed up in Bank3 (1ms) and Bank4 (1ms), is compared. When they match, the effect backup information (1fr), which is the content stored in Bank1 (1fr) with respect to Bank0 (1fr), which is the normally used storage area of the peripheral control RAM 4150c shown in FIG. When the production backup information (1 ms), which is the content stored in Bank 1 (1 ms), is copied back to Bank 0 (1 ms) to make a hot start, but the compared contents do not match (that is,). , When there is a discrepancy), the value 0 is forcibly written to Bank0 (1fr) and Bank0 (1ms), which are the normally used storage areas of the peripheral control RAM 4150c, and cold start is performed.

Further, in the hot start / cold start determination process, the peripheral control SRAM 4150d shown in FIG. 16 is also backed up in Bank1 (SRAM) and Bank2 (SRAM) in the backup first area 4150db. (SRAM) are compared, and the effect backup information (SRAM), which is the content backed up in Bank 3 (SRAM) and Bank 4 (SRAM), in the backup second area 4150 dc is compared. When the compared contents match, the effect backup information (SRAM) which is the contents stored in Bank0 (SRAM) with respect to Bank0 (SRAM) which is a normally used storage area of the peripheral control SRAM 4150d shown in FIG. ) Is copied back to make a hot start, while when the compared contents do not match (that is, when they do not match), the value is set with respect to Bank0 (SRAM), which is a normally used storage area of the peripheral control SRAM 4150d. Forcibly write 0 to make it a cold start. Following such a hot start or cold start, a value 0 is forcibly written to the backup unmanaged work area 4150cf of the peripheral control RAM 4150c shown in FIG. 16 to clear zero. After performing this initialization setting process, the peripheral control MPU4150a outputs a clear signal to the peripheral control built-in WDT4150af shown in FIG. 16 and the peripheral control external WDT4150e shown in FIG. 15 and resets to the peripheral control MPU4150a. I try not to take it.

Following step S1000, the effect control program performs the current time information acquisition process (step S1002). In this current time information acquisition process, the calendar information for specifying the date and the time information for specifying the hour, minute, and second are acquired from the RTC built-in RAM4165aa of the RTC41654a of the RTC control unit 4165 shown in FIG. In the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in the above, the current calendar information is set in the calendar information storage unit, and the current time information is set in the time information storage unit. Further, in the current time information acquisition process, the brightness setting process of the liquid crystal display device is also performed. In the brightness setting process of this liquid crystal display device, the peripheral control MPU4150a acquires the brightness setting information from the RTC built-in RAM4165aa of the RTC control unit 4165 so that the brightness of the LED is included in the acquired brightness setting information. A process of adjusting the brightness of the backlight of the side liquid crystal display device 1900 to turn it on is performed. As described above, the brightness setting information includes brightness adjustment information for adjusting the brightness of the LED, which is the backlight of the liquid crystal display device 1900 on the game board side, in a range of 100% to 70% in 5% increments, and presently. The brightness of the LED, which is the backlight of the liquid crystal display device 1900 on the game board side, which is set, is included.

In the brightness setting process of the liquid crystal display device, specifically, the brightness of the LED included in the brightness setting information stored in the RTC built-in RAM4165aa of the RTC control unit 4165 is 75%, and the backlight of the liquid crystal display device 1900 on the game board side. Is turned on by adjusting the brightness of the backlight of the game board side liquid crystal display device 1900 based on the brightness adjustment information included in the brightness setting information, and the brightness stored in the RTC built-in RAM4165aa of the RTC control unit 4165. When the backlight of the liquid crystal display device 1900 on the game board side is turned on when the brightness of the LED included in the setting information is 80%, the backlight of the liquid crystal display device 1900 on the game board side is based on the brightness adjustment information included in the brightness setting information. Adjust the brightness to turn on. In the brightness setting process of the liquid crystal display device, the same correction as the brightness correction program for correcting the brightness of the liquid crystal display device 1900 on the game board side according to the usage time of the liquid crystal display device 1900 on the game board side is performed. It is not done at all. This is because a correction program similar to the brightness correction program is incorporated into the brightness setting process of the liquid crystal display device, so that the brightness of the LED is corrected toward 100% each time the brightness setting process of the liquid crystal display device is executed. This is to prevent it from being done.

In the present embodiment, the peripheral control MPU4150a acquires the calendar information and the time information from the RTC built-in RAM4165aa of the RTC4165a only once when the power is turned on. Further, the peripheral control MPU4150a outputs a clear signal to the peripheral control built-in WDT4150af and the peripheral control external WDT4150e after performing the current time information acquisition process so that the peripheral control MPU4150a is not reset.

Following step S1002, the power saving mode transition determination process at the time of power recovery is performed (step S1004). The detailed description of the power saving mode transition determination process at the time of power recovery will be described later, but when the power is turned off (power supply) based on the power consumption status history information stored and held in the power consumption status history RAM 4150f shown in FIG. The power status consumed by the pachinko game machine 1 in (immediately before the disconnection) is grasped at the time of power recovery, and it is determined whether or not to shift to the power saving mode at the time of power recovery to suppress the power consumed by the pachinko game machine 1, and the power is restored. When shifting to the power saving mode, the door frame 5 is provided with a setting to reduce the volume of the effect sound flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. Settings are made to reduce the brightness of the LEDs for light emission decoration and the various LEDs mounted on the various decorative boards provided in the game board 4.

Following step S1004, the effect control program sets the value 0 in the V blank signal detection flag VB-FLG (step S1006). This V blank signal detection flag VB-FLG is a flag for determining whether or not to execute the peripheral control unit steady processing described later, and has a value of 1 when the peripheral control unit steady processing is executed, and the peripheral control unit steady processing. Is set to a value of 0 when is not executed. The V-blank signal detection flag VB-FLG is executed when a V-blank signal indicating that screen data from the peripheral control MPU4150a can be accepted is input from the sound source built-in VDP4160a, which will be described later. The value 1 is set in the part V blank signal interrupt processing. In this step S1006, the V blank signal detection flag VB-FLG is initialized once by setting the value 0 in the V blank signal detection flag VB-FLG. Further, the peripheral control MPU4150a outputs a clear signal to the peripheral control built-in WDT4150af and the peripheral control external WDT4150e after setting the value 0 in the V blank signal detection flag VB-FLG so that the peripheral control MPU4150a is not reset. There is.

Following step S1006, the effect control program determines whether or not the V blank signal detection flag VB-FLG has a value of 1 (step S1008). When the V blank signal detection flag VB-FLG is not a value 1 (value 0), the process returns to step S1008 again to repeatedly determine whether or not the V blank signal detection flag VB-FLG has a value 1. By repeating such a determination, it becomes a state of waiting until the peripheral control unit steady processing is executed. Further, the peripheral control MPU4150a outputs a clear signal to the peripheral control built-in WDT4150af and the peripheral control external WDT4150e after determining whether or not the V blank signal detection flag VB-FLG has a value of 1, and resets the peripheral control MPU4150a to the peripheral control MPU4150a. I try not to take it.

When the V blank signal detection flag VB-FLG has a value of 1 in step S1008, that is, when the peripheral control unit steady-state processing is executed, the value 1 is first set in the steady-state processing flag SP-FLG (step S1009). The steady processing flag SP-FLG is set to a value of 1 when the peripheral control unit steady processing is being executed and a value of 0 when the peripheral control unit steady processing is completed.

Following step S1009, the effect control program performs a 1 ms interrupt timer activation process (step S1010). In this 1 ms interrupt timer activation process, the 1 ms interrupt timer for executing the peripheral control unit 1 ms timer interrupt process, which will be described later, is activated, and the number of times the 1 ms interrupt timer is activated and the peripheral control unit 1 ms timer interrupt process is executed. The 1ms timer interrupt execution count STN for counting is set to a value of 1, and the 1ms timer interrupt execution count STN is also initialized. The 1ms timer interrupt execution count STN is updated by the peripheral control unit 1ms timer interrupt processing.

Following step S1010, the effect control program performs lamp data output processing (step S1012). In this lamp data output process, the effect control program performs DMA serial continuous transmission to the lamp drive board 4170 shown in FIG. Here, the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. 16 is used to continuously transmit the serial I / O port for the lamp drive board. When the continuous transmission of the serial I / O port for the lamp drive board is started, the transmission data storage area 4150caa on the lamp drive board side of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. 16 is shown in FIG. The game board side light emission data SL-DAT for outputting lighting signals, blinking signals, or gradation lighting signals to a plurality of LEDs of various decorative boards provided on the game board 4 is created by the lamp data creation process described later. It is in the set state.

The peripheral control CPU core 4150aa of the peripheral control MPU 4150a shown in FIG. 16 specifies the transmission of the serial I / O port for the lamp drive board as a requirement factor of the peripheral control DMA controller 4150ac, and the transmission data storage area 4150caa on the lamp drive board side. The first byte of the game board side light emission data SL-DAT stored at the start address is sent to the serial I / O port for the lamp drive board via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer to the transmit buffer register of and write. As a result, the serial I / O port for the lamp drive board transfers the written data of the transmission buffer register to the transmission shift register, and synchronizes with the game board side emission clock signal SL-CLK to 1 byte of the transmission shift register. Data is started to be transmitted bit by bit.

The peripheral control DMA controller 4150ac triggers each time a transmission interrupt request for the serial I / O port for the lamp drive board is generated (in the present embodiment, the transmission buffer register for the serial I / O port for the lamp drive board is used). The written 1-byte data is transferred to the transmission shift register, and the transmission buffer register runs out of 1-byte data and becomes empty.) The peripheral control CPU core 4150aa is using the bus. If not, the remaining game board side light emission data SL-DAT stored in the lamp drive board side transmission data storage area 4150ca is sent byte by byte via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. By transferring and writing to the transmission buffer register of the serial I / O port for the lamp drive board, the serial I / O port for the lamp drive board transfers the data of the written transmission buffer register to the transmission shift register and plays a game. In synchronization with the board-side emission clock signal SL-CLK, 1-byte data of the transmission shift register is started to be transmitted bit by bit, and continuous transmission is performed by the serial I / O port for the lamp drive board.

Further, in the lamp data output processing, the effect control program performs the DMA serial continuous transmission processing to the frame decoration drive amplifier board 194 shown in FIG. Here, too, the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a is used to continuously transmit the serial I / O port for the frame decoration drive amplifier board LED. When the continuous transmission of the serial I / O port for the frame decoration drive amplifier board LED is started, the transmission data storage area for the frame decoration drive amplifier board side LED of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. Door-side light emission data STL-DAT for outputting lighting signals, blinking signals, or gradation lighting signals to a plurality of LEDs of various decorative substrates provided on the door frame 5 is created on the 4150cab by the lamp data creation process described later. It is in the set state.

The peripheral control CPU core 4150aa of the peripheral control MPU 4150a specifies the transmission of the serial I / O port for the frame decoration drive amplifier board LED as a requirement factor of the peripheral control DMA controller 4150ac, and the transmission data storage area for the frame decoration drive amplifier board side LED. The first byte of the door-side emission data STL-DAT stored at the start address of the 4150cab is serialized for the frame decoration drive amplifier board LED via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer to the transmit buffer register of the I / O port and write. As a result, the serial I / O port for the frame decoration drive amplifier board LED transfers the written transmission buffer register data to the transmission shift register, and synchronizes with the door-side emission clock signal STL-CLK of the transmission shift register. Transmission of 1 byte of data is started bit by bit.

The peripheral control DMA controller 4150ac triggers each time a transmission interrupt request for the frame decoration drive amplifier board LED serial I / O port is generated (in this embodiment, the frame decoration drive amplifier board LED serial I / O). The 1-byte data written in the transmission buffer register of the port is transferred to the transmission shift register, and the transmission buffer register is empty when the 1-byte data is exhausted.), Peripheral control CPU core 4150aa When the bus is not used, the remaining door-side emission data STL-DAT stored in the transmission data storage area 4150cab for the frame decoration drive amplifier board side LED is stored in byte by byte, external bus 4150h, peripheral control bus controller 4150ad. Then, the serial I / O port for the frame decoration drive amplifier board LED is written by transferring the data to the transmission buffer register of the serial I / O port for the frame decoration drive amplifier board LED via the peripheral bus 4150ai. The data of the transmission buffer register is transferred to the transmission shift register, and the 1-byte data of the transmission shift register is started to be transmitted bit by bit in synchronization with the door-side emission clock signal STL-CLK, for the frame decoration drive amplifier board LED. Continuous transmission is performed by the serial I / O port.

Following step S1012, the effect control program performs the operation unit monitoring process (step S1014). In this operation unit monitoring process, in the operation unit information acquisition process in the peripheral control unit 1 ms timer interrupt process described later, the dial operation unit 401 is based on the detection signals from various detection switches provided in the operation unit 400 shown in FIG. Rotation (rotation direction) of the dial operation unit 401 created based on various information acquired from the rotation (rotation direction) and the operation of the pressing operation unit 405 (for example, detection signals from various detection switches provided in the operation unit 400). ) History information, operation history information of the pressing operation unit 405, etc.) Based on the operation unit information acquisition storage area 4150kai of the peripheral control RAM 4150c shown in FIG. 16, the rotation direction and pressing operation of the dial operation unit 401. The presence or absence of operation of the unit 405 is monitored, and it is appropriately determined whether or not the rotation direction of the dial operation unit 401 and the operation state of the pressing operation unit 405 are reflected in the game effect.

Following step S1014, the effect control program performs display data output processing (step S1016). In this display data output process, the drawing data for one screen (one frame) generated on the built-in VRAM of the sound source built-in VDP4160a in the display data creation process described later is transferred from the channels CH1 and 2 shown in FIG. 17 by the sound source built-in VDP4160a. The data is output to the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. As a result, various screens are drawn on the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. In the display data output processing, when drawing exceeding the drawing capacity of the sound source built-in VDP4160a is performed, the generated drawing data for one screen (one frame) is displayed on the game board side liquid crystal display device 1900 and the movable liquid crystal display device. The output to the 1925a to 1925d and the liquid crystal display device 470 on the upper plate side is canceled. As a result, it is possible to prevent a delay in the processing time, but so-called frame dropping occurs, but the various decorative substrates provided on the game board 4 shown in FIG. 8 by the lamp data output processing in step S1012. The speaker and the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 by the effect of the plurality of LEDs and the plurality of LEDs of the various decorative substrates provided on the door frame 5 and the sound data output processing described later. The speaker 130 provided on the door frame 5 shown in FIG. 2 has a mechanism that allows priority to be synchronized with the production by music, sound effects, etc. that match various effects.

Following step S1016, the effect control program performs sound data output processing (step S1018). In this sound data output process, the effect control program outputs sound data such as music and sound effects set in the sound source built-in VDP4160a in the sound data creation process described later to the audio data transmission IC 4160c as serialized audio data. In addition to music and sound effects, sound data of notification sounds and notification sounds are output to the audio data transmission IC 4160c as serialized audio data. When the serialized audio data from the VDP4160a with a built-in sound source is input, the audio data transmission IC 4160c is directed toward the frame decoration drive amplifier board 194 as differential serial data in which the right audio data is a positive signal and a negative signal. At the same time, the left side audio data is transmitted to the frame decoration drive amplifier board 194 as differential serial data having a positive signal and a negative signal. As a result, music, sound effects, and the like that match various effects are reproduced in stereo from the speakers housed in the speaker box 820 provided in the main body frame 3 and the speakers 130 provided in the door frame 5, as well as notification sounds and notification sounds. Is also played back in stereo.

Following step S1018, the effect control program performs scheduler update processing (step S1020). In this scheduler update process, the effect control program updates various schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. For example, in the scheduler update process, the number of screen data from the first screen data among the screen data arranged in the time series constituting the screen generation schedule data set in the schedule data storage area 4150 cage is set to the sound source built-in VDP4160a. Update the pointer to indicate whether to output.

Further, in the scheduler update process, among the light emission data arranged in the time series constituting the light emission mode generation schedule data set in the schedule data storage area 4150 cage, the light emission data at which number from the first light emission data is emitted from various LEDs. Update the pointer to indicate whether it is the mode.

Further, in the scheduler update process, sound data such as music and sound effects, and sound data of notification sound and notification sound arranged in a time series constituting the sound generation schedule data set in the schedule data storage area 4150 cage are instructed. Among the sound command data, the pointer is updated in order to indicate which sound command data is to be output to the sound source built-in VDP4160a from the first sound command data.

Further, in the scheduler update process, the first drive data among the drive data of the electric drive sources such as the motor and the solenoid arranged in the time series constituting the electric drive source schedule data set in the schedule data storage area 4150 cage is started. Update the pointer to indicate which drive data to output. Electrical drive source The drive data of electric drive sources such as motors and solenoids arranged in time series that compose the schedule data is repeatedly executed every time a 1 ms timer interrupt occurs, which will be described later. Peripheral control unit 1 ms timer interrupt. Updated with motor and solenoid drive processing in processing. In the motor and solenoid drive processing that is repeatedly executed each time this 1 ms timer interrupt occurs, the electric drive source such as the motor or solenoid is driven according to the drive data indicated by the pointer, and the next drive specified in time series is performed. It updates the pointer to the data and updates the pointer each time it executes its own processing. That is, since the drive data indicated by the pointer updated in the motor and solenoid drive processing is forcibly updated in the scheduler update processing, the pointer is originally instructed in the motor and solenoid drive processing for some reason. Even if another drive data is instructed from the drive data that should be used, the drive data that should be originally instructed in the scheduler update process is forcibly updated.

Further, in the scheduler update process, the number of game balls scheduled to be paid out as prize balls, which are arranged in the time series constituting the schedule data for the main prize ball information output signal set in the schedule data storage area 4150 cage, is reduced to 10. Main prize ball information that conveys the fact that it has been reached to the hall computer as main prize ball information Of the output waveform data for generating the output signal, the number of output waveform data from the first output waveform data is to be output. Update the pointer to indicate. The output waveform data arranged in time series that constitutes the schedule data for the main prize ball information output signal is the number of main prize balls in the peripheral control unit 1 ms timer interrupt process that is repeatedly executed each time a 1 ms timer interrupt occurs, which will be described later. Updated by information output processing. In the main prize ball number information output process that is repeatedly executed every time this 1 ms timer interrupt occurs, the main prize ball information output signal is output to the external terminal board 784 according to the output waveform data indicated by the pointer, and is specified in time series. The pointer is updated to the next output waveform data that has been generated, and the pointer is updated each time its own processing is executed. That is, since the output waveform data indicated by the pointer updated in the main prize ball number information output process is forcibly updated in the scheduler update process, the pointer is assumed to be in the main prize ball number information output process. Even if another output waveform data is specified from the output waveform data that should be originally specified for some reason, the output waveform data that should be originally specified in the scheduler update process is forcibly updated. It has become.

Following step S1020, the effect control program performs reception command analysis processing (step S1022). In this reception command analysis process, the effect control program transmits information transmitted from the touch panel drive board 450 via the peripheral door relay terminal board 882 and the frame peripheral relay terminal board 868 (for example, to the touch panel 480) shown in FIG. (Contact position data indicating the position where the finger is touching, etc.) is received in the touch panel processing described later, the received information is analyzed, and various commands transmitted from the main control board 4100 are subjected to peripheral control described later. Part Command reception Analyzes various commands received in interrupt processing (command receiving means) (command analysis means). The effect control program includes screen generation schedule data, light emission mode generation schedule data, and sound generation based on information transmitted from the touch panel drive board 450 via the peripheral door relay terminal plate 882 and the frame peripheral relay terminal plate 868. Schedule data, electrical drive source schedule data, etc. are extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c, and set in the schedule data storage area 4150cae of the peripheral control RAM 4150c. Further, in the effect control program, the command from the main control board 4100 received in the peripheral control unit command interrupt process is, for example, a start port winning command for instructing the start of the start port winning effect, and the number of reserved symbols. A normal symbol memory command for identifying (0 to 4), a symbol synchronization effect start command for instructing the start of the symbol synchronization effect, a symbol memory command output when the number of pending starts changes, and a large winning opening 2103 The large winning opening 1 count display command (large winning opening count command) output each time the game ball is accepted, or the frame state 1 command (second error occurrence command,) indicating the content of full tank shown in FIG. It analyzes whether or not it is a full tank error occurrence command (command analysis means), and recognizes which game state it is currently in. Further, in this effect control program, after a predetermined time has elapsed from the time when the power is turned on, the commands received by the peripheral control unit command reception interrupt processing are the main body frame open command, the main body frame close command, the door open command, or the door frame close. Analyze whether it is a command or not. Various commands from the main control board 4100 are received by the peripheral control unit command reception interrupt processing and stored in the reception command storage area 4150cc of the peripheral control RAM 4150c shown in FIG. 16, and are stored in the reception command storage area 4150cc in the reception command analysis processing. , The effect control program analyzes various commands stored in the received command storage area 4150 cc. The various commands are classified into the various commands shown in FIG. 40, which are classified as related to the special figure 1 synchronization effect, the various commands classified as related to the special figure 2 synchronization effect, the various commands classified as related to the jackpot, and the power-on. Various commands to be executed, various commands classified to be related to the normal electric service production, various commands classified to be related to the normal electric service production, various commands classified to the notification display shown in FIG. 41, and the above-mentioned door frame opening command. , Door frame closing command, main body frame opening command, main body frame closing command, error cancellation navigation command (corresponding to the second error canceling command), frame state 1 command (corresponding to the second error occurrence command), and frame state 2 There are various commands that are classified into status displays such as commands, various commands that are classified into test-related commands, and various commands that are classified into others.

Here, in the effect control program, the command analyzed in the received command analysis process (step S1022) is a frame state 1 command (second error occurrence command) or the large winning opening 1 count display command (large winning opening count command). ), A suggestion display for urging the pressing operation unit 405 (operation unit) to be pressed using the upper plate side liquid crystal display device 470 (second display device) as shown in FIG. 75. As an object, based on the suggestion display object image data, for example, the display of an arrow-shaped icon in a display mode in which the words "press a button to call a clerk" is superimposed is performed (operation arousing means). Subsequently, the effect control program starts displaying this arrow-shaped icon as a call control function, and then controls a call operation different from the most recent effect operation to the outside (call) triggered by the operation of the pressing operation unit 405. Control means), the mode is such that it is easy to attract the attention of the hall clerk.

In this way, the player who tried to call the hall clerk does not have to stretch his arm or body to reach the data counter, which was often located above the pachinko machine 1. Since it is sufficient to press the pressing operation unit 405 provided on the door frame 5, which is located closer to the player, it is possible to suppress the physical inconvenience and physical burden of calling the hall clerk. Therefore, even if the pachinko machine 1 is played for a long time, it is less likely to receive unnecessary stress. Therefore, such a configuration can contribute to the improvement of the operating rate.

By the way, the work by the hall clerk who appeared at the player in response to the above-mentioned call should be completed as soon as possible, considering the psychological state of the player who wants to resume the game as soon as possible. You should have a desire to cooperate with the hall clerk as much as possible. On the other hand, in the pachinko machine 1, the effect control program analyzes the error content based on the frame state 1 command (second error occurrence command) received from the main control board 4100 (error content analysis means). Further, the production control program is based on an error content management table (not shown) that manages whether or not the player should leave the seat according to each error content, and the hall clerk performs complicated coping work (for example) according to the error content. When it is determined that (opening and closing of the main body frame 3 or the door frame 5) is necessary, as described above, only the standard message "Please press the button to call the clerk" is superimposed on the above arrow-shaped icon. On the other hand, if it is determined that complicated handling work by the hall clerk is not necessary according to the content of the error, in addition to the above standard message, an additional message "Please leave your seat" is added to the above arrow icon. The display mode is superimposed. In this way, the player who encounters such an error will act immediately, without hesitation, whether or not to leave the seat and wait for the hall clerk due to the presence of the additional message mentioned above. It is possible to determine what should be done, and if necessary, give the hall clerk ample work space to complete subsequent work.

Further, when the effect control program detects the operation signal output in response to the operation of the pressing operation unit 405, it determines whether or not the arrow-shaped icon is displayed, and when the arrow-shaped icon is displayed, the effect control program determines whether or not the arrow-shaped icon is displayed. Is considered that the operation signal is operated by the pressing operation unit 405 in response to the appearance of the arrow-shaped icon. On the other hand, when the effect control program detects the operation signal, if the arrow-shaped icon is not displayed, the operation signal is not the appearance of the arrow-shaped icon but other factors (operation is prompted for the effect). It is considered that the pressing operation unit 405 has been operated in response to the above.

Here, when it is determined that the effect control program has shifted from the normal gaming state to the jackpot gaming state (special gaming state) based on the command received from the main control board 4100, the suggestion read from the liquid crystal and the sound control ROM 4160b thereafter. Based on the display image data, an arrow-shaped icon is displayed on the upper plate side liquid crystal display device 470 (second display device), for example, the phrase "Please press the pressing operation unit to call the clerk when the dollar box is about to overflow." The display mode may be superimposed on the above. In this way, when the player is about to overflow the game ball discharged through the lower plate 302 after being paid out in the jackpot game state, the player is likely to overflow from the storage box (corresponding to the above dollar box). Since it is not necessary to extend the arm or body to operate the so-called data counter call button by hand, it is possible to concentrate more on the game and suppress the decrease in the operating rate.

By the way, in order to call the hall clerk in search of a new storage box in the big hit game state, the display mode of the upper plate side liquid crystal display device 470 prompts the player to operate the pressing operation unit 405. At first glance, the control program seems to be difficult to distinguish the operation signal from the case where the player is actually urged to operate the pressing operation unit 405 in the jackpot game state itself. That is, in the effect control program, when the operation signal is detected, the player operates the pressing operation unit 405 in search of a new storage box, or the player presses the operation in response to the effect in the jackpot game state. It seems that it is not possible to distinguish whether the unit 405 was operated.

However, the effect control program uses the concept of time sharing to actually urge the player to operate the pressing operation unit 405 in the big hit game state (special game state) and execute the call operation by the call control function. The participation operationable time zone in which is restricted and the clerk callable time zone in which the hall clerk can be called by the operation of the pressing operation unit 405 and the call operation by the call control function is allowed to be executed are distinguished. (Time sharing control means). Specifically, the effect control program was found to be a frame state 1 command (second error occurrence command) indicating that the command analyzed in the received command analysis process (step S1022) is full. In this case, it is regarded as the clerk callable time zone, while the other time zone is the participation operation possible time zone. This effect control program is shown in FIG. 76 by using the upper plate side liquid crystal display device 470 (second display device) that displays that the jackpot is in progress when it is considered that the store clerk is in the callable time zone. In addition to controlling the display of the phrase "please pull out the ball" at the top of the screen, control the display of the arrow-shaped icon in the display mode in which the phrase "please press the button to call the clerk" is superimposed. ing. In this way, when the effect control program detects the operation signal in the jackpot game state, if the detection timing is within the participation operation possible time zone, the pressing operation unit responds to the effect of the jackpot game state. While it is determined that the 405 has been operated, if the detection timing is within the above-mentioned clerk callable time zone, it is determined that the pressing operation unit 405 has been operated to call the hall clerk, and the distinction is made. In the above-mentioned effect control program, a touch panel is mounted on the surface of the upper plate side liquid crystal display device 470 to prompt the operation of the button displayed on the upper plate side liquid crystal display device 470 instead of the pressing operation unit 405. good. By the way, the effect control program indicates that the command analyzed in the reception command analysis process (step S1022) is the large winning opening 1 count display command (large winning opening count command) and is full. If it turns out to be the frame state 1 command (second error occurrence command), the game ball is likely to not fit in the storage box at the time of a big hit, and the above-mentioned is used as an opportunity for the player to call the hall clerk. The screen shown in FIG. 76 is displayed.

By the way, in this effect control program, when it is found that the command analyzed in the reception command analysis process (step S1022) is a door opening command or a main body frame opening command (that is, the door frame 5 is relative to the main body frame 3). When the main body frame 3 is opened with respect to the outer frame 2), the upper plate side liquid crystal display device 470 (second display device) is made to display in the following display mode. That is, the effect control program gives an instruction to display the service mode screen (see FIG. 77) for work by the hall clerk on the upper plate side liquid crystal display device 470, and then the dial operation unit 401 (see FIG. 77) by the player. When it is detected that the "meal break setting" is selected by the pressing operation of the pressing operation unit 405 (operation unit) after the rotation operation of the operation unit), the operation for setting the operation stop time that does not allow the above-mentioned operation is performed. An instruction is given to display the break timer setting screen (see FIG. 78) corresponding to the setting screen (operation setting screen display control means). By triggering the door opening command or the main body frame opening command that can be generated only by the operation of the hall clerk in this way, it is difficult to display such a break timer setting screen by the operation by the player. Can be done.

Further, the effect control program displays the time information (for example, 60 minutes) input to the break timer setting screen (operation setting screen) in response to the operation of the hall clerk using the dial operation unit 401 (operation unit) and the pressing operation unit 405. Set as the operation stop time (operation stop time setting means). Further, the effect control program takes the opportunity of setting the operation stop time on the break timer setting screen (operation setting screen) to set the operation stop time on the upper plate side liquid crystal display device 470 (second display device). The remaining time of is displayed as shown in FIG. 79 (remaining time display control means). At the same time, the effect control program may set at least a part of the effect operations by the peripheral control board 4140 into a stopped state or a suppressed state (remaining time display control means). It should be noted that this effect control program at least suppresses the display operation of the game board side liquid crystal display device 1900 (first display device) by the peripheral control board 4140 over the set operation stop time, for example, a blackout display mode. (First display control suppressing means). By doing so, it is possible to suppress the power consumption of the liquid crystal display device 1900 on the game board side during the operation stop time when the player does not play the game.

Further, in the effect control program, when the remaining time of the operation stop time becomes a specified state, for example, the count becomes zero, or the command analyzed in the above-mentioned reception command analysis process (step S1022) is the door closing command or the main body. When it is found that the command is a frame closing command, the display control of the remaining time of the operation stop time shown in FIG. 79 is terminated, and the stopped state or the suppressed state of some of the above-mentioned effect operations is released (stop state releasing means). In this way, by triggering the door closing command or the main body frame closing command that can be generated only by the operation of the hall clerk in this way, it is difficult for the player to perform such a release. Can be done.

By the way, in this effect control program, the remaining time of the operation stop time becomes zero (specified state), and the command analyzed in the above-mentioned reception command analysis process (step S1022) is a door closing command or a main body frame. If it is not a close command, for example, the liquid crystal display device 1900 on the game board side is controlled in a specific mode different from the latest effect operation, and a notification operation indicating that the remaining operation stop time has ended is executed (notification operation). Getting started). In this way, not only the hall clerk but also the player who is waiting for the pachinko machine 1 to be opened to a third party can immediately and easily know that the allowable break time has expired. can. Further, when the effect control program finds that the command analyzed in the above-mentioned reception command analysis process (step S1022) is a door closing command or a main body frame closing command after the start of such a notification operation (that is, the door). When the frame 5 is closed with respect to the main body frame 3 or when the main body frame 3 is closed with respect to the outer frame 2), the above-mentioned notification operation is stopped (notification operation stopping means). In this way, the time during which the pachinko machine 1 cannot be operated based on the player's intention such as a break can be shortened as much as possible.

In this way, it is necessary to open and close the main body frame 3 or the door frame 5 in order to suspend or restart the operation of the pachinko machine 1, so only the hall clerk who possesses the key necessary for opening and closing such pachinko machines. It is possible to suspend and restart the operation of the machine 1. Moreover, after a hall clerk suspends the operation of the pachinko machine 1 for a while because he is taking a break, he receives calls from many players and pays sufficient attention to each pachinko machine 1 and each player. Even if it is not possible, as soon as the downtime of the pachinko machine 1 that has been suspended from operation has elapsed, it becomes publicly easily recognizable by a third party that the low operation time has elapsed. .. For this reason, even if the player does not easily return from the break, the hall clerk can quickly put the pachinko machine 1 into a state in which other players can play, so that the pachinko machine can be used as a hall. The operating rate of the machine 1 can be increased as much as possible, and the operating rate of each pachinko machine 1 installed in each island facility can be increased as a whole.

By the way, the effect control program is based on the calendar information and the time information stored in the RTC built-in RAM4165aa of the RTC control unit 4165 mounted on the peripheral control board 4140, according to the time zone in which the player takes a break. When setting the operation stop time, the unit time that can be changed per operation (hereinafter referred to as "variable unit time") is changed from 5 minutes to the desired unit time (for example, 15 minutes) as shown in FIG. 78. You may. If such a change is possible, the operation stop time can be flexibly set according to the time zone such as the day of the week or the day of the week, so that the weekday night time zone (or weekend) where a high utilization rate is desired can be secured. ), By shortening the variable unit time, the operating rate can be maintained as high as possible, and during the time zone (weekday daytime) when it is difficult to expect a high operating rate, a longer variable unit time is used to improve the feelings for hall service. As a result, it is possible to prevent the player's motivation to play the game again in the hall from being impaired next time.

On the other hand, in this effect control program, when the command analyzed in the received command analysis process (step S1022) is the error release navigation command (second error occurrence command) as described above, this error release navigation command The error occurrence position information included in is extracted and acquired (error occurrence location identification means).

Following step S1022, the effect control program performs warning processing (step S1024). In this warning process, further, when the command analyzed by the effect control program in the received command analysis process in step S1022 includes various commands classified into the notification display shown in FIG. 41, various commands are included. The peripheral control unit 4150 sets the screen generation schedule data, the light emission mode generation schedule data, the sound generation schedule data, the electrical drive source schedule data, etc., which are set in the abnormality display mode for executing the abnormality notification, to the peripheral control unit 4150. It is extracted from various control data copy areas 4150ce of the peripheral control ROM 4150b or the peripheral control RAM 4150c and set in the schedule data storage area 4150cae of the peripheral control RAM 4150c. In the warning process, when a plurality of abnormalities occur at the same time, the abnormality notification is performed in descending order of priority registered in advance, and the abnormality is automatically resolved and the remaining abnormality notification is automatically transitioned to. It is designed to do. This allows multiple anomalies to be monitored simultaneously without losing information that another anomaly has occurred and one anomaly has occurred after one anomaly has occurred but before the anomaly has been resolved. Can be done.

Further, in this warning process, after a predetermined time has elapsed from the time when the power is turned on, the command analyzed by the effect control program in the received command analysis process (step S1022) described above is classified into the state display shown in FIG. 41. In the case of various commands such as an error release navigation command (second error release command), for example, by controlling the liquid crystal and the sound control unit 4160 in a mode different from the normal effect mode accompanying the effect operation, for example, the game board. A side liquid crystal display device 1900 (effect device), a precision plate side liquid crystal display device 470 (effect device), and a lamp (effect device) are used to visually warn the outside, or a pair of side speakers 130 (effect device) are used. And audibly warn the outside (error notification means). In this way, when a malicious player attempts to input an error release navigation command to the main control board 4100 by operating the operation switch 860a of the payout control board 4110 even though the player is in the gaming state. Since the pachinko machine 1 is configured to give a warning to the outside, fraudulent acts on the main control board 4100, which may affect the progress of the game, are suppressed.

When notified to the outside as described above, the effect control program reads the rear image data of the main body frame from the liquid crystal and the sound control ROM 4160b (data storage unit), and the read back image of the main body frame Based on the data, the rear image of the main body frame specified on the upper plate side liquid crystal display device 470 (second display device) based on the error occurrence position information included in the frame state 1 command (second error occurrence command). A maintenance screen in which the above specific area is set as a specified display mode is displayed as shown in FIG. 75 (error occurrence position suggestion means).

In the maintenance screen shown in FIG. 75, the error number and the error content are displayed horizontally elongated on the upper part thereof, and in addition to the arrow-shaped icon described above on the slightly left side of the center, for example, "Insufficient payout". The details of the error content are displayed. Furthermore, on this maintenance screen, the back image of the main body frame is displayed on the right half. This back image of the main body frame is a schematic view of the pachinko machine 1 viewed from the back, that is, the arrangement of each part on the back side of the main body frame 3 on which the game board 4 is mounted. The above-mentioned effect control program corresponds to a specific area (corresponding to the area 740Z) on the rear image of the main body frame based on the error occurrence position information included in the frame state 1 command (second error generation command) received from the main control board 4100. ) Is specified, and the specific area 740Z is blinked on the back image of the main body frame (specified display mode).

In this way, the hall clerk who arrives at the player in response to the call of the player opens the main body frame 3 with respect to the outer frame 2 and is attached to the main body frame 3 as in the conventional case. The upper plate side liquid crystal display device 470 (second display device) provided in a part of the door frame 5 without checking the error content of the error LED display 860c provided on the payout control board 4110 of the board 4. By confirming the area 740Z on the image of the back surface of the main body frame on the maintenance screen, it is possible to immediately grasp which part of the pachinko machine 1 the error has occurred by visually recognizing the blinking mode of the area 740Z. Therefore, according to the configuration of the present embodiment, even in a situation where the pachinko machine 1 is complicated as in recent years, it is possible to prevent the time required for error handling from becoming long, and the pachinko machine 1 having a complicated configuration is suppressed. In this case as well, the hall clerk can complete the error handling as soon as possible, and the player's impatience and dissatisfaction during the error handling can be less likely to occur.

Here, in addition to extinguishing the error occurrence position suggestion image from the upper plate side liquid crystal display device 470 when the effect control program receives the error release navigation command (second error release command), instead When the main body frame closing command is received before this error release navigation command, this main body frame closing command is regarded as the error canceling navigation command, and the upper plate side liquid crystal display device is triggered by receiving this main body frame closing command. The main body frame maintenance image is erased from 470 (second display device) (screen return means). By doing so, even if the hall clerk who has completed the error handling forgets to operate the operation switch 860a, the main body frame closing command is regarded as a substitute for the error canceling navigation command, and not only the error notification is canceled but also the upper plate side. The display on the maintenance screen of the liquid crystal display device 470 can be turned off. In this way, even if the hall clerk forgets to turn off the maintenance screen of the upper plate side liquid crystal display device 470 after dealing with the error, it is automatically turned off by closing the main body frame 3 with respect to the outer frame 2, and then the player feels uncomfortable. You can continue the game without feeling.

Next, following step S1024 described above, the effect control program performs the main prize ball number information output determination process (step S1025). In this main prize ball number information output determination process, when the effect control program is the main prize ball number information output command classified into other categories shown in FIG. 41, the command analyzed in the received command analysis process in step S1022 is the main prize ball number information output command. Peripheral control side Main prize ball number information Main prize that tells the hall computer that the number of game balls to be paid out as prize balls has reached 10 as main prize ball information based on the value of the output judgment counter. It is determined whether or not to output the ball information output signal to the external terminal plate 784. The counter for determining the number of main prize balls on the peripheral control side is used as a prize ball based on the other main prize ball number information output command shown in FIG. 41 analyzed in the reception command analysis process in step S1022. It counts the number of game balls to be paid out, and is stored and updated in a prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c. As described above, the other main prize ball number information output command shown in FIG. 41 conveys that the number of game balls to be paid out as prize balls has reached 10. When this main prize ball number information output command is received, a value 10 is added to the value of the peripheral control side main prize ball number information output determination counter, and the memory is updated in the prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c. It has become so.

In the main prize ball number information output determination process, the effect control program is for determining the main prize ball number information output at power-on when the command analyzed in the received command analysis process in step S1022 is classified into the power-on shown in FIG. When the counter notification command is used, the main control board 4100 is provided on the game board 4 and the upper start port 2101 shown in FIG. 8 is provided based on the content instructed by the counter notification command for determining the number of main prize balls when the power is turned on. , Lower start opening 2102, general winning opening 2104, 2201 and large winning opening 2103, etc. Main prize balls that count the number of game balls to be paid out as prize balls based on the game balls entered in various winning openings. While the value of the counter for determining the number information output is set as the initial value of the counter for determining the number of main prize balls on the peripheral control side, the commands analyzed in the received command analysis process in step S1022 are classified into the other categories shown in FIG. When it is the main prize ball number information output command to be executed, this main prize ball number information output command conveys that the number of game balls to be paid out as prize balls has reached 10 balls. The value 10 is added to the value of the control side main prize ball number information management counter.

Further, in the main prize ball number information output determination process, the effect control program determines the main prize ball number information output at power-on when the command analyzed in the reception command analysis process in step S1022 is classified into the power-on shown in FIG. When the counter notification command is used, the main control board 4100 is provided on the game board 4 based on the content instructed by the counter notification command for determining the number of main prize balls when the power is turned on. The main prize that counts the number of game balls to be paid out as prize balls based on the game balls that have entered various winning openings such as 2101, lower starting opening 2102, general winning opening 2104, 2201, and large winning opening 2103. When the value of the counter for determining the number of balls information output is set as the initial value of the counter for determining the number of main prize balls on the peripheral control side, the peripheral control acquired in the current time information acquisition process in step S1002 and shown in FIG. Based on the time information set in the time information storage unit in the RTC information acquisition storage area 4150cad of the RAM 4150c, the power to the pachinko game machine 1 is turned on (or the pachinko game machine 1 is installed) in order to start the operation of the hall. When it is determined that the power to the Pachinko Island facility is turned on), the value of the main prize ball number information management counter on the peripheral control side is forcibly reset and set to the default value as the initial value. The value is returned to 0 (zero) and stored and updated in the prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c (for example, the command analyzed in the received command analysis process in step S1022 is classified into the power-on shown in FIG. 40. This is a counter notification command for determining the number of main prize balls when the power is turned on, and the value of the counter for determining the number of main prize balls information output when the power is turned on is 9. In the case of the content indicating that, even if this value 9 is set as the initial value of the counter for determining the number of main prize balls on the peripheral control side, it is reset and the default value is 0 (zero). As a result, when the command analyzed in the received command analysis process in step S1022 is the main prize ball number information output command classified into other categories shown in FIG. 41, this main prize ball number information output is performed. Every time a command is received, the value 10 is added to the value of the counter for determining the number of main prize balls on the peripheral control side. That is, the value is changed on the main control board 4100 side. The value of the new main prize ball number information output determination counter and the value of the peripheral control side main prize ball number information output determination counter updated on the peripheral control board 4140 side are the same value. ) On the other hand, when it is determined that the power to the pachinko game machine 1 is not turned on to start the operation of the hall, and the power is restored due to a power failure or a momentary power failure during the operation of the hall. By forcibly resetting the value of the peripheral control side main prize ball number information management counter and setting it to the default value, the value of the peripheral control side main prize ball number information management counter is not returned to the initial value of 0 (zero). (For example, the command analyzed in the reception command analysis process in step S1022 is a counter notification command for determining the number of main prize balls at power-on, which is classified into the power-on shown in FIG. 40, and this power supply. When the main prize ball number information output judgment counter notification command indicates that the value of the main prize ball number information output judgment counter is value 9, this value 9 is the peripheral control side main prize ball. It is set as the initial value of the counter for determining the number information output. As a result, when the command analyzed in the received command analysis process in step S1022 is the main prize ball number information output command classified into the others shown in FIG. 41. Is set to a value 9 set as the value of the main prize ball number information output judgment counter, which is the value of the main prize ball number information output judgment counter on the peripheral control side each time this main prize ball number information output command is received. The value 10 is added. That is, the value of the main prize ball number information output determination counter updated on the main control board 4100 side and the peripheral control side main prize ball number updated on the peripheral control board 4140 side. Does not have the same value as the value of the information output judgment counter).

Then, in the main prize ball number information output determination process, the effect control program sets the value of the peripheral control side main prize ball number information management counter based on the added value of the peripheral control side main prize ball number information management counter. When the number exceeds 10, (that is, when the number of game balls to be paid out as prize balls has reached 10), a main prize ball information output signal is transmitted to the hall computer as main prize ball information to that effect. The schedule data for the main prize ball information output signal for output to the external terminal board 784 is set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. As the value of the control side main prize ball number information management counter, it is stored and updated in the prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c.

Here, in the main prize ball number information output determination process, the main prize ball information output signal is transmitted to the hall computer as the main prize ball information that the number of game balls to be paid out as prize balls has reached 10. A point will be described where the value of the counter for determining the number of main prize balls on the peripheral control side for determining whether or not to output to the external terminal plate 784 is maintained or reset at the time of power recovery. First, without determining whether the power is turned on from the power off state or the power is restored from the power failure or momentary power failure, the power is always restored in step S1022. When the command analyzed in the received command analysis process is the counter notification command for determining the number of main prize balls at power-on, which is classified into the power-on shown in FIG. 40, the main prize ball number information output determination at power-on is performed. Based on the content instructed by the counter notification command, the main control board 4100 is provided on the game board 4, and the upper starting port 2101, the lower starting port 2102, the general winning opening 2104, 2201, and the large winning opening 2103 shown in FIG. 8 are provided. Main prize ball number information output that counts the number of game balls that are scheduled to be paid out as prize balls based on the game balls that have entered various winning openings such as A problem when the initial value of the judgment counter is set as it is will be described.

First, as described above, the main control MPU 4100a of the main control board 4100 enters the general winning openings 2104 and 2201 shown in FIG. 8 in the switch input process of step S104 in the main control side timer interrupt process shown in FIG. 45. The detection signals from the general winning opening switches 3020 and 3020 shown in FIG. 12 for detecting the balled game ball, and the count switch 2110 shown in FIG. 12 for detecting the game ball entering the large winning opening 2103 shown in FIG. Detection signal from, detection signal from the upper start port switch 3022 shown in FIG. 12 for detecting a game ball entering the upper start port 2101 shown in FIG. 8, and entry into the lower start port 2102 shown in FIG. The detection signals and the like from the lower start port switch 2109 shown in FIG. 12 are read and stored as input information in the input information storage area of the main control built-in RAM. Input information is read from the input information storage area of the above, and based on this input information, in the prize ball control process of step S108 in the same process, the number of game balls to be paid out as prize balls is counted and the number of main prize balls is counted. When the value of the information output judgment counter is updated and stored, and the value of the main prize ball number information output judgment counter reaches a value of 10 based on the value of the main prize ball number information output judgment counter (that is, the prize). When the number of game balls to be paid out as balls has reached 10), a main prize ball number information output command shown in FIG. 41 is created to convey that fact. It is stored in the transmission information storage area as transmission information. Then, the main control MPU 4100a of the main control board 4100 transmits the main prize ball number information output command to the peripheral control board 4140 in the peripheral control board command transmission process of step S120 in the same process.

After the hall is closed, the staff in the hall may perform maintenance with the pachinko machine 1 turned on until late at night, and in such a case, after the maintenance is completed. Even if the power to the pachinko island facility where the pachinko gaming machine 1 is installed is cut off, the power (power) stored in the capacitor BC0 as the backup power supply provided in the power supply board 851 shown in FIG. 18 causes the power to be cut off. However, power (electric power) is supplied to the main control board 4100 for a predetermined time. As a result, the power supply (electric power) stored in the capacitor BC0 is completely discharged from the time when the power supply to the pachinko island equipment is cut off until the power supply to the pachinko island equipment is turned on again in order to start the operation of the hall. If not, the capacitor BC0 puts the main control MPU4100a in a state where various information is stored and held in the main control built-in RAM. Then, if a staff member such as a clerk in the hall does not operate the operation switch 860a of the payout control board 4110 in order to initialize the main control built-in RAM (game storage unit) for a predetermined time from the time when the power is turned on, By reading various information from the game backup information in step S34 in the main control side power-on processing shown in FIG. 43 and storing various commands corresponding to the various information in a predetermined storage area of the main control built-in RAM, yesterday's game The state is restored, and the value of the counter for determining the number of main prize balls of yesterday is taken over as it is, so that in the peripheral control board command transmission process of step S120 in the timer interrupt process on the main control side shown in FIG. 45. , The problem of transmitting the main prize ball number information output command to the peripheral control board 4140 arises.

Therefore, in the present embodiment, in the effect control program, in the main prize ball number information output determination process in step S1025, the command analyzed in the received command analysis process in step S1022 is classified into the power on as shown in FIG. 40. When the main prize ball number information output determination counter notification command is used when the power is turned on, the main control board 4100 is provided on the gaming board 4 based on the content instructed by the main prize ball number information output determination counter notification command when the power is turned on. A game scheduled to be paid out as a prize ball based on the game balls entered into various winning openings such as the upper starting opening 2101, the lower starting opening 2102, the general winning opening 2104, 2201, and the large winning opening 2103 shown in FIG. When the value of the main prize ball number information output determination counter that counts the number of balls is set as the initial value of the main prize ball number information output determination counter on the peripheral control side, it is acquired in the current time information acquisition process in step S1002. Then, based on the time information set in the time information storage unit in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in FIG. 16, this time information starts the operation of the hall (or maintenance of the pachinko gaming machine 1). When it is within the period before the start of business (in this embodiment, the period is set from 0:00 am to 9:00 am and is stored in advance in the peripheral control ROM 4150b). , When it is determined that the power to the pachinko game machine 1 is turned on (or the power is turned on to the pachinko island facility where the pachinko game machine 1 is installed) in order to start the operation of the hall. By forcibly resetting the value of the main prize ball number information management counter on the peripheral control side and setting it to the default value, it is returned to the initial value of 0 (zero) and the prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c. While the memory is updated to, within the period (in this embodiment, the period during which the hall is open) that is not the period before the opening of business for this time information to start the operation of the hall (or to start the maintenance of the pachinko gaming machine 1). In this case, the power to the pachinko gaming machine 1 was not turned on to start the operation of the hall, and the power was restored due to a power failure or a momentary power failure during the operation of the hall. When it is determined, the value of the peripheral control side main prize ball number information management counter is forcibly reset and set to the default value, so that the value is not returned to 0 (zero) as the initial value, and the peripheral control side main prize ball number information We adopted a mechanism to maintain the value of the management counter as it is.

As a result, the probability that a power outage or momentary power failure will actually occur between the start and end of the hall's business is extremely low, but if a power outage or momentary power failure occurs, the hall's business has already started. The main control board 4100 is provided on the game board 4 based on the content instructed by the counter notification command for determining the number of main prize balls when the power is turned on from the main control board 4100 at the time of power recovery. Count the number of game balls to be paid out as prize balls based on the game balls that have entered various winning openings such as the upper starting opening 2101, the lower starting opening 2102, the general winning opening 2104, 2201, and the large winning opening 2103. When the value of the main prize ball number information output judgment counter is set as the initial value of the main prize ball number information output judgment counter on the peripheral control side, the number of game balls to be paid out as prize balls is reduced to 10. The value of the counter for determining the number of main prize balls on the peripheral control side for determining whether or not to output the main prize ball information output signal to the hall computer as the main prize ball information to the effect that the signal has been reached is output to the external terminal board 784. By maintaining the value without forcibly resetting, the value of the counter for determining the number of main prize balls information output immediately before the occurrence of a power failure or momentary power failure can be set to the subsequent power recovery from the power failure or momentary power failure ( When the power is restored by recovery), it is taken over as it is and set as the value of the counter for determining the number of main prize balls on the peripheral control side.

On the other hand, when the hall is closed and the hall is reopened, the hall computer is notified that the number of game balls to be paid out as prize balls has reached 10 as the main prize ball information. Peripheral control side for determining whether to output the main prize ball information output signal to be transmitted to the external terminal board 784 Forcibly reset the value of the main prize ball number information output judgment counter and set it to the default value. The value was returned to the initial value of 0 (zero), and when the hall was closed and the power of the pachinko game machine 1 was cut off (or the power of the pachinko island facility where the pachinko game machine 1 was installed was cut off. The value of the counter for determining the number of main prize balls at (at the time) is set when the power is restored by turning on the power to the pachinko game machine 1 (or the pachinko island facility where the pachinko game machine 1 is installed) in order to start the operation of the hall. Even if it is set as the value of the counter for determining the number of main prize balls on the peripheral control side, it will not be inherited as it is, and the value of the counter for determining the number of main prize balls on the peripheral control side will not be inherited. Is forcibly reset and set to the default value to return to the initial value of 0 (zero), so the main that is updated and stored until the hall is opened and closed. Based on the main prize ball number information output command from the main control board 4100 transmitted based on the value of the prize ball number information output judgment counter, the value of the peripheral control side main prize ball number information output judgment counter is updated. As a result, it is possible to determine whether or not to output the main prize ball number information to the external terminal board 784 based on the value of the peripheral control side main prize ball number information output determination counter. As a result, accurate main prize ball information can be output from the peripheral control board 4140 to the hall computer via the external terminal board 784 based on the value of the counter for determining the number of main prize balls on the peripheral control side. As described above, the main prize ball number information is obtained from the light blue output terminal PT10 on the external terminal board 784, the upper starting port 2101, the lower starting port 2102, and the general winning ports 2104, 2201 shown in FIG. And as a main prize ball number information output signal that tells that every time the number of game balls scheduled to be paid out as prize balls based on the game balls entered in various prize openings such as the large prize opening 2103 reaches 10. Output to the hall computer. Therefore, the hall computer can accurately grasp the number of game balls to be paid out from the start to the end of the hall business.

Next, following step S1025 described above, the effect control program performs RCT acquisition information update processing (step S1026). In this RTC acquisition information update process, the effect control program acquires the current time information in step S1002 and sets it in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in FIG. 16 and stores it in the calendar information storage unit. The stored calendar information and the time information stored in the time information storage unit are updated. By this RCT acquisition information update process, the hour, minute, and second, which is the time information stored in the time information storage unit, is updated, and the year and month, which is the calendar information stored in the calendar information storage unit based on the updated time information. The day is updated.

Following step S1026, the effect control program performs power consumption monitoring processing (step S1027). This power consumption monitoring process is a process for adjusting the volume and the brightness of various LEDs in order to suppress the power consumption according to the power consumption in the pachinko gaming machine 1, and a detailed description thereof will be described later. do.

Following step S1027, the effect control program performs a lamp data creation process (step S1028). In this lamp data creation process, the effect control program updates the pointer in the scheduler update process of step S1020, and the pointer indicates the light emission data arranged in time series that constitutes the schedule data for generating the light emission mode. Based on the light emission data to be output, the game board side light emission data SL- for outputting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs of various decorative boards provided on the game board 4 shown in FIG. The DAT is created by extracting from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c, and is set in the lamp drive board side transmission data storage area 4150ca of the peripheral control RAM 4150c shown in FIG. At the same time, the door-side light emission data STL-DAT for outputting lighting signals, blinking signals or gradation lighting signals to a plurality of LEDs of various decorative substrates provided on the door frame 5 is provided to the peripheral control ROM 4150b of the peripheral control unit 4150. Alternatively, it is created by extracting from various control data copy areas 4150ce of the peripheral control RAM 4150c, and set in the frame decoration drive amplifier board side LED transmission data storage area 4150cab of the peripheral control RAM 4150c shown in FIG.

Following step S1028, the effect control program performs display data creation processing (step S1030). In this display data creation process, the effect control program updates the pointer in the scheduler update process of step S1020, and among the screen data arranged in time series constituting the screen generation schedule data, the screen data indicated by the pointer. Is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP 4160a. When screen data is input from the peripheral control MPU4150a, the sound source built-in VDP4160a extracts character data from the liquid crystal and sound control ROM 4160b based on the input screen data to create sprite data, and creates a liquid crystal display device on the game board side. Drawing data for one screen (one frame) to be displayed on the 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470 is generated on the built-in VRAM.

Following step S1030, the effect control program performs touch panel processing (step S1031). In this touch panel processing, the effect control program detects and controls the contact state of the capacitive touch panel 480 provided so as to cover the display area of the upper plate side liquid crystal display device 470 shown in FIG. It is a process of exchanging (transmitting and receiving) control commands and various information (various data) with. For example, as control commands, a detection control start command for starting the detection control of the contact state of the touch panel 480, a contact position data request command for requesting the position where the finger is touching the touch panel 480 (contact position data), and saving. There is a power saving mode transition command to shift to the power mode. The effect control program acquires the coordinate value of the contact surface of the touch panel 480 indicating the center of the contact portion touched by the finger based on the contact position data from the touch panel drive board 450, and determines the position represented by this coordinate value. Specify as a detection point (detection point acquisition means). It should be noted that this effect control program may acquire not only such coordinate values but also the range of the contact surface (hereinafter, referred to as the contact range).

Following step S1031, the effect control program performs sound data creation processing (step S1032). In this sound data creation process, the effect control program updates the pointer in the scheduler update process of step S1020, and the pointer indicates among the sound command data arranged in time series that constitutes the sound generation schedule data. Sound command data is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP4160a. When sound command data is input from the peripheral control MPU4150a, the sound source built-in VDP4160a extracts sound data such as music and sound effects stored in the liquid crystal and sound control ROM 4160b to control the built-in sound source to control the sound command. Sound data such as music and sound effects are incorporated according to the track number specified in the data, and the output channel to be used is set according to the output channel number.

In the sound data creation process, each time the sound data creation process is performed (that is, each time the peripheral control unit routine process is performed), the peripheral control A / D converter 4150ak shown in FIG. 16 is activated to adjust the volume. The voltage divided by the resistance value at the rotation position of the knob portion of 4140a is converted into a value of 1024 steps from a value of 0 to a value of 1023. In the present embodiment, the value of 1024 steps is divided into seven and managed as the board volumes 0 to 6, the board volume 0 is set to mute, the board volume 6 is set to the maximum volume, and the board volume 0 to the board. The volume is set so as to increase toward the volume 6. The LCD and the VDP4160a with built-in sound source of the sound control unit 4160 are controlled so that the volume is set to the board volumes 0 to 6, and the sound data is serialized in the sound data output process of step S1018 described above. By outputting to the transmission IC 4160c, music and sound effects can be played from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5.

In addition, the notification sound and the notification sound flow without depending on the volume adjustment based on the rotation operation of the knob part, and the volume from the mute to the maximum volume is programmed to be the sound source of the liquid crystal and the sound control unit 4160. The built-in VDP4160a can be controlled and adjusted. The volume adjusted by this program is different from the substrate volume divided into the above-mentioned seven stages, and can smoothly change from mute to maximum volume. For example, even when a hall clerk or the like rotates the knob portion of the volume adjustment volume 4140a to set the volume low, the speaker and the door frame 5 housed in the speaker box 820 provided in the main body frame 3 can be used. Although the production sounds such as music and sound effects flowing from the provided speaker 130 are reduced, the volume is loud when the pachinko gaming machine 1 has a problem or when the player is cheating (in this embodiment, the volume is high). The notification sound set to (maximum volume) can be played. Therefore, even if the volume of the effect sound is reduced, it is possible to prevent the hall clerk and the like from being less likely to notice the occurrence of a problem or the cheating of the player due to the notification sound. In addition, based on the current board volume set by adjusting the volume based on the rotation operation of the knob, the volume at which the advertisement sound is played is reduced so as not to interfere with music and sound effects, while the advertisement sound is played. In addition to music and sound effects, increase the volume of the sound to make the screen unfolded by the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470 more powerful. It is also possible to direct and announce that there is a high possibility that the gaming state will be favorable to the player.

Following step S1032, the effect control program performs backup processing (step S1034). In this backup process, the effect control program converts the contents stored in the peripheral control MPU 4150a and the external peripheral control RAM 4150c shown in FIG. 16 into the backup first area 4150 cc and the backup second area 4150 cc. In addition to copying and backing up each, the contents stored in the peripheral control MPU 4150a and the external peripheral control SRAM 4150d are copied and backed up in the backup first area 4150db and the backup second area 4150dc, respectively.

Specifically, in the backup process, the peripheral control RAM 4150c is backed up for each frame (1 frame) in the backup target work area 4150ca shown in FIG. 16, that is, every time the peripheral control unit routine processing is executed. The lamp drive board side transmission data storage area 4150caa, the frame decoration drive amplifier board side LED transmission data storage area 4150cab, the reception command storage area 4150cac, the RTC information acquisition storage area 4150cad, and Peripheral control DMA controller 4150ac is set in Bank1 (1fr) and Bank2 (1fr) of the backup first area 4150cc by using the effect information (1fr) stored in the schedule data storage area 4150cae as the effect backup information (1fr). Copy at high speed, and the peripheral control DMA controller 4150ac copies at high speed to Bank 3 (1fr) and Bank 4 (1fr) in the backup second area 4150cc.

To briefly explain the high-speed copying of the contents stored in Bank0 (1fr) by the peripheral control DMA controller 4150ac, the peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. 16 is a requirement factor of the peripheral control DMA controller 4150ac. Specify a copy of the contents stored in Bank0 (1fr) to Bank1 (1fr) of the backup first area 4150cc, and change the contents stored in the start address of Bank0 (1fr) to the end address of Bank0 (1fr). All the stored contents are continuously copied in order from the start address of Bank1 (1fr) of the backup first area 4150cc by a predetermined byte (for example, 1 byte), and the peripheral control MPU core 4150aa is the peripheral control DMA controller. Specify the copy of the contents stored in Bank0 (1fr) as the request factor of 4150ac to Bank2 (1fr) of the backup first area 4150cc, and from the contents stored in the start address of Bank0 (1fr), Bank0 (1fr). ) Is continuously copied by a predetermined byte (for example, 1 byte) from the start address of Bank 2 (1fr) in the backup first area 4150 kb up to the contents stored in the terminal address.

Subsequently, the peripheral control MPU core 4150aa specifies a copy of the contents stored in Bank0 (1fr) as a requirement factor of the peripheral control DMA controller 4150ac to Bank3 (1fr) of the backup second area 4150cc, and specifies Bank0 (1fr). ) From the content stored in the start address to the content stored in the end address of Bank0 (1fr), the start address of Bank3 (1fr) in the second area 4150cc is continuously backed up by a predetermined byte (for example, 1 byte). Copy everything in order from, and specify the copy of the contents stored in Bank0 (1fr) as the requirement factor of the peripheral control DMA controller 4150ac to Bank4 (1fr) of the backup second area 4150cc. Then, the contents stored in the start address of Bank0 (1fr) to the contents stored in the end address of Bank0 (1fr) are continuously backed up by a predetermined byte (for example, 1 byte). Copy everything in order from the start address of 1fr).

Further, in the backup process, the peripheral control SRAM 4150d is backed up for each frame (1 frame) in the backup target work area 4150da shown in FIG. 16, that is, every time the peripheral control unit routine processing is executed. Peripheral control DMA controller 4150ac is high-speed in Bank1 (SRAM) and Bank2 (SRAM) of backup first area 4150db using the effect information (SRAM) stored in Bank0 (SRAM) as the effect backup information (SRAM). And the peripheral control DMA controller 4150ac copies to Bank3 (SRAM) and Bank4 (SRAM) in the backup second area 4150dc at high speed.

To briefly explain the high-speed copy of the contents stored in Bank0 (SRAM) by the peripheral control DMA controller 4150ac, the peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. 16 is a requirement factor of the peripheral control DMA controller 4150ac. Specify the copy of the contents stored in Bank0 (SRAM) to Bank1 (SRAM) of the backup first area 4150db, and change the contents stored in the start address of Bank0 (SRAM) to the end address of Bank0 (SRAM). Up to the stored contents are continuously copied by predetermined bytes (for example, 1 byte) in order from the start address of Bank1 (SRAM) in the first area 4150db, and the peripheral control MPU core 4150aa is the peripheral control DMA controller. Specify the copy of the contents stored in Bank0 (SRAM) as the request factor of 4150ac to Bank2 (SRAM) of the backup first area 4150db, and from the contents stored in the start address of Bank0 (SRAM), Bank0 (SRAM). ) Is continuously copied by a predetermined byte (for example, 1 byte) from the start address of Bank2 (SRAM) in the backup first area 4150db.

Subsequently, the peripheral control MPU core 4150aa specifies a copy of the contents stored in Bank0 (SRAM) as a requirement factor of the peripheral control DMA controller 4150ac to Bank3 (SRAM) of the backup second area 4150dc, and specifies Bank0 (SRAM). ) Is continuously backed up from the contents stored in the start address of Bank0 (SRAM) to the contents stored in the end address of Bank0 (SRAM) by predetermined bytes (for example, 1 byte). All are copied in order from, and the peripheral control MPU core 4150aa specifies the copy of the contents stored in Bank0 (SRAM) as the requirement factor of the peripheral control DMA controller 4150ac to Bank4 (SRAM) of the backup second area 4150dc. Then, from the contents stored in the start address of Bank0 (SRAM) to the contents stored in the end address of Bank0 (SRAM), predetermined bytes (for example, 1 byte) are continuously backed up in Bank4 of the second area 4150dc (Bunk4). Copy everything in order from the start address of SRAM).

Following step S1034, the WDT clear process is performed (step S1036). In this WDT clear processing, a clear signal is output to the peripheral control built-in WDT4150af and the peripheral control external WDT4150e so that the peripheral control MPU4150a is not reset.

Following step S1036, the effect control program sets the value 0 in the steady processing flag SP-FLG as the execution of the peripheral control unit steady processing is completed (step S1038), returns to step S1006 again, and returns to the V blank signal detection flag VB. The value 0 is set in −FLG for initialization, and the determination in step S1008 is repeated until the value 1 is set in the V blank signal detection flag VB—FLG in the peripheral control unit V blank signal interrupt processing described later. That is, in step S1008, it waits until the value 1 is set in the V blank signal detection flag VB-FLG, and when it is determined in step S1008 that the V blank signal detection flag VB-FLG has a value 1, steps S1009 to step S1009. The process of S1038 is performed, and the process returns to step S1006 again. As described above, when it is determined in step S1008 that the V blank signal detection flag VB-FLG has a value of 1, the processes of steps S1009 to S1038 are performed. The processing of steps S1009 to S1038 is referred to as "peripheral control unit steady processing".

This peripheral control unit steady-state processing starts from the effect control program first setting a value 1 in the steady-state processing flag SP-FLG assuming that the peripheral control unit steady-state processing is being executed in step S1009, and 1 ms in step S1010. The interrupt timer start processing is performed, each processing of step S1012, step S1014, ..., And step S1036 is performed, and finally, in step S1038, the value 0 is set to the steady processing flag SP-FLG as the execution of the peripheral control unit steady processing is completed. If you set, it will be completed. The peripheral control unit steady processing is executed when the V blank signal detection flag VB-FLG has a value of 1 in step S1008. As described above, the V blank signal detection flag VB-FLG is executed when a V blank signal indicating that the screen data from the peripheral control MPU4150a can be accepted is input from the sound source built-in VDP4160a. The value 1 is set in the peripheral control unit V blank signal interrupt processing described later. In the present embodiment, as the frame frequency (the number of screen updates per second) between the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470, as described above, it is approximately seconds. Since it is set to 30 fps, the interval at which the V blank signal is input is about 33.3 ms (= 1000 ms ÷ 30 fps). That is, the peripheral control unit steady processing is repeatedly executed about every 33.3 ms.

[17-1-2. Peripheral control unit V blank signal interrupt processing]
Next, a V blank signal indicating that the screen data from the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 15 can be accepted was input from the liquid crystal and the sound source built-in VDP 4160a of the sound control unit 4160. Peripheral control unit V blank signal interrupt processing to be executed with this as an opportunity will be described. When the peripheral control unit V blank signal interrupt processing is started, the peripheral control MPU 4150a of the peripheral control unit 4150 determines whether the steady-state processing flag SP-FLG has a value of 0, as shown in FIG. 64 (step). S1045). As described above, the steady-state processing flag SP-FLG has a value of 1 when the peripheral control unit steady-state processing in steps S1009 to S1038 in the peripheral control unit power-on processing in FIG. 63 is being executed, and the peripheral control unit steady-state. The value is set to 0 when the processing is completed.

When the steady-state processing flag SP-FLG is not a value 0 (value 1) in step S1045, that is, when the peripheral control unit steady-state processing is being executed, this routine is terminated as it is. On the other hand, when the steady processing flag SP-FLG is a value 0 in step S1045, that is, when the execution of the peripheral control unit steady processing is completed, the value 1 is set in the V blank signal detection flag VB-FLG (step S1050). Exit this routine. As described above, this V blank signal detection flag VB-FLG is a flag for determining whether or not to execute the peripheral control unit steady processing, and has a value of 1 when the peripheral control unit steady processing is executed, and peripheral control. The value is set to 0 when the steady processing is not executed.

In the present embodiment, in step S1045, it is determined whether or not the steady processing flag SP-FLG has a value of 0, that is, whether or not the peripheral control unit steady processing has been executed, and the peripheral control unit steady processing has been executed. Occasionally, in step S1050, the value 1 is set in the V blank signal detection flag VB-FLG, but this is because the V blank signal is input and the V blank is executed while the peripheral control unit steady processing is being executed. When the value 1 is set in the signal detection flag VB-FLG, the peripheral control unit steady processing currently being executed is assumed to be executed in the determination of step S1008 in the peripheral control unit power-on processing in FIG. Since the peripheral control unit steady processing is forcibly canceled in the middle and the execution is started from the beginning, in order to prevent this, the peripheral control unit power-on processing (peripheral control unit steady processing) in FIG. By setting the value 1 to the processing flag SP-FLG, it is notified to the peripheral control unit V blank signal interrupt processing, which is this routine, that the peripheral control unit steady processing is being executed, and the peripheral control unit power supply in FIG. 63. Peripheral control unit V blank, which is this routine, indicates that the execution of peripheral control unit steady processing is completed by setting the value 0 in the steady processing flag SP-FLG in step S1038 in the on-time processing (peripheral control unit steady processing). By transmitting to the signal interrupt processing, whether or not the constant processing flag SP-FLG has a value of 0 in the determination of step S1045 in the peripheral control unit V blank signal interrupt processing, which is this routine, that is, the peripheral control unit steady processing is executed. It is designed to determine whether or not it has been completed. In other words, it is a measure when the peripheral control unit steady-state processing cannot be completed by the time the V-blank signal is input and the next V-blank signal is input, so-called processing failure.

As a result, in the peripheral control unit steady processing this time, if the processing cannot be completed in about 33.3 ms and the processing fails, the next time is determined in step S1008 in the peripheral control unit power-on processing in FIG. It is in a state of waiting until the V blank signal of is input. That is, the time for executing the current peripheral control unit steady processing that has failed the processing is about 66.6 ms. Normally, the peripheral control unit 1ms timer interrupt processing, which will be described later, is repeatedly executed every time the 1ms interrupt timer is activated by starting the 1ms interrupt timer in step S1010 in the peripheral control unit power-on processing (peripheral control unit steady processing) of FIG. Is executed only 32 times for one peripheral control unit steady processing, but if the above-mentioned processing failure this time peripheral control unit steady processing exists, the peripheral control unit 1ms timer interrupt processing is 64 times. It is designed to be executed only 32 times. That is, even if the peripheral control unit steady processing fails, the consistency between the production progress state by the peripheral control unit steady processing and the production progress state by the peripheral control unit 1ms timer interrupt processing, which is the timer interrupt control, is consistent. It is designed not to collapse. Therefore, even if the peripheral control unit steady processing fails, the progress state of the effect can be reliably matched.

[17-1-3. Peripheral control unit 1ms timer interrupt processing]
Next, the peripheral control unit 1ms timer interrupt processing that is repeatedly executed every time the 1ms interrupt timer is generated by the activation of the 1ms interrupt timer in step S1010 in the peripheral control unit steady processing of the peripheral control unit power-on processing of FIG. 63 will be described. .. When the peripheral control unit 1ms timer interrupt processing is started, the peripheral control MPU4150a of the peripheral control unit 4150 shown in FIG. 15 has whether or not the 1ms timer interrupt execution count STN is smaller than 33 times, as shown in FIG. 65. Is determined (step S1100). As described above, the 1 ms timer interrupt execution count STN is determined by the 1 ms interrupt timer activation process in step S1010 in the peripheral control unit steady process of the peripheral control unit power-on processing in FIG. 63, in which the 1 ms interrupt timer is activated in this routine. A peripheral control unit 1ms timer A counter that counts the number of times interrupt processing is executed. In the present embodiment, as the frame frequency (the number of screen updates per second) between the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470, as described above, it is approximately seconds. Since it is set to 30 fps, the interval at which the V blank signal is input is about 33.3 ms (= 1000 ms ÷ 30 fps). That is, since the peripheral control unit steady processing is repeatedly executed about every 33.3 ms, after the 1 ms interrupt timer is started in step S1010 in the peripheral control unit steady process, the next peripheral control unit steady process is executed. Is executed, the peripheral control unit 1ms timer interrupt processing is executed only 32 times. Specifically, when the 1 ms interrupt timer is activated in step S1010 in the peripheral control unit steady processing, the first 1 ms timer interrupt is generated first, the second, ..., And the 32nd 1 ms timer interrupt is sequentially performed. It will occur.

When the 1ms timer interrupt execution count STN is not smaller than 33 times in step S1100, that is, when the 33rd 1ms timer interrupt occurs and the peripheral control unit 1ms timer interrupt processing is started, this routine is terminated as it is. When the occurrence of the 33rd 1ms timer interrupt happens to precede the generation of the next V blank signal, in the present embodiment, the peripheral control unit 1ms timer interrupt processing has the peripheral control unit V as the priority of the interrupt processing. Although it is set higher than the blank interrupt processing, the start of the peripheral control unit 1ms timer interrupt processing by the 33rd 1ms timer interrupt is forcibly canceled. In other words, in the present embodiment, since the V blank signal is a signal that controls the entire system of the peripheral control board 4140, when the occurrence of the 33rd 1 ms timer interrupt happens to precede the generation of the next V blank signal, , The start of the peripheral control unit 1ms timer interrupt processing by the 33rd 1ms timer interrupt is forcibly canceled in order to execute the peripheral control unit V blank interrupt processing. Then, after the 1ms interrupt timer is restarted in step S1010 in the peripheral control unit steady processing due to the generation of the V blank signal, the peripheral control unit 1ms timer interrupt processing due to the generation of the first 1ms timer interrupt is newly started. ing.

On the other hand, when the 1 ms timer interrupt execution count STN is smaller than 33 in step S1100, a value 1 is added (incremented, step S1102) to the 1 ms timer interrupt execution count STN. By adding the value 1 to the 1ms timer interrupt execution count STN, the 1ms interrupt timer is activated in the 1ms interrupt timer activation processing of step S1010 in the peripheral control unit steady processing of the peripheral control unit power-on processing in FIG. The number of times the peripheral control unit 1ms timer interrupt processing, which is this routine, is executed is increased by one time.

Following step S1102, a motor and solenoid drive process is performed (step S1104). In this motor and solenoid drive process, they are arranged in a time series constituting the electrical drive source schedule data set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the external peripheral control RAM 4150c shown in FIG. Among the drive data of the electric drive sources such as the motor and the solenoid, the electric drive sources such as the motor and the solenoid of the frame decoration drive amplifier board 194 and the motor drive board 4180 shown in FIG. 15 according to the drive data indicated by the pointer. The pointer is updated to the next drive data specified in time series, and the pointer is updated each time the motor and solenoid drive process is executed.

Specifically, in the motor and solenoid drive processing, the DMA serial continuous transmission process to the frame decoration drive amplifier board 194 is performed. Here, the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. 16 is used to continuously transmit the serial I / O port for the frame decoration drive amplifier board motor. When continuous transmission of the serial I / O port for the frame decoration drive amplifier board motor is started, first, the electrical drive source schedule data set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the external peripheral control RAM 4150c is input. Of the drive data of the electric drive sources such as motors and solenoids arranged in the time series, the drive signal to the dial drive motor 414 of the operation unit 400 shown in FIG. 7 is based on the drive data indicated by the pointer. The door-side motor drive data STM-DAT for outputting is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c, and is created, and the peripheral control RAM 4150c shown in FIG. The frame is set in the transmission data storage area 4150 caf for the motor on the board side of the decorative drive amplifier. The peripheral control CPU core 4150aa of the peripheral control MPU 4150a specifies the transmission of the serial I / O port for the frame decoration drive amplifier board motor as a requirement factor of the peripheral control DMA controller 4150ac, and stores the transmission data for the frame decoration drive amplifier board side motor. The first byte of the door-side motor drive data STM-DAT stored at the start address of the region 4150 caf is sent to the frame decoration drive amplifier board motor via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer to the transmission buffer register of the serial I / O port for writing. As a result, the serial I / O port for the frame decoration drive amplifier board motor transfers the written transmission buffer register data to the transmission shift register, and synchronizes with the door side motor drive clock signal STM-CLK to transmit the transmission shift register. 1 byte of data is started to be transmitted bit by bit.

The peripheral control DMA controller 4150ac triggers each time a transmission interrupt request for the frame decoration drive amplifier board motor serial I / O port is generated (in this embodiment, the frame decoration drive amplifier board motor serial I / O). The 1-byte data written in the transmission buffer register of the port is transferred to the transmission shift register, and the transmission buffer register is empty when the 1-byte data is exhausted.), Peripheral control CPU core 4150aa When the bus is not used, the remaining door-side motor drive data STM-DAT stored in the transmission data storage area 4150 caf for the frame decoration drive amplifier board side motor is stored in byte by byte, external bus 4150h, peripheral control bus controller. The serial I / O port for the frame decoration drive amplifier board motor is written by transferring to the transmission buffer register of the serial I / O port for the frame decoration drive amplifier board motor via the 4150ad and the peripheral bus 4150ai. The data of the transmitted buffer register is transferred to the transmission shift register, and the 1-byte data of the transmission shift register is started to be transmitted bit by bit in synchronization with the door side motor drive clock signal STM-CLK, and the frame decoration drive amplifier board is used. Continuous transmission is performed by the serial I / O port for the motor.

Further, in the motor and solenoid drive processing, the DMA serial continuous transmission process to the motor drive board 4180 is performed. Here, too, the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. 16 is used to continuously transmit the serial I / O port for the motor drive board. When the continuous transmission of the serial I / O port for the motor drive board is started, first, when configuring the electrical drive source schedule data set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the external peripheral control RAM 4150c. Motors for moving various movable bodies provided on the game board 4 shown in FIG. 8 based on the drive data instructed by the pointer among the drive data of the electric drive sources such as motors and solenoids arranged in series. The game board side motor drive data SM-DAT for outputting the drive signal to the or solenoid is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c, and is also shown in the figure. It is set in the transmission data storage area 4150 cg on the motor drive board side of the peripheral control RAM 4150 c shown in 16. Then, the peripheral control CPU core 4150aa of the peripheral control MPU 4150a specifies the transmission of the serial I / O port for the motor drive board as the required factor of the peripheral control DMA controller 4150ac, and stores it in the start address of the transmission data storage area 4150 cg on the motor drive board side. The first byte of the game board side motor drive data SM-DAT is sent to the transmission buffer of the serial I / O port for the motor drive board via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer to register and write. As a result, the serial I / O port for the motor drive board transfers the written data of the transmission buffer register to the transmission shift register, and synchronizes with the game board side motor drive clock signal SM-CLK to be one of the transmission shift registers. Transmission of byte data is started bit by bit.

The peripheral control DMA controller 4150ac triggers each time a transmission interrupt request for the serial I / O port for the motor drive board is generated (in the present embodiment, the transmission buffer register for the serial I / O port for the motor drive board is used). The written 1-byte data is transferred to the transmission shift register, and the transmission buffer register runs out of 1-byte data and becomes empty.) The peripheral control CPU core 4150aa is using the bus. If not, the remaining game board side motor drive data SM-DAT stored in the motor drive board side transmission data storage area 4150 cag is sent byte by byte via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. By transferring and writing to the transmission buffer register of the serial I / O port for the motor drive board, the serial I / O port for the motor drive board transfers the data of the written transmission buffer register to the transmission shift register. In synchronization with the game board side motor drive clock signal SM-CLK, 1-byte data of the transmission shift register is started to be transmitted bit by bit, and continuous transmission is performed by the serial I / O port for the motor drive board.

Following step S1104, the movable body information acquisition process is performed (step S1106). In this movable body information acquisition process, history information of detection signals from various detection switches (for example, in-situ history information) is determined by determining whether or not detection signals from various detection switches provided on the game board 4 are input. , Movable position history information, etc.) is created and set in the movable body information acquisition storage area 4150cah of the peripheral control MPU 4150a and the external peripheral control RAM 4150c shown in FIG. From the history information of the detection signals from the various detection switches set in the movable body information acquisition storage area 4150cah, the original position, the movable position, and the like of the various movable bodies provided in the game board 4 can be acquired.

Following step S1106, the operation unit information acquisition process is performed (step S1108). In this operation unit information acquisition process, the history information of the detection signals from the various detection switches (for example, the dial operation unit) is determined by determining whether or not the detection signals from the various detection switches provided in the operation unit 400 are input. The rotation (rotation direction) history information of 401, the operation history information of the pressing operation unit 405, etc.) are created, and the operation unit information acquisition storage area of the peripheral control MPU 4150a and the external peripheral control RAM 4150c shown in FIG. Set to 4150 kai. From the history information of the detection signals from the various detection switches set in the operation unit information acquisition storage area 4150 kai, the rotation direction of the dial operation unit 401 and the operation presence / absence of the pressing operation unit 405 can be acquired.

Following step S1108, drawing state information acquisition processing is performed (step S1110). In this drawing state information acquisition process, history information of the LOCKN signal output from the LOCKN terminal of the upper plate side liquid crystal receiver ICSDIC0 provided in the touch panel drive board 450 shown in FIG. 35 is created, and the peripheral control shown in FIG. It is set in the drawing state information acquisition storage area 4150cak of the peripheral control RAM 4150c externally attached to the MPU4150a. As described above, the LOCKN signal determines that the drawing data received by the upper plate side liquid crystal receiver ICSDIC0 provided on the touch panel drive board 450 from the upper plate side liquid crystal transmitter IC4160d provided on the peripheral control board 4140 is abnormal data. Then, it is a signal to be output to convey that fact, and specifically, the transmitter IC4160d for the upper plate side liquid crystal provided in the peripheral control board 4140 and the receiver ICSDIC0 for the upper plate side liquid crystal provided in the touch panel drive board 450. It is a signal output to request transmission of a predetermined data pattern (SYNC pattern) for confirming (recovering) the connection between connections, that is, between the transmitter and the receiver. Acquisition of drawing state information The frequency of defects between the connection between the peripheral control board 4140 and the touch panel drive board 450 and the state of occurrence of defects are acquired from the history information of the LOCKN signal set in the storage area 4150 ack, and the liquid crystal display device 470 on the upper plate side. You can get the drawing state of.

Following step S1110, the main prize ball number information output process is performed (step S1112). In this main prize ball number information output process, when configuring the schedule data for the main prize ball information output signal set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the external peripheral control RAM 4150c shown in FIG. Output waveform data for generating the main prize ball information output signal that conveys to the hall computer as the main prize ball information that the number of game balls to be paid out as prize balls has reached 10 balls arranged in a series. Of these, the main prize ball information output signal is output to the external terminal board 784 shown in FIG. 30 according to the output waveform data indicated by the pointer, and the pointer is updated to the next output waveform data specified in time series. The pointer is updated every time the main prize ball number information output process is executed.

Following step S1112, the power consumption status history information creation process is performed (step S1113). In this power consumption status history information creation process, the value transmitted by the power consumption suppression signal from the power supply board 851 (power consumption suppression stage) is sampled, and the power consumption of the peripheral control unit 4150 shown in FIG. 15 as the power consumption status history information. The status history RAM 4150f is sequentially stored. As described above, the power consumption suppression signal is output from the power consumption monitoring circuit 855da. As shown in FIG. 19A, the power consumption monitoring circuit 855da includes a power measurement circuit 855da and a power consumption suppression stage determination circuit 855da. The + 37V supplied from the smoothing circuit 855c is supplied to the + 5V power supply creation circuit 855db, the + 12V power supply creation circuit 855dc, and the + 24V power supply creation circuit 855dd via the power measurement circuit 855da, respectively. The power measurement circuit 855da measures the power consumption of + 37V supplied from the smoothing circuit 855c in real time and outputs it to the power consumption suppression stage determination circuit 855da. The power consumption suppression stage determination circuit 855da determines the power consumption suppression stage indicating how much power consumption should be suppressed based on the power consumption measured by the power measurement circuit 855daa, and determines the determination result of three lines. By setting the value of the power consumption suppression signal configured as the signal wiring and outputting it to the frame peripheral relay terminal plate 868, the power consumption suppression signal is input to the peripheral control unit 4150 via the frame peripheral relay terminal plate 868. It is supposed to be done. As described above, the power consumption suppression signal is configured as three signal wirings (that is, is configured as three parallel signals), and transmits eight values from a value to a value of 7. Can be done.

As described above, the power consumption suppression stage determination circuit 855da determines that the power consumption suppression stage is stage 0 when the power consumption of + 37V measured by the power measurement circuit 855daa is 0% or more and less than 10%, and consumes power. A value of 0 is set as the value of the suppression signal, and when the power consumption of + 37V measured by the power measurement circuit 855daa is 10% or more and less than 20%, it is determined that the power consumption suppression stage is step 1 and the power consumption suppression signal is used. A value of 1 is set as the value, and when the power consumption of + 37V measured by the power measurement circuit 855da is 20% or more and less than 30%, it is determined that the power consumption suppression stage is stage 2, and the value is used as the value of the power consumption suppression signal. 2 is set, and when the power consumption of + 37V measured by the power measurement circuit 855daa is 30% or more and less than 40%, it is determined that the power consumption suppression stage is stage 3, and the value 3 is set as the value of the power consumption suppression signal. Then, when the power consumption of + 37V measured by the power measurement circuit 855daa is 40% or more and less than 50%, it is determined that the power consumption suppression stage is step 4, and the value 4 is set as the value of the power consumption suppression signal, and the power consumption is set. When the power consumption of + 37V measured by the measurement circuit 855daa is 50% or more and less than 60%, it is determined that the power consumption suppression stage is step 5, and a value 5 is set as the value of the power consumption suppression signal, and the power consumption suppression circuit 855daa When the power consumption of + 37V measured in 1 is 60% or more and less than 70%, it is determined that the power consumption suppression stage is stage 6, a value 6 is set as the value of the power consumption suppression signal, and the power consumption measurement circuit 855da measures the power consumption. When the power consumption of + 37V is 70% or more, it is determined that the power consumption suppression stage is step 7, and the value 7 is set as the value of the power consumption suppression signal.

In this way, in the power consumption status history information creation process, the value (value 0 to value 7) transmitted by the power consumption suppression signal from the power supply board 851 is sampled every time this routine is executed, that is, every 1 ms. By sequentially storing in the power consumption status history RAM 4150f of the peripheral control unit 4150 as the power consumption suppression stage (stages 0 to 7), the power consumption suppression stages are arranged in chronological order as power consumption status history information.

Following step S1113, a backup process is performed (step S1114), and this routine is terminated. In this backup process, the contents stored in the peripheral control MPU 4150a and the external peripheral control RAM 4150c shown in FIG. 16 are copied to the backup first area 4150 cc and the backup second area 4150 cc, respectively, and backed up. At the same time, the contents stored in the peripheral control MPU 4150a and the external peripheral control SRAM 4150d are copied and backed up in the backup first area 4150db and the backup second area 4150dc, respectively.

Specifically, in the backup process, the peripheral control RAM 4150c is executed every time the 1 ms interrupt timer is generated in the backup target work area 4150ca shown in FIG. 16, that is, the peripheral control unit 1 ms timer interrupt process, which is this routine, is executed. Each time it is backed up, the frame decoration drive amplifier board side motor transmission data storage area 4150 caf, motor drive board side transmission data storage area 4150 cag, and movable body information acquisition storage area 4150 cah included in the backup target Bank0 (1 ms). , And the effect information (1 ms) stored in the operation unit information acquisition storage area 4150 kai is used as the effect backup information (1 ms), and peripheral control is performed on Bank 1 (1 ms) and Bank 2 (1 ms) of the backup first area 4150 cc. The DMA controller 4150ac copies at high speed, and the peripheral control DMA controller 4150ac copies at high speed to Bank 3 (1 ms) and Bank 4 (1 ms) in the backup second area 4150 cc.

To briefly explain the high-speed copying of the contents stored in Bank 0 (1 ms) by the peripheral control DMA controller 4150ac, the peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. 16 is a requirement factor of the peripheral control DMA controller 4150ac. Specify a copy of the contents stored in Bank0 (1ms) to Bank1 (1ms) of the backup first area 4150cc, and change the contents stored in the start address of Bank0 (1ms) to the end address of Bank0 (1ms). All the stored contents are continuously copied in order from the start address of Bank 1 (1 ms) of the backup first area 4150 kb by a predetermined byte (for example, 1 byte), and the peripheral control MPU core 4150aa is the peripheral control DMA controller. Specify the copy of the contents stored in Bank0 (1ms) as the request factor of 4150ac to Bank2 (1ms) of the backup first area 4150cc, and Bank0 (1ms) from the contents stored in the start address of Bank0 (1ms). ), The contents stored in the terminal address of) are continuously copied in order from the start address of Bank 2 (1 ms) in the backup first area 4150 kb by a predetermined byte (for example, 1 byte).

Subsequently, the peripheral control MPU core 4150aa specifies a copy of the contents stored in Bank0 (1ms) as a requirement factor of the peripheral control DMA controller 4150ac to Bank3 (1ms) of the backup second area 4150cc, and specifies Bank0 (1ms). ), The contents stored in the end address of Bank0 (1 ms) are continuously backed up by predetermined bytes (for example, 1 byte). The start address of Bank3 (1 ms) in the second area 4150 cc. Copy everything in order from, and the peripheral control MPU core 4150aa specifies the copy of the contents stored in Bank0 (1ms) as the requirement factor of the peripheral control DMA controller 4150ac to Bank4 (1ms) of the backup second area 4150cc. Then, the contents stored in the start address of Bank0 (1 ms) to the contents stored in the end address of Bank0 (1 ms) are continuously backed up by a predetermined byte (for example, 1 byte). Copy everything in order from the start address of 1ms).

As described above, in the peripheral control unit 1 ms timer interrupt process, various processes related to the effect of steps S1104 to S1108 described above are executed as the progress of the effect within the period of 1 ms. On the other hand, in the peripheral control unit steady processing in the peripheral control unit power-on processing of FIG. 63, various processes related to the production of steps S1012 to S1032 described above are executed as the progress of the production within a period of about 33.3 ms. is doing. In the peripheral control unit 1ms timer interrupt processing, when the 1ms timer interrupt execution count STN is not smaller than the value 33 in step S1100, that is, when the 33rd 1ms timer interrupt occurs and the peripheral control unit 1ms timer interrupt processing is started. Since this routine is terminated as it is, even if the occurrence of the 33rd 1ms timer interrupt happens to precede the generation of the next V blank signal, the peripheral control unit due to this 33rd 1ms timer interrupt Peripheral control by forcibly canceling the start of the 1 ms timer interrupt process, restarting the 1 ms interrupt timer in step S1010 in the peripheral control unit steady process due to the generation of the V blank signal, and then newly generating the 1 ms timer interrupt. Part 1ms timer interrupt processing is started. That is, the consistency between the progress state of the effect by the peripheral control unit steady processing and the progress state of the effect by the peripheral control unit 1 ms timer interrupt process, which is the timer interrupt control, is not broken. Therefore, it is possible to surely match the progress state of the production.

Further, as described above, the interval at which the V blank signal is output varies slightly depending on the liquid crystal size of the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. Even in the production lot of the peripheral control board 4140 on which the peripheral control MPU 4150a and the VDP 4160a with a built-in sound source are mounted, the interval at which the V blank signal is output may change slightly. In the present embodiment, since the V blank signal is a signal that controls the entire system of the peripheral control board 4140, if the occurrence of the 33rd 1 ms timer interrupt happens to precede the generation of the next V blank signal, peripheral control is performed. The start of the peripheral control unit 1ms timer interrupt processing by the 33rd 1ms timer interrupt is forcibly canceled in order to execute the unit V blank interrupt processing. That is, in the present embodiment, even if the interval at which the V blank signal is output changes slightly, the start of the peripheral control unit 1ms timer interrupt processing by the 33rd 1ms timer interrupt is forcibly canceled. It is possible to absorb the time lag due to a slight change in the interval at which the V blank signal is output.

[17-1-4. Peripheral control unit command reception interrupt processing]
Next, peripheral control unit command reception interrupt processing for receiving various commands from the main control board 4100 will be described. When various commands from the main control board 4100 are started to be transmitted as serial data, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 15 triggers the main control to incorporate the main peripheral serial data into the peripheral control MPU 4150a. 1 byte (8 bits) of information is fetched into the reception buffer by the serial I / O port for the board, and when this fetching is completed, an interrupt is generated with this as a trigger, and peripheral control unit command reception interrupt processing is performed. In the main peripheral serial data, one packet is composed of 3 bytes, the status is assigned as the 1st byte, the mode is assigned as the 2nd byte, and the status and mode are regarded as numerical values as the 3rd byte, and the total thereof. The calculated sum value is assigned.

When the peripheral control unit command reception interrupt process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 determines whether or not the 1-byte reception period timer has timed out, as shown in FIG. 66 (step S1200). This 1-byte reception period timer sets a period during which 1-byte (8-bit) information of the main peripheral serial data transmitted from the main control board 4100 can be received.

When the 1-byte reception period timer has not timed out in step S1200, that is, within the period during which 1-byte (8-bit) information of the main peripheral serial data transmitted from the main control board 4100 can be received, the periphery 1 byte of information received from the receive buffer of the serial I / O port for the main control board built in the control MPU4150a is taken in (step S1202), and a value 1 is added to the reception counter SRXC (increment, step S1204). This reception counter SRXC is a counter indicating the number of times the data has been fetched from the receive buffer, and when the status which is the first byte of the main cycle serial data is fetched from the receive buffer, the value is 1, and the mode which is the second byte of the main cycle serial data is set. When it is taken out from the receive buffer, it becomes a value 2, and when the sum value which is the third byte of the main peripheral serial data is taken out from the receive buffer, it becomes a value 3. The initial value 0 of the reception counter SRXC is set when the power is turned on or the like.

Following step S1204, it is determined whether or not the reception counter SRXC has a value of 3, that is, whether or not the sum value, which is the third byte of the main peripheral serial data, has been fetched from the reception buffer (step S1206). In this determination, following the status that is the first byte of the main peripheral serial data, the mode that is the second byte of the main circumference serial data, and the sum value that is the third byte of the main circumference serial data are sequentially input from the receive buffer. It is determined whether or not it has been taken out.

In step S1206, when the reception counter SRXC is not a value 3, that is, following the status which is the first byte of the main peripheral serial data, the mode which is still the second byte of the main peripheral serial data, and the third byte of the main peripheral serial data. When the sum values are not sequentially fetched from the receive buffer, the 1-byte reception period timer is set (step S1208), and this routine is terminated. By setting the 1-byte reception period timer in step S1208, the mode in which the second byte of the main cycle serial data or the sum value which is the third byte of the main cycle serial data can be received is set.

On the other hand, when the reception counter SRXC has a value of 3 in step S1206, that is, the status which is the first byte of the main peripheral serial data, the mode which is the second byte of the main peripheral serial data, and 3 of the main peripheral serial data. When the sum value, which is the byte th, is sequentially taken out from the reception buffer, the initial value 0 is set in the reception counter SRXC (step S1210), and the sum value is calculated (step S1212). In this calculation, the status which is the first byte of the main peripheral serial data and the mode which is the second byte of the main peripheral serial data already taken out from the receive buffer in step S1202 are regarded as numerical values, and the total (sum value). ) Is calculated.

Following step S1212, it is determined whether or not the sum value, which is the third byte of the main peripheral serial data already fetched from the receive buffer in step S1202, and the sum value calculated in step S1212 match (step). S1214). The thumb value, which is the third byte of the main peripheral serial data already taken out from the receive buffer in step S1202, is the sum value allocated as the third byte of the main peripheral serial data among the main peripheral serial data from the main control board 4100. Therefore, it should match the sum value calculated in step S1212. However, in the pachinko gaming machine 1, game balls are supplied from the pachinko island facility, and when the gaming balls rub against each other and become charged, they are electrostatically discharged and generate noise. Therefore, the pachinko gaming machine 1 is affected by noise. It is in a vulnerable environment. Therefore, in the present embodiment, on the peripheral control unit 4150 side, the status allocated as the first byte of the received main peripheral serial data and the mode allocated as the second byte of the main peripheral serial data are regarded as numerical values. The total (sum value) is calculated, and whether the calculated sum value matches the sum value allocated as the third byte of the main circumference serial data in the main circumference serial data from the main control board 4100. It is judged whether or not. As a result, the peripheral control MPU 4150a determines whether or not the main peripheral serial data has changed to the main peripheral serial data different from the normal one due to the influence of noise between the substrates of the main control board 4100 and the peripheral control board 4140. be able to.

In step S1214, when the sum value which is the third byte of the main circumference serial data already taken out from the reception buffer in step S1202 and the sum value calculated in step S1212 match, the received main circumference serial data is received. The status allocated as the first byte of the above and the mode allocated as the second byte of the main peripheral serial data are shown in FIG. 16, and the reception command storage area 4150cc of the peripheral control MPU 4150a and the external peripheral control RAM 4150c shown in FIG. (Step S1216), and the routine ends. This reception command storage area 4150cc is used as a ring buffer, and the status allocated as the first byte of the main circumference serial data and the mode allocated as the second byte of the main circumference serial data are the reception command storage area. It is stored in the peripheral control unit reception ring buffer of 4150 cc. This "peripheral control unit receive ring buffer" is a buffer that is used so that the end and the beginning of the buffer are connected. Data is stored sequentially from the beginning of the buffer, and when the end of the buffer is reached, it returns to the beginning. Remember. The peripheral control MPU4150a is allocated as the status allocated as the first byte of the main peripheral serial data received when stored in the peripheral control unit reception ring buffer in step S1216 and as the second byte of the main peripheral serial data. The mode is stored in association with the specified mode, and the sum value allocated as the third byte is discarded.

On the other hand, when the 1-byte reception period timer has not timed out in step S1200, that is, the period during which 1 byte (8 bits) of information of the main peripheral serial data transmitted from the main control board 4100 can be received has been exceeded. Occasionally, or in step S1214, if the sum value, which is the third byte of the main peripheral serial data already fetched from the receive buffer in step S1202, and the sum value calculated in step S1212 do not match, this routine is used as it is. finish.

[17-1-5. Peripheral control unit power failure warning signal interrupt processing]
Next, the peripheral control unit power failure warning signal executed when the power failure warning signal (peripheral power failure warning signal) from the power failure monitoring circuit 4100e of the main control board 4100, which is shown in FIG. 18, is input from the main control board 4100. The interrupt processing will be described. When the peripheral control unit power failure warning signal interrupt process is started, the peripheral control MPU4150a of the peripheral control unit 4150 shown in FIG. 15 first activates a 2-microsecond timer (step S1300), and then starts a power failure warning signal (peripheral power failure warning). It is determined whether or not the signal) is input (step S1302). If the power failure warning signal (peripheral power failure warning signal) is not input in this determination, this routine is terminated as it is.

On the other hand, when the power failure warning signal is input in step S1302, it is determined whether or not 2 microseconds have elapsed (step S1304). In this determination, it is determined whether or not the timer started in step S1300 has elapsed 2 microseconds. When 2 macro seconds have not elapsed in step S1304, the process returns to step S1302 to determine whether or not the power failure warning signal has been input, and when the power failure warning signal has not been input, this routine is terminated as it is, while the power failure warning is terminated. When the signal is input, it is determined again in step S1304 whether or not 2 microseconds have elapsed. That is, in the determination in step S1304, it is determined whether or not the power failure warning signal is continuously input for 2 microseconds after the peripheral control unit power failure warning signal interrupt processing, which is the routine, is started.

When the peripheral control unit power failure warning signal interrupt process, which is the routine, is started in step S1304 and the power failure warning signal is continuously input for 2 microseconds, power saving processing is performed (step S1306). In this power saving process, the backlights of the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the precision plate side liquid crystal display device 470 are turned off, the excitation to the motor and solenoid provided in the game board 4 is turned off, and various types are used. By suppressing the power consumption of the entire system of the pachinko gaming machine 1 by sequentially turning off the LEDs and the like, the peripheral control MPU4150a can operate for 20 milliseconds even if the power of the pachinko gaming machine 1 is cut off. Stable operation is secured only for the period.

Following step S1306, command reception standby processing is performed (step S1308). In this command reception standby process, assuming that there are various commands being transmitted by the main control board 4100, the peripheral control MPU4150a can receive the commands being transmitted for a period of at least 17 milliseconds. It is supposed to wait. When the command is received, the above-mentioned peripheral control unit command reception interrupt processing is started, and the reception command storage area 4150cc (peripheral control unit reception ring buffer) of the peripheral control MPU 4150a and the external peripheral control RAM 4150c shown in FIG. The received command is stored in).

Following step S1308, command backup processing is performed (step S1310). In the backup process of this command, the contents stored in the reception command storage area 4150cc included in Bank0 (1fr) in the backup target work area 4150ca shown in FIG. 16 are transferred to Bank1 (1fr) in the backup first area 4150cc and The peripheral control DMA controller 4150ac copies to Bank2 (1fr) at high speed, and the peripheral control DMA controller 4150ac copies to Bank3 (1fr) and Bank4 (1fr) of the backup second area 4150cc at high speed.

The high-speed copy of the contents stored in the received command storage area 4150cc included in Bank0 (1fr) by the peripheral control DMA controller 4150ac will be briefly described. The peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. 16 is peripheral. Specify the copy of the contents stored in the received command storage area 4150cc included in Bank0 (1fr) to the receiving command storage area included in Bank1 (1fr) of the backup first area 4150cc as the request factor of the control DMA controller 4150ac. Then, from the content stored in the start address of the receive command storage area 4150cc included in Bank0 (1fr) to the content stored in the end address of the receive command storage area 4150cc included in Bank0 (1fr), a predetermined byte (for example, , 1 byte) in succession Copy all in order from the start address of the received command storage area included in Bank 1 (1fr) of the first area 4150 kb, and the peripheral control MPU core 4150aa is a requirement factor of the peripheral control DMA controller 4150ac. Specify a copy of the contents stored in the reception command storage area 4150cc included in Bank0 (1fr) to the reception command storage area included in Bank2 (1fr) of the backup first area 4150cc, and set it to Bank0 (1fr). From the content stored in the start address of the received command storage area 4150cc included to the content stored in the end address of the received command storage area 4150cc included in Bank0 (1fr), a predetermined byte (for example, 1 byte) is consecutive. Then, all copies are made in order from the start address of the received command storage area included in Bank 2 (1fr) of the backup first area 4150 kb.

Subsequently, the peripheral control MPU core 4150aa includes the contents stored in the reception command storage area 4150cc included in the Bank0 (1fr) as a requirement factor of the peripheral control DMA controller 4150ac in the Bank3 (1fr) of the backup second area 4150cc. Specify the copy to the received command storage area to be stored, and store the contents stored in the start address of the received command storage area 4150cc included in Bank0 (1fr) in the terminal address of the receiving command storage area 4150cc included in Bank0 (1fr). The contents are copied in order from the start address of the received command storage area included in Bank3 (1fr) of the second area 4150cc, which is continuously backed up by a predetermined byte (for example, 1 byte), and the peripheral control MPU core. 4150aa is a requirement factor of the peripheral control DMA controller 4150ac, and the contents stored in the reception command storage area 4150cc included in Bank0 (1fr) are transferred to the reception command storage area included in Bank4 (1fr) of the backup second area 4150cc. Specify a copy, and specify the contents stored in the start address of the receive command storage area 4150cc included in Bank0 (1fr) to the contents stored in the end address of the receive command storage area 4150cc included in Bank0 (1fr). All bytes (for example, 1 byte) are continuously copied in order from the start address of the received command storage area included in Bank 4 (1fr) of the second area 4150 cc.

Following step S1310, it is determined whether or not a power failure warning signal (peripheral power failure warning signal) has been input (step S1312). When the power failure warning signal is input in this determination, the WDT clear process is performed (step S1314). In this WDT clear processing, the peripheral control MPU4150a outputs a clear signal to the peripheral control built-in WDT4150af shown in FIG. 16 and the peripheral control external WDT4150e shown in FIG. 15 so that the peripheral control MPU4150a is not reset. ..

On the other hand, when the power failure warning signal is not input in step S1312, or after step S1314, the process returns to step S1312 again to determine whether or not the power failure warning signal is input. That is, it is infinitely determined whether or not the power failure warning signal (peripheral power failure warning signal) is input. By continuing the determination indefinitely in this way, when the power failure warning signal (peripheral power failure warning signal) is not input in step S1312, the peripheral control MPU4150a clear signals to the peripheral control built-in WDT4150af and the peripheral control external WDT4150e. Is not output and the peripheral control MPU4150a is reset. On the other hand, when the power failure warning signal is input in step S1312, the WDT clear process is performed in step S1314 and the peripheral control MPU4150a is not reset. When the peripheral control MPU4150a is reset, the peripheral control unit power-on processing shown in FIG. 63 is restarted.

In this way, when the input of the power failure warning signal (peripheral power failure warning signal) continues in the infinite loop according to the determination in step S1312, the WDT clear processing is executed in step S1314 to perform peripheral control immediately before the power failure state occurs. The MPU4150a is not reset. On the other hand, if the input of the power failure warning signal is not continued and canceled in the infinite loop according to the determination in step S1312, the WDT clear process is not executed, so that the peripheral control built-in WDT4150af and the peripheral control external WDT4150e are displayed. The output of the clear signal is interrupted. As a result, even if the peripheral control unit power failure warning signal interrupt process, which is this routine, is erroneously started due to noise or the like, and the noise occurs beyond the period of 2 microseconds, the determination in step S1302 is passed. If the input of the power failure warning signal (peripheral power failure warning signal) is not continued and is canceled in the infinite loop by the determination by S1312, the peripheral control MPU4150a is reset because the WDT clear processing in step S1314 is not executed. Therefore, it is possible to deal with such noise by automatically resetting and returning.

[17-1-6. Power saving mode transition judgment processing at the time of power recovery]
Next, when the power is turned off (immediately before the power is turned off), the power status consumed by the pachinko game machine 1 is grasped at the time of power recovery, and the mode shifts to the power saving mode at the time of power recovery to suppress the power consumed by the pachinko game machine 1. When it is determined whether or not the power is restored and the mode shifts to the power saving mode at the time of power recovery, the volume of the effect sound flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 is reduced. The power saving mode transition determination process at the time of power recovery will be described, which is set to reduce the brightness of the LED for light emission decoration provided in the door frame 5 and the brightness of various LEDs mounted on various decorative boards provided in the game board 4. This power saving mode transition determination process at the time of power recovery is performed in the process of step S1004 in the peripheral control unit steady process of the peripheral control unit power-on process shown in FIG. 63.

When the power saving mode transition determination process at the time of power recovery is started, the peripheral control MPU4150a of the peripheral control unit 4150 shown in FIG. 15 identifies the power consumption suppression stage based on the power consumption status history information as shown in FIG. 68. (Step S1350). As described above, the power consumption status history information is a value transmitted by the power consumption suppression signal from the power supply board 851 in the power consumption status history information creation process in step S1113 in the peripheral control unit 1 ms timer interrupt process shown in FIG. 65 ( By sampling the values 0 to 7) and sequentially storing them in the power consumption status history RAM 4150f of the peripheral control unit 4150 shown in FIG. 15 as the power consumption suppression stages (stages 0 to 7), the power consumption suppression stage is timed. They are arranged in a series. When the power is turned off, the power consumption status history RAM 4150f is stored with the power consumption status history information of the power consumption status history storage unit 4150f by supplying backup power from the battery 4150 g of the peripheral control unit 4150 shown in FIG. It is supposed to be done.

In step S1350, among the power consumption status history information in which the values sampled and stored by the peripheral control MPU4150a are arranged in chronological order, the power of the pachinko game machine 1 is turned off (power failure or momentary power failure due to the power consumption of the pachinko game machine 1). For example, in addition to power outages due to lightning strikes and momentary power outages due to lightning strikes, power outages due to power outages supplied to the hall and instability of power supplied to the hall, pachinko game machines by staff such as hall clerk (Including power cutoff to 1) Immediately before the power is cut off, the value sampled and stored is extracted to specify the power consumption suppression stage immediately before the power is turned off. As a result, it is possible to grasp the power consumption suppression stage immediately before the power of the pachinko gaming machine 1 is turned off.

Following step S1350, it is determined whether or not the power consumption suppression step has reached the threshold value (step S1352). In this determination, it is determined whether or not the power consumption suppression step immediately before the power off of the pachinko gaming machine 1 specified in step S1350 has reached the threshold value. In this embodiment, step 7 is set as a threshold value.

When the power consumption suppression step has not reached the threshold value in step S1352, the power saving mode transition flag ECO-FLG at the time of power recovery is set to a value 0 (step S1354) to end this routine, while power consumption is consumed in step S1352. When the suppression stage has reached the threshold value, the value 1 is set in the power saving mode transition flag ECO-FLG at the time of power recovery (step S1356), the power saving mode timer activation process at the time of power recovery is performed (step S1358), and this routine To finish.

The power saving mode transition flag ECO-FLG at the time of power recovery is the effect sound flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 at the time of power recovery of the pachinko game machine 1. Whether to shift to the power saving mode at the time of power recovery, such as setting to reduce the volume, setting to reduce the brightness of the LED for light emitting decoration provided in the door frame 5 and various LEDs mounted on the various decorative boards provided in the game board 4. The value is set to 0 when not shifting to the power saving mode at the time of power recovery, and to 0 when shifting to the power saving mode at the time of power recovery.

The power-recovery power-saving mode timer activated in step S1358 measures the power-recovery power-saving mode state maintenance period during which the pachinko gaming machine 1 is maintained in the state of being activated as the power-recovery power-saving mode. In the mode, 5 minutes is set as the power saving mode state maintenance period at the time of power recovery. When the power recovery mode timer is activated, the time counting of the power saving mode state maintenance period at the time of power recovery is started, and the power saving mode state maintenance period at the time of power recovery elapses, the power saving mode timer at the time of power recovery is stopped, and FIG. 63 shows. In order to suppress the power consumption according to the power consumption in the pachinko game machine 1 by the power processing amount monitoring process in step S1027 in the peripheral control unit steady processing of the peripheral control unit power-on processing shown in the main body frame. It is mounted on the speaker housed in the speaker box 820 provided in 3 and the volume of the effect sound flowing from the speaker 130 provided in the door frame 5, the LED for light emission decoration provided in the door frame 5, and various decorative boards provided in the game board 4. The brightness of various LEDs is adjusted.

[17-1-7. Power consumption monitoring process]
Next, a power consumption monitoring process for adjusting the volume and the brightness of various LEDs in order to suppress the power consumption according to the power consumption in the pachinko gaming machine 1 will be described. This power consumption monitoring process is performed in the process of step S1027 in the peripheral control unit steady process of the peripheral control unit power-on process shown in FIG. 63.

When the power consumption monitoring process is started, the peripheral control MPU4150a of the peripheral control unit 4150 shown in FIG. 15 identifies the power consumption suppression stage based on the power consumption suppression signal as shown in FIG. 69 (step S1400). ). As described above, the power consumption suppression signal is output from the power consumption monitoring circuit 855da. As shown in FIG. 19A, the power consumption monitoring circuit 855da includes a power measurement circuit 855da and a power consumption suppression stage determination circuit 855da. The + 37V supplied from the smoothing circuit 855c is supplied to the + 5V power supply creation circuit 855db, the + 12V power supply creation circuit 855dc, and the + 24V power supply creation circuit 855dd via the power measurement circuit 855da, respectively. The power measurement circuit 855da measures the power consumption of + 37V supplied from the smoothing circuit 855c in real time and outputs it to the power consumption suppression stage determination circuit 855da. The power consumption suppression stage determination circuit 855da determines the power consumption suppression stage indicating how much power consumption should be suppressed based on the power consumption measured by the power measurement circuit 855daa, and determines the determination result of three lines. By setting the value of the power consumption suppression signal configured as the signal wiring and outputting it to the frame peripheral relay terminal plate 868, the power consumption suppression signal is input to the peripheral control unit 4150 via the frame peripheral relay terminal plate 868. It is supposed to be done. As described above, the power consumption suppression signal is configured as three signal wirings (that is, is configured as three parallel signals), and transmits eight values from a value to a value of 7. Can be done.

As described above, the power consumption suppression stage determination circuit 855da determines that the power consumption suppression stage is stage 0 when the power consumption of + 37V measured by the power measurement circuit 855daa is 0% or more and less than 10%, and consumes power. A value of 0 is set as the value of the suppression signal, and when the power consumption of + 37V measured by the power measurement circuit 855daa is 10% or more and less than 20%, it is determined that the power consumption suppression stage is step 1 and the power consumption suppression signal is used. A value of 1 is set as the value, and when the power consumption of + 37V measured by the power measurement circuit 855da is 20% or more and less than 30%, it is determined that the power consumption suppression stage is stage 2, and the value is used as the value of the power consumption suppression signal. 2 is set, and when the power consumption of + 37V measured by the power measurement circuit 855daa is 30% or more and less than 40%, it is determined that the power consumption suppression stage is stage 3, and the value 3 is set as the value of the power consumption suppression signal. Then, when the power consumption of + 37V measured by the power measurement circuit 855daa is 40% or more and less than 50%, it is determined that the power consumption suppression stage is step 4, and the value 4 is set as the value of the power consumption suppression signal, and the power consumption is set. When the power consumption of + 37V measured by the measurement circuit 855daa is 50% or more and less than 60%, it is determined that the power consumption suppression stage is step 5, and a value 5 is set as the value of the power consumption suppression signal, and the power consumption suppression circuit 855daa When the power consumption of + 37V measured in 1 is 60% or more and less than 70%, it is determined that the power consumption suppression stage is stage 6, a value 6 is set as the value of the power consumption suppression signal, and the power consumption measurement circuit 855da measures the power consumption. When the power consumption of + 37V is 70% or more, it is determined that the power consumption suppression stage is step 7, and the value 7 is set as the value of the power consumption suppression signal.

The value of the power consumption suppression signal set by the power consumption suppression stage determination circuit 855dab in step S1400 can be acquired, and the power consumption suppression stage can be specified from the acquired value.

Following step S1400, it is determined whether or not the power saving mode transition flag ECO-FLG at the time of power recovery has a value of 1 (step S1402). As described above, the power recovery mode transition flag ECO-FLG is set in the power recovery mode transition determination process of step S1004 in the peripheral control unit steady processing of the peripheral control unit power-on processing shown in FIG. 63. A setting to reduce the volume of the effect sound flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 when the power of the pachinko game machine 1 is restored, and the light emission provided in the door frame 5. It sets whether or not to shift to the power saving mode at the time of power recovery, which sets to reduce the brightness of the LEDs for decoration and the various LEDs mounted on the various decorative boards provided in the game board 4. The value is set to 0 when not shifting to the mode, and to 0 when shifting to the power saving mode at the time of power recovery.

When the power recovery mode transition flag ECO-FLG is not a value 1 (value 0) in step S1402, that is, when the power recovery mode does not shift to the power saving mode, the normal power suppression volume setting process is performed (step S1404). .. In this normal power suppression volume setting process, the master volume value for adjusting the volume of the output channel specified in the sound command data constituting the sound generation schedule data is forcibly changed to the power suppression master volume value. Change to.

Briefly explaining the value set as the master volume value for power suppression, as shown in FIG. 70A, the peripheral control MPU4150a has steps 0 to 7 as the horizontal axis as the power consumption suppression step, and sounds. Ratio to the master volume value for adjusting the volume of the output channel specified in the command data (hereinafter referred to as "master volume value specified in the sound command data") (that is, as a master volume value for power consumption suppression) When the power consumption suppression stage is stage 0 or stage 1, that is, when the power consumption suppression stage acquired in step S1400 is stage 0 or stage 1, the master volume for power suppression is set on the vertical axis. As a value, 100% volume is set with respect to the master volume value specified by the sound command data (in other words, the volume itself of the master volume value specified by the sound command data as the master volume value for power suppression), and the power consumption suppression stage is set. When the stage 2 or stage 3, that is, when the power consumption suppression stage acquired in step S1400 is stage 2 or stage 3, the master volume value for power suppression is 90% of the master volume value specified in the sound command data. When the volume is set and the power consumption suppression stage is stage 4, that is, when the power consumption suppression stage acquired in step S1400 is stage 4, the master volume value specified in the sound command data is used as the master volume value for power suppression. When the volume of 80% is set and the power consumption suppression stage is stage 5, that is, when the power consumption suppression stage acquired in step S1400 is stage 5, the master of the sound command data regulation is used as the master volume value for power suppression. A sound command is set as a master volume value for power suppression when a volume of 70% is set with respect to the volume value and the power consumption suppression stage is stage 6, that is, when the power consumption suppression stage acquired in step S1400 is stage 6. A master volume for power suppression is set at a volume of 60% of the master volume value specified in the data, and when the power consumption suppression stage is stage 7, that is, when the power consumption suppression stage acquired in step S1400 is stage 7. As a value, set a volume of 50% with respect to the master volume value specified in the sound command data.

The multiple output channels of the built-in sound source of the built-in sound source VDP4160a include the sound data of the production sound incorporated in the track to be used and the production sound incorporated in the track to be used among the multiple tracks in the built-in sound source of the built-in sound source VDP4160a. The sub-volume value for adjusting the volume is combined, and the volume of the combined effect sound is actually obtained from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. It is amplified to the master volume value for power suppression, which is the flowing volume, and the amplified production sound is serialized and output as audio data to the audio data transmission IC 4160c. That is, when the normal power suppression volume setting process is performed, the production content by the production sound does not change, but the volume of the production sound is the master volume specified by the sound command data in the power consumption suppression stage from stage 0 to stage 1. While it becomes the volume of the value itself, the volume set as the master volume value for power suppression becomes almost smaller as the power consumption suppression stage progresses from stage 2 to stage 7, so that the volume of the effect sound is produced. Is getting smaller.

Returning to FIG. 69, following step S1404, the normal power suppression brightness setting process is performed (step S1406). In this normal power suppression brightness setting process, the brightness of various LEDs in the light emission mode of various LEDs defined in the light emission data constituting the light emission mode generation schedule data is forcibly changed and set to the brightness for power suppression.

Briefly explaining the brightness set as the brightness for power suppression, as shown in FIG. 70 (b), the peripheral control MPU4150a has steps 0 to 7 as the horizontal axis as the power consumption suppression step, and the light emission data When the ratio (that is, the brightness set as the brightness for power suppression) to the brightness of various LEDs (hereinafter, referred to as "brightness specified for light emission data") in the specified light emitting mode of the various LEDs is taken as the vertical axis When the power consumption suppression stage is one of the stages 0, stage 1, stage 2, stage 3, and stage 4, that is, the power consumption suppression stage acquired in step S1400 is stage 0, stage 1, stage 2, When one of the stages 3 and 4 is performed, the brightness for power suppression is 100% of the brightness specified for the light emission data (in other words, the brightness itself specified for the light emission data as the brightness for power suppression). When the power consumption suppression stage is stage 5, that is, when the power consumption suppression stage acquired in step S1400 is stage 5, the brightness for power suppression is 70% of the brightness specified in the light emission data. When the power consumption suppression stage is stage 6, that is, when the power consumption suppression stage acquired in step S1400 is stage 6, the brightness of 60% of the brightness specified in the light emission data is set as the brightness for power suppression. Then, when the power consumption suppression stage is stage 7, that is, when the power consumption suppression stage acquired in step S1400 is stage 7, the brightness of 50% of the brightness specified in the light emission data is set as the brightness for power suppression. ..

When the normal brightness setting process for power consumption is performed, the effect contents depending on the light emitting mode of the LED for light emitting decoration provided in the door frame 5 and the various LEDs mounted on the various decorative boards provided in the game board 4 do not change, but various The brightness of the LED becomes the brightness specified by the light emission data in the power consumption suppression stage from stage 0 to stage 4, and is set as the brightness for power suppression as the power consumption suppression stage progresses from stage 5 to stage 7. Since the brightness is reduced, the brightness of various LEDs is reduced.

Following step S1406, the power saving mode transition notification LED 4150k shown in FIG. 15 is set to the non-power saving notification mode (step S1407a). As described above, as the power saving mode transition notification LED 4150k, a high-intensity single color that emits green light is adopted. The non-power saving notification mode notifies a staff member such as a clerk in the hall that the mode does not shift to the power saving mode at the time of power recovery, and is in a lit state (that is, a lit state that emits green light). Since the non-power saving notification mode (that is, the lighting state of emitting green light) of the power saving mode transition notification LED 4150k set in step S1407a is configured to be directly defined (set) each time this routine is executed. The difference is that the light emitting modes of the various LEDs described above are configured to be defined in the light emitting data constituting the light emitting mode generation schedule data. A clerk such as a clerk in the hall inserts a key into the cylinder lock 1010 of the lock device 1000 shown in FIGS. 1 and 5 and rotates to release the closed state of the main body frame 3 with respect to the outer frame 2 to release the outer frame. By opening the main body frame 3 with respect to 2 and visually observing the non-power saving mode (that is, the lighting state in which light is emitted in green) of the power saving mode transition notification LED 4150k, it is understood that the power saving mode does not shift to the power saving mode. can do.

Following step S1407a, the output of the power saving mode information output signal is set to stop (step S1407b), and this routine ends. As described above, the power saving mode information output signal transmits the transition state to the power saving mode at the time of power recovery to the hall computer via the external terminal board 784 shown in FIG. 15, and the power saving mode at the time of power recovery in step S1402. When the transition to is not performed, the power saving mode information output signal is set to no output in step S1407b.

On the other hand, when the power recovery mode transition flag ECO-FLG is a value 1 (not a value 0) in step S1402, that is, when the power recovery mode shifts to the power recovery mode, the power recovery mode timer has reached the upper limit time. Whether or not it is determined (step S1408). As described above, the power saving mode timer at the time of power recovery measures the power saving mode state maintenance period at the time of power recovery in which the pachinko gaming machine 1 is maintained in the state of being activated as the power saving mode at the time of power recovery. In, 5 minutes is set as the power saving mode state maintenance period at the time of power recovery. The upper limit time used for the determination is 5 minutes of the power saving mode state maintenance period at the time of power recovery.

When the power recovery mode timer has not reached the upper limit time in step S1408, that is, when the power recovery mode timer has not reached 5 minutes of the power recovery mode state maintenance period, the power recovery power suppression volume. Perform the setting process (step S1410). In this power recovery volume setting process, the volume of the output channel defined in the sound command data constituting the sound generation schedule data is set in the same manner as the normal power suppression volume setting process in step S1404 described above. Although the master volume value for adjustment is forcibly changed to the master volume value for power suppression, the volume is always set to 50% of the master volume value specified in the sound command data as the master volume value for power suppression. It differs in that it does. That is, in the power recovery volume setting process, the power suppression master volume value set when the power consumption suppression stage is stage 7 in the normal power suppression volume setting process is always set. ing.

When the power recovery volume setting process is performed, the production content of the production sound does not change, but the volume of the production sound is set to the lowest level of the power consumption suppression stage of stage 7. (In other words, the volume of the production sound is set so that the power consumption suppression stage is stage 7, which is the smallest power consumption).

Following step S1410, the brightness setting process for power suppression at the time of power recovery is performed (step S1412). In this brightness setting process for power suppression during power recovery, similarly to the brightness setting process for normal power suppression in step S1406 described above, in the light emission modes of various LEDs defined in the light emission data constituting the schedule data for generating the light emission mode. Although the brightness of various LEDs is forcibly changed and set to the brightness for power suppression, the difference is that the brightness for power suppression is always set to 50% of the brightness specified in the emission data. That is, in the power recovery brightness setting process, the power suppression brightness set when the power consumption suppression stage is stage 7 in the normal power suppression brightness setting process is always set. ..

When the brightness setting process for suppressing the power consumption at the time of power recovery is performed, the effect contents depending on the light emitting mode of the LED for light emitting decoration provided in the door frame 5 and the various LEDs mounted on the various decorative boards provided in the game board 4 do not change. The brightness of various LEDs is set to be the smallest in the power consumption suppression stage of stage 7 (in other words, the brightness of various LEDs is the smallest in the power consumption suppression stage of stage 7). Things are set up).

Following step S1412, the power saving mode transition notification LED 4150k is set to the power saving notification mode (step S1413a). The power saving notification mode informs a staff member such as a clerk in the hall that the mode will be changed to the power saving mode at the time of power recovery, and the light is turned off. Since the power saving mode transition notification LED 4150k set in step S1413a is configured so that the power saving notification mode (that is, the off state) is directly defined (set) each time this routine is executed, the various LEDs described above are used. Is different in that the light emitting mode is configured to be defined in the light emitting data constituting the schedule data for generating the light emitting mode. A clerk such as a clerk in the hall inserts a key into the cylinder lock 1010 of the lock device 1000 shown in FIGS. 1 and 5 and rotates to release the closed state of the main body frame 3 with respect to the outer frame 2 to release the outer frame. It is possible to grasp that the light emitting mode of the power saving mode transition notification LED 4150k has shifted to the power saving mode at the time of power recovery by visually observing the power saving notification mode (that is, the off state) by opening the main body frame 3 with respect to 2. can. In the present embodiment, as the light emitting mode of the power saving mode transition notification LED 4150k, the lighting state is set when the power saving mode is not shifted to the power saving mode, whereas the lighting state is set when the power saving mode transitioning mode is shifted. However, this is because it is necessary to suppress the power consumption in the power saving mode at the time of power recovery. Therefore, when the power saving mode is not shifted to the power saving mode, the power saving mode transition notification LED 4150k is turned on and the power is restored. When shifting to the power saving mode, the power saving mode transition notification LED 4150k is turned off.

Following step S1413a, the output of the power saving mode information output signal is set to start (step S1413b), and this routine ends. When shifting to the power saving mode during power recovery in step S1402 If the power saving mode information output signal is set to be output in step S1413b, the power saving mode information output signal is set to the upper limit in step S1408 every time this routine is executed. The state in which the power saving mode information output signal is output is maintained in step S1413b until the time is reached, that is, until the power saving mode timer reaches 5 minutes of the power saving mode state maintenance period at the time of power recovery, and the power saving mode information output signal is maintained. Is output to the external terminal plate 784 and transmitted to the hall computer via the external terminal plate 784, and the hall computer knows that the pachinko game machine 1 has shifted to the power saving mode at the time of power recovery.

On the other hand, when the power recovery mode timer reaches the upper limit time in step S1408, that is, when the power recovery mode timer reaches 5 minutes of the power recovery mode state maintenance period, the power recovery power saving motor In order to end the transition of the power recovery mode, the power saving mode transition flag ECO-FLG at the time of power recovery is set to a value 0 (step S1414), the power saving mode timer stop processing at the time of power recovery is performed (step S1416), and this routine is terminated. The power saving mode timer stop processing at the time of power recovery only performs the processing of stopping the power saving mode timer at the time of power recovery, and does not include the processing of initializing (resetting) the power saving mode timer at the time of power recovery. This means that even if the value of the power saving mode transition flag ECO-FLG at the time of power recovery changes from a value 0 to a value 1 for some reason (for example, under the influence of noise) and the determination in step S1402 proceeds to step S1408. , In the power recovery time power saving mode timer stop processing, the power recovery time power saving mode timer is already stopped at 5 minutes of the power recovery time power saving mode state maintenance period, which is the upper limit time, so that the power recovery time power saving mode timer is the upper limit time. By maintaining the state of reaching 5 minutes of the power saving mode state maintenance period at the time of power recovery, the determination of step S1408 always proceeds to the process of step S1414, and the power saving mode transition flag at the time of power recovery in the process of step S1414. This is so that the value of ECO-FLG can be forcibly returned to the normal value 0. In the initial setting process of step S1000 in the peripheral control unit power-on processing shown in FIG. 63, the power saving mode timer at the time of power recovery is initialized (reset).

Further, in step S1408, the power saving mode transition timer at the time of power recovery reaches the upper limit time, and in step S1414, the value 0 is set to the power saving mode transition flag ECO-FLG at the time of power recovery in order to end the transition of the power saving motor at the time of power recovery. As a result, when this routine is executed again, the process of step S1404 to step 1407b is sequentially proceeded by the determination of step S1402, and the output state of the power saving mode information output signal is stopped in step S1407b. That is, when the power saving mode timer at the time of power recovery reaches the upper limit time in step S1408, the output state of the power saving mode information output signal is maintained in the stopped state every time this routine is executed again, and the power saving mode is maintained. The state in which the information output signal is not output to the external terminal board 784 is transmitted to the hall computer via the external terminal board 784, and the pachinko gaming machine 1 has finished the state of shifting to the power saving mode at the time of power recovery in the hall computer. Will be grasped. When the power is restored, if the determination in step S1402 does not shift to the power saving mode at the time of power recovery, the state in which the power saving mode information output signal is not output to the external terminal board 784 in step S1407b is transmitted to the hall computer via the external terminal board 784. In the hall computer, it is understood that the pachinko gaming machine 1 is not in the state of not shifting to the power saving mode at the time of power recovery.

As described above, in the power saving mode transition determination process at the time of power recovery in step S1004 in the peripheral control unit steady processing of the peripheral control unit power-on processing shown in FIG. For the setting to reduce the volume of the effect sound flowing from the speaker housed in the provided speaker box 820 and the speaker 130 provided in the door frame 5, the LED for light emission decoration provided in the door frame 5 and various decorative boards provided in the game board 4. When it is determined whether or not to shift to the power saving mode at the time of power recovery, which is set to reduce the brightness of various mounted LEDs, and the result of this determination is that the mode does not shift to the power saving mode at the time of power recovery, the above-mentioned In step S1400, the value of the power consumption suppression signal set by the power consumption suppression stage determination circuit 855dab can be acquired, and the power consumption suppression stage can be specified from the acquired value. According to the power consumption in the machine 1, the power consumption suppression stage is specified from the stages 0 to 7, and the volume setting process for normal power consumption suppression in step S1404 described above corresponding to each stage. The power suppression master volume value forcibly changed and set in step 1 and the power suppression brightness forcibly changed and set in the normal power consumption suppression brightness setting process in step S1406 described above corresponding to each step are small. The progress of the production can be controlled by the power consumption. Therefore, it is possible to prevent a power failure from occurring due to the power consumption of the pachinko gaming machine 1 itself. Further, it is possible to prevent the game from being interrupted due to a power failure due to the power consumption of the pachinko gaming machine 1 itself.

On the other hand, in the power saving mode transition determination process at the time of power recovery in step S1004 in the peripheral control unit steady processing of the peripheral control unit power-on processing shown in FIG. 63, the power is provided on the main body frame 3 at the time of power recovery of the pachinko gaming machine 1. It is mounted on the speaker housed in the speaker box 820 and the setting to reduce the volume of the effect sound flowing from the speaker 130 provided in the door frame 5, the LED for light emission decoration provided in the door frame 5, and various decorative boards provided in the game board 4. If it is determined whether or not to shift to the power saving mode at the time of power recovery, and the result of this determination is to shift to the power saving mode at the time of power recovery, the steps described above are performed. The master volume value for power suppression that is forcibly changed and set in the power recovery volume setting process of S1410 (that is, it is set when the power consumption suppression stage is stage 7 in the normal power suppression volume setting process. Power suppression master volume value) and power suppression brightness forcibly changed and set in the power recovery power suppression brightness setting process in step S1412 described above (that is, power consumption in the normal power suppression brightness setting process). The power saving mode state is maintained when the power saving mode timer is the upper limit time. It can be controlled for up to 5 minutes of the period. As a result, the power is not turned off due to a power outage or a momentary power failure due to the power consumption of the pachinko gaming machine 1, for example, when a power outage or a momentary power failure due to a lightning strike occurs and the pachinko gaming machine 1 is turned off. In addition, when the power of the pachinko game machine 1 is cut off due to a power outage of the power supplied to the hall or an unstable power supply to the hall, and a staff member such as a clerk of the hall goes to the pachinko game machine 1. Even when the power is cut off and the power is turned off, the power status consumed by the pachinko gaming machine 1 at the time of the power off (immediately before the power is turned off) can be grasped at the time of power recovery. In step 7, the pachinko gaming machine 1 can be started in a state where the production can proceed with the smallest power consumption of step 7. Therefore, even when the power is restored, it is possible to prevent a power failure due to the power consumption of the pachinko gaming machine 1 itself. Further, it is possible to prevent the game from being interrupted due to a power failure due to the power consumption of the pachinko gaming machine 1 itself.

Further, in the present embodiment, when the normal power suppression volume setting process of step S1404 described above is performed, the effect content of the effect sound does not change, but the volume of the effect sound is such that the power consumption suppression stage is from stage 0. Up to 1, the volume becomes the volume of the master volume value itself specified by the sound command data, while the volume set as the master volume value for power suppression becomes almost smaller as the power consumption suppression stage progresses from stage 2 to stage 7. Therefore, the volume of the effect sound is reduced, and when the above-described normal power consumption suppression brightness setting process of step S1406 is performed, the LED for light emission decoration provided in the door frame 5 and various decorations provided in the game board 4 are provided. Although the effect content does not change depending on the light emission mode of the various LEDs mounted on the board, the brightness of the various LEDs is the brightness specified by the light emission data in the power consumption suppression stages from stage 0 to stage 4, while the power consumption suppression stage is As the process progresses from step 5 to step 7, the brightness set as the brightness for power consumption becomes smaller, so that the brightness of various LEDs becomes smaller. In the present embodiment, when the power consumption suppression stage proceeds to the stage 2, the volume of the effect sound is controlled to be smaller than the brightness of the various LEDs. This is because multiple types of pachinko gaming machines are installed in the hall and emit various production sounds at high volumes, so even if the volume of the production sounds is reduced, the players will not notice the production sounds. It is possible to suppress the power consumed by the pachinko gaming machine 1 by reducing the volume of the effect sound without causing a decrease in the player's motivation to play due to the decrease in the volume of the pachinko machine.

[17-1-8. LOCKN signal history creation process]
Next, the LOCKN signal history creation process executed as one of the drawing state information acquisition processes in step S1110 in the peripheral control unit 1 ms timer interrupt process shown in FIG. 65 will be described. In this LOCKN signal history creation process, the history of the LOCKN signal output from the LOCKN terminal of the upper plate side liquid crystal receiver ICSDIC0 provided in the touch panel drive board 450 shown in FIG. 35 is created. As described above, the LOCKN signal has abnormal drawing data received by the upper plate side liquid crystal receiver ICSDIC0 provided on the touch panel drive board 450 from the upper plate side liquid crystal transmitter IC4160d provided on the peripheral control board 4140 shown in FIG. If it is determined that the data is data, it is a signal to be output to convey that fact. Specifically, the transmitter IC 4160d for the upper plate side liquid crystal provided in the peripheral control board 4140 and the upper plate side liquid crystal provided in the touch panel drive board 450. This is a signal output to request transmission of a predetermined data pattern (SYNC pattern) for confirming (recovering) the connection between the receiver ICSDIC0 and the connection, that is, between the transmitter and the receiver.

When the LOCKN signal history creation process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 15 becomes the peripheral control RAM 4150a externally attached to the peripheral control MPU 4150a shown in FIG. The LOCKN signal detection history information LOCKN-HIST is read from the drawing state information acquisition storage area 4150 ack of the above (step S1500). This LOCKN signal detection history information LOCKN-HIST stores 1 byte (8 bits: most significant bit B7, B6, B5, B4, B3, B2, B1, least significant bit B0, "B" represents a bit). The history of the LOCKN signal output from the LOCKN terminal of the upper plate side liquid crystal receiver ICSDIC0 provided in the touch panel drive board 450 has a capacity and is stored in the drawing state information acquisition storage area 4150 kk as the LOCKN signal detection history information LOCKN-HIST. Has been done.

Following step S1500, it is determined whether or not there is a LOCKN signal output from the LOCKN terminal of the upper plate side liquid crystal receiver ICSDIC0 provided on the touch panel drive board 450 (step S1502). In this determination, when there is a LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0, the upper plate side liquid crystal receiver ICSDIC0 determines that the drawing data received from the upper plate side liquid crystal transmitter IC4160d is abnormal data. Requests transmission of a predetermined data pattern (SYNC pattern) for confirming (recovering) the connection between the upper plate side liquid crystal transmitter IC4160d and the upper plate side liquid crystal receiver ICSDIC0, that is, the connection between the transmitter and the receiver. On the other hand, when there is no LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0, the drawing data received by the upper plate side liquid crystal receiver ICSDIC0 from the upper plate side liquid crystal transmitter IC4160d is not abnormal data (normal). Data), and the predetermined data for confirming (recovering) the connection between the upper plate side liquid crystal transmitter IC4160d and the upper plate side liquid crystal receiver ICSDIC0, that is, the connection between the transmitter and the receiver. It is determined that the pattern (SYNC pattern) is not requested to be transmitted.

When there is a LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0 in step S1502, the LOCKN signal detection history information is shifted (step S1504). In this shift processing of the LOCKN signal detection history information, when there is a LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0, the LOCKN signal detection history information LOCKN-HIST read in step S1500 is set to the most significant bit B7 ← B6, B6 ← B5, B5 ← B4, B4 ← B3, B3 ← B2, B2 ← B1, B1 ← least significant bit B0, and so on, shifting from the least significant bit B0 to the most significant bit B7 one bit at a time.

When the LOCKN signal detection history information LOCKN-HIST is shifted in step S1504, the value 1 is set in the least significant bit B0 of the LOCKN signal detection history information LOCKN-HIST (step S1506), and this routine is terminated.

On the other hand, when there is no LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0 in step S1502, the LOCKN signal detection history information is shifted (step S1508). In this shift processing of the LOCKN signal detection history information, the same processing as the shift processing of the LOCKN signal detection history information in step S1504 is performed, and when there is no LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0, the LOCKN read in step S1500 is performed. The signal detection history information LOCKN-HIST is set to the most significant bit B7 ← B6, B6 ← B5, B5 ← B4, B4 ← B3, B3 ← B2, B2 ← B1, B1 ← least significant bit B0, and so on. Shifts bit by bit from to the most significant bit B7.

When the LOCKN signal detection history information LOCKN-HIST is shifted in step S1508, the value 0 is set in the least significant bit B0 of the LOCKN signal detection history information LOCKN-HIST (step S1510), and this routine is terminated.

In this way, each time this LOCKN signal history creation process is executed, the LOCKN signal detection history information LOCKN-HIST is shifted by one bit from the least significant bit B0 toward the most significant bit B7, and then to the least significant bit B0. Since the value 1 or the value 0 is set, the history of the LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0 can be created.

[17-1-9. Connection failure judgment processing]
Next, a connection failure determination process to be executed as one process of the warning process in step S1024 in the peripheral control unit steady process of the peripheral control unit power-on processing shown in FIG. 63 will be described. In this connection failure determination process, the upper plate side liquid crystal provided in the peripheral control board 4140 is based on the history of the LOCKN signal output from the LOCKN terminal of the upper plate side liquid crystal receiver ICSDIC0 provided in the touch panel drive board 450 shown in FIG. It is determined whether or not there is a problem between the connection between the transmitter IC 4160d and the LCD receiver ICSDIC0 on the upper plate side provided in the touch panel drive board 450, that is, the connection between the transmitter and the receiver.

When the connection failure determination process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 15 becomes the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. The LOCKN signal detection history information LOCKN-HIST is read from the drawing state information acquisition storage area 4150 ack (step S1520). As described above, the LOCKN signal detection history information LOCKN-HIST stores the history of the LOCKN signal output from the LOCKN terminal of the upper plate side liquid crystal receiver ICSDIC0 provided in the touch panel drive substrate 450. As described above, the LOCKN signal indicates that the drawing data received by the upper plate side liquid crystal receiver ICSDIC0 provided on the touch panel drive board 450 from the upper plate side liquid crystal transmitter IC4160d provided on the peripheral control board 4140 is abnormal data. When it is determined, it is a signal to be output to convey that fact. Specifically, the transmitter IC4160d for the upper plate side liquid crystal provided in the peripheral control board 4140, the receiver ICSDIC0 for the upper plate side liquid crystal provided in the touch panel drive board 450, and the like. This is a signal output to request transmission of a predetermined data pattern (SYNC pattern) for confirming (recovering) the connection between the connections of the transmitter and the receiver.

Following step S1520, it is determined whether or not there is a LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0 (step S1522). This determination determines whether or not the LOCKN signal detection history information LOCKN-HIST read in step S1520 matches the connection confirmation determination value. This connection confirmation determination value is stored in advance in the peripheral control ROM 4150b shown in FIG. 15, and in the present embodiment, it is "00001111B (" B "represents a bit)", and the upper 4 bits B7 to B4. Is a value 0, and B3 to B0 of the lower 4 bits are a value 1. In the determination in step S1522, it is determined whether or not the lower 4 bits B3 to B0 of the LOCKN signal detection history information LOCKN-HIST and the lower 4 bits B3 to B0 of the connection confirmation determination value match.

In step S1522, when the lower 4 bits B3 to B0 of the LOCKN signal detection history information LOCKN-HIST read in step S1520 and the lower 4 bits B3 to B0 of the connection confirmation determination value do not match, the peripheral control board 4140 is provided. It is determined that there is no problem in the connection between the transmitter IC4160d for the upper plate side liquid crystal and the receiver ICSDIC0 for the upper plate side liquid crystal provided in the touch panel drive board 450, that is, the connection between the transmitter and the receiver has not occurred. And exit this routine as it is.

On the other hand, in step S1522, when the lower 4 bits B3 to B0 of the LOCKN signal detection history information LOCKN-HIST read in step S1520 and the lower 4 bits B3 to B0 of the connection confirmation determination value match, the peripheral control board 4140 It is said that there is a problem in the connection between the upper plate side liquid crystal transmitter IC4160d provided in the above and the upper plate side liquid crystal receiver ICSDIC0 provided in the touch panel drive board 450, that is, the connection between the transmitter and the receiver. The determination is made and the value 1 is added to the communication check counter CC-CNT (increment, step S1524). The communication check counter CC-CNT counts up the number of times it is determined in step S1522 that the connection between the transmitter and the receiver is defective each time this routine is executed. (Counting the cumulative number of times). The communication check counter CC-CNT is set to a value of 0 and reset when the pachinko gaming machine 1 is turned on, but it is not reset due to a momentary power failure or a power failure, and is restored. It is designed to be restored to the value of the communication check counter CC-CNT immediately before the moment or power failure during power failure.

Following step S1524, it is determined whether or not the value of the communication check counter CC-CNT is smaller than the cumulative number upper limit value CC-LMT (step S1526). In this determination, when the value of the communication check counter CC-CNT is smaller than the cumulative number upper limit CC-LMT, the cumulative number of times it is determined that the connection between the transmitter and the receiver is defective is the cumulative number of times. When it is determined that the upper limit value CC-LMT has not been reached, but the value of the communication check counter CC-CNT is not smaller (larger) than the cumulative number upper limit value CC-LMT, a problem occurs in the connection between the transmitter and the receiver. It is determined that the cumulative number of times determined to be in this state has reached the cumulative number upper limit value CC-LMT.

When the value of the communication check counter CC-CNT is smaller than the cumulative number upper limit value CC-LMT in step S1526, that is, the cumulative number of times it is determined that the connection between the transmitter and the receiver is defective is the cumulative number of times. When the upper limit value CC-LMT has not been reached, the communication error flag CC-FLG is set to a value 0 (step S1528), and this routine is terminated. On the other hand, in step S1526, it is determined that the value of the communication check counter CC-CNT is not smaller (larger) than the cumulative number upper limit value CC-LMT, that is, a problem has occurred in the connection between the transmitter and the receiver. When the cumulative number of times has reached the cumulative number upper limit value CC-LMT, the value 1 is set in the communication error flag CC-FLG (step S1530), and this routine is terminated. The communication error flag CC-FLG is the connection between the transmitter and the receiver when the cumulative number of times it is determined that the connection between the transmitter and the receiver is defective reaches the cumulative number upper limit CC-LMT. It is a flag indicating whether or not a problem has definitely occurred. When the connection between the transmitter and the receiver is definitely defective, the value is 1, and the connection between the transmitter and the receiver has a problem. When the cumulative number of times determined to be in the state of being in the state does not reach the cumulative number upper limit value CC-LMT, the value is set to 0, respectively. The communication abnormality flag CC-FLG is set to a value of 0 and reset when the pachinko gaming machine 1 is turned on, but it is not reset due to a momentary power failure or a power failure, and is restored. It is designed to be restored to the value of the communication abnormality flag CC-FLG immediately before the moment or power failure during power failure.

[17-1-10. Connection recovery process]
Next, a connection recovery process to be executed as one process of the warning process in step S1024 in the peripheral control unit steady process of the peripheral control unit power-on processing shown in FIG. 63 will be described. This connection recovery process is executed following the connection failure determination process shown in FIG. 72, and includes the transmitter IC4160d for the upper plate side liquid crystal provided on the peripheral control board 4140 and the receiver ICSDIC0 for the upper plate side liquid crystal provided on the touch panel drive board 450. Outputs a predetermined data pattern (SYNC pattern) to confirm (recover) the connection between the transmitter and the receiver, while the connection between the transmitter and the receiver is abnormal. Notify that.

When the connection recovery process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 15 is in the peripheral control unit steady processing of the peripheral control unit power-on processing shown in FIG. 63, as shown in FIG. In the scheduler update process of step S1020, it is determined whether or not the screen generation schedule data is being activated among the various schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. 16 (step). S1540). In this determination, in the scheduler update process, among the screen data arranged in the time series constituting the screen generation schedule data, the number of the screen data from the first screen data is to be output to the sound source built-in VDP4160a. To determine if the pointer has been updated. In other words, in the scheduler update process, when the pointer is being updated, the effect is proceeding along the screen generation schedule data, so it is determined that the screen generation schedule data is running, while the screen generation schedule. When the effect is completed according to the data and all the pointer updates are completed, it is determined that the screen generation schedule data has not been started. In this determination, a period during which the start-up screen when the pachinko gaming machine 1 is turned on is displayed on the liquid crystal display device 1900 on the game board side, or a demonstration is performed by the liquid crystal display device 1900 on the game board side while waiting for customers. It is possible to determine whether or not the pachinko machine is in the operating period based on the screen generation schedule data, and the startup screen when the power of the pachinko game machine 1 is turned on is displayed on the liquid crystal display device 1900 on the game board side. During the period of waiting for customers or during the period of demonstrating with the liquid crystal display device 1900 on the game board side, the process proceeds to step S1542, which will be described later, while the start-up screen when the pachinko game machine 1 is turned on is displayed. When it is not the period when it is displayed on the liquid crystal display device 1900 on the game board side or the period when it is in the waiting state for customers and the demonstration is performed by the liquid crystal display device 1900 on the game board side (when it is just waiting for customers). Is supposed to end this routine as it is.

When the production is proceeding according to the screen generation schedule data in step S1540, that is, when the screen generation schedule data is running, this routine is terminated as it is, while the screen generation schedule data is followed in step S1540. When the production is completed and all the pointer updates are completed, that is, when the screen generation schedule data is not started, it is determined whether or not the value of the communication check counter CC-CNT is not 0 (step). S1542). As described above, this communication check counter CC-CNT is used for the upper plate side liquid crystal provided in the peripheral control board 4140 in the determination of step S1522 in each time the connection failure determination process shown in FIG. 72 is executed. The number of times it is determined that there is a problem in the connection between the transmitter IC 4160d and the upper plate side liquid crystal receiver ICSDIC0 provided in the touch panel drive board 450, that is, the connection between the transmitter and the receiver is counted up. (Counting the cumulative number of times). In this determination, it is determined whether or not the number of times it is determined that the connection between the transmitter and the receiver has a problem has occurred even once.

When the value of the communication check counter CC-CNT is 0 in step S1542, that is, when it is determined that there is a problem in the connection between the transmitter and the receiver, this is the case as it is. While terminating the routine, even once it is determined in step S1542 that the value of the communication check counter CC-CNT is not 0, that is, the connection between the transmitter and the receiver is defective. If so, it is determined whether or not the value of the communication abnormality flag CC-FLG is 0 (step S1544). As described above, the communication abnormality flag CC-FLG reaches the cumulative number upper limit CC-LMT when the cumulative number of times it is determined that the connection between the transmitter and the receiver has a problem has reached the transmitter and the transmitter. It is a flag indicating whether or not the connection between the receiver and the receiver is definitely defective. When the connection between the transmitter and the receiver is definitely defective, the value is 1, between the transmitter and the receiver. When the cumulative number of times it is determined that a problem has occurred in the connection of the above has not reached the cumulative number upper limit value CC-LMT, the value is set to 0, respectively.

When the value of the communication abnormality flag CC-FLG is 0 in step S1544, that is, the cumulative number of times it is determined that a problem has occurred in the connection between the transmitter and the receiver is the cumulative number upper limit value CC-LMT. When the value has not been reached, the SYNC pattern output process is performed (step S1546), and this routine is terminated. In this SYNC pattern output processing, the peripheral control MPU 4150a outputs a connection confirmation signal to the INIT terminal of the upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140, so that the peripheral control board 4140 is provided for the upper plate side liquid crystal. The transmitter IC 4160d outputs a predetermined data pattern (SYNC pattern) to the upper plate side liquid crystal receiver ICSDIC0 provided on the touch panel drive board 450. This predetermined data pattern (SYNC pattern) is stored in advance in the upper plate side liquid crystal transmitter IC4160d and is output to the upper plate side liquid crystal receiver ICSDIC0, and is used for the upper plate side liquid crystal. It restores the connection between the transmitter IC 4160d and the upper plate side liquid crystal receiver ICSDIC0, that is, the connection between the transmitter and the receiver.

On the other hand, when the value of the communication error flag CC-FLG is not 0 (value 1) in step S1544, that is, when there is a certain problem in the connection between the transmitter and the receiver, the communication error display process is performed. Perform (step S1548) and end this routine. In this communication error display process, in order to convey that a problem has definitely occurred in the connection between the transmitter and the receiver, the display area of the liquid crystal display device 1900 on the game board side provided in the game board 4 shown in FIG. Performs the process of drawing on. For example, the message "There was a problem with the liquid crystal display device on the upper plate side. Please call a clerk." Is displayed in the display area of the liquid crystal display device 1900 on the game board side. Further, in the communication error display processing, the period during which the start screen when the power of the pachinko game machine 1 is turned on is displayed on the liquid crystal display device 1900 on the game board side, and the demonstration by the liquid crystal display device 1900 on the game board side in the waiting state for customers. During this period, the connection between the upper plate side liquid crystal transmitter IC4160d provided on the peripheral control board 4140 and the upper plate side liquid crystal receiver ICSDIC0 provided on the touch panel drive board 450, that is, the connection between the transmitter and the receiver. As an operation check request for the upper plate side liquid crystal display device 470, LOCKN signal output request data is sent from the serial I / O port for the touch panel drive board built in the peripheral control MPU 4150a in order to confirm whether or not a problem has occurred. The LCD receiver ICSDIC0 on the precision plate side outputs a LOCKN signal from the LOCKN terminal to the peripheral control MPU4150a as a response signal to the transmission of the LOCKN signal output request data, and when this LOCKN signal is not input, the transmitter and the receiver It is determined that a problem has occurred in the upper plate side liquid crystal display device 470 as a problem has occurred in the connection between the two, and a notification image (for example, "a problem has occurred in the upper plate side liquid crystal display device" to that effect. (Please call a clerk. ”) Performs the process of displaying in the display area of the liquid crystal display device 1900 on the game board side, and the notification sound (for example,“ There is a problem with the liquid crystal display device on the upper plate side. ” ) Repeatedly flows from the speakers 130, 222, 262 and the like provided on the door frame 5. At this time, the process of turning on all the LEDs for light emitting decoration provided in the door frame 5 and the various LEDs mounted on the various decorative boards provided in the game board 4 may be performed.

Next, the timing at which the peripheral control MPU 4150a outputs a connection confirmation signal to the INIT terminal of the upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140 shown in FIG. 17 will be described with reference to the timing chart of FIG. 74.

First, a decorative pattern that is variablely displayed in the display area of the game board side liquid crystal display device 1900 provided in the game board 4 shown in FIG. 8 will be briefly described. The variable display of the decorative symbol is executed by the stationary processing or the like, and the main control side of the main control board 4100 shown in FIG. 12 is the main control side of the main control side of the main control board 4100a shown in FIG. The result of the first special lottery drawn by accepting the game ball to the upper start port 2101 shown in FIG. 8 by the main process, the timer interrupt process on the main control side shown in FIG. 45, or the lower start port shown in FIG. When the result of the second special lottery drawn by accepting the game ball to 2102 is a "big hit", the number of repetitions (number of rounds) of the opening and closing operation of the big winning opening 2103 shown in FIG. 8 is from 1 round to 15 rounds. There are a total of 15 rounds, and in each round, when a game ball enters the large winning opening 2103 within a predetermined time (for example, 30 seconds) and the number of balls reaches a predetermined number (for example, 9 balls), that round. Is digested, and a predetermined number (for example, 15 balls) of game balls are paid out every time one game ball enters the large winning opening 2103.

The result of the first special lottery drawn by accepting the game ball to the upper starting port 2101 or the result of the second special lottery drawn by accepting the game ball to the lower starting port 2102 is a command from the main control board 4100. Based on this, the peripheral control unit 4150 of the peripheral control board 4140 controls the liquid crystal and the sound control unit 4160, so that the left decorative symbol is on the left side of the display area of the liquid crystal display device 1900 on the game board side, and the central decorative symbol is in the center. Then, the variable display of the right decorative symbol is started on the right side, and after a predetermined time elapses, the variable display of the left decorative symbol, the central decorative symbol, and the right decorative symbol is stopped, and the first special lottery result or the second special lottery result is displayed. The player can recognize the first special symbol or the first special symbol displayed on the upper special symbol display 1185 or the lower special symbol display 1186 of the function display unit 1180 shown in FIG. (Ii) The result of the first special lottery or the result of the second special lottery can be confirmed even in the special symbol. When the left decorative symbol, the central decorative symbol, and the right decorative symbol are displayed in a variable manner, the left decorative symbol, the central decorative symbol, and the right decorative symbol are translucent so that the background image can be visually recognized, and the left decorative symbol is displayed. The reels rotate from the upper left side to the lower left side of the area, the central decorative symbol from the upper center to the lower center of the display area, and the right decorative symbol from the upper right side to the lower right side of the display area. When the left decorative symbol, the central decorative symbol, and the right decorative symbol are stopped and displayed, they correspond to the left decorative symbol, the central decorative symbol, and the right decorative symbol that are stopped and displayed. The left decorative symbol, the central decorative symbol, and the right decorative symbol are opaque so that the background image at the position is difficult to see. As described above, the first special symbol or the second special symbol which is started and stopped by the variable display on the upper special symbol display 1185 or the lower special symbol display 1186 of the function display unit 1180 shown in FIG. 11 and the game board. The left decorative symbol, the central decorative symbol, and the right decorative symbol, which are displayed in a variable display start and stop display in the display area of the side liquid crystal display device 1900, are synchronized.

The peripheral control unit 4150 of the peripheral control board 4140 is the first special lottery result drawn by accepting the game ball to the upper starting port 2101 or the second special lottery drawn by accepting the game ball to the lower starting port 2102. When a command from the main control board 4100 for transmitting the result is received, the liquid crystal and the sound control unit 4160 are controlled based on the received command, so that the liquid crystal on the game board side shown in FIG. 8 is shown as shown in FIG. When the variable display of the left decorative symbol, the central decorative symbol, and the right decorative symbol is started in the display area of the display device 1900 (timing K0), the peripheral control unit steady processing of the peripheral control unit power-on processing shown in FIG. In the scheduler update process of step S1020 in step S1020, the first screen data among the screen data arranged in time series constituting the screen generation schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. Because the pointer is updated to indicate the number of screen data to be output to the VDP4160a with built-in sound source, that is, in the scheduler update process, when the pointer is updated, it is produced according to the screen generation schedule data. Is in progress, the screen generation schedule data is running, and while the screen generation schedule data is running, that is, the variable display of the left decorative symbol, the central decorative symbol, and the right decorative symbol is started. Until the stop display is displayed, even if the connection recovery process shown in FIG. 73 is executed in the warning process of step S1024 in the peripheral control unit steady process of the peripheral control unit power-on processing shown in FIG. At the determination of step S1540 in this connection recovery process, the routine is forcibly terminated as it is.

As a result, the communication check counter CC-CNT can be used until the variable display of the left decorative symbol, the central decorative symbol, and the right decorative symbol is started and stopped in the display area of the liquid crystal display device 1900 on the game board side. Even when the value is not 0, that is, between the connection between the upper plate side liquid crystal transmitter IC4160d provided on the peripheral control board 4140 and the upper plate side liquid crystal receiver ICSDIC0 provided on the touch panel drive board 450 (that is, the transmitter and the receiver). Even if it is determined that a problem has occurred in the connection between the transmitter and the receiver even once, the SYNC pattern output process in step S1546 in the connection recovery process is not performed, and the transmitter and the receiver The process of recovering the connection between the two is not performed, and the communication error display process of step S1548 in the connection recovery process is not performed. For example, in the display area of the liquid crystal display device 1900 on the game board side, "upper plate side" is displayed. Since the message "There was a problem with the liquid crystal display device. Please call a clerk." Is not displayed, it is necessary to inform that the drawing data received from the LCD transmitter IC4160d on the upper plate side is abnormal data. The LOCKN signal from the dish-side liquid crystal receiver ICSDIC0 is invalidated, and the upper-dish-side liquid crystal display device 470 displays an image based on the drawing data received by the upper-dish-side liquid crystal receiver ICSDIC0 from the upper-dish-side liquid crystal transmitter IC4160d. indicate.

When the variable display of the left decorative symbol, the central decorative symbol, and the right decorative symbol is started and stopped in the display area of the game board side liquid crystal display device 1900 (timing K1), the peripheral control unit power is turned on as shown in FIG. Peripheral control unit of time processing In the scheduler update process of step S1020 in the steady processing, the effect is completed according to the screen generation schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. Since all the updates have been completed, that is, while the screen generation schedule data has not been started and the screen generation schedule data has not been started in the scheduler update process, the power of the peripheral control unit shown in FIG. 63 is turned on. Peripheral control unit of time processing In the determination of step S1540 in the connection recovery processing shown in FIG. 73 executed as one processing of the warning processing in step S1024 in the steady processing, the process proceeds to the processing of step S1542 in the same processing, and the communication check counter CC- When the CNT value is 0, that is, when it has not been determined that the connection between the transmitter and the receiver has a problem even once, the routine is terminated as it is, while the communication check counter is used. When the value of CC-CNT is not 0, that is, when it is determined that the connection between the transmitter and the receiver has a problem even once, the process of step S1544 in the same process is performed. When the value of the communication error flag CC-FLG is 0, that is, the cumulative number of times it is determined that there is a problem in the connection between the transmitter and the receiver is set to the cumulative number upper limit value CC-LMT. If it has not reached, the process proceeds to step S1546 in the same process, the above-described SYNC pattern output process is performed, and the routine is terminated. On the other hand, when the value of the communication error flag CC-FLG is not 0 (value 1), That is, when there is a certain problem in the connection between the transmitter and the receiver, the process proceeds to the process of step S1548 in the same process, the above-mentioned communication error display process is performed, and the routine is terminated. In other words, while the left decorative symbol, the central decorative symbol, and the right decorative symbol are stopped and displayed in the display area of the liquid crystal display device 1900 on the game board side, the upper plate side liquid crystal transmitter IC4160d and the upper plate side liquid crystal receiver IC4160d. When there is a problem with the connection between the ICS DC0, that is, between the transmitter and the receiver even once, and there is a problem with the connection between the transmitter and the receiver. When the cumulative number of times determined to be present does not reach the cumulative number upper limit value CC-LMT, the SYNC pattern output process is always performed so that the connection between the upper plate side liquid crystal transmitter IC4160d and the upper plate side liquid crystal receiver ICSDIC0, In other words, while the process of recovering the connection between the transmitter and the receiver is performed, the cumulative number of times it is determined that the connection between the transmitter and the receiver is defective reaches the cumulative number upper limit CC-LMT. When (that is, there is definitely a problem in the connection between the transmitter and the receiver), the communication error display process is always performed, so that, for example, the display area of the liquid crystal display device 1900 on the game board side is displayed. A problem has occurred in the liquid crystal display device on the upper plate side. Please call a clerk. ”Is displayed and notified, and the drawing data received from the LCD transmitter IC4160d on the upper plate side is abnormal. The LOCKN signal from the LCD receiver ICSDIC0 on the upper plate side, which conveys that the data is data, is enabled.

In the display area of the liquid crystal display device 1900 on the game board side, the variable display of the left decorative symbol, the central decorative symbol, and the right decorative symbol is started and stopped, and the variable display of the left decorative symbol, the central decorative symbol, and the right decorative symbol is displayed again. During the interval period until the start of, the left decorative symbol, the central decorative symbol, and the right decorative symbol are stopped and displayed in the display area of the liquid crystal display device 1900 on the game board side. The LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0, which conveys that the drawing data received from the upper plate side liquid crystal transmitter IC 4160d is abnormal data, is enabled, and the upper plate side liquid crystal transmitter IC 4160d and the upper plate side liquid crystal are used. A state in which there is a problem in the connection between the receiver LCD0, that is, a state in which the connection between the transmitter and the receiver has occurred even once, and a state in which the connection between the transmitter and the receiver has a problem. When the cumulative number of times determined to be is not reaching the cumulative number upper limit value CC-LMT, the SYNC pattern output process is always performed to connect the upper plate side liquid crystal transmitter IC 4160d and the upper plate side liquid crystal receiver ICSDIC0. That is, while the process of recovering the connection between the transmitter and the receiver is performed, the cumulative number of times it is determined that the connection between the transmitter and the receiver is defective is set to the cumulative number upper limit CC-LMT. When it reaches (that is, there is definitely a problem in the connection between the transmitter and the receiver), the communication error display process is always performed so that, for example, the display area of the liquid crystal display device 1900 on the game board side is displayed. The process of notifying is performed by displaying the message "There was a problem with the liquid crystal display device on the upper plate side. Please call a clerk."

When the variable display of the left decorative symbol, the central decorative symbol, and the right decorative symbol is started again (timing K2), as described above, since the screen generation schedule data is activated, the left decorative symbol and the central decorative symbol are activated. , And until the right decorative symbol is stopped and displayed (timing K3), even when the value of the communication check counter CC-CNT is not 0, that is, for the upper plate side liquid crystal provided on the peripheral control board 4140. The number of times it is determined that a problem has occurred between the connection between the transmitter IC 4160d and the upper plate side liquid crystal receiver ICSDIC0 provided in the touch panel drive board 450 (that is, the connection between the transmitter and the receiver) is once. Even in such a case, the SYNC pattern output process of step S1546 in the connection recovery process is not performed, the process of recovering the connection between the transmitter and the receiver is not performed, and the step in the connection recovery process is performed. The communication error display process of S1548 is not performed, and for example, the message "There was a problem with the liquid crystal display device on the upper plate side. Please call a clerk." Is not displayed in the display area of the liquid crystal display device 1900 on the game board side. Therefore, the LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0, which conveys that the drawing data received from the upper plate side liquid crystal transmitter IC 4160d is abnormal data, is invalidated, and the upper plate side liquid crystal display device 470. Displays an image based on the drawing data received from the upper plate side liquid crystal receiver ICSDIC0 from the upper plate side liquid crystal transmitter IC4160d.

In this way, the variable display of the left decorative symbol, the central decorative symbol, and the right decorative symbol is started and stopped in the display area of the liquid crystal display device 1900 on the game board side, and the left decorative symbol, the central decorative symbol, and the right decorative symbol are displayed again. During the interval period until the variable display of the symbol is started, the LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0 that conveys that the drawing data received from the upper plate side liquid crystal transmitter IC4160d is abnormal data is enabled. On the other hand, until the variable display of the left decorative symbol, the central decorative symbol, and the right decorative symbol is started and stopped in the display area of the liquid crystal display device 1900 on the game board side, the upper plate side liquid crystal transmitter is displayed. The LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0, which conveys that the drawing data received from the IC4160d is abnormal data, is invalidated. This is the information that the player is most interested in the combination result of the left decorative symbol, the central decorative symbol, and the right decorative symbol being stopped and displayed in the display area of the liquid crystal display device 1900 on the game board side, which is beneficial to the player. Since the player can determine whether or not a jackpot game state in which is given is generated, the left decorative symbol, the central decorative symbol, and the right decorative symbol are variablely displayed in the display area of the liquid crystal display device 1900 on the game board side. Then, until the left decorative symbol, the central decorative symbol, and the right decorative symbol are stopped and displayed, the effect image drawn in the display area of the upper plate side liquid crystal display device 470 is disturbed correctly due to the influence of noise or the like. Even if it becomes impossible to draw, the left decorative symbol, the central decorative symbol, and the central decorative symbol are displayed in the display area of the liquid crystal display device 1900 on the game board side, instead of interrupting the production in the middle and recovering to the state where the drawing can be performed correctly. By stopping and displaying the decoration pattern on the right side, the drawing of the information most of interest to the player is completed.

In this respect, the period during which the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140 displays the start-up screen when the pachinko gaming machine 1 is turned on on the game board side liquid crystal display device 1900, or the customer waiting state. During the demonstration period using the liquid crystal display device 1900 on the game board side, the LOCKN signal output request data was sent from the built-in serial I / O port for the touch panel drive board to the differential circuit 4160e provided on the peripheral control board 4140. It is very different from the case of sending. This LOCKN signal output request data is used for a period during which the startup screen when the power of the pachinko game machine 1 is turned on is displayed on the liquid crystal display device 1900 on the game board side, or a demonstration by the liquid crystal display device 1900 on the game board side in a customer waiting state. During this period, the data is transmitted from the serial I / O port for the touch panel drive board built into the peripheral control MPU 4150a, and the upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140 and the touch panel drive board 450 Request to confirm the operation of the upper plate side liquid crystal display device 470 in order to confirm whether or not there is a problem in the connection between the upper plate side liquid crystal receiver ICSDIC0 and the connection between the transmitter and the receiver. Is sent as.

The LOCKN signal output request data, which is serial data output from the serial I / O port for the touch panel drive board built in the peripheral control MPU 4150a, is the difference between the positive signal and the negative signal in the differential circuit 4160e provided in the peripheral control board 4140. When activated, as described above, two signals differentiated into a positive signal and a negative signal in the differential circuit 4160e are input to the forced switching circuit 4160f provided in the peripheral control board 4140. When two signals differentiated into a plus signal and a minus signal are input in the differential circuit 4160e, the forced switching circuit 4160f is circuit-connected so as to transmit the two signals. Two signals are transmitted from the peripheral control board 4140 to the touch panel drive board 450 housed in the dish unit 300 of the door frame 5. Then, when the receiver ICSDIC0 for the upper plate side liquid crystal of the liquid crystal module circuit 450V provided in the touch panel drive board 450 determines that the two received signals are the LOCKN signal output request data from the serial I / O port for the touch panel drive board. In the first place, as described above, the LOCKN signal output request data has a structure different from that of the signal output from the upper plate side liquid crystal transmitter IC4160d, so that it is judged to be abnormal data, and the LOCKN signal is peripheral to the LOCKN signal. Output to the peripheral control MPU 4150a of the peripheral control unit 4150 of the control board 4140. As a result, the peripheral control MPU4150a has a problem with the touch panel drive board 450 because the connection between the transmitter and the receiver is not defective when the LOCKN signal is input as a response signal to the transmission of the LOCKN signal output request data. However, when the LOCKN signal is not input, it is determined that the touch panel drive board 450 has a problem because the connection between the transmitter and the receiver has a problem. Then, a notification image (for example, "A problem has occurred in the upper plate side liquid crystal display device. Please call a clerk.") Is sent to the game board side liquid crystal display device 1900 by controlling the VDP4160a with a built-in sound source. Along with the output, a notification sound (for example, "There is a problem with the liquid crystal display device on the upper plate side") is output to the audio data transmission IC4160c by controlling the VDP4160a with a built-in sound source. Notification sounds flow from the speakers 130, 222, 262 and the like provided in 5. As a result, the notification image displayed in the display area of the liquid crystal display device 1900 on the game board side and the notification sound repeatedly flowing from the speakers 130, 222, 262 and the like provided on the door frame 5 can be used for notification. It has become. At this time, all the LEDs for light emitting decoration provided in the door frame 5 and the various LEDs mounted on the various decorative boards provided in the game board 4 may be turned on.

In this way, when the peripheral control MPU 4150a of the peripheral control unit 4150 transmits the LOCKN signal output request data which is serial data from the built-in serial I / O port for the touch panel drive board, the forced switching circuit 4160f causes the LOCKN signal output request data. Is connected in a circuit so that the receiver ICSDIC0 for the upper plate side liquid crystal can receive the data, and the receiver ICSDIC0 for the upper plate side liquid crystal that has received the LOCKN signal output request data is used as a response signal from the LOCKN terminal of the receiver ICSDIC0 for the upper plate side liquid crystal. Since the LOCKN signal is output to the peripheral control MPU4150a, when the LOCKN signal is input, it is assumed that there is no problem in the connection between the transmitter and the receiver, and the upper plate side liquid crystal display device 470 has a problem. While it can be determined that it has not occurred, when the LOCKN signal is not input, the upper plate side liquid crystal display device 470 has a problem because the connection between the transmitter and the receiver has a problem. Can be judged. Then, when it is determined that the upper plate side liquid crystal display device 470 has a problem, the peripheral control MPU 4150a can execute the communication error display process of step S1548 in the connection recovery process of FIG. 73 as a notification process. It has become. In other words, when the peripheral control MPU4150a finds a defect in the upper plate side liquid crystal display device 470, it can notify the clerk of the hall or the like by executing the notification process. The clerk in the hall can extremely easily check whether or not the upper plate side liquid crystal display device 470 has a problem before the player plays the game, and the check can be done without any trouble. ing. Therefore, it is possible to find a defect of the upper plate side liquid crystal display device 470 without any trouble.

Further, as described above, as for the LOCKN signal, the drawing data received from the upper plate side liquid crystal receiver ICSDIC0 provided in the touch panel drive board 450 from the upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140 is abnormal data. If it is determined that the data is determined, it is a signal to be output to convey that fact. Specifically, the transmitter IC4160d for the upper plate side liquid crystal provided in the peripheral control board 4140 and the receiver ICSDIC0 for the upper plate side liquid crystal provided in the touch panel drive board 450. , That is, it is a signal output to request transmission of a predetermined data pattern (SYNC pattern) for confirming (recovering) the connection between the transmitter and the receiver. Is a drawing received due to a communication problem between the image communication between the upper plate side liquid crystal receiver ICSDIC0 and the upper plate side liquid crystal transmitter IC 4160d when the image transmitted from the upper plate side liquid crystal transmitter IC 4160d cannot be normally received. The LOCKN signal can be output to the peripheral control MPU 4150a of the peripheral control unit 4150 in order to convey that the data becomes abnormal data. As a result, the peripheral control MPU4150a to which the LOCKN signal is input sends a connection confirmation signal indicating that a predetermined data pattern (SYNC pattern) is to be transmitted from the upper plate side liquid crystal transmitter IC4160d to the upper plate side liquid crystal receiver ICSDIC0. By outputting to the dish-side LCD transmitter IC4160d, it is possible to eliminate communication problems between image communications. In other words, the peripheral control MPU4150a can detect a defect of the upper plate side liquid crystal display device 470 due to a communication defect between image communications at an early stage, and work on the upper plate side liquid crystal transmitter IC 4160d to eliminate the defect. It has become like. Therefore, it is possible to suppress a decrease in the player's motivation to play by discovering and eliminating the defect of the upper plate side liquid crystal display device 470.

Further, the upper plate side liquid crystal receiver ICSDIC0 that receives the image transmitted from the upper plate side liquid crystal transmitter IC 4160d and outputs it to the upper plate side liquid crystal display device 470 receives the image transmitted from the upper plate side liquid crystal transmitter IC 4160d. When it cannot be received normally, the LOCKN signal, which is a communication failure occurrence signal that conveys that a communication failure has occurred between the image communication between the upper plate side liquid crystal receiver ICSDIC0 and the upper plate side liquid crystal transmitter IC4160d, is produced by the effect control microprocessor. Since it is possible to output to the peripheral control MPU 4150a of a certain peripheral control unit 4150, the peripheral control MPU 4150a to which the LOCKN signal is input controls the liquid crystal and the sound source built-in VDP 4160a of the sound control unit 4160 to cause a communication problem. A message "There was a problem with the liquid crystal display device on the upper plate side. Please call a clerk." Is generated, which is an image indicating that it has occurred, and this generated image is displayed on the liquid crystal display device 1900 on the game board side. It can be displayed in the area and notified. In other words, the peripheral control MPU4150a detects a defect in the upper plate side liquid crystal display device 470 due to a communication defect between image communications at an early stage, and notifies the player seated in front of the pachinko gaming machine 1 to that effect. Since the player can inform the clerk of the hall or directly notify the clerk of the hall who happened to pass in front of the pachinko game machine 1, the clerk of the hall has a problem. Then, the work to solve the problem can be started at an early stage. Therefore, it is possible to suppress a decrease in the player's motivation to play by early detecting and eliminating the defect of the upper plate side liquid crystal display device 470.

Furthermore, the peripheral control MPU 4150a of the peripheral control unit 4150 is provided with the upper plate side liquid crystal transmitter IC 4160d provided on the peripheral control board 4140 and the upper plate side provided on the touch panel drive board 450 during the period (interval period) of timing K1 to timing K2. There is a case where the connection between the LCD receiver ICSDIC0 and the connection, that is, the connection between the transmitter and the receiver has occurred even once, and the connection between the transmitter and the receiver has a problem. When the cumulative number of times determined to be in the above state has not reached the cumulative number upper limit value CC-LMT, a predetermined data pattern (SYNC pattern) for enabling the LOCKN signal and solving a communication problem between image communications is performed. A connection confirmation signal for transmitting from the upper plate side LCD transmitter IC 4160d to the upper plate side liquid crystal receiver ICSDIC0 is sent to the upper plate side LCD transmitter IC 4160d until the cumulative number of times reaches the cumulative number upper limit CC-LMT. It is possible to keep outputting repeatedly. As a result, in the peripheral control MPU 4150a of the peripheral control unit 4150, the main control MPU 4100a of the main control board 4100 starts to change the first special symbol or the second special symbol game on the upper special symbol display 1185 or the lower special symbol display 1186. Since the connection confirmation signal can be repeatedly output only during the period when the stop display is displayed and the progress of the game is not executed, it is possible to move toward the direction in which the communication failure is resolved.

Then, in the peripheral control MPU 4150a of the peripheral control unit 4150, during the period (interval period) of timing K1 to timing K2, the upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140 and the upper plate side liquid crystal provided in the touch panel drive board 450 The connection between the receiver ICSDIC0 and the receiver, that is, the connection between the transmitter and the receiver has occurred even once, and the connection between the transmitter and the receiver has a problem. When the cumulative number of times determined to be in the above state has not reached the cumulative number upper limit CC-LMT, a predetermined data pattern (SYNC pattern) for enabling the LOCKN signal and eliminating a communication problem between image communications is added. A connection confirmation signal for transmitting from the dish side liquid crystal transmitter IC 4160d to the upper dish side liquid crystal receiver ICSDIC0 is repeatedly sent to the upper dish side liquid crystal transmitter IC 4160d until the cumulative number of times reaches the cumulative number upper limit CC-LMT. While continuing to output, the main control MPU 4100a of the main control board 4100 starts changing the first special symbol or the second special symbol game on the upper special symbol display 1185 or the lower special symbol display 1186 to advance the game. When the execution is started again, the output of the connection confirmation signal is stopped, and when the connection confirmation signal output from the peripheral control MPU4150a is stopped and the connection confirmation signal is not input, the transmitter IC4160d for the upper plate side liquid crystal has a predetermined data pattern. (SYNC pattern) can be stopped to be transmitted to the receiver ICSDIC0 for the upper plate side liquid crystal, and the image generated by the sound source built-in VDP4160a of the liquid crystal and the sound control unit 4160 can be output to the receiver ICSDIC0 for the upper plate side liquid crystal. It has become. As a result, in the peripheral control MPU 4150a of the peripheral control unit 4150, the main control MPU 4100a of the main control board 4100 starts to change the first special symbol or the second special symbol game on the upper special symbol display 1185 or the lower special symbol display 1186. By continuing to output the connection confirmation signal, which is a defect resolution signal, only during the period when the stop display is displayed and the progress of the game is not being executed, it is possible to move toward the direction in which the communication defect is resolved. Therefore, the main control MPU 4100a of the main control board 4100 starts and stops the first special symbol or the second special symbol game on the upper special symbol display 1185 or the lower special symbol display 1186 to display the progress of the game. When the connection confirmation signal is repeatedly output only during the non-execution period, the main control MPU 4100a of the main control board 4100 causes the first special symbol or the first special symbol on the upper special symbol display 1185 or the lower special symbol display 1186. Even if the second special symbol game is started to fluctuate and the progress of the game is started again, the distortion (image distortion) of the effect that progresses on the display screen of the upper plate side liquid crystal display device 470 is the main of the main control board 4100. Every time the control MPU4100a starts executing the game again and ends it (every time the period (interval period) of the timing K1 to the timing K2 is reached), the control MPU4100a can be directed to be resolved.

According to the above embodiment, the pachinko gaming machine 1 includes the main control board 4100 of FIG. 12 and the payout control board 4110 of FIG. FIG. 8 shows that the main control board 4100 is a starting area in which a game ball launched by the hitting ball launching device 650 of FIG. 5 is provided in the game area 1100 toward the game area 1100 partitioned on the game board 4 of FIG. The main control MPU 4100a of FIG. 12, which is a game control microprocessor that controls the progress of the game based on the intrusion into the upper start port 2101 and the lower start port 2102, is mounted. The payout control board 4110 is a payout control micro that controls the payout of game balls by the prize ball device 740 of FIG. 5 based on the prize ball commands of FIGS. 39 (a) and 39 (b), which are payout commands from the main control board 4100. The payout control MPU4120a of FIG. 13, which is a processor, is implemented.

The main control MPU 4100a, which is a game control microprocessor, includes at least a RAM (main control built-in RAM) built in the main control MPU 4100a. The main control built-in RAM can store information about the game even after the power is cut off.

The payout control MPU 4120a, which is a payout control microprocessor, includes at least a RAM (a payout control built-in RAM) built in the payout control MPU 4120a. The payout control built-in RAM can store information about payout even after the power is cut off.

The pachinko gaming machine 1 of the present embodiment further includes the operation switch 860a shown in FIG. When the operation switch 860a is operated within the period from the time when the power is turned on to the time when the determination process of step S16 in the main control side power-on processing in FIG. 43 is performed, the information about the game stored in the main control built-in RAM is erased. The RAM clear signal of FIG. 21 is output from the main control MPU4100a, which is a game control microprocessor, and is operated within the period from the time when the power is turned on to the time when the determination process of step S512 in the process when the payout control unit is turned on in FIG. 46 is performed. Then, the RAM clear function that outputs the RWMCLR signal of FIG. 26 to the payout control microprocessor MPU4120a as the RAM clear signal for erasing the information about the payout stored in the payout control built-in RAM, and the power-on From time to time, the period during which the determination process of step S16 in the main control side power-on process of FIG. 43 is performed (or the period during which the determination process of step S512 in the payout control unit power-on process of FIG. 46 is performed from time of power-on). When the operation is performed after the lapse of time, the RWMCLR signal of FIG. 26 is not output to the main control MPU4100a, which is a game control microprocessor, as an error release signal for canceling the error generated in the prize ball device 740, and the payout control microprocessor is used. It also has an error canceling function for outputting to the payout control MPU4120a.

As described above, when the operation switch 860a is operated within the period from the time when the power is turned on to the time when the determination process of step S16 in the process when the main control side power is turned on in FIG. 43 is performed, the game stored in the main control built-in RAM. The RAM clear signal of FIG. 21 for erasing the information related to the above is output to the main control MPU4100a which is a game control microprocessor, and the determination process of step S512 in the process of power-on of the payout control unit of FIG. 46 is performed from the time of power-on. When operated within the specified period, the RWMCLR signal of FIG. 26 is output to the payout control microprocessor MPU4120a as a RAM clear signal for erasing the payout information stored in the payout control built-in RAM. The function and the period during which the determination process of step S16 in the main control side power-on process of FIG. 43 is performed from the time of power-on (or the determination process of step S512 in the payout control unit power-on process of FIG. 46 from the time of power-on). When the operation is performed after the elapse of the period), the RWMCLR signal of FIG. 26 is not output to the main control MPU4100a, which is a game control microprocessor, as an error release signal for canceling the error generated in the prize ball device 740. Since it also has an error canceling function that outputs to the payout control MPU4120a, which is a payout control microprocessor, two different functions, a RAM clear function and an error clearing function, can be performed by operating one operation switch 860a. It can be provided in the game machine 1. Therefore, the RAM clear function and the error release function can be provided while contributing to cost reduction.

By the way, as described above, in the pachinko machine 1, the touch panel 480 is provided on the door frame 5 that can be opened and closed with respect to the main body frame 3 so that the operation surface overlaps the display area of the upper plate side liquid crystal display device 470. The effect control program uses the VDP4160a with a built-in sound source controlled by the peripheral control MPU4140a to display the selected display object image data and the operation menu background image data used for displaying the read selected display object stored in advance in the liquid crystal and the sound control ROM 4160b. Based on the above, the upper plate side liquid crystal display device 470 (second display device) displays the operation menu screen in a display mode in which at least one selection display object is superimposed on the operation menu background image as shown in FIG. 80 (selection). Display object display control means). Specifically, on this operation menu screen, for example, a volume light amount selection display object for resetting the volume / light amount, an extra selection display object imitating a violent person wearing sunglasses and calling himself "Bomb King", and Along with the word "first pachinko" that catches the eyes of unfamiliar pachinko beginners, the selection display items for beginners that imitate a game ball are arranged and displayed at approximately equal intervals along the horizontal direction, and are arranged almost in the center. The selected display item is displayed in a slightly larger size than the other selected display items.

As shown in FIG. 81, the operator touches the contact surface of the touch panel 480 with the finger F at the position of the selection display object for beginners displayed slightly to the right of the display area of the upper plate side liquid crystal display device 470, from right to left. When the slide is made toward, the effect control program reduces the extra selection display object based on the contact state of the contact surface of the touch panel 480, and expands the selection display object for beginners as a candidate to be selected next, for example. As shown in FIG. 82, each selected display object is displayed so as to be moved to the left.

Subsequently, when the operator touches the pachinko selection display object KHB for the first time with the finger F as shown in FIG. 83 (hereinafter, referred to as “tap”), the effect control program is shown in the figure as described above. The detection point is specified based on the contact portion according to the contact state of the contact surface of the touch panel 480 based on the contact position data from the touch panel drive substrate 450 shown in 36 (detection point acquisition means). Further, the effect control program is the first time based on the annular image data read from the liquid crystal and the sound control ROM 4160b (effect control storage unit) at the corresponding detection point in the display area of the upper plate side liquid crystal display device 470. A small initial ring-shaped display KHB is displayed at the position of the pachinko selection display (initial display control means).

Next, as shown in FIG. 85, the effect control program enlarges and displays the above-mentioned wording “first pachinko” and makes the player visually recognize that the first pachinko selection display object has been selected. As shown in FIG. 86, this effect control program reduces the density while leaving an afterimage of the annular display in the middle of the display mode in which the initial annular display is continuously enlarged with the passage of time at the detection point. While continuously enlarging the final ring-shaped display, the next transition destination screen associated with the first pachinko selection display is displayed while the first pachinko selection display corresponding to the detection point disappears. Display (afterimage display control means).

In this way, the operator of the touch panel 480 can visually recognize the annular display object KHB displayed in the display area of the upper plate side liquid crystal display device 470 through the contact surface in response to his / her own operation. .. Here, in today's world where precise production display has become possible, it seems that the player is not responding to his or her own operation at first glance, as the response of the touch panel generally remains even slightly slow. It seems that the psychology of actively participating in the player-participation-type production will be difficult to work, erroneously recognizing that it may be. However, according to the present embodiment, even if a precise effect display is possible, an afterimage of the annular display object KHB remains according to the operation of the operator, so that the operator operates even if the response to the operation is slightly delayed. It can be visually recognized that the response to is surely made.

By the way, instead of constantly displaying the afterimage as described above in the upper plate side liquid crystal display device 470, the effect control program causes an error release navigation command (second error) associated with the operation of the payout control board 4110 operation switch 860a. When the release command) is received from the main control board 4100, the test mode may be temporarily switched to the test mode for confirming the operation of the upper plate side liquid crystal display device 470 and executed. That is, although the effect control program normally does not execute the afterimage display using the upper plate side liquid crystal display device 470, when the operation switch 860a is operated, it then switches to the test mode to execute the afterimage display. You may do so. In this case, the effect control program controls to switch from the test mode to the normal mode when the operation switch 860a is operated again. In this way, depending on the convenience of the operator, the display operation of the upper plate side liquid crystal display device 470 can be temporarily tested (for example, at the time of shipment of the pachinko machine 1) in the test mode, or the upper plate side liquid crystal display device 470 can be temporarily tested. Afterimages can be displayed constantly as part of the production using.

On the other hand, on the operation menu screen as shown in FIG. 87, the operator touches the touch panel 480 corresponding to the volume adjustment selection display object displayed in the display area of the upper plate side liquid crystal display device 470 as shown in FIG. 88. When the surface is tapped to select, the effect control program displays a small initial annular display KHB as shown in FIG. 89 based on the contact portion based on the contact state. This effect control program displays the final annular display KHB as shown in FIG. 90 via the annular display KHB in the middle of the display mode in which the initial annular display KHB is continuously enlarged (final display). Control means). That is, the effect control program expands the annular display object KHB steplessly, for example, from the initial annular display object KHB to the final annular display object KHB, or, for example, divides the annular display object KHB into 10 stages and displays the annular display stepwise. The object KHB may be expanded.

In this way, as described above, the operator of the touch panel 480 visually recognizes the annular display object displayed in the display area of the upper plate side liquid crystal display device 470 through the contact surface in response to his / her own operation. be able to. Here, if the reaction remains sluggish in today's world where precise production display is becoming possible, when it becomes possible to realize more precise production display in the future, such a detailed production display will be used. At first glance, it is possible that the player feels relatively uncomfortable. However, according to the present embodiment, due to the appearance (display) of the annular display object displayed in the display area of the upper plate side liquid crystal display device 470 when the contact surface of the touch panel 480 is touched, the accuracy using vision is used. Since the response inspection becomes possible, even if it becomes possible to realize a more detailed effect display in the future, it is possible to make it difficult for the operator to feel uncomfortable by the direct response to the operation.

On the other hand, similarly, on the operation menu screen as shown in FIG. 87, the operator touches the touch panel corresponding to the volume adjustment selection display object displayed in the display area of the upper plate side liquid crystal display device 470 as shown in FIG. 88. When the contact surface of 480 is tapped and selected, the effect control program determines that the contact area of the contact portion based on the contact state is larger than the predetermined contact area (that is, when the pressing force is strong), FIG. 89. After displaying or without displaying the small initial ring-shaped display KHB as shown in FIG. 90, at least a part of the ring-shaped display KHB in the middle is omitted, and the final ring-shaped display KHB is displayed as shown in FIG. It may be displayed. When the pressing force is strong in this way, the initial annular display KHB in the display area that is visually recognized through the contact surface of the touch panel 480 by the operator's finger, or the annular display in the middle of a part of the above. Although the KHB is also hidden, the production control program reduces the unnecessary display that the player cannot see and reduces the processing load by omitting the display control of some of the annular display objects KHB in this way. can do.

After the final ring display KHB is displayed as described above, the effect control program is based on the tone adjustment background image data read from the liquid crystal and the sound control ROM 4160b, and the volume from 1 to 6 as shown in FIG. A volume adjustment icon OCI with a note mark based on the volume setting icon image data also read from the liquid crystal and sound control ROM 4160b is superimposed on the volume adjustment background image including the scale VSCL so as to be slidable along the volume scale VSCL. Display the volume adjustment screen of the mode.

When the operator taps the volume adjustment icon OCI on the volume adjustment screen with the finger F and slides it to the left as shown in FIG. 91, the effect control program drives the touch panel shown in FIG. 36 as described above. The detection point is specified based on the contact portion based on the contact state from the contact position data from the substrate 450 (detection point acquisition means), and the corresponding display area of the upper plate side liquid crystal display device 470 (second display device) corresponds to the detection point. First, a small initial ring-shaped display object KHB is displayed at the detection point based on the ring-shaped image data read from the liquid crystal and the sound control ROM 4160b (initial display control means).

Further, when the operator slides the volume adjustment icon OCI along the volume scale VSC with the finger F as shown in FIG. 92, the effect control program makes a contact from the touch panel drive board 450 as shown in FIG. The movement locus of the position where the contact portion based on the contact state is located (hereinafter referred to as the initial position) is detected for each movement detection point based on the position data (movement locus acquisition means). Next, as shown in FIG. 92, the effect control program independently and continuously expands the initial annular display KHB at each movement detection point along the detected movement locus with the passage of time. The final ring-shaped display object KHB is displayed via the ring-shaped display object KHB in the middle of the display mode (movement locus display control means). At this time, as shown in FIG. 93, the effect control program moves and displays the volume adjustment icon OCI so as to slide along the volume scale according to the slide of the finger F that taps the volume adjustment icon OCI, and finally displays the volume adjustment icon OCI. Similarly, as shown in FIG. 94, the volume adjustment icon OCI is moved to the position of the finger F where the slide is completed via the display of the annular display object in the middle of the display mode. When the operator releases the finger F from the contact surface of the touch panel 480, the effect control program loses any of the contact objects based on the contact position data from the touch panel drive substrate 450. Therefore, as shown in FIG. 95, the final effect control program is used. A further enlarged final annular display is displayed near the contact surface.

In this way, as described above, the operator of the touch panel 480 visually recognizes the annular display object KHB displayed in the display area of the upper plate side liquid crystal display device 470 through the contact surface in response to his / her own operation. can do. Therefore, at each movement detection point along the movement locus of the contact portion on the contact surface operated by the operator, the final ring-shaped display object KHB is displayed via the ring-shaped display object KHB in the middle, which is represented like an afterimage of the initial ring-shaped display object KHB. Since the annular display object KHB is displayed, the operator does not need to memorize the latest operation history along the movement locus one by one, and the operator is less likely to feel stress during operation.

By the way, the above-mentioned effect control program may be controlled so as to increase the size of the final annular display object KHB in proportion to the maximum area of the contour area of the contact portion based on the contact state of the touch panel 480 described above. Good (final display control means, afterimage display control means, movement locus display means). Specifically, this effect control program relatively increases the size of the final annular display object KHB when the contour area is relatively large, while it is final when the contour area is relatively small. The size of the annular display KHB is made relatively small. In this way, since the size of the final annular display KHB is proportional to the pressing force of the contact surface by the operator, it is possible to determine how much this pressing force was after the fact from the operator's point of view. Can be recognized.

Instead or in combination, the effect control program controls, for example, the expansion mode of the final annular display KHB in proportion to the change in the contour area per unit time in the contact portion based on the contact state of the touch panel 480 described above. (Final display control means, afterimage display control means, movement locus display means). Specifically, when the change in the contour area per unit time is large, the size of the annular display KHB in the middle is changed in a relatively short time, while the contour area per unit time. When the change is small, the size of the ring-shaped display KHB on the way is changed in a relatively long time. In this way, when the operator touches the contact surface in a relatively short time, the annular display KHB expands relatively quickly, while when the operator touches the contact surface in a relatively long time, the annular display is displayed. The object KHB expands relatively slowly, and not only can the reaction of the touch panel 480 according to the operation mode of the operator be inspected more accurately, but also the player operates the object in the real world. It becomes possible to obtain an operation feeling closer to the operation feeling at the time.

[18. Screen displayed in the display area of the liquid crystal display device on the game board side]
Next, the screen displayed in the display area of the liquid crystal display device 1900 on the game board side provided in the game board 4 shown in FIG. 8 will be briefly described with reference to FIGS. 96 and 97. The screen displayed in the display area of the liquid crystal display device 1900 on the game board side is the periphery of the peripheral control unit power-on processing shown in FIG. 63 by the peripheral control MPU 4150a of the peripheral control unit 4150 on the peripheral control board 4140 shown in FIG. Control unit Displayed by executing steady processing, etc. As a result, various effects are advanced in the display area of the liquid crystal display device 1900 on the game board side. Here, first, the effect of the variable display and the like displayed in the display area of the liquid crystal display device 1900 on the game board side will be described, and then the effect of notifying the firing operation defect displayed in the display area of the liquid crystal display device 1900 on the game board side will be described. explain. FIG. 96 is a diagram showing an example of a variable display effect displayed in the display area of the liquid crystal display device on the game board side, and FIG. 97 is an example of a firing operation failure notification effect displayed in the display area of the liquid crystal display device on the game board side. It is a figure which shows.

[18-1. Production of variable display, etc. displayed in the display area of the liquid crystal display device on the game board side]
First, an image such as a variable display displayed in the display area of the liquid crystal display device 1900 on the game board side will be described with reference to FIG. 96. FIG. 8 shows the main control side main processing of the main control side power-on processing shown in FIG. 44 and the main control side timer interrupt processing shown in FIG. 45 by the main control MPU 4100a of the main control board 4100 shown in FIG. The result of the first special lottery drawn by accepting the game ball to the upper starting port 2101 or the result of the second special lottery drawn by accepting the game ball to the lower starting port 2102 shown in FIG. 8 is a "big hit". Then, the number of repetitions (number of rounds) of the opening / closing operation of the large winning opening 2103 shown in FIG. 8 is a total of 15 rounds from 1 round to 15 rounds, and in each round, within a predetermined time (for example, 30 seconds). When a game ball enters the large winning opening 2103 and the number of balls reaches a predetermined number (for example, 9 balls), the round is digested, and one game ball enters the large winning opening 2103. A predetermined number (for example, 15 balls) of game balls are paid out for each ball.

The first special lottery result drawn by accepting the game ball to the upper starting port 2101 or the second special lottery result drawn by accepting the game ball to the lower starting port 2102 is shown in FIG. 40 from the main control board 4100. FIG. 96A shows the peripheral control unit 4150 of the peripheral control board 4140 shown in FIG. 15 controlling the liquid crystal and the sound control unit 4160 based on the production commands related to the game effect, which are various commands shown in FIG. As described above, the decorative symbol 1950a is started on the left side of the display area of the liquid crystal display device 1900 on the game board side, the decorative symbol 1950b is started in the center, and the decorative symbol 1950c is started on the right side. The variable display of ~ 1950c is stopped so that the player can recognize the first special lottery result or the second special lottery result. At this time, the upper special of the function display unit 1180 shown in FIG. The result of the first special lottery or the result of the second special lottery can also be confirmed in the first special symbol or the second special symbol displayed on the symbol display 1185 or the lower special symbol display 1186. When the decorative symbols 1950a to 1950c are displayed in a variable manner, the decorative symbols 1950a to 1950c are translucent so that the background image can be visually recognized, and the decorative symbols 1950a are arranged from the upper left side to the lower left side of the display area from the upper left side to the lower left side. Is displayed in a variable manner from the upper center to the lower center of the display area, and the decorative symbol 1950c is displayed as if the reels are rotating from the upper right side to the lower right side of the display area. There is.

Specifically, in the peripheral control unit command reception interrupt process of FIG. 66, the effect control program executed by the peripheral control MPU 4150a receives various commands from the main control board 4100. Then, in the reception command analysis processing of step S1022 in the peripheral control unit steady processing of the peripheral control unit power-on processing of FIG. 63, the effect control program analyzes various commands received in the peripheral control unit command reception interrupt processing of FIG. 66. I do. When the analyzed command is, for example, the special figure 1 synchronized effect start command shown in FIG. 40 related to the special figure 1 synchronized effect, the effect control program uses the effect pattern specified in this mode in FIG. 96 (a). ) Is set in the variable display mode of the decorative symbols 1950a to 1950b, the screen generation schedule data, the light emission mode generation schedule data, the sound generation schedule data, the electrical drive source schedule data, and the like are set in the peripheral control unit. It is extracted from the peripheral control ROM 4150b of the 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and set in the schedule data storage area 4150cae of the peripheral control RAM 4150c.

For example, the screen generation schedule data set in the variable display mode of the decorative symbols 1950a to 1950b is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c, and the schedule of the peripheral control RAM 4150c. When set in the data storage area 4150 cage, the pointer is updated in the scheduler update process of step S1020 in the peripheral control unit steady processing of the peripheral control unit power-on processing of FIG. 63, and in the display data creation process of step S1030 in the same process. Of the screen data arranged in time series constituting the screen generation schedule data, the screen data indicated by the pointer is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c. And output to VDP4160a with built-in sound source. When screen data is input from the peripheral control MPU4150a, the sound source built-in VDP4160a extracts character data from the liquid crystal and sound control ROM 4160b based on the input screen data to create sprite data, and creates a sprite data on the game board side liquid crystal display device. Drawing data for one screen (one frame) to be displayed in 1900 is generated on the built-in VRAM. Then, in the display data output process of step S1016 in the same process, the effect control program incorporates the drawing data for one screen (one frame) generated on the built-in VRAM of the sound source built-in VDP4160a in the above-mentioned display data creation process. The VDP4160a outputs from the channel CH1 shown in FIG. 17 to the liquid crystal display device 1900 on the game board side. As a result, the variable display screens of the decorative symbols 1950a to 1950b are displayed in the display area of the liquid crystal display device 1900 on the game board side as the game effect shown in FIG. 96 (a).

As shown in FIG. 96A, when the variable display of the decorative symbols 1950a to 1950c is started and a predetermined time elapses, the stop symbols of the decorative symbols 1950a to 1950c are stopped and displayed with the same decorative symbol. It becomes a "big hit". On the other hand, as shown in FIG. 96A, the variable display of the decorative symbols 1950a to 1950c is started, and after a predetermined time has elapsed, as shown in FIG. 96B, the stop symbols of the decorative symbols 1950a to 1950c are displayed. If the same decorative pattern is not stopped and displayed, it will be "off".

When the state in which the game ball does not enter the upper start port 2101 or the lower start port 2102 continues and the state in which the reserved balls are digested to zero is continued for a predetermined time (for example, in the present embodiment, 60 seconds). The demonstration screen, which is the screen in the customer waiting state shown in FIG. 96 (c), is displayed in the display area of the liquid crystal display device 1900 on the game board side. At this time, the sound effect and music are set to mute. Then, when the demonstration screen is displayed in the display area of the liquid crystal display device 1900 on the game board side a predetermined number of times (for example, 15 times in this embodiment), the mode shifts to the power saving mode and the liquid crystal on the game board side is displayed. Nothing is displayed in the display area of the display device 1900 (that is, a black screen is displayed). At this time, the various lamps provided on the door frame 5 and the various lamps provided on the game board 4 shown in FIG. 2 are also turned off.

[18-2. Launch operation malfunction notification effect displayed in the display area of the liquid crystal display device on the game board side]
Next, the firing operation failure notification effect displayed in the display area of the liquid crystal display device 1900 on the game board side will be described. When the player is seated on the front surface of the pachinko gaming machine 1 and starts the game by rotating the rotary handle main body front 506 shown in FIG. 7, for some reason, the payout control shown in FIG. 13 is performed. The status obtained by the payout control MPU 4120a from the launch ball feed defect monitoring circuit 4120ah in which the payout control MPU 4120a has a problem in the launch ball feed control circuit 4120ag built in the payout control MPU 4120a of the board 4110. Judging from the information, in order to forcibly stop the launch control of the game ball by the launch ball feed control circuit 4120ag, the launch operation prohibition is set for the launch ball feed control circuit 4120ag, and the fact is notified to the main control board 4100. It is supposed to tell. By notifying the peripheral control board 4140 that the main control board 4100 is in the firing operation prohibited state, the peripheral control board 4140 has a firing operation defect in the display area of the liquid crystal display device 1900 on the game board side as shown in FIG. As a notification effect, the screen for notifying the launch operation malfunction is displayed.

Specifically, in the launch ball feed control circuit error check process of step S557 of the payout control unit main process in the payout control unit power-on processing in FIG. 48, the payout control program has the launch ball feed defect shown in FIG. Status information is acquired from the monitoring circuit 4120ah to determine whether or not a problem has occurred in the launch ball feed control circuit 4120ag. As described above, the launch ball feed defect monitoring circuit 4120ah determines whether or not a defect has occurred in the launch ball feed control circuit 4120ag that performs launch control by the launch solenoid 654 and ball feed control by the ball feed solenoid 585. It is monitored, and the monitoring result (whether or not a problem has occurred) can be stored and retained as status information. The payout control program acquires status information from the launch ball feed defect monitoring circuit 4120ah and determines whether or not a defect has occurred in the launch ball feed control circuit 4120ag. When the payout control program acquires the status information from the launch ball feed defect monitoring circuit 4120ah and determines that no defect has occurred in the launch ball feed control circuit 4120ag, the payout control program controls the launch of the game ball by the launch ball feed control circuit 4120ag. In order to start, the launch operation permission is set for the launch ball feed control circuit 4120ag, and the launch operation permission information indicating that the launch operation permission state is stored is stored in the state information storage area of the discharge control built-in RAM, while firing. When it is determined that a problem has occurred in the ball feed control circuit 4120ag, the launch operation is prohibited for the launch ball feed control circuit 4120ag in order to forcibly stop the launch control of the game ball by the launch ball feed control circuit 4120ag. At the same time as setting, the firing operation prohibition information indicating that the firing operation is prohibited is stored in the state information storage area of the payout control built-in RAM.

Then, in the command transmission process of step S566 in the same process, when the payout control program reads the firing operation permission information from the state information storage area of the payout control built-in RAM, it is shown in FIG. 42 based on the firing operation permission information. Create a 1-byte (8-bit) frame status 2 command (set a value of 0 in B0 to convey that it is not a launch ball feed control circuit error) and send it to the main control board 4100. Or, when the firing operation prohibition information is read from the state information storage area of the payout control built-in RAM, the 1-byte (8-bit) frame state 2 classified into the state display shown in FIG. 42 based on the firing operation prohibition information. A command (a value of 1 is set in B0 to convey that the launch ball feed control circuit error has occurred) is created and transmitted to the main control board 4100.

In the frame command reception process of step S110 in the main control side timer interrupt process of FIG. 45, when the main control program receives the 1-byte (8-bit) frame state 2 command classified into the state display shown in FIG. 42, As a 2-byte (16-bit) command, it is shaped into a frame state 2 command classified into the state display shown in FIG. 41, and stored as transmission information in the transmission information storage area of the main control built-in RAM.

Then, in the peripheral control board command transmission process in step S120 in the same process, the main control program reads the transmission information from the transmission information storage area of the main control built-in RAM and transmits this transmission information to the peripheral control board 4140.

In the peripheral control unit command reception interrupt process of FIG. 66, the effect control program receives various commands from the main control board 4100. Then, in the reception command analysis processing of step S1022 in the peripheral control unit steady processing of the peripheral control unit power-on processing of FIG. 63, the effect control program analyzes various commands received in the peripheral control unit command reception interrupt processing of FIG. 66. I do. When the analyzed command is a frame state 2 command classified into the state display shown in FIG. 41 and conveys that it is not a launch ball feed control circuit error, the effect control program is as it is next. While proceeding to step S1024, which is a step, if it conveys that the launch ball feed control circuit error has occurred, it is set to the launch operation failure notification mode for executing the launch operation failure notification, for screen generation. Schedule data, light emission mode generation schedule data, sound generation schedule data, electrical drive source schedule data, etc. are extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c. It is set in the schedule data storage area 4150cae of the control RAM 4150c.

For example, the screen generation schedule data and the sound generation schedule data set in the firing operation failure notification mode are extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c, and the peripheral control RAM 4150c. When set in the schedule data storage area 4150cae of FIG. 63, the pointer is updated in the scheduler update process of step S1020 in the peripheral control unit steady processing of the peripheral control unit power-on processing of FIG. 63, and the display data creation of step S1030 in the same process. In the processing, among the screen data arranged in time series constituting the screen generation schedule data, the screen data indicated by the pointer is transferred from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c. It is extracted and output to the VDP4160a with a built-in sound source. When screen data is input from the peripheral control MPU4150a, the sound source built-in VDP4160a extracts character data from the liquid crystal and sound control ROM 4160b based on the input screen data to create sprite data, and creates a sprite data on the game board side liquid crystal display device. Drawing data for one screen (one frame) to be displayed in 1900 is generated on the built-in VRAM. Then, in the display data output process of step S1016 in the same process, the effect control program incorporates the drawing data for one screen (one frame) generated on the built-in VRAM of the sound source built-in VDP4160a in the above-mentioned display data creation process. The VDP4160a outputs from the channel CH1 shown in FIG. 17 to the liquid crystal display device 1900 on the game board side. As a result, the screen for notifying the firing operation failure is displayed in the display area of the liquid crystal display device 1900 on the game board side as the firing operation failure notification effect shown in FIG. 97.

Further, the screen generation schedule data and the sound generation schedule data set in the firing operation failure notification mode are extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c, and the peripheral control RAM 4150c. When set in the schedule data storage area 4150cae of the above, the pointer is updated in the scheduler update process of step S1020 in the same process, and in the sound data creation process of step S1032 in the same process, the time series constituting the schedule data for sound generation is set. Of the arranged sound command data, the sound command data indicated by the pointer is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP 4160a. Then, in the sound data output process of step S1018 in the same process, the sound data such as music and sound effects set in the sound source built-in VDP4160a in the above-mentioned sound data creation process is output to the audio data transmission IC 4160c as serialized audio data. In addition to music and sound effects, sound data of notification sounds and notification sounds are output to the audio data transmission IC 4160c as serialized audio data. As a result, the voice "There is a launch problem. Please call the staff." Is heard on the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and in the door frame 5 shown in FIG. It will flow repeatedly from the provided speaker 130.

In this way, the payout control MPU 4120a determines whether or not a defect has occurred in the built-in launch ball feed control circuit 4120ag from the status information stored and held by the built-in launch ball feed defect monitoring circuit 4120ah. When the determination result determines that a problem has occurred in the launch ball feed control circuit 4120ag, the launch ball feed control circuit 4120ag is set to the launch operation prohibited state, and the launch operation is prohibited via the main control board 4100 (main control MPU 4100a). Since the peripheral control MPU 4150a can be transmitted to the peripheral control MPU 4150a as a frame state 2 command formatted into 2 bytes (16 bits) divided into the status display of FIG. 41, the peripheral control MPU 4150a is shown by the liquid crystal display device 1900 on the game board side in FIG. 97. It is possible to control the progress of the firing operation failure notification effect. As a problem in the launch ball feed control circuit 4120ag, as described above, it is difficult to adjust the drive current for launching (launching) the game ball toward the game area 1100 based on the operation signal from the potentiometer 512. If this is the case, the operation signal from the potentiometer 512 is affected by noise and turns into an extremely disturbed signal, and the drive current for launching (launching) the game ball toward the game area 1100 cannot be specified. When it is difficult to adjust the drive current, the detection signal from the touch switch 516 is disguised as an extremely disturbed signal due to the influence of noise, and the player's palm or finger touches the 506 in front of the rotating handle body. When it is difficult to specify whether or not the game ball is launched (launched) by the player's will, the detection signal from the launch stop switch 518 is disguised as an extremely disturbed signal due to the influence of noise. In addition to cases where it is difficult to identify whether or not the vehicle has been forcibly stopped, when the launch ball feed control circuit 4120ag itself has been destroyed for some reason and becomes unusable, or at a predetermined time. When the number of game balls launched (launched) toward the game area 1100 exceeds a predetermined number (in the present embodiment, the game balls launched (launched) toward the game area 1100 per minute). (When the number of balls exceeds 100) and the like can be mentioned.

As a defect in the launch ball feed control circuit 4120ag, for example, the drive current for launching (launching) the game ball toward the game area 1100 by turning the operation signal from the potentiometer 512 into an extremely disturbed signal due to the influence of noise. If it is difficult to specify the driving current and it is difficult to adjust the drive current, it is not possible to obtain a stable firing intensity. Therefore, the upper starting port provided in the game area 1100 shown in FIG. The entry rate of the game ball into 2101 cannot be stabilized, and the game is continued in a state disadvantageous to the player. Therefore, in the present embodiment, when a problem occurs in the launch ball feed control circuit 4120ag built in the payout control MPU 4120a and the ball launching device 650 launches the game ball, which is disadvantageous to the player. Pachinko gaming machine 1 automatically stops firing by the ball launching device 650 by setting a firing operation prohibition state for the launching ball feed control circuit 4120ag built in the payout control MPU 4120a to continue the game. Can be difficult. Therefore, it is possible to prevent the game from being continued in a state that is disadvantageous to the player that a defect has occurred.

According to the pachinko gaming machine 1 of the present embodiment described above, the game board side liquid crystal display device 1900 as the first display means and the movable liquid crystal display devices 1925a to 1925d of FIG. 10 as the second display means. The game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d are provided with a plurality of display devices. The liquid crystal display device 1900 on the game board side can display an effect image. The movable liquid crystal display devices 1925a to 1925d are provided separately from the game board side liquid crystal display device 1900 and can display an effect image.

The pachinko gaming machine 1 of the present embodiment further includes the VDP4160a with a built-in sound source shown in FIG. 31. The sound source built-in VDP4160a can generate an effect image and store it in the built-in VRAM, and output the stored effect image by a dual link method.

The VDP4160a with a built-in sound source stores at least the drawing data of the effect image to be displayed on the game board side liquid crystal display device 1900 in the even address of the built-in VRAM, and also has the drawing data of the effect image to be displayed on the movable liquid crystal display devices 1925a to 1925d. After storing in the odd address of the VRAM, the drawing data of the effect image stored in the even address of the built-in VRAM for the game board side liquid crystal display device 1900 is output, and the drawing data is stored in the odd address of the built-in VRAM for the movable liquid crystal display devices 1925a to 1925d. It is possible to output the drawing data of the produced effect image at the same time.

Specifically, drawing data for the game board side liquid crystal display device 1900 transmitted from the even channel to the liquid crystal output board 3420 and drawing for the four movable liquid crystal display devices 1925a to 1925d transmitted from the odd channel to the liquid crystal output board 3420. The data is created in the frame buffers MVD and SVD on the liquid crystal of the peripheral control board 4140 and the built-in VRAM of the sound source built-in VDP 4160a of the sound control unit 4160, respectively.

As described above, the channel CH1 in the VDP4160a with a built-in sound source employs a dual link system as the LVDS. The first signal transmission line is an even number channel, the signal transmission line on the two sides is an odd number channel, and the drawing data for the game board side liquid crystal display device 1900 is transmitted from the even number channel to the liquid crystal output board 3420, while the odd number channel is 4 Drawing data for the two movable liquid crystal display devices 1925a to 1925d is transmitted to the liquid crystal output board 3420. Drawing data is transmitted simultaneously for even-numbered addresses and odd-numbered addresses by the dual link method. When the drawing data for the game board side liquid crystal display device 1900 created in the frame buffer MVD is transmitted from the even channels of channel CH1 in the sound source built-in VDP4160a to the liquid crystal output board 3420, the game board side liquid crystal display is displayed via the liquid crystal output board 3420. The original image MVD0 output to the device 1900 is drawn in the display area of the liquid crystal display device 1900 on the game board side, and is also drawn for the movable liquid crystal display devices 1925a to 1925d transmitted to the liquid crystal output board 3420 created in the frame buffer SVD. When the data is transmitted from the odd channel of channel CH1 in the sound source built-in VDP4160a to the liquid crystal output board 3420, the data is disassembled and enlarged in the liquid crystal output board 3420 and output to the movable liquid crystal display devices 1925a to 1925d, respectively, and the original image SVDA0. ~ S VDD0 are drawn in the display areas of the movable liquid crystal display devices 1925a to 1925d, respectively.

As described above, the VDP4160a with a built-in sound source uses the dual link method to output drawing data of the effect image stored in the even addresses of the built-in VRAM to the liquid crystal display device 1900 on the game board side and to output the drawing data of the effect image stored in the even addresses of the built-in VRAM to the movable liquid crystal display devices 1925a to 1925d. Since the drawing data of the effect image stored in the odd address can be output at the same time, the effect image is displayed on a plurality of display devices by the dual link method conventionally used for displaying one display device. It can be applied to the pachinko game machine 1 as a novel method that has never existed before. Therefore, by associating a plurality of display devices by the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d with respect to the output by one dual link method, the effect image is displayed on each of the plurality of display devices. Can be done.

[19. Another example]
It goes without saying that the present invention is not limited to the above-described embodiment, and can be implemented in various aspects as long as it belongs to the technical scope of the present invention.

For example, in the above-described embodiment, a plurality of game board-side liquid crystal display devices 1900 as the first display means and movable liquid crystal display devices 1925a to 1925d as the second display means are used for the output by one dual link method. By associating the display devices of the above, it was possible to display the effect image on a plurality of display devices, respectively, but with the game board side liquid crystal display device 1900 as the first display means for the output by one dual link method. One game board side sub liquid crystal display device as a second display means provided separately from the game board side liquid crystal display device 1900 (this game board side sub liquid crystal display device is, for example, the game board shown in FIG. By associating a plurality of display devices with the character body of the character unit 3400 of 4 with a plurality of display devices by the game board side liquid crystal display device 1900 (), the effect image is displayed on each of the plurality of display devices. It can also be configured, and for the output by one dual link system, one door frame side sub as a second display means provided separately from the game board side liquid crystal display device 1900 as the first display means. Liquid crystal display device (This door frame side sub liquid crystal display device is separate from the game board side liquid crystal display device 1900 in the upper decorative unit 280 attached to the upper outer periphery of the game window 101 of the door frame 5 shown in FIG. 2, for example. By associating a plurality of display devices according to (1), it is also possible to configure the display devices to display the effect images on the plurality of display devices. In this case, the drawing data for the game board side sub liquid crystal table display device or the door frame side sub liquid crystal display device created in the frame buffer SVD shown in FIGS. 32 (d) to 32 (e) is shown in FIGS. 32 (a) to 32 (e). Although it can be created by the procedure as in c), the image size of the game board side sub liquid crystal display device or the door frame side sub liquid crystal display device is larger than that of the game board side liquid crystal display device 1900 due to structural restrictions. Therefore, the image size of the original image for drawing in the display area of the game board side sub liquid crystal table display device or the door frame side sub liquid crystal display device is also from the image size 800 × 600 dots shown in FIG. 32 (a). It becomes smaller.

Further, in the above-described embodiment, the pachinko gaming machine 1 has been described as an example, but the gaming machine to which the present invention can be applied is not limited to the pachinko gaming machine, and a gaming machine other than the pachinko gaming machine, for example, a slot machine ( It can also be applied to a spinning game machine) or a fusion game machine in which a pachinko game machine and a slot machine are fused (a machine that plays a slot game using a game ball). Here, a slot machine as a rotating drum type gaming machine will be described with reference to FIG. 98. FIG. 98 is a schematic perspective view of the slot machine.

As shown in FIG. 98, the slot machine 6000 is configured to include a front door 6002 and a main body portion 6004. The front door 6002 and the main body portion 6004 are connected to each other via a hinge (not shown). The front door 6002 can be opened from the main body portion 6004 by inserting the key into the keyhole 6005 provided at the right end of the front door 6002 and turning it clockwise with this hinge as the center of rotation.

A game panel 6006 is provided on the upper half of the front door 6002, and a protruding portion protruding forward from the game panel 6006 is formed on the lower half of the front door 6002. A medal insertion slot 6008, bet buttons 6010, 6012, a start lever 6014, a left stop button 6016, a middle stop button 6018, a right stop button 6020, and the like are arranged along the lower edge of the game panel 6006. Further, a storage settlement button 6022 and a decorative plate 6024 are arranged in the lower half of the front door 6002, and a saucer 6026 is provided below the decorative plate 6024. These bet buttons 6010, 6012, start lever 6014, left stop button 6016, middle stop button 6018, right stop button 6020, storage settlement button 6022, etc. are main control boards (main control MPU) that control the progress of the game (not shown). ) Is electrically connected.

A rectangular display window (not shown) is formed at a substantially central position of the game panel 6006, and three variable rotating bodies (not shown) installed inside the slot machine 6000 through this display window, a plurality of liquid crystal display devices, etc. Can be seen through. On these variable rotating bodies, a translucent symbol band on which a plurality of types of symbols (for example, bell, watermelon, cherry, 7, V, etc.) are printed as symbol information is attached to each tubular frame. ing. Such a tubular variable rotating body is called a reel or a drum in a gaming machine such as a slot machine, and an output shaft of a stepping motor (not shown) and each variable rotating body are connected to each other. These stepping motors are driven and controlled by a main control board (main control MPU), and by rotating the output shaft of the stepping motor, a plurality of types of symbols are continuously displayed from the top to the bottom from the above-mentioned display window. It seems to change to. The display of the plurality of liquid crystal display devices is controlled by an effect control board (one VDP with a built-in sound source) that controls the progress of the effect (not shown), and these display controls are performed based on various commands from the main control board. ing. The main control board and the effect control board are installed inside the slot machine 6000.

On the main control board (main control MPU), a predetermined number of medals are inserted into the medal insertion slot 6008 as a game medium, and the variable display of the symbol information is started based on the operation of the start lever 6014, and the left stop button 6016 and the middle stop. The variable display of the symbol information is stopped based on the operation of the button 6018 and the right stop button 6020 or the passage of a predetermined time. Then, the main control board (main control MPU) generates a profit-giving state (big hit game state) on condition that the symbol information has a predetermined specific display mode, and a large amount of medals as a game medium are placed on the tray 6026. Pay out.

In the fusion gaming machine, the medal insertion slot 6008 becomes the ball insertion slot 6008', and in the main control board (main control MPU), a predetermined number of game balls are inserted into the ball insertion slot 6008' as a game medium, and the start lever. The variable display of the symbol information is started based on the operation of 6014, and the variable display of the symbol information is stopped based on the operation of the left stop button 6016, the middle stop button 6018, the right stop button 6020, or the passage of a predetermined time. Then, the main control board (main control MPU) generates a profit-giving state (big hit game state) on condition that the symbol information has a predetermined specific display mode, and a large amount of game balls as a game medium is placed on the tray 6026. Pay out to.

1 ... Pachinko game machine (game machine), 2 ... Outer frame, 3 ... Main body frame, 4 ... Game board, 5 ... Door frame, 192 ... Handle relay terminal board, 300 ... Dish unit, 450 ... Touch panel drive board, 450V ... Liquid crystal module circuit, 450W ... Touch panel circuit, 470 ... Upper plate side liquid crystal display device, 480 ... Touch panel, 650 ... Ball launcher, 740 ... Prize ball device, 744 ... Payout motor, 751 ... Counting switch, 784 ... External terminal board, 851 ... Power supply board, 855 ... Power supply control unit, 855d ... Power supply creation circuit, 855da ... Power consumption monitoring circuit, 855da ... Power measurement circuit, 855da ... Power consumption suppression stage determination circuit, 860a ... Operation switch, 860b ... Error LED indicator 1,100 ... Game area, 1900 ... Game board side liquid crystal display device (first display means), 1925a to 1925d ... Movable liquid crystal display device (second display means), 2100 ... Attacker unit, 2105 ... Start port solenoid, 2108 ... Attacker solenoid, 4100 ... Main control board, 4100a ... Main control MPU, 4110 ... Payout control board, 4120 ... Payout control unit, 4120a ... Payout control MPU, 4120ag ... Launch ball feed control circuit, 4120ah ... Launch ball feed defect monitoring circuit 4,140 ... Peripheral control board, 4150 ... Peripheral control unit, 4150a ... Peripheral control MPU, 4150f ... Power consumption status history RAM, 4150g ... Battery, 4150k ... Power saving mode transition notification LED, 4160 ... Liquid crystal and sound control unit, 4160a ... Sound source Built-in VDP (image generation means), 4165 ... RTC control unit, 4165a ... RTC, 4165b ... battery, 4170 ... lamp drive board, 4180 ... motor drive board, BC0 ... capacitor, MC2 ... electrolytic capacitor.

Claims (1)

In a game board in which a game area is formed and a game machine having a game window on the door frame so that the game area of the game board can be visually recognized.
Main control that outputs a prize ball command that defines the number of game balls to be paid out as prize balls based on the fact that the game balls flowing down the game area enter various prize openings provided in the game area. Means and
A payout control means for controlling a prize ball device that pays out a game ball as a prize ball based on the prize ball command from the main control means.
Equipped with an external output means that is electrically connected to the outside and has multiple terminals that can transmit various information.
The prize ball device pays out a game ball by a drive signal from the payout control means, and detects the game ball to be paid out by a predetermined counting switch.
The main control means
Every time the number of game balls to be paid out by the prize ball device as prize balls reaches a predetermined number based on the game balls flowing down the game area entering the various winning openings. Main control prize ball number A main control microprocessor that performs calculations to output to the external output means as a schedule information output signal, and
A prize ball command output control means that outputs the prize ball command to the payout control means, and
With
When the main control prize ball number schedule information output signal is continuously output, the signal width of the main control prize ball number schedule information output signal is prevented so that the main control prize ball number schedule information output signal is not continuously output. Output the signal at the same interval as
The payout control means
Withdrawal control microprocessor and
An output circuit on the payout control side that can output various signals,
Every time the number of game balls detected by the counting switch included in the prize ball device reaches a predetermined number of balls, the payout control prize ball number information output signal is output to the external output means. Means and
An opening information output means that outputs to the external output means as an opening information signal that the opening of the door frame has been detected, and
Including
In the external output means, the terminal of the payout control prize ball number information output signal and the terminal of the main control prize ball number schedule information output signal are arranged at distant positions not adjacent to each other.
The signal width of the payout control prize ball number information output signal is preset based on the interrupt cycle of the payout control means.
The payout control side output circuit includes an output circuit having a reset function and an output circuit not having a reset function.
The payout control prize ball number information output signal is output from the output circuit having the reset function of the payout control side output circuit by the payout control prize ball number information output means.
The output circuit having no reset function includes a first output circuit having no reset function and a second output circuit having no reset function.
A signal from the serial port of the payout control microprocessor is output from the first output circuit having no reset function.
The signal from the payout control microprocessor is not output from the second output circuit that does not have the reset function, and the open information output means outputs the open information signal.
A gaming machine characterized in that the output circuit having the reset function of the payout control side output circuit is reset at the time of power recovery.

Images