JP6905368B2 - Transmitter, receiver and program - Google Patents

Description

The present invention relates to a transmitting device, a receiving device and a program.

A wireless transmission device for transmitting program material is called an FPU (Field Pickup Unit), and is indispensable as a tool for relaying a program or sending an interviewed video to a broadcasting station.

In recent years, in particular, a digital FPU using OFDM (Orthogonal Frequency Division Multiplexing), which is resistant to frequency-selective fading, has attracted attention, and practical standards have already been proposed in various frequency bands ( See Non-Patent Documents 1 to 4).

In digital wireless transmission, an error correction code is indispensable for correcting an error occurring in a propagation path. Also in Non-Patent Documents 1 to 4, stable digital wireless transmission is realized by using a Reed-Solomon (RS) code as an external code and a convolutional code as an internal code.

In recent years, the LDPC (Low Density Parity Check) code has attracted attention as an error correction code having an extremely excellent error correction capability, and a combination using a BCH code as an external code and an LDPC code as an internal code has been realized. (See Non-Patent Document 5).

Since the BER can be improved compared to the combination in which the Reed-Solomon code is used as the outer code and the convolutional code is used as the inner code used in the current digital FPU, the external code can also be improved in the digital FPU. It is expected that the BCH code will be used for and the LDPC code will be used for the internal code.

In Patent Document 1, a digital FPU using an LDPC code as both an external code and an internal code is proposed.

Hereinafter, the prior art will be described with reference to FIGS. 5 to 9.

The LDPC code is an error correction code called a block code, and the information bit input to the LDPC code encoder has a fixed length. For example, in the LDPC code having a coding rate of 1/2, which is standardized as an internal code in Non-Patent Document 5, 22,814 bits are input to the LDPC code encoder as shown in FIG. 5, and 22,066. Bit parity bits are added to form 44,880 bits as one LDPC code block. Similarly, in the BCH code standardized as an external code in Patent Document 5, a 192 bit parity bit is added. Therefore, the maximum information bit length that can be input to the entire encoder is 22,814-192 = 22,622 bits.

Further, as shown in FIG. 6, the digital FPU is a system for transmitting a TS packet consisting of 204 bytes (1,632 bits) or 188 bytes (1,504 bits). A 1-byte synchronization byte (“0x47” in hexadecimal notation) is arranged at the beginning of each TS packet, and the TS packet can be separated by using the synchronization byte as a mark.

As shown in FIG. 6, the latter 16 bytes (128 bits) of the 204-byte TS packet is a part called a dummy byte having no data, and the size of the TS packet from which the dummy byte has been removed is 188 bytes. It becomes.

Similarly, since a dummy byte is only added to convert a 188-byte TS packet into a 204-byte TS packet, the following description will be made with reference to the 188-byte TS packet.

In coding a TS packet using a BCH code and an LDPC code, when the number of TS packets contained in one LDPC code block is an integer, that is, when the TS packet is divided and not encoded, the figure is shown in the figure. As shown in 7, an 187-byte (1,496-bit) TS packet from which the synchronization bytes have been removed can be input to the encoder as information bits. This is because it is known that there is a delimiter every 187 bytes from the beginning after decoding, so by adding a synchronization byte ("0x47" in hexadecimal notation) to the beginning, the original 188 bytes can be easily added. This is because the TS packet of can be restored.

Data transmission efficiency can be improved by removing the synchronization bytes of the TS packet and encoding it. Therefore, even in Non-Patent Document 5, when the TS packet is transmitted, the synchronization byte is removed and the coding is performed.

Portable microwave band digital wireless transmission system standard for transmission of television broadcast program material (ARIB STD-B11 2.2 version), Association of Radio Industries and Businesses Portable OFDM system digital wireless transmission system standard for transmission of television broadcast program material (ARIB STD-B33 1.2 version), Association of Radio Industries and Businesses Portable millimeter-wave band digital wireless transmission system standard for transmission of television broadcast program material (ARIB STD-B43 1.0 version), Association of Radio Industries and Businesses 1.2GHz / 2.3GHz band Television broadcast program material transmission portable OFDM digital wireless transmission system standard (ARIB STD-B57 2.1 version), Association of Radio Industries and Businesses Transmission method standard for high-speed broadband satellite digital broadcasting (ARIB STD-B44 2.1 version), Association of Radio Industries and Businesses

Patent No. 4881355

On the other hand, in the digital FPU, as shown in FIG. 8, eight TS packets to be transmitted are set as one frame, and the synchronization byte of the first TS packet is inverted. Such a frame is called a data frame, and the inverted synchronization byte (“0xB8” in hexadecimal notation) is called a data frame synchronization byte.

In the digital FPU, it is desirable to maintain the structure of the data frame because the processing may be performed in units of the data frame or the data frame synchronization byte may be used as an auxiliary for synchronizing.

However, as shown in FIG. 9, if the synchronization bytes are removed in order to improve the data transmission efficiency, there is a problem that it becomes impossible to know where the data frame synchronization bytes are contained.

That is, the number of TS packets stored in one LDPC code block differs depending on the coding rate and may not be a multiple of 8, so that the data frame synchronization byte comes to the beginning of the LDPC code block every time. is not it.

In Patent Document 1, in which the LDPC code is used for both the external code and the internal code, the coding is performed while leaving all the synchronization bytes, so that the above-mentioned problems do not occur, but the data transmission is performed by the synchronization bytes. There is a problem that efficiency is reduced.

Further, the method of leaving only the data frame synchronization byte breaks the rule that the data frame is divided every 187 bytes, so that there is a problem that the synchronization byte itself cannot be restored.

Therefore, the present invention has been made to solve the above-mentioned problems, and is capable of preventing a decrease in data transmission efficiency and avoiding a situation in which the location of a data frame synchronization byte is unknown. The purpose is to provide equipment and programs.

The first feature of the present invention is a transmission device configured to transmit a TS packet containing a synchronization byte and data by a digital FPU so as to remove the synchronization byte from the TS packet. It is configured to add a header including information indicating the position of the first TS packet of the data frame including the eight TS packets to the configured synchronous byte removal unit and the LDPC code block containing the data. The header addition part to which the header is added, the BCH coding part configured to perform the BCH coding process on the LDPC code block to which the header is added, and the BCH coding process to be performed. The gist is to include an LDPC coding processing unit configured to perform LDPC coding processing on the LDPC code block.

The second feature of the present invention is a receiving device configured to receive a TS packet including synchronization bytes and data transmitted from the transmitting device according to the first feature described above, and the received TS. The LDPC decoding unit configured to perform the LDPC decoding process on the LDPC code block containing the packet, and the LDPC code block configured to perform the BCH decoding process on the LDPC code block subjected to the LDPC decoding process. Based on the BCH decoding unit and the header of the LDPC code block subjected to the BCH decoding process, it is configured to acquire the position of the first TS packet of the data frame including the eight TS packets. It is a gist to include a header analysis unit and a synchronization block restoration unit configured to restore the synchronization block based on the position.

A third feature of the present invention is a program for making a computer function as a transmitter according to the above-mentioned first feature.

A fourth feature of the present invention is a program for causing a computer to function as a receiving device according to the second feature described above.

According to the present invention, it is possible to provide a transmitting device, a receiving device, and a program that can prevent a situation in which the location of a data frame synchronization byte is unknown while preventing a decrease in data transmission efficiency.

FIG. 1 is a diagram showing an example of a functional block of the coding device 1 according to the first embodiment. FIG. 2 is a diagram showing an example of the operation of the coding device 1 and the decoding device 3 according to the first embodiment. FIG. 3 is a diagram showing an example of a header configuration used in the first embodiment. FIG. 4 is a diagram showing an example of a functional block of the decoding device 3 according to the first embodiment. FIG. 5 is a diagram for explaining the prior art. FIG. 6 is a diagram for explaining the prior art. FIG. 7 is a diagram for explaining the prior art. FIG. 8 is a diagram for explaining the prior art. FIG. 9 is a diagram for explaining the prior art.

(First Embodiment)
Hereinafter, the coding device 1 and the decoding device 3 according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 4.

Here, the coding device 1 and the decoding device 3 according to the present embodiment are configured to send and receive TS packets including synchronization bytes and data by a digital FPU.

In this embodiment, a case where an LDPC code having a coding rate of 1/2 as defined in Non-Patent Document 5 is used will be described as an example. The present invention is not limited to the case where numerical values such as the coding rate and code length of the LDPC code and the BCH code and the number of TS packets in the present embodiment are used.

As shown in FIG. 1, the coding device 1 according to the present embodiment includes a synchronous byte removing unit 11, a header adding unit 12, a BCH coding unit 13, an LDPC coding unit 14, and a modulation unit 15. It is equipped.

The synchronous byte removing unit 11 is configured to remove synchronous bytes from the TS packet.

As shown in FIG. 2A, each LDPC code block used in this embodiment may contain 15 TS packets. In the example of FIG. 2A, the third and eleventh TS packets in the LDPC code block are the first TS packets (hereinafter, the first packets) of the data frame including the eight TS packets.

Here, as shown in FIGS. 2A and 2B, the synchronization byte removing unit 11 removes synchronization bytes from each of the 15 TS packets, and 187 bytes of data # 1 to # 15 ( It is configured to acquire (22,440 bits) and transmit it to the header addition unit 12.

The header addition unit 12 is configured to add a header including information indicating the position of the first packet to the LDPC code block containing the data # 1 to # 15.

As shown in FIG. 2C, since the third and eleventh TS packets in the LDPC code block are the head packets, the header addition unit 12 indicates the position of the head packet with respect to the LDPC code block. It is configured to add a header containing information, that is, a 4-bit header indicating that the "third TS packet is the first packet".

In the example of FIG. 2C, such a header is arranged at the head of the LDPC code block, but if the position arranged between the transmitting device 1 and the receiving device is shared, the LDPC code block can be used. It may be placed in any position.

FIG. 3 shows an example of the above-mentioned 4-bit header configuration. Since the period of the data frame is the length of eight TS packets, any of the 1st to 8th TS packets in the LDPC code block is always the first packet. Therefore, in such a case, the position of the first packet can be indicated by the 3-bit header.

In the example of the present embodiment, since the LDPC code block includes 15 TS packets, there are always two leading packets in the LDPC code block. However, when the coding rate is not 1/2, for example, when only 7 or less TS packets are included in one LDPC code block, the first packet is included in one LDPC code block. It may exist if it is not.

Therefore, in the present embodiment, the above-mentioned header is composed of 4 bits, and as shown in FIG. 3, all the bits are set to "0" so that such a case can be dealt with.

The header may be composed of a part of the header including other information. For example, such a header may consist of 4 bits of a 16-bit header containing other information.

As shown in FIG. 2C, the LDPC code block to which the header is added has 22,444 bits, and the header addition unit 12 is configured to transmit the LDPC code block to the BCH coding unit. ..

The BCH coding unit 13 is configured to perform a BCH coding process using a BCH code as an external code on the LDPC code block transmitted by the header addition unit 12.

Further, the LDPC coding processing unit 14 is configured to perform LDPC coding processing using an LDPC code as an internal code on the LDPC code block subjected to the BCH coding processing.

As shown in FIG. 2D, when the LDPC code block subjected to the BCH coding process does not reach the specified 22,618 bits, the BCH coding process unit 13 has no information for adjustment. It is configured to insert stuff bits and shortening bits of.

Alternatively, when the LDPC code block input to the LDPC coding processing unit 14 does not reach the specified 22,618 bits, the LDPC coding processing unit 14 inserts such a stuff bit or a shortening bit. It may be configured.

The LDPC coding processing unit 14 is configured to transmit the LDPC code block subjected to the LDPC coding processing to the modulation unit 15.

FIG. 4 shows an example of the functional block of the decoding device 3 according to the first embodiment.

As shown in FIG. 4, the receiving device 3 according to the present embodiment includes a demodulation unit 30, an LDPC decoding unit 31, a BCH decoding unit 32, a header analysis unit 33, and a synchronous byte restoration unit 34. There is.

As shown in FIG. 2E, the LDPC decoding unit 31 is configured to perform an LDPC decoding process using an LDPC code as an internal code on the LDPC code block received from the demodulation unit 30.

Further, the BCH decoding unit 32 is configured to perform a BCH decoding process using a BCH code as an external code on the LDPC code block that has been subjected to the LDPC decoding process by the LDPC decoding unit 31.

Here, if the decoding process by the LDPC decoding unit 31 and the BCH decoding unit 32 is successful, all the errors generated in the transmission line are eliminated, and all 22,444 bits transmitted by the transmitting device 1 are correctly received by the receiving device 3. Can be done.

The header analysis unit 33 is configured to acquire the position of the first packet described above based on the header of the LDPC code block subjected to the BCH decoding process by the BCH decoding unit 32.

In the present embodiment, as shown in FIG. 2F, the header analysis unit 33 analyzes the 4-bit header included in the LDPC code block, and “the third TS packet is the first packet”. Can be determined.

The synchronization block restoration unit 34 is configured to restore the synchronization block based on the position of the first packet described above.

As shown in FIG. 2 (g), the synchronous block restoration unit 34 acquires the TS packet by dividing the LDPC code block into 187 bytes, and 3 in the LDPC coded block shown at the position of the first packet described above. The second TS packet is recognized as the first packet, and the synchronization byte of the TS packet is restored as a data frame synchronization byte (“0xB8” in hexadecimal notation).

Further, since the period of the data frame is the length of eight TS packets, the synchronization block restoration unit 34 recognizes that the eleventh TS packet in the LDPC coding block is the first packet, and takes the data frame. The synchronization byte of the TS packet is also configured to be restored as a data frame synchronization byte (“0xB8” in hexadecimal notation).

Since the number of TS packets contained in the LDPC-encoded block is 15, it can be seen that the first packet no longer exists in the LDPC-encoded block.

The synchronization block restoration unit 34 is configured to restore other TS packets as normal synchronization bytes (“0x47” in hexadecimal notation) for synchronization bytes.

According to the transmitting device 1 and the receiving device 3 according to the present embodiment, in the digital FPU, the synchronization byte of the TS packet is removed by adding a header with a small number of bits in one LDPC code block. The structure of the data frame can be restored while performing the coding process.

(Other embodiments)
As mentioned above, the invention has been described by the embodiments described above, but the statements and drawings that form part of the disclosure in such embodiments should not be understood as limiting the invention. Such disclosure will reveal to those skilled in the art various alternative embodiments, examples and operational techniques.

Further, although not particularly mentioned in the above-described embodiment, a program for causing a computer to execute each process performed by the above-mentioned transmitting device 1 and receiving device 3 may be provided. The program may also be recorded on a computer readable medium. Computer-readable media can be used to install such programs on computers. Here, the computer-readable medium on which such a program is recorded may be a non-transient recording medium. The non-transient recording medium is not particularly limited, but may be, for example, a recording medium such as a CD-ROM or a DVD-ROM.

Alternatively, a chip composed of a memory for storing a program for realizing at least a part of the functions in the transmission device 1 and the reception device 3 described above and a processor for executing the program stored in the memory may be provided. ..

Alternatively, at least a part of the functions in the transmission device 1 and the reception device 3 described above is an FPGA (Field-Programmable Gate Array) which is a kind of PLD (Programmable Logic Device) whose configuration can be set by a purchaser or a designer after manufacturing. It may be configured to be realized by an integrated circuit such as.

1 ... Transmission device 11 ... Synchronous byte removal unit 12 ... Header addition unit 13 ... BCH coding unit 14 ... LDPC coding unit 15 ... Modulation unit 3 ... Reception device 30 ... Demodulation unit 31 ... LDPC decoding unit 32 ... BCH decoding unit 33 ... Header analysis unit 34 ... Synchronous byte restoration unit

Claims (6)

A transmission device configured to transmit TS packets containing synchronous bytes and data by a digital FPU.
One data frame contains eight said TS packets.
The head of the data frame is the head of any of the eight TS packets.
The process of inverting the synchronization byte of the TS packet at the beginning of the data frame is performed.
A synchronous byte removing unit configured to remove the synchronous byte from the TS packet constituting the data frame, and a synchronous byte removing unit.
A header addition part configured to add a header including information indicating the position of the TS packet at the beginning of the data frame to the LDPC code block containing the data, and a header addition part.
A BCH coding unit configured to perform BCH coding processing on the LDPC code block to which the header is added, and a BCH coding unit.
A transmission device including an LDPC coding processing unit configured to perform LDPC coding processing on the LDPC code block subjected to the BCH coding processing. The header is composed of 4 bits .
The information is claimed to indicate any one of the 1st to 8th TS packets and one of the LDPC code blocks not including the first TS packet of the data frame. Item 1. The transmitting device according to item 1. A receiving device configured to receive a TS packet including synchronization bytes and data transmitted from the transmitting device according to claim 1.
One data frame contains eight said TS packets.
The head of the data frame is the head of any of the eight TS packets.
An LDPC decoding unit configured to perform LDPC decoding processing on the received LDPC code block including the TS packet, and an LDPC decoding unit.
A BCH decoding unit configured to perform BCH decoding processing on the LDPC code block subjected to the LDPC decoding processing, and a BCH decoding unit.
A header analysis unit configured to acquire the position of the TS packet at the beginning of the data frame based on the header of the LDPC code block subjected to the BCH decoding process.
It includes a synchronization block restorer configured to restore the synchronization bytes based on the position .
The synchronization block restoration unit is a receiving device that performs a process of inverting the synchronization byte of the TS packet at the beginning of the data frame. The header is composed of 4 bits .
The information is claimed to indicate any one of the 1st to 8th TS packets and one of the LDPC code blocks not including the first TS packet of the data frame. Item 3. The receiving device according to item 3. A program for causing a computer to function as the transmitter according to claim 1 or 2. A program for causing a computer to function as the receiving device according to claim 3 or 4.

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