JP6908240B2 - Nitride semiconductor transistor manufacturing method and nitride semiconductor transistor - Google Patents

Description

The present invention relates to a method for manufacturing a nitride semiconductor transistor and a nitride semiconductor transistor.

Patent Document 1 discloses a high electron mobility transistor (HEMT) using a GaN-based semiconductor. This HEMT includes a first GaN-based semiconductor layer and a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer and having a bandgap larger than that of the first GaN-based semiconductor layer. A source electrode and a train electrode are electrically connected to the second GaN-based semiconductor layer. A gate electrode is provided between the source electrode and the drain electrode. A first insulating film containing nitrogen having a film thickness of 0.2 nm or more and less than 2 nm is provided on the second GaN-based semiconductor layer between the source electrode and the drain electrode and the gate electrode. A second insulating film containing oxygen is provided on the first insulating film.

Japanese Unexamined Patent Publication No. 2016-143843

In recent years, HEMTs using nitride semiconductors such as GaN have been known. The HEMT has, for example, a channel layer, a barrier layer, and a cap layer which are epitaxially grown on a crystal growth substrate. A two-dimensional electron gas (2DEG) is formed at the interface with the barrier layer in the channel layer, and this two-dimensional electron gas functions as a channel layer.

An electron capture level (trap) is formed on the surface of the cap layer. When a drain bias is applied to the gate with a reverse bias applied, a surface leak current is generated from the drain electrode toward the gate electrode, but some of the electrons are captured at the electron capture level. The lifetime of the capture level (the time until the captured electrons are ejected) is on the order of microseconds, which is sufficiently longer than the on / off cycle depending on the application of HEMT. When an electron is captured at the electron capture level, the surface of the channel layer is maintained in a negatively charged state. This has the effect of narrowing the channel width between the gate and drain (widening the depletion region between the gate and drain), and the drain voltage gradually decreases when the on / off operation is repeated continuously. Such a phenomenon is called current coplus. In HEMTs using nitride semiconductors, reduction of current collapse is desired in order to realize higher speed operation.

The present invention has been made in view of such problems, and an object of the present invention is to provide a method for manufacturing a nitride semiconductor transistor capable of reducing current collapse and a nitride semiconductor transistor.

In order to solve the above-mentioned problems, in the method for manufacturing a nitride semiconductor transistor according to one embodiment, an epitaxial substrate is produced by sequentially growing a channel layer, a barrier layer, and a cap layer containing Ga in the composition on the substrate. The growth step, the immersion step of immersing the epitaxial substrate in a solution containing metal ions and adhering the metal ions on the surface of the cap layer, and the epitaxial substrate taken out from the solution and forming a silicon nitride film on the surface of the cap layer. It includes a film forming step of forming.

Further, the nitride semiconductor transistor according to the embodiment includes a substrate, a channel layer provided on the substrate, a barrier layer provided on the channel layer, and a cap provided on the barrier layer including Ga in the composition. A layer, a silicon nitride film provided on the cap layer, a source electrode and a drain electrode in contact with the barrier layer, a gate electrode provided between the source electrode and the drain electrode, and at least a gate electrode and a drain electrode. It comprises metal atoms arranged at a density in the range ^{of 1.0 × 10 11} cm- ^{2 to} 1.0 × 10 ¹² cm- ² at the interface between the cap layer and the silicon nitride film in the interstitial region.

According to the method for manufacturing a nitride semiconductor transistor and the nitride semiconductor transistor according to the present invention, current collapse can be reduced.

FIG. 1 is a cross-sectional view showing a high electron mobility transistor according to an embodiment. 2 (a) to 2 (c) are diagrams illustrating a method for manufacturing a high electron mobility transistor according to an embodiment. 3 (a) and 3 (b) are diagrams illustrating a method for manufacturing a high electron mobility transistor according to an embodiment. 4 (a) to 4 (c) are diagrams showing a method of manufacturing a high electron mobility transistor according to a comparative example. FIG. 5 is a graph showing the relationship between the gate-drain voltage and the surface leakage current in the high electron mobility transistor of one embodiment and the high electron mobility transistor of the comparative example. FIG. 6 is a graph plotting the magnitude of the gate-drain current that flows first when the drain bias and the gate bias are returned to the first state.

A method for manufacturing a nitride semiconductor transistor and a specific example of the nitride semiconductor transistor according to the embodiment of the present invention will be described below with reference to the drawings. It should be noted that the present invention is not limited to these examples, and is indicated by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims. In the following description, the same elements will be designated by the same reference numerals in the description of the drawings, and duplicate description will be omitted.

FIG. 1 is a cross-sectional view showing a high electron mobility transistor (hereinafter referred to as “HEMT”) according to the present embodiment. This HEMT1A is mainly composed of a nitride semiconductor. Specifically, HEMT1A includes a substrate 10, a channel layer 11, a barrier layer 12, a cap layer 13, a silicon nitride (SiN) film 16, a drain electrode 21, a source electrode 22, and a gate electrode 23. The channel layer 11, the barrier layer 12, and the cap layer 13 are provided on the substrate 10 in this order.

The substrate 10 is a substrate having a surface for crystal growth of the channel layer 11, the barrier layer 12, and the cap layer 13. The substrate 10 has semi-insulating properties. The substrate 10 is, for example, a SiC substrate. A buffer layer such as an AlN layer and / or an AlGaN layer for improving the crystallinity of the channel layer 11 may be provided between the substrate 10 and the channel layer 11.

The channel layer 11 is an electron traveling layer epitaxially grown on the substrate 10, and is composed of a group III-V nitride semiconductor such as GaN. The thickness of the channel layer 11 is, for example, 0.2 μm or more and 1.0 μm or less.

The barrier layer 12 is an electron supply layer epitaxially grown on the channel layer 11, and is composed of a group III-V nitride semiconductor having a bandgap larger than that of the channel layer 11, such as AlGaN. The thickness of the barrier layer 12 is, for example, 10 nm or more and 30 nm or less. The barrier layer 12 may be n-shaped.

The cap layer 13 is a layer epitaxially grown on the barrier layer 12, and is composed of a group III-V nitride semiconductor including Ga in the composition, for example, GaN. The thickness of the cap layer 13 is, for example, 3 nm or more and 10 nm or less. The cap layer 13 may be n-shaped. A natural oxide layer 14 is formed on the surface of the cap layer 13. Native oxide layer 14 is a GaO _X layer Ga contained in the cap layer 13 is formed by oxidation. The thickness of the natural oxide layer 14 is, for example, 0.5 nm or more and 2 nm or less.

The drain electrode 21 and the source electrode 22 are provided in a portion of the cap layer 13 from which a part has been removed. Each of the drain electrode 21 and the source electrode 22 is in contact with the surface of the barrier layer 12. Each of the drain electrode 21 and the source electrode 22 is an ohmic electrode, and has, for example, a laminated structure of a titanium (Ti) layer and an aluminum (Al) layer. In this case, the barrier layer 12 and the titanium layer come into contact with each other.

The gate electrode 23 is on the cap layer 13 and is provided between the drain electrode 21 and the source electrode 22. The gate electrode 23 has, for example, a laminated structure of a nickel (Ni) layer and a gold (Au) layer. The gate electrode 23 may be provided so as to be in contact with the surface of the barrier layer 12, or may be provided with the SiN film 16 sandwiched between the gate electrode 23 and the surface of the barrier layer 12.

The SiN film 16 is a film that protects the channel layer 11, the barrier layer 12, and the cap layer 13, and is provided on the cap layer 13 to cover the cap layer 13. The thickness of the SiN film 16 is, for example, 1 nm or more and 50 nm or less.

At least in the region between the drain electrode 21 and the gate electrode 23, a large number of metal atoms are placed at the interface between the cap layer 13 and the SiN film 16 (more specifically, the interface between the natural oxide layer 14 and the SiN film 16). There is a metal diffusion layer 15 containing. In this embodiment, the metal diffusion layer 15 exists between the drain electrode 21 and the source electrode 22. In the metal diffusion layer 15, the metal atoms are distributed at a density in the range ^{of, for example, 1.0 × 10 11} cm- ^{2 to} 1.0 × 10 ¹² cm- ^2. The magnitude of such density is a magnitude that can be detected by SIMS analysis. That is, in the metal diffusion layer 15, metal atoms are distributed in a plane (two-dimensionally) in a plane perpendicular to the stacking direction. The metal diffusion layer 15 increases the surface conductivity between the drain electrode 21 and the gate electrode 23, and increases the surface leakage current. The metal contained in the metal diffusion layer 15 is, for example, a refractory metal or a compound thereof, and is at least one of Ti, Ta, W, and TiW. As will be described later, the metal diffusion layer 15 is formed by adhering metal ions to the surface of the cap layer 13. However, the metal ion changes from an ionized metal to a metal when it dries after adhering to the surface of the cap layer 13.

In such HEMT1A, a two-dimensional electron gas (2DEG) is generated at the interface between the channel layer 11 and the barrier layer 12, so that the channel region 11a is formed at the interface with the barrier layer 12 in the channel layer 11. This channel region 11a serves as a current path, a current flows between the drain electrode 21 and the source electrode 22, and HEMT1A is turned on.

Subsequently, the method for producing HEMT1A according to the present embodiment will be described with reference to FIGS. 2 (a) to 2 (c) and FIGS. 3 (a) and 3 (b). 2 (a) to 2 (c), 3 (a), and 3 (b) are diagrams illustrating a method for producing HEMT1A according to the present embodiment.

First, the substrate 10 is prepared. The substrate 10 is put into a growth furnace, and as shown in FIG. 2A, the channel layer 11, the barrier layer 12, and the cap layer 13 are formed by, for example, the organic metal vapor phase epitaxy (OMVPE) method. It grows sequentially on the surface of the substrate 10 (growth step). By this step, an epitaxial substrate 2A including the substrate 10, the channel layer 11, the barrier layer 12, and the cap layer 13 is produced. When the channel layer 11 and the cap layer 13 are GaN layers, the raw materials thereof are, for example, TMG gas and NH ₃ gas. When the barrier layer 12 is an AlGaN layer, the raw materials thereof are, for example, TMA gas, TMG gas, and NH ₃ gas.

Then, the epitaxial substrate 2A is taken out from the growth furnace. At this time, since the surface of the epitaxial substrate 2A is exposed to the atmosphere, Ga is oxidized on the surface of the cap layer 13, a native oxide layer 14 is formed consisting of GaO _X.

Next, as shown in FIG. 2B, a water tank 30 containing the solution 31 containing metal ions is prepared. Then, the epitaxial substrate 2A is immersed in the solution 31 (immersion step). In this step, for example, another substrate 32 on which a metal film 32a, which is a base of metal ions, is formed on the surface is immersed in the solution 31 together with the epitaxial substrate 2A. At this time, the metal ions dissolved from the film 32a adhere (precipitate) on the surface of the cap layer 13. The metal ion is an ion of a refractory metal or a compound thereof, and the refractory metal is, for example, at least one of Ti, Ta, W, and TiW. The solution 31 is, for example, a persulfuric acid solution (generally, a mixed solution of hydrogen peroxide solution + sulfuric acid is referred to as persulfuric acid, caroic acid, adherent SPM treatment, etc.) or a dilute sulfuric acid solution. In this step, the epitaxial substrate 2A is immersed in the solution 31 until the metal surface density on the surface of the cap layer 13 is ^{within the range of 1.0 × 10 11} cm ^{-2 to} 1.0 × 10 ¹² cm ^-2. .. The metal surface density can be controlled by adjusting at least one of the number of substrates 32, the temperature of the solution 31, and the immersion time of the epitaxial substrate 2A. Then, the epitaxial substrate 2A is taken out from the solution 31. By this dipping step, as shown in FIG. 2C, the metal diffusion layer 15 is formed on the cap layer 13 (more accurately, on the natural oxide layer 14).

Subsequently, the epitaxial substrate 2A is taken out from the water tank 30, and the SiN film 16 is formed on the surface of the cap layer 13 as shown in FIG. 3A (film formation step). In this step, for example, the SiN film 16 is formed by plasma CVD.

Subsequently, a mask is formed on the SiN film 16 using a normal photolithography technique, and a part of the SiN film 16 and the cap layer 13 is etched. As a result, openings are formed in the SiN film 16 and the cap layer 13. Then, as shown in FIG. 3B, the source electrode 22 and the drain electrode 21 are formed on the barrier layer 12 exposed from the opening by, for example, a lift-off method. At the same time, the gate electrode 23 is formed on the SiN film 16 between the source electrode 22 and the drain electrode 21 (or on the cap layer 13 where the SiN film 16 is etched and exposed). Then, the source electrode 22 and the drain electrode 21 are alloyed by heating to realize ohmic contact with the barrier layer 12. Through the above steps, HEMT1A of the present embodiment is produced.

In the steps shown in FIGS. 3A to 3B, the SiN film 16, the drain electrode 21, the source electrode 22, and the gate electrode 23 may be formed in the following order. First, the natural oxide layer 14 in the region where the source electrode 22 and the drain electrode 21 are formed is removed, the source electrode 22 and the drain electrode 21 are formed on the region, and these are alloyed by heating to form a barrier layer 12. Achieve ohmic contact. Next, a SiN film 16 is formed on the barrier layer 12, the source electrode 22, and the drain electrode 21, and the cap layer is exposed on the SiN film 16 on the barrier layer 12 (or the SiN film 16 is etched and exposed). The gate electrode 23 is formed (on 13).

The effects obtained by the HEMT1A of the present embodiment and the method for producing the same described above will be described. 4 (a) to 4 (c) are diagrams showing a method for producing a HEMT according to a comparative example. In this comparative example, first, as shown in FIG. 4A, the epitaxial substrate 2A is produced in the same manner as in the present embodiment. As described above, when the epitaxial substrate 2A is taken out from the growth furnace, the natural oxide layer 14 is formed on the surface of the cap layer 13. Next, as shown in FIG. 4B, a SiN film 16 is formed on the surface of the cap layer 13. After that, an opening is formed in the SiN film 16 and the cap layer 13. Then, as shown in FIG. 4C, the source electrode 22 and the drain electrode 21 are formed on the barrier layer 12 exposed from the opening. At the same time, the gate electrode 23 is formed on the SiN film 16 between the source electrode 22 and the drain electrode 21. In this way, HEMT100 according to a comparative example is produced.

In such HEMT 100, an electron capture level (trap) is formed on the surface of the cap layer 13. The electron capture level is formed, for example, due to N omission of the GaN outermost layer when the cap layer 13 is grown, a deviation in the composition ratio of the GaN outermost layer due to variations in growth conditions, a natural oxide layer 14, and the like.

When a bias voltage is applied to the drain electrode 21 while a reverse bias voltage is applied to the gate electrode 23, a surface leak current is generated from the drain electrode 21 toward the gate electrode 23. Then, some of the electrons 17 are captured at the electron capture level. As a result, the channel width between the gate and the drain is narrowed, and when the on / off operation is repeated continuously, the drain voltage gradually decreases. Therefore, for example, when HEMT is used for signal amplification in a base station of a mobile phone, it affects the operation at high frequency and high output.

FIG. 5 is a graph showing the relationship between the gate-drain voltage and the surface leakage current in the HEMT1A of the present embodiment and the HEMT100 of the comparative example. This graph shows the surface flowing from the drain electrode 21 toward the gate electrode 23 when a bias (the drain side is high and the gate Schottky junction is in the reverse bias state) is applied between the gate and the drain with the source electrode 22 open. This is the result of measuring the leak current. In FIG. 5, the horizontal axis represents the gate-drain voltage (unit: V), and the horizontal axis represents the surface leakage current (unit: A / mm). Graph G1 shows the measurement result of HEMT1A of the present embodiment, and graph G2 shows the measurement result of HEMT100 of the comparative example.

With reference to FIG. 5, it can be seen that in the HEMT1A of the present embodiment, the surface leakage current is remarkably increased as compared with the HEMT100 according to the comparative example at any of the gate-drain voltages. In the production method of the present embodiment, as described above, the metal diffusion layer 15 is formed on the cap layer 13 by immersing the epitaxial substrate 2A in the solution 31 containing metal ions (FIG. 2B) (FIG. 2B). FIG. 2 (c). Further, in HEMT1A of the present embodiment, the metal diffusion layer 15 is provided on the cap layer 13. That is, metal atoms are arranged at the interface between the cap layer 13 and the SiN film 16 at least in the region between the gate electrode 23 and the drain electrode 21. It is considered that this metal atom increased the surface conductivity of HEMT1A and increased the surface leakage current.

Here, the following experiments were conducted on the HEMT1A of the present embodiment and the HEMT100 of the comparative example in order to confirm the influence of the current coplus. First, HEMT1A, 100 including an undoped GaN channel layer 11 having a thickness of 1000 nm, an AlGaN barrier layer 12 having a thickness of 20 nm, and a GaN cap layer 13 having a thickness of 5 nm were prepared. Then, the drain bias Vds was set to 50 V for both HEMT1A and 100, and the gate bias Vgs was set so that the drain current Id was 600 mA. At this time, the magnitudes of the gate bias Vgs in HEMT1A and 100 are different from each other. This state is referred to as the first state. Next, a gate bias Vgs was applied so that the drain current Id was substantially turned off. At this time, −5 V was applied as a sufficiently low (large in the negative direction) gate bias Vgs. Since the turn-on voltage Vth of the HEMT is usually about -3V, the gate bias Vgs may be a voltage lower than this. This state is referred to as the second state. Subsequently, the drain bias Vds and the gate bias Vgs were returned to the first state again.

FIG. 6 is a graph plotting the magnitude of the gate-drain current that first flows when the drain bias Vds and the gate bias Vgs are returned to the first state. The horizontal axis shows the gate-drain current (unit: A / mm), and the vertical axis shows the maximum pulse current (unit: mA / mm). Further, plots P1 and P2 show comparative examples, and plot P3 shows the present embodiment. With reference to FIG. 6, it is understood that in the present embodiment, the gate-drain current that initially flows when the state is returned to the first state is significantly larger than that of the comparative example. This result shows that the current coplus phenomenon is remarkably reduced from the comparative example in the present embodiment. This is considered to be due to the action described below.

In the first state of the first time, in the HEMT1A of the present embodiment in which the surface leakage current is large, the ratio of traps capturing electrons is large with respect to the HEMT100 of the comparative example in which the surface leakage current is small. On the contrary, in the HEMT100 of the comparative example in which the surface leakage current is small, the proportion of traps capturing electrons is smaller than that of the HEMT1A of the present embodiment in which the surface leakage current is large.

Then, even in the second state, the capture of electrons into the trap proceeds due to the surface leakage current. However, in the HEMT100 of the comparative example, since the proportion of traps that capture electrons in the first state before that is small, the proportion of traps that newly capture electrons is relatively large. Further, in the second state, since a large gate bias Vgs is applied in the negative direction, the Fermi level on the surface rises and the trap is newly depleted. This newly depleted trap also captures electrons from the surface leak current. In the HEMT100 of the comparative example, since the proportion of traps that capture electrons in the first state before that is small, the influence (negative charge) of the trap that newly captures electrons is compared with that of HEMT1A of the present embodiment. Appears prominently.

After that, when the gate bias Vgs is returned to the first state again, in the HEMT100 of the comparative example, the relative ratio of the traps newly trapped in the second state becomes large, so that the surface negative charge of this surface negative charge becomes large. The effect is large and the width of the channel is narrowed, resulting in a large current collapse. On the contrary, in HEMT1A of the present embodiment, since the relative ratio of the trap newly trapped in the second state becomes small, the influence of this surface negative charge becomes small, and the ratio of narrowing the channel width becomes small. It is suppressed and the current collapse is reduced.

As described above, according to the HEMT1A and the manufacturing method of the present embodiment, the current collapse can be effectively reduced. Therefore, it is possible to reduce variations in the operating characteristics of HEMT1A and improve reliability.

Further, as in the present embodiment, the density of metal atoms in the metal diffusion layer 15 may be in the range of ^{1.0 × 10 11} cm- ^{2 to} 1.0 × 10 ¹² cm- ^2. Further, in the dipping step, the epitaxial substrate 2A is immersed in the solution 31 until the metal density on the surface of the cap layer 13 is ^{within the range of 1.0 × 10 11} cm ^{-2 to} 1.0 × 10 ¹² cm ^-2. You may. When the metal density is 1.0 × 10 ¹² cm- ² or less, the withstand voltage defect can be suppressed and the pinch-off defect can be reduced. Further, when the metal density is 1.0 × 10 ¹¹ cm- ² or more, the collapse improving effect can be effectively obtained.

Further, as in the present embodiment, the metal ion may be an ion of a refractory metal or a compound thereof, and the solution 31 may be a perwater sulfuric acid solution or a dilute sulfuric acid solution. In particular, the refractory metal or a compound thereof may be at least one of Ti, Ta, W, and TiW. This is because the refractory metal can exist relatively stably in a solution 31 such as a hydrogen peroxide solution or a dilute sulfuric acid solution.

Further, as in the present embodiment, in the dipping step, the substrate 32 on which the metal film 32a which is the base of the metal ion is formed on the surface may be immersed in the solution 31 together with the epitaxial substrate 2A. Thereby, the metal ion can be contained in the solution 31 by a simple method. The metal ion may be contained in the solution 31 by another method.

1A ... HEMT, 2A ... epitaxial substrate, 10 ... substrate, 11 ... channel layer, 11a ... channel region, 12 ... barrier layer, 13 ... cap layer, 14 ... natural oxide layer, 15 ... metal diffusion layer, 16 ... SiN film, 17 ... electron, 21 ... drain electrode, 22 ... source electrode, 23 ... gate electrode, 30 ... water tank, 31 ... solution, 32 ... substrate, 32a ... metal film.

Claims (5)

A method for manufacturing nitride semiconductor transistors.
A growth step of sequentially growing a channel layer, a barrier layer, and a cap layer containing Ga in the composition on the substrate to prepare an epitaxial substrate.
A dipping step of immersing the epitaxial substrate in a solution containing metal ions and adhering the metal ions on the surface of the cap layer.
The epitaxial substrate was taken out, see containing and a film forming step of forming a silicon nitride film on a surface of the cap layer from said solution,
A method for producing a nitride semiconductor transistor, wherein the metal ion is at least one ion of Ti, Ta, W, and TiW. Before SL solution is hydrogen peroxide sulphate solution or dilute sulfuric acid solution, the method of manufacturing the nitride semiconductor transistor according to claim 1. The nitride semiconductor transistor according to claim 1 or 2 , wherein in the dipping step, another substrate having a metal film on the surface of which the metal film to be the base of the metal ion is formed is immersed in the solution together with the epitaxial substrate. Production method. In the dipping step, the epitaxial substrate is immersed in the solution until the metal density on the surface of the cap layer is ^{within the range of 1.0 × 10 11} cm- ^{2 to} 1.0 × 10 ¹² cm- ^2. , The method for manufacturing a nitride semiconductor transistor according to any one of claims 1 to 3. With the board
The channel layer provided on the substrate and
A barrier layer provided on the channel layer and
A cap layer containing Ga in the composition and provided on the barrier layer, and
A silicon nitride film provided on the cap layer and
The source electrode and drain electrode in contact with the barrier layer,
A gate electrode provided between the source electrode and the drain electrode,
Density within the range ^{of 1.0 × 10 11} cm- ^{2 to} 1.0 × 10 ¹² cm- ² at least at the interface between the cap layer and the silicon nitride film in the region between the gate electrode and the drain electrode. With the metal atoms arranged in
Bei to give a,
A nitride semiconductor transistor in which the metal atom is at least one of Ti, Ta, W, and TiW.

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