JP6910901B2 - AC / DC converter - Google Patents

Description

The invention disclosed herein relates to an AC / DC converter.

In recent years, an AC / DC converter capable of directly converting an AC input voltage into a DC output voltage has been proposed (see, for example, Patent Document 1 by the applicant of the present application).

JP-A-2017-99261

However, in the above-mentioned conventional AC / DC converter, there is room for further improvement in its power factor.

Therefore, the invention disclosed in the present specification aims to provide an AC / DC converter capable of improving the power factor in view of the above-mentioned problems found by the inventor of the present application.

The AC / DC converter disclosed in the present specification is connected in series with a primary winding to which an AC input voltage is applied, a secondary winding electromagnetically coupled to the primary winding, and the primary winding. A full-wave rectifying circuit that full-wave rectifies the bidirectional switch, the resonant capacitor connected in parallel to at least one of the bidirectional switch and the primary winding, the resonant inductance component, and the induced voltage generated in the secondary winding. A smoothing capacitor that smoothes the output of the full-wave rectifier circuit and a control circuit that turns the bidirectional switch on and off, and extracts both the forward voltage and the flyback voltage from the secondary winding. This is an AC / DC converter that directly converts the AC input voltage into a DC output voltage, and the control circuit is the bidirectional when the primary current flowing through the primary winding becomes larger than the overcurrent detection threshold. The overcurrent protection unit includes an overcurrent protection unit that forcibly turns off the switch, and the overcurrent protection unit includes an overcurrent detection threshold setting unit that lowers the overcurrent detection threshold as the load is lighter (first configuration). There is.

In the AC / DC converter having the first configuration, the control circuit sets the off timing of the bidirectional switch based on an error signal between the feedback signal corresponding to the DC output voltage and a predetermined reference signal. The overcurrent detection threshold setting unit may include an off-timing setting unit to set the overcurrent detection threshold by multiplying the error signal by a predetermined coefficient (second configuration).

Further, in the AC / DC converter having the second configuration, the coefficient may be a predetermined fixed value or a variable value according to the AC input voltage (third configuration).

Further, in the AC / DC converter having the second or third configuration, the off-timing setting unit includes an error amplifier that amplifies the difference between the feedback signal and the reference signal, and a first output terminal of the error amplifier. The node signal appearing at the second output end of the error amplifier, including the phase compensator connected to the error amplifier and the resistor connected between the first output end and the second output end of the error amplifier, causes the error. The configuration used as a signal (fourth configuration) may be used.

Further, in the AC / DC converter having any of the first to fourth configurations, the control circuit is based on a comparison result between a voltage across the bidirectional switch or a voltage dividing voltage thereof and a zero cross detection threshold value. It is preferable that the on-timing setting unit includes an on-timing setting unit for setting the on-timing of the bidirectional switch, and the on-timing setting unit includes a zero-cross detection threshold value setting unit that raises the zero-cross detection threshold value as the load is lighter (fifth configuration). ..

Further, in the AC / DC converter having the fifth configuration, the control circuit sets the off timing of the bidirectional switch based on an error signal between the feedback signal corresponding to the DC output voltage and a predetermined reference signal. The zero-cross detection threshold value setting unit may include an off-timing setting unit to set the zero-cross detection threshold value by multiplying the inverse number of the error signal by a predetermined coefficient (sixth configuration).

Further, the AC / DC converter having the fifth or sixth configuration has a configuration having a capacitance voltage dividing circuit for generating the voltage dividing voltage by capacitively dividing the voltage between both ends of the bidirectional switch (seventh configuration). ).

Further, in the AC / DC converter having any of the first to seventh configurations, the control circuit turns on the bidirectional switch when the AC input voltage or the voltage dividing voltage thereof is lower than the low input detection threshold value. The skip control unit may include a skip control unit that skips timing, and the skip control unit may include a low input detection threshold setting unit that raises the low input detection threshold as the load is lighter (eighth configuration).

Further, in the AC / DC converter having the eighth configuration, the control circuit sets the off timing of the bidirectional switch based on an error signal between the feedback signal corresponding to the DC output voltage and a predetermined reference signal. The low input detection threshold setting unit may include an off-timing setting unit to set the low input detection threshold by multiplying the inverse number of the error signal by a predetermined coefficient (nineth configuration).

Further, the control circuit disclosed in the present specification is a control main body of a switching power supply that generates an output voltage from an input voltage, and amplifies the difference between a feedback signal corresponding to the output voltage and a predetermined reference signal. The error amplifier, a phase compensation unit connected to the first output end of the error amplifier, and a resistor connected between the first output end and the second output end of the error amplifier include the error. The on-duty of the switching power supply is controlled based on the error signal appearing at the second output end of the amplifier (tenth configuration).

According to the invention disclosed in the present specification, it is possible to provide an AC / DC converter capable of improving the power factor (particularly, the power factor at the time of light load).

Circuit diagram showing the basic configuration (comparative example) of the AC / DC converter Circuit diagram showing the first modification of the AC / DC converter Circuit diagram showing a second modification of the AC / DC converter Equivalent circuit diagram of transformer Schematic diagram for explaining the relationship between the input / output ratio and the winding ratio of a transformer Schematic diagram showing the relationship between AC input voltage and operation mode Circuit diagram showing the current path during the switch-on period in the first operation mode Circuit diagram showing the current path during the switch-off period in the first operation mode Waveform diagram showing current behavior in the first operation mode Circuit diagram showing the current path during the switch-on period in the second operation mode Circuit diagram showing the current path during the switch-off period in the second operation mode Waveform diagram showing current behavior in the second operation mode A circuit diagram showing a first embodiment of an AC / DC converter Circuit diagram showing the first embodiment of the control circuit Timing chart showing the set signal generation operation Timing chart showing the generation operation of the overcurrent protection signal Timing chart showing load interlocking operation of overcurrent detection threshold Circuit diagram showing the second embodiment of the control circuit Circuit diagram showing a third embodiment of a control circuit Timing chart showing load-linked operation of zero cross detection threshold Circuit diagram showing a second embodiment of an AC / DC converter Circuit diagram showing a fourth embodiment of a control circuit Timing chart showing skip signal generation operation Timing chart showing load-linked operation with low input detection threshold

<Basic configuration (comparative example)>
FIG. 1A is a circuit diagram showing a basic configuration of an AC / DC converter (= corresponding to a comparative example compared with the embodiment described later). The AC / DC converter 1 of this configuration example electrically insulates between the primary circuit system 1p (GND1 system) and the secondary circuit system 1s (GND2 system), and the AC input voltage supplied from the AC power supply PW. It is a power supply device that directly converts Vi into DC output voltage Vo and supplies it to load Z. It is a transformer 10, a bidirectional switch 20, a resonance capacitor 30, a full-wave rectifier circuit 40, a smoothing capacitor 50, and a feedback circuit. It has 60, a control circuit 70, a sense resistor 80, a power fuse 90, and a filter circuit 100.

The transformer 10 includes a primary winding 11 provided in the primary circuit system 1p and a secondary winding 12 provided in the secondary circuit system 1s and magnetically coupled to the primary winding 11. The first tap T11 of the primary winding 11 is connected to the first end of the AC power supply PW via the filter circuit 100 and the power fuse 90. The second tap T12 of the primary winding 11 is connected to the second end of the AC power supply PW via the bidirectional switch 20, the sense resistor 80, and the filter circuit 100. The first tap T21 and the second tap T22 of the secondary winding 12 are respectively connected to the output end (= first end of the load Z) of the DC output voltage Vo via the full-wave rectifier circuit 40. The center tap T23 of the secondary winding 12 is connected to the secondary side common GND2 (= the second end of the load Z).

In particular, in the AC / DC converter 1 of this configuration example, a leakage transformer or a resonance transformer having a leakage inductance of 11x is used as the transformer 10 (the reason will be described later). In this figure, for convenience of illustration, the leakage inductance 11x is depicted as being attached to the first tap T11 side of the primary winding 11.

The first end of the bidirectional switch 20 is connected to the second tap T12 of the primary winding 11. The second end of the bidirectional switch 20 is connected to the first end of the sense resistor 80 and the primary side common GND1, respectively. The bidirectional switch 20 connected in this way functions as an output switch for turning on / off the primary current I1 flowing in the primary winding 11 according to the control signal Sctrl input from the control circuit 70.

The resonance capacitor 30 is connected in parallel to the bidirectional switch 20, and forms an LLC resonance circuit together with the primary winding 11 of the transformer 10 and the leakage inductance 11x. Therefore, even if excess energy that is not supplied from the primary winding 11 to the secondary winding 12 is generated due to the use of the leakage transformer or the resonant transformer as the transformer 10, it can be regenerated and used. It is not necessary to reduce the conversion efficiency of the / DC converter 1.

Further, by providing the resonance capacitor 30, the energy fluctuation of the transformer 10 when the bidirectional switch 20 is turned off becomes gentle. Therefore, a surge absorbing element such as a snubber circuit, which has been indispensable in the past, becomes unnecessary, and harmonic components can be reduced.

As shown in FIG. 1B, the connection position of the resonance capacitor 30 may be a configuration in which the resonance capacitor 30 is connected in series to the bidirectional switch 20 (= a configuration in which the resonance capacitor 30 is connected in parallel to the primary winding 11 of the transformer 10). However, as shown in FIG. 1C, the configuration may include both a resonance capacitor 30a connected in parallel to the bidirectional switch 20 and a resonance capacitor 30b connected in series to the bidirectional switch 20.

The full-wave rectifier circuit 40 is a circuit unit that full-wave rectifies the induced voltage (= flyback voltage or forward voltage, details will be described later) generated in the secondary winding 12, and includes diodes 41 and 42. The anode of the diode 41 is connected to the first tap T21 of the secondary winding 12. The anode of the diode 42 is connected to the second tap T22 of the secondary winding 12. Both the cathode of the diode 41 and the cathode of the diode 42 are connected to the output end of the DC output voltage Vo.

When the diode 41 is forward biased and the diode 42 is reverse biased, the secondary current I2 is generated in the current path from the first tap T21 of the secondary winding 12 to the output end of the DC output voltage Vo via the diode 41. It flows. On the other hand, when the diode 42 is forward biased and the diode 41 is reverse biased, the secondary current I2 is generated in the current path from the second tap T22 of the secondary winding 12 to the output end of the DC output voltage Vo via the diode 42. It flows.

Further, the full-wave rectifier circuit 40 may be made into a diode bridge after eliminating the center tap T23 of the secondary winding 12.

The smoothing capacitor 50 is connected between the output end of the DC output voltage Vo and the secondary side common GND2, and smoothes the output of the full-wave rectifier circuit 40 to generate the DC output voltage Vo.

The feedback circuit 60 generates a feedback signal Sfb corresponding to the DC output voltage Vo and outputs the feedback signal Sfb to the control circuit 70. In order to transmit the feedback signal Sfb from the secondary circuit system 1s to the primary circuit system 1p, an insulating transmission element such as a photocoupler may be used.

The control circuit 70 operates with the primary side common GND1 as a reference potential, and generates a control signal Sctrl for turning on / off the bidirectional switch 20. The control circuit 70 has a function of monitoring the feedback signal Sfb input from the feedback circuit 60 and turning on / off the bidirectional switch 20 so that the DC output voltage Vo matches a desired target value (= output feedback). It has a control function). By providing such a function, it is possible to stably supply a constant DC output voltage Vo to the load Z.

Further, the control circuit 70 monitors the sense voltage Vcs (= voltage signal corresponding to the primary current I1) appearing at the second end of the sense resistor 80, and bidirectionally so that the primary current I1 does not exceed a predetermined upper limit value. It has a function to turn on / off the switch 20 (= constant current control function). By providing such a function, an excessive primary current I1 does not flow in the primary circuit system 1p, so that the safety of the AC / DC converter 1 can be enhanced.

Further, the control circuit 70 has a function of monitoring the voltage between both ends of the resonance capacitor 30 (and the voltage between both ends of the bidirectional switch 20) and turning on the bidirectional switch 20 at the timing when the voltage value becomes 0V. (= ZVS [zero-volt switching] function) is provided. By providing such a function, the switching loss due to the parasitic capacitor and the resonance capacitor 30 of the bidirectional switch 20 can be reduced, so that the conversion efficiency of the AC / DC converter 1 can be improved.

Further, the control circuit 70 has a function (= power factor improving function) of monitoring the feedback signal Sfb and the sense voltage Vcs and turning on / off the bidirectional switch 20 so that the power factor approaches 1. By providing such a function, a separate power factor improving circuit is not required, so that a one-converter type AC / DC converter 1 can be realized. In order to improve the power factor improvement accuracy, it is desirable to monitor the AC input voltage Vi in the control circuit 70 as well.

The sense resistor 80 (resistance value: R80) is inserted in the current path through which the primary current I1 flows, and generates a sense voltage Vcs (= I1 × R80) corresponding to the primary current I1.

The power fuse 90 blows when a current exceeding the rating flows to protect the circuit in the subsequent stage.

The filter circuit 100 is wound in the same direction as the annular core and the X capacitor for reducing the differential mode noise (also called the normal mode noise) and the common mode filter for reducing the common mode noise (= circular core). Two coils) are included, and various noise components superimposed on the AC input voltage Vi are removed. The first input end of the filter circuit 100 is connected to the first end of the AC power supply PW via the power fuse 90. The second input end of the filter circuit 100 is connected to the second end of the AC power supply PW. The first output end of the filter circuit 100 is connected to the first tap T11 of the primary winding 11. The second output end of the filter circuit 100 is connected to the second end of the sense resistor 80.

FIG. 2 is an equivalent circuit diagram of the transformer 10. As shown in the upper part of this figure, when the coupling coefficient of the transformer 10 is K, the exciting inductance of the transformer 10 is represented by KL, and the leakage inductance of the transformer 10 is represented by (1-K) L.

Now, consider the case where the load R connected to the secondary side of the transformer 10 is 0Ω (when the AC / DC converter 1 is started, when the output is short-circuited, etc.). In this case, as shown in the middle part of this figure, both ends of the exciting inductance KL are short-circuited. Therefore, the equivalent inductance of the transformer 10 is represented as ^{(1-K 2) L as shown in the lower part of this figure.}

Here, when the coupling coefficient K of the transformer 10 is large (for example, when ^{K≈1), the equivalent inductance (1-K 2} ) L of the transformer 10 becomes almost 0. Therefore, an extremely large current flows through the transformer 10, which is not good.

Therefore, in the AC / DC converter 1 of this configuration example, a leakage transformer or a resonance transformer having a small coupling coefficient K (for example, K = 0.6 to 0.9) is used as the transformer 10. ^{With such a configuration, the equivalent inductance (1-K 2} ) L of the transformer 10 does not become too small even when the AC / DC converter 1 is started up or the output is short-circuited, so that the above problem can be solved. Is possible.

Further, as described above, since the leakage inductance 11x of the transformer 10 can also be used as a component of the LLC resonance circuit, it can contribute to the improvement of the conversion efficiency of the AC / DC converter 1.

Further, the leakage inductance 11x of the transformer 10 also functions as a choke coil. Therefore, in the case of the AC / DC converter 1 of this configuration example, the flyback method and the forward method can be used together even though the circuit configuration is the flyback method.

If a tightly coupled transformer (K = about 0.99) having a large coupling coefficient K is used as the transformer 10, the on-time of the bidirectional switch 20 during the forward operation becomes too short, so that the control circuit 70 Switching control by means of is very difficult. Therefore, from the viewpoint of control stability, it can be said that it is important to use a leakage transformer or a resonance transformer having a small coupling coefficient K as the transformer 10.

FIG. 3 is a schematic diagram for explaining the relationship between the input / output ratio and the winding ratio of the transformer 10. The number of turns of the primary winding 11 is n1, the number of turns of the secondary winding 12 (in this configuration example, the number of turns from the first tap T21 or the second tap T22 to the center tap T23) is n2, and the primary winding 11 is applied. When the voltage is V1 and the applied voltage of the secondary winding 12 is V2, the following equation (1) generally holds.

V2 = (n2 / n1) x V1 x K ... (1)

Here, in order to drive the transformer 10 using only the flyback method, it is necessary to satisfy the following equation (2). Note that V1max in the equation (2) indicates the maximum applied voltage of the primary winding 11.

n2 / n1 <V2 / (V1max × K)… (2)

On the other hand, in the AC / DC converter 1 of this configuration example, the flyback method and the forward method can be used in combination by establishing the following equation (3).

n2 / n1 ≧ V2 / (V1max × K)… (3)

FIG. 4 is a schematic diagram showing the correlation between the AC input voltage Vi (= applied voltage V1 of the primary winding 11) and the operation mode of the AC / DC converter 1. As shown in this figure, the operation mode of the AC / DC converter 1 of this configuration example is the first operation mode (voltage range) in which the flyback method is used independently according to the periodic fluctuation of the AC input voltage Vi. (See (1)) and the second operation mode (see voltage range (2)) in which the flyback method and the forward method are used together.

Specifically, when the threshold voltage ± Vth is set so that -V1max <-Vth <0 <+ Vth <+ V1max, flyback is performed in the voltage range (1) where -Vth <Vi <+ Vth. This is the first operation mode in which the method is used independently. On the other hand, in the voltage range (2) where −V1max ≦ Vi ≦ −Vth or + Vth ≦ Vi ≦ + V1max, the flyback method and the forward method are used in combination in the second operation mode.

FIG. 5 is a circuit diagram showing a current path during the switch-on period in the first operation mode (flyback method only). Since the primary current I1 flows through the primary circuit system 1p during the on period of the bidirectional switch 20, energy is stored in the primary winding 11. For example, when the AC input voltage Vi is positive (T11> T12), as shown by the thick solid arrow in this figure, the direction is AC power supply PW → primary winding 11 → bidirectional switch 20 → AC power supply PW. , Primary current I1 flows. On the other hand, no current flows through the secondary winding 12.

FIG. 6 is a circuit diagram showing a current path during the switch-off period in the first operation mode (flyback method only). During the off period of the bidirectional switch 20, an induced voltage (referred to here as a flyback voltage) is generated in the secondary winding 12 magnetically coupled to the primary winding 11, so that the secondary current I2 is generated in the secondary circuit system 1s. Flows. For example, when energy is stored in the primary winding 11 when the AC input voltage Vi is positive (T11> T12), the secondary winding 12 (as shown by the thick broken line arrow in this figure) The secondary current I2 flows in the direction of the second tap T22) → diode 42 → load Z → secondary winding 12 (center tap T23).

Further, when the bidirectional switch 20 is turned off, LLC resonance due to the resonance capacitor 30 occurs in the primary circuit system 1p. As a result, as shown by the thick solid arrow in this figure, the primary current I1 flows in the direction opposite to the immediately preceding switch-on period.

FIG. 7 is a waveform diagram showing the current behavior in the first operation mode (flyback method only). The solid line shows the primary current I1 and the broken line shows the secondary current I2. In addition, this figure describes the current behavior when the AC input voltage Vi is positive (T11> T12).

As shown in this figure, while the bidirectional switch 20 is turned on, the primary current I1 linearly increases with a positive inclination according to the inductance of the primary winding 11. After that, when the bidirectional switch 20 is turned off, the primary current I1 starts to decrease and further starts to flow in the negative direction.

On the other hand, the secondary current I2 does not flow while the bidirectional switch 20 is turned on, and greatly jumps up when the bidirectional switch 20 is turned off. As described above, in the first operation mode, the peak value of the secondary current I2 becomes relatively large as in the conventional flyback method. However, as shown in FIG. 4 above, the AC / DC converter 1 is in the first operation mode only during the period when −Vth <Vi <+ Vth, so that it does not pose a big problem.

FIG. 8 is a circuit diagram showing a current path during the switch-on period in the second operation mode (flyback method + forward method). During the ON period of the bidirectional switch 20, the primary current I1 flows through the primary circuit system 1p as in the first operation mode, so that energy is stored in the primary winding 11. For example, when the AC input voltage Vi is positive (T11> T12), as shown by the thick solid arrow in this figure, the direction is AC power supply PW → primary winding 11 → bidirectional switch 20 → AC power supply PW. , Primary current I1 flows.

Further, in the second operation mode, since an induced voltage (referred to as a forward voltage here) is generated in the secondary winding 12 during the on period of the bidirectional switch 20, a secondary current I2 flows in the secondary circuit system 1s. Specifically, as shown by the thick dashed arrow in this figure, the direction is secondary winding 12 (first tap T21) → diode 41 → load Z → secondary winding 12 (center tap T23). The next current I2 flows.

FIG. 9 is a circuit diagram showing a current path during the switch-off period in the second operation mode (flyback method + forward method). During the off period of the bidirectional switch 20, an induced voltage (= flyback voltage) is generated in the secondary winding 12 magnetically coupled to the primary winding 11 as in the first operation mode, so that the secondary circuit system 1s A secondary current I2 flows. Specifically, as shown by the thick broken line arrow in this figure, the direction is as follows: secondary winding 12 (second tap T22) → diode 42 → load Z → secondary winding 12 (center tap T23). A secondary current I2 flows.

Further, when the bidirectional switch 20 is turned off, LLC resonance due to the resonance capacitor 30 occurs in the primary circuit system 1p. As a result, as shown by the thick solid arrow in this figure, the primary current I1 flows in the direction opposite to the immediately preceding switch-on period. This point is also the same as the first operation mode described above.

FIG. 10 is a waveform diagram showing the current behavior in the second operation mode (flyback method + forward method). Similar to FIG. 7, the solid line shows the primary current I1 and the broken line shows the secondary current I2. Further, this figure also depicts the current behavior when the AC input voltage Vi is positive (T11> T12).

As shown in this figure, the behavior of the primary current I1 is basically the same as that of the first operation mode (FIG. 7). That is, the primary current I1 flows in the positive direction during the on period of the bidirectional switch 20, and flows in the negative direction during the off period of the bidirectional switch 20.

On the other hand, the behavior of the secondary current I2 is significantly different from that of the first operation mode (FIG. 7) in that it flows not only during the off period of the bidirectional switch 20 but also during the on period of the bidirectional switch 20. .. Further, as the secondary current I2 flows during the on period of the bidirectional switch 20, the energy stored in the primary winding 11 is reduced by that amount. As a result, it can be seen that the peak value of the secondary current I2 generated when the bidirectional switch 20 is turned off is suppressed lower than that in the first operation mode (FIG. 7).

As described above, if the AC / DC converter 1 uses both the flyback method and the forward method, both the forward voltage and the flyback voltage appearing in the secondary winding 12 can be taken out as outputs. Therefore, the drawback of the flyback method that the peak value of the secondary current I2 is large can be eliminated, and the AC input voltage Vi can be directly converted to the DC output voltage Vo with high efficiency even when medium or high power is applied.

<First Embodiment>
FIG. 11 is a circuit diagram showing a first embodiment of the AC / DC converter 1. The AC / DC converter 1 of the present embodiment is based on the above basic configuration (FIG. 1C), and has new features in the internal configuration and operation of the control circuit 70. Further, the AC / DC converter 1 of the present embodiment is newly provided with a capacitance voltage dividing circuit 150. Therefore, with respect to the same components as described above, duplicate explanations will be omitted by assigning the same reference numerals as those in FIG. 1C, and the feature portions of the present embodiment will be mainly described below.

First, prior to the description of the control circuit 70, the capacitance voltage dividing circuit 150 will be described. The capacitance voltage dividing circuit 150 is a circuit unit that generates a voltage dividing voltage Vsw by capacitively dividing the voltage V20 between both ends of the bidirectional switch 20, and includes capacitors 151 and 152 and a discharge switch 153.

The first end of each of the capacitor 151 and the discharge switch 153 is connected to the second end of the bidirectional switch 20 (= primary side common GND1 corresponding to the reference potential end of the control circuit 70). The second end of each of the capacitor 151 and the discharge switch 153 and the first end of the capacitor 152 are both connected to the output end of the voltage dividing voltage Vsw. The second end of the capacitor 152 is connected to the first end of the bidirectional switch 20 (= the second tap T12 of the primary winding 11).

In this way, the capacitors 151 and 152 are connected in series between both ends of the bidirectional switch 20, and the divided voltage Vsw is output from the connection nodes between the capacitors.

Now, when the capacitance value of the capacitor 151 is C151 and the capacitance value of the capacitor 152 is C152, the voltage dividing voltage Vsw is expressed by the following equation (4).

Vsw = V20 × C152 / (C151 + C152)… (4)

Therefore, if the capacitance values of the capacitors 151 and 152 are appropriately selected so that C152 << C151, it is possible to generate a voltage dividing voltage Vsw that falls within the input dynamic range of the control circuit 70.

During the resonance operation of the AC / DC converter 1 (= when the bidirectional switch 20 is off), the voltage V20 between both ends of the bidirectional switch 20 is generally as high as several hundred V to over 1000V. Therefore, it is difficult to directly input the voltage V20 between both ends of the bidirectional switch 20 to the control circuit 70 and monitor it.

On the other hand, as for the voltage dividing voltage Vsw generated by the capacitance voltage dividing circuit 150, the voltage value can be contained in the input dynamic range of the control circuit 70 as described above, so that the voltage value can be directly input to the control circuit 70. It becomes.

In particular, the waveform of the voltage V20 between both ends and the waveform of the divided voltage Vsw are similar to each other. Therefore, by monitoring the voltage dividing voltage Vsw in the control circuit 70, it is possible to appropriately detect the on-timing of the bidirectional switch 20.

Further, in the capacitance voltage divider circuit 150 of this configuration example, since a resistor that advances the phase of the detection signal is not used, a separate delay circuit is not required. In addition, there is no power loss in the resistor.

Further, since the capacitance voltage divider circuit 150 of this configuration example is provided separately from the resonance capacitors 30a and 30b, the voltage divider ratio can be arbitrarily set regardless of the capacitance value of the resonance capacitor 30.

The control circuit 70 that receives the input of the voltage dividing voltage Vsw has a soft switching function (= ZVS function) that turns on the bidirectional switch 20 at the timing when the voltage dividing voltage Vsw becomes 0V. By providing such a soft switching function, as described above, the switching loss due to the parasitic capacitor and the resonance capacitor 30 of the bidirectional switch 20 can be reduced, so that the conversion efficiency of the AC / DC converter 1 can be reduced. Can be increased.

The discharge switch 153 is connected in parallel to the capacitor 151. The discharge switch 153 is turned on / off in synchronization with the bidirectional switch 20 according to the control signal Sctrl from the control circuit 70. More specifically, the discharge switch 153 is turned on during the on period of the bidirectional switch 20 and turned off during the off period of the bidirectional switch 20.

That is, in the capacitance voltage divider circuit 150 of this configuration example, each time the bidirectional switch 20 is turned on, both ends of the capacitor 151 are short-circuited and the voltage divider voltage Vsw is initialized to 0V. Therefore, when the bidirectional switch 20 is switched from on to off, the voltage dividing voltage Vsw always changes starting from 0V.

As a result, in the control circuit 70, the voltage dividing voltage Vsw and a predetermined threshold voltage (0V or its vicinity value) are simply compared without considering the offset of the voltage dividing voltage Vsw due to the resonance operation. It is possible to detect the zero cross timing of the voltage dividing voltage Vsw (and thus the on-timing of the bidirectional switch 20) with high accuracy.

<Control circuit (first embodiment)>
FIG. 12 is a circuit diagram showing a first embodiment of the control circuit 70 (= an example of a circuit configuration suitable for the AC / DC converter 1 of the first embodiment). The control circuit 70 of this embodiment includes an on-timing setting unit 710, an off-timing setting unit 720, an RS flip-flop 730, and an overcurrent protection unit 740.

The on-timing setting unit 710 includes comparators 711 and 712, an AND gate 713, and a signal delay unit 714.

The comparator 711 compares the voltage dividing voltage Vsw input to the non-inverting input end (+) with the zero cross detection threshold value V11 input to the inverting input terminal (−) to generate a comparison signal S11. The comparison signal S11 has a high level when Vsw> V11 and a low level when Vsw <V11.

The comparator 712 compares the voltage dividing voltage Vsw input to the inverting input end (−) with the zero cross detection threshold value V12 (> V11) input to the non-inverting input end (+) to generate the comparison signal S12. The comparison signal S12 has a low level when Vsw> V12 and a high level when Vsw <V12.

The AND gate 713 generates the AND signal S13 of the comparison signals S11 and S12. The AND signal S13 becomes high level when both the comparison signals S11 and S12 are high level, and becomes low level when at least one of the comparison signals S11 and S12 is low level.

The signal delay unit 714 generates a set signal SET (= corresponding to the on-timing setting signal of the bidirectional switch 20) by delaying the pulse edge of the AND signal S13 by a predetermined delay time τ.

FIG. 13 is a timing chart showing the generation operation of the set signal SET in the on-timing setting unit 710, in which the voltage dividing voltage Vsw, the comparison signals S11 and S12, the AND signal S13, and the set signal SET are drawn in this order from the top. Has been done.

In this figure, the voltage dividing voltage Vsw is set to a sine wave voltage based on 0V, and the zero cross detection thresholds V11 and V12 are set to fixed values (however, V11 <0V <V12).

At time t11, when the voltage dividing voltage Vsw becomes higher than the zero cross detection threshold value V11, the comparison signal S11 rises to a high level. Further, at this point, the voltage dividing voltage Vsw is lower than the zero cross detection threshold value V12, so that the comparison signal S12 is maintained at a high level. Therefore, since both the comparison signals S11 and S12 are at a high level, the AND signal S13 rises to a high level. However, at this point, since the delay time τ has not elapsed, the set signal SET remains maintained at the low level.

When the delay time τ elapses from the time t11, the set signal SET rises to a high level at the time t12. As a result, the control signal Sctrl (not shown) is set to a high level, so that the bidirectional switch 20 is turned on. Therefore, if the time required for the voltage dividing voltage Vsw to rise from the zero cross detection threshold value V11 to 0V is set as the delay time τ, soft switching (ZVS) of the bidirectional switch 20 can be realized.

At time t13, when the voltage dividing voltage Vsw becomes higher than the zero cross detection threshold value V12, the comparison signal S12 falls to a low level, so that the logical product signal S13 also falls to a low level. In this figure, the set signal SET is also lowered to the low level without delay in response to the fact that the AND signal S13 is lowered to the low level, but the falling timing is not limited to this. Instead, for example, the set signal SET may be lowered to a low level when the delay time τ has elapsed from the time t13.

After that, the voltage dividing voltage Vsw changes from rising to falling, and when the voltage dividing voltage Vsw becomes lower than the zero cross detection threshold value V12 at time t14, the comparison signal S12 falls to a low level. Further, at this point, the voltage dividing voltage Vsw is higher than the zero cross detection threshold value V11, so that the comparison signal S11 is maintained at a high level. Therefore, since both the comparison signals S11 and S12 are at a high level, the AND signal S13 rises to a high level. However, at this point, since the delay time τ has not elapsed, the set signal SET remains maintained at the low level.

When the delay time τ elapses from the time t14, the set signal SET rises to a high level at the time t15. As a result, the control signal Sctrl (not shown) is set to a high level, so that the bidirectional switch 20 is turned on. Therefore, if the time required for the voltage dividing voltage Vsw to drop from the zero cross detection threshold value V12 to 0V is set as the delay time τ, soft switching (ZVS) of the bidirectional switch 20 can be realized.

At time t16, when the voltage dividing voltage Vsw becomes lower than the zero cross detection threshold value V11, the comparison signal S11 falls to a low level, so that the logical product signal S13 also falls to a low level. In this figure, the set signal SET is also lowered to the low level without delay in response to the fact that the AND signal S13 is lowered to the low level, but the falling timing is not limited to this. Instead, for example, the set signal SET may be lowered to a low level when the delay time τ has elapsed from the time t16.

After the time t16, when the voltage dividing voltage Vsw changes from falling to rising, the same behavior as described above is repeated, and the set signal SET generation operation by the on-timing setting unit 710 is continued.

As described above, according to the on-timing setting unit 710 having the above configuration, the soft switching (ZVS) of the bidirectional switch 20 is based on the comparison result between the voltage dividing voltage Vsw which fluctuates in both positive and negative directions and the zero cross detection thresholds V11 and V12. ) Can be appropriately set, so that the conversion efficiency of the AC / DC converter 1 can be improved.

Returning to FIG. 12, the description of the components of the control circuit 70 will be continued. The off-timing setting unit 720 includes an oscillator 721, an error amplifier 722, a phase compensation unit 723, a comparator 724, and an OR gate 725.

The oscillator 721 generates a sawtooth slope signal SLP. For example, the oscillator 721 starts ascending the slope signal SLP at the rising timing of the control signal Sctrl input to the set end (S), while the slope signal is started at the rising timing of the reset signal RST input to the reset end (R). Reset the SLP to zero.

The error amplifier 722 is a current output type transmission amplifier (so-called gm amplifier), and has a feedback signal Sfb input to the inverting input end (-) and a reference signal Vref input to the non-inverting input end (+). The difference value is amplified and the error signal ERR is output. The error signal ERR becomes higher as the difference value between the feedback signal Sfb and the reference signal Vref is larger, and conversely becomes lower as the difference value between the feedback signal Sfb and the reference signal Vref is smaller. When paying attention to the relationship between the weight of the load and the error signal ERR, the error signal ERR becomes higher as the load is heavier, and conversely becomes lower as the load is lighter.

The phase compensation unit 723 includes a capacitor 723a and a resistor 723b connected in series between the output end of the error amplifier 722 and the primary side common GND1, and performs phase compensation of the error signal ERR so that the error amplifier 722 does not oscillate.

The cutoff frequency fc of the phase compensation unit 723 is usually set to several hundred Hz to several kHz in many cases. On the other hand, in the control circuit 70 of this embodiment, the cutoff frequency fc is set to a value (several Hz) lower than usual in order to bring the power factor of the AC / DC converter 1 closer to 1.

The comparator 724 compares the slope signal SLP input to the non-inverting input end (+) with the error signal ERR input to the inverting input terminal (−) to generate a comparison signal CMP. The comparison signal CMP has a low level when SLP <ERR and a high level when SLP> ERR.

The OR gate 725 generates a logical sum signal of the comparison signal CMP and the overcurrent protection signal OCP, and outputs this as a reset signal RST (= corresponding to the off-timing setting signal of the bidirectional switch 20). The reset signal RST becomes low level when both the comparison signal CMP and the overcurrent protection signal OCP are low level, and becomes high level when at least one of the comparison signal CMP and the overcurrent protection signal OCP is high level. ..

When the overcurrent protection signal OCP is at a low level (= logic level at normal time), the rise timing of the reset signal RST (= off timing of the bidirectional switch 20) becomes faster as the error signal ERR becomes lower, and vice versa. In addition, the higher the error signal ERR, the slower it becomes.

As described above, according to the off-timing setting unit 720 having the above configuration, the off-timing of the bidirectional switch 20 is set based on the error signal ERR corresponding to the difference value between the feedback signal Sfb and the predetermined reference signal Vref. be able to.

The RS flip-flop 730 is a logic of a control signal Sctrl output from an output end (Q) according to a set signal SET input to the set end (S) and a reset signal RST input to the reset end (R). Determine the level. More specifically, the RS flip-flop 730 sets the control signal Sctrl to a high level at the rising timing of the set signal SET, while resetting the control signal Sctrl to a low level at the rising timing of the reset signal RST, for example.

The overcurrent protection unit 740 includes an overcurrent detection threshold setting unit 741, comparators 742 and 743, and an OR gate 744.

The overcurrent detection threshold setting unit 741 multiplies the error signal ERR by a coefficient ± α to set the overcurrent detection thresholds V21 and V22 (for example, V21 = + αERR, V22 = −αERR). As mentioned earlier, the error signal ERR becomes lower as the load is lighter. Therefore, in the overcurrent detection threshold setting unit 741, the lighter the load, the lower the absolute values of the overcurrent detection thresholds V21 and V22, respectively. In particular, if the error signal ERR is multiplied by a coefficient ± α to set the overcurrent detection thresholds V21 and V22, the overcurrent detection threshold setting unit 741 can be easily implemented. The load interlocking operation of the overcurrent detection thresholds V21 and V22 will be described in detail later.

The comparator 742 compares the sense voltage Vcs input to the non-inverting input end (+) with the overcurrent detection threshold value V21 input to the inverting input terminal (−) to generate a comparison signal S21. The comparison signal S21 has a high level when Vcs> V21 and a low level when Vcs <V21. The operation of comparing the sense voltage Vcs and the overcurrent detection threshold value V21 is an operation of determining whether or not the primary current I1 (> 0) flowing in the positive direction is larger than the positive overcurrent detection threshold value + Iocp (> 0). Is equivalent to.

The comparator 743 compares the sense voltage Vcs input to the inverting input end (−) with the overcurrent detection threshold V22 (<V21) input to the non-inverting input end (+) to generate the comparison signal S22. The comparison signal S22 has a low level when Vcs> V22 and a high level when Vcs <V22. The comparison operation between the sense voltage Vcs and the overcurrent detection threshold value V22 determines whether or not the primary current I1 (<0) flowing in the negative direction is larger than the negative overcurrent detection threshold value −Iocp (<0). Equivalent to operation.

The OR gate 744 generates a logic sum signal of the comparison signals S21 and S22, and outputs this as an overcurrent protection signal OCP. The overcurrent protection signal OCP becomes low level when both the comparison signals S21 and S22 are low level, and becomes high level when at least one of the comparison signals S21 and S22 is high level.

FIG. 14 is a timing chart showing the operation of generating the overcurrent protection signal OCP in the overcurrent protection unit 740, and the sense voltage Vcs, the comparison signals S21 and S22, and the overcurrent protection signal OCP are depicted in order from the top. There is.

In this figure, the sense voltage Vcs will be a sinusoidal voltage based on 0V, and the overcurrent detection thresholds V21 and V22 will be described as variable values (V21 = + αERR, V22 = −αERR) according to the error signal ERR, respectively.

At time t21, when the sense voltage Vcs becomes higher than the overcurrent detection threshold value V22, the comparison signal S22 drops to a low level. Further, at this time point, since the sense voltage Vcs is lower than the overcurrent detection threshold value V21, the comparison signal S21 is maintained at a low level. Therefore, since both the comparison signals S21 and S22 are at the low level, the overcurrent protection signal OCP falls to the low level. As a result, the forced off of the bidirectional switch 20 is released.

At time t22, when the sense voltage Vcs becomes higher than the overcurrent detection threshold value V21, the comparison signal S21 rises to a high level, so that the overcurrent protection signal OCP also rises to a high level. As a result, the bidirectional switch 20 is forcibly turned off.

After that, when the sense voltage Vcs changes from rising to falling and the sense voltage Vcs becomes lower than the overcurrent detection threshold value V21 at time t23, the comparison signal S21 falls to a low level. Further, at this time point, since the sense voltage Vcs is higher than the overcurrent detection threshold value V22, the comparison signal S22 is maintained at a low level. Therefore, since both the comparison signals S21 and S22 are at the low level, the overcurrent protection signal OCP falls to the low level. As a result, the forced off of the bidirectional switch 20 is released.

At time t24, when the sense voltage Vcs becomes lower than the overcurrent detection threshold value V22, the comparison signal S22 rises to a high level, so that the overcurrent protection signal OCP also rises to a high level. As a result, the bidirectional switch 20 is forcibly turned off.

After the time t24, when the sense voltage Vcs changes from falling to rising, the same behavior as described above is repeated, and the overcurrent protection signal OCP generation operation by the overcurrent protection unit 740 is continued.

As described above, according to the overcurrent protection unit 740 having the above configuration, when the positive / negative primary current I1 flowing through the primary winding 11 of the transformer 10 becomes larger than the predetermined overcurrent detection threshold ± Iocp, it is bidirectional. The switch 20 can be forcibly turned off.

As shown by the white arrows in this figure, the overcurrent detection thresholds V21 and V22 (and thus the overcurrent detection threshold ± Iocp) correspond to the error signal ERR (and the weight of the load). It is a variable value. Hereinafter, such a load interlocking operation of the overcurrent detection threshold ± Iocp will be described in detail.

FIG. 15 is a timing chart showing the load interlocking operation of the overcurrent detection threshold ± Ioc, in order from the top, the AC input voltage Vi, the primary current I1 when the overcurrent detection threshold ± Iocp is a fixed value, and The primary current I1 when the overcurrent detection threshold ± Iopp is a variable value is depicted.

Regarding the primary current I1, the thin solid line and the broken line indicate the ideal waveforms (power factor = 1) under heavy load and light load, respectively. On the other hand, the thick solid line and the broken line indicate the actual waveforms (power factor ≠ 1) under heavy load and light load, respectively.

In addition, as shown by the white arrows in the lower part of this figure, the overcurrent detection threshold ± Iocp that fluctuates in conjunction with the load is set to ± IocpH under heavy load and ± IocpL under light load. As you can see, each is described separately.

In this figure, at times t31 to t32, times t33 to t34, and times t35 to t36, −Vth <Vi <+ Vth. Therefore, in each period, the AC / DC converter 1 enters the first operation mode (1) using only the flyback method.

At this time, the magnitude of the primary current I1 is determined by the on-duty control (on-time control) based on the error signal ERR according to the voltage value of the AC input voltage Vi and the L value of the transformer 10. In particular, if the cutoff frequency fc of the phase compensation unit 723 is appropriately set, the power factor in the first operation mode (1) can be brought close to 1.

On the other hand, in this figure, Vi> + Vth at times t32 to t33, and Vi <−Vth at times t34 to t35. Therefore, in each period, the AC / DC converter 1 enters the second operation mode (2) in which both the flyback method and the forward method are used in combination. As a result, the drawbacks of the flyback method can be eliminated, and the AC input voltage Vi can be directly converted to the DC output voltage Vo with high efficiency even when medium or high power is applied.

However, in the second operation mode (2), the peak value of the primary current I1 is higher than that in the first operation mode (1), and its rise and fall are steeper. Therefore, the primary current I1 reaches the overcurrent detection threshold ± Iocp before the bidirectional switch 20 is turned off by the on-duty control based on the error signal ERR, and the primary current I1 is limited.

Here, when the overcurrent detection threshold ± Iocp is a fixed value, as shown in the middle part of this figure, in the second operation mode (2), the actual waveform (thick line) and the ideal waveform of the primary current I1. Since the similarity with (thin line) is broken, the power factor deteriorates. In particular, when the load is light (broken line), the deviation between the peak value of the ideal waveform and the overcurrent detection threshold ± Iocp becomes large, so that the deterioration of the power factor becomes more remarkable.

On the other hand, in the AC / DC converter 1 of the present embodiment, the overcurrent detection threshold ± Iocp is set to a variable value according to the error signal ERR (and thus the weight of the load). More specifically, as the load is heavier, the error signal ERR increases, so that the absolute value of the overcurrent detection threshold ± Iocp increases (see ± IocpH in the lower part of this figure). On the contrary, the lighter the load, the lower the error signal ERR, so that the absolute value of the overcurrent detection threshold ± Iocp becomes smaller (see ± IocpL in the lower part of this figure).

By performing the load interlocking operation of the overcurrent detection threshold ± Iocp in this way, the power factor in the second operation mode (2) can be brought close to 1 regardless of the weight of the load.

Further, in both the first operation mode (1) and the second operation mode (2), the peak value of the primary current I1 can be suppressed to the optimum value according to the load (for example, the peak value of the ideal waveform), so that AC This also leads to an improvement in the efficiency of the / DC converter 1.

In this figure, the coefficient α multiplied by the error signal ERR is set as a fixed value, and the overcurrent detection threshold ± IocpH and ± IocpL are uniquely set according only to the weight of the load. α may be, for example, a variable value according to the AC input voltage Vi. By making such changes, the overcurrent detection thresholds ± IocpH and ± IocpL change with the same behavior as the AC input voltage Vi, so the actual waveform (thick line) and ideal waveform (thin line) of the primary current I1 It is possible to further enhance the similarity with the above, and by extension, it is possible to further improve the power factor in the second operation mode (2).

<Control circuit (second embodiment)>
FIG. 16 is a circuit diagram showing a second embodiment of the control circuit 70. The control circuit 70 of the second embodiment is based on the first embodiment (FIG. 12), and the circuit configuration of the off-timing setting unit 720 has been changed.

More specifically, in the off-timing setting unit 720 of this embodiment, the error amplifier 722 is provided with a first output end (1) and a second output end (2), and the first output end (1) thereof. ) And the second output terminal (2), a resistor 726 (resistance value: R) is newly newly connected. The above-mentioned phase compensation unit 723 is connected between the first output terminal (1) of the error amplifier 722 and the primary side common GND1.

In the following, the node signals appearing at the first output terminal (1) and the second output end (2) of the error amplifier 722 will be described separately as error signals ERR and ERR2, respectively.

The first output end (1) and the second output end (2) of the error amplifier 722 both output in-phase output currents Iout. For example, when the feedback signal Sfb decreases and the difference value from the reference signal Vref increases, the output current Iout of the error amplifier 722 increases, so that both the error signals ERR and ERR2 increase.

However, there is a significant difference in the rate of increase between the two when the load fluctuates. Specifically, the error signal ERR gradually rises via the phase compensation unit 723. On the other hand, the error signal ERR2 rises sharply by the potential difference (= Iout × R) appearing between both ends of the resistor 726.

Here, the error signal ERR2 is input to the comparator 724 in the subsequent stage instead of the error signal ERR. Therefore, the response speed of the output feedback loop to the load fluctuation is increased as compared with the first embodiment (FIG. 12). As a result, the load response characteristics of the AC / DC converter 1 can be improved, so that, for example, overshoot and undershoot of the DC output voltage Vo due to load fluctuation can be suppressed.

The error signal ERR2 is also input to the overcurrent detection threshold setting unit 741 of the overcurrent protection unit 740. Therefore, it is possible to enhance the load response characteristic of the load interlocking operation of the overcurrent detection threshold ± Iocp.

Further, when the load fluctuation disappears, the error signals ERR and ERR2 converge to the same value. That is, the response speed of the output feedback loop increases only when the load fluctuates, and the stability of the output feedback loop is not impaired.

The off-timing setting unit 720 of this embodiment can be applied not only to the AC / DC converter 1 but also to a general switching power supply that generates an output voltage from an input voltage.

<Control circuit (third embodiment)>
FIG. 17 is a circuit diagram showing a third embodiment of the control circuit 70. The control circuit 70 of the third embodiment is based on the second embodiment (FIG. 16), and the circuit configuration of the on-timing setting unit 710 has been changed.

More specifically, the on-timing setting unit 710 of this embodiment includes a zero cross detection threshold value setting unit 715. The zero-cross detection threshold setting unit 715 multiplies the reciprocal of the error signal ERR by a coefficient ± β to set the zero-cross detection thresholds V11 and V12 (for example, V11 = −β / ERR, V12 = + β / ERR).

As described above, the error signal ERR becomes lower as the load is lighter. Therefore, in the zero-cross detection threshold setting unit 715, the lighter the load, the higher the absolute values of the zero-cross detection thresholds V11 and V12, respectively.

FIG. 18 is a timing chart showing load interlocking operations of the zero cross detection thresholds V11 and V12, and the voltage dividing voltage Vsw, the comparison signals S11 and S12, the AND signal S13, and the set signal SET are depicted in order from the top. ing.

The timing chart of this figure is basically the same as that of FIG. 13, but as shown by the white arrows in the figure, the zero cross detection thresholds V11 and V12 are error signals ERR (and thus the weight of the load). ) Is a variable value.

Generally, the lighter the load, the lower the peak value of the voltage dividing voltage Vsw, and it becomes difficult for the voltage dividing voltage Vsw to cross the zero cross detection thresholds V11 and V12. In such a situation, the set signal SET does not rise to a high level, and the on-timing of the bidirectional switch 20 may be missed, so that the DC output voltage Vo tends to become unstable.

Therefore, in the control circuit 70 of this embodiment, the lighter the load, the higher the absolute values of the zero cross detection thresholds V11 and V12, respectively. As a result, when the load is light, even if the peak value of the voltage dividing voltage Vsw becomes low, the voltage dividing voltage Vsw easily crosses the zero cross detection threshold values V11 and V12, so that the on-timing of the bidirectional switch 20 is not missed. .. On the other hand, when the load is heavy, the absolute values of the zero cross detection thresholds V11 and V12 are lowered, so that the detection accuracy of the zero cross timing can be improved.

In this embodiment, the second embodiment (FIG. 16) is used as the base, but the first embodiment (FIG. 12) may be used as the base.

<Second Embodiment>
FIG. 19 is a circuit diagram showing a second embodiment of the AC / DC converter 1. The AC / DC converter 1 of the present embodiment is based on the first embodiment (FIG. 11) described above, and some modifications have been made. Therefore, the same components as those described above will be designated by the same reference numerals as those in FIG. 11, and duplicated explanations will be omitted. Hereinafter, the feature portions of the present embodiment will be mainly described.

As a first change, the AC / DC converter 1 of the present embodiment further includes an AC voltage dividing unit 170. The AC voltage divider 170 includes resistors 171 and 172 (resistance values R171 and R172) connected in series between the output end (= application end of the AC input voltage Vi) of the filter circuit 100 and the primary side common GND1. From those connection nodes, the AC voltage dividing voltage Vac (= Vi × {R172 / (R171 + R172)}) of the AC input voltage Vi is output. The control circuit 70 receives the input of the AC voltage dividing voltage Vac and determines whether or not to skip the on-timing of the bidirectional switch 20. This skip control will be described in detail later.

Next, as a second change, in the AC / DC converter 1 of the present embodiment, the inductance transformer or the resonance transformer is not used as the transformer 10, and the center tap T23 of the secondary winding 12 and the secondary side common are used. A coil 120 is connected to the GND2 as an element corresponding to the resonance inductance component (the leakage inductance 11x above).

By adopting such a configuration, the same operations and effects as those of the above basic configuration (FIGS. 1A to 1C) and the first embodiment (FIG. 11) can be enjoyed, so that when medium or high power is applied, It is also possible to directly convert the AC input voltage Vi into the DC output voltage Vo with high efficiency.

Further, in the AC / DC converter 1 of the present embodiment, in the second operation mode (flyback method + forward method), the secondary current I2 in the off period of the bidirectional switch 20 can be further reduced. Moreover, the secondary current I2 during the ON period of the bidirectional switch 20 can be further increased.

In particular, in the case of the AC / DC converter 1 of the present embodiment, in the second operation mode (flyback method + forward method), the secondary current I2 during the ON period of the bidirectional switch 20 does not fall below 0A. Therefore, the secondary circuit system 1s can be operated in the current continuous mode.

The coil 120 is located between the first tap T11 of the primary winding 11 and the output end of the filter circuit 100, the first tap T21 to the second tap T22 of the secondary winding 12, and the input end of the full-wave rectifier circuit 40. It is also conceivable to connect between the output end of the full-wave rectifier circuit 40 and the output end of the DC output voltage Vo. However, in order to enjoy the above effect to the maximum, it is found from the simulation that it is desirable to connect the coil 120 between the center tap T23 of the secondary winding 12 and the secondary common GND2. ing.

<Control circuit (4th embodiment)>
FIG. 20 is a circuit diagram showing a fourth embodiment of the control circuit 70 (= an example of a circuit configuration suitable for the AC / DC converter 1 of the second embodiment). The control circuit 70 of this embodiment is based on the first embodiment (FIG. 12) described above, and a skip control unit 750 is newly added separately.

The skip control unit 750 includes a low input detection threshold setting unit 751, comparators 752 and 753, and a NAND gate 754.

The low input detection threshold setting unit 751 sets the low input detection thresholds V31 and V32 (for example, V31 = −γ / ERR, V32 = + γ / ERR) by multiplying the reciprocal of the error signal ERR by a predetermined coefficient ± γ. As described above, the error signal ERR becomes lower as the load is lighter. Therefore, in the low input detection threshold setting unit 751, the lighter the load, the higher the absolute value of each of the low input detection thresholds V31 and V32. The load interlocking operation of such low input detection thresholds V31 and V32 will be described in detail later.

The comparator 752 compares the AC voltage dividing voltage Vac input to the non-inverting input terminal (+) with the low input detection threshold V31 input to the inverting input terminal (−) to generate a comparison signal S31. The comparison signal S31 has a high level when Vac> V31 and a low level when Vac <V31.

The comparator 753 compares the AC voltage dividing voltage Vac input to the inverting input end (-) with the low input detection threshold V32 (> V31) input to the non-inverting input end (+) to generate a comparison signal S32. do. The comparison signal S32 has a low level when Vac> V32 and a high level when Vac <V32.

The NAND gate 754 generates a negative logic product signal of the comparison signals S31 and S32, and outputs this as a skip signal SKIP. The skip signal SKIP becomes low level when both the comparison signals S31 and S32 are high level, and becomes high level when at least one of the comparison signals S31 and S32 is low level.

This skip signal SKIP is input to the AND gate 713 of the on-timing setting unit 710. Therefore, when the skip signal SKIP is at a low level, the AND signal S13 is fixed at a low level regardless of the logic level of each of the comparison signals S11 and S12. In this way, when the logical product signal S13 is fixed at a low level, the set signal SET does not rise to a high level even when the zero cross timing of the voltage dividing voltage Vsw arrives, so that the on-timing of the bidirectional switch 20 is set. It will be skipped.

FIG. 21 is a timing chart showing the operation of generating the skip signal SKIP by the skip control unit 750, and the AC voltage dividing voltage Vac, the comparison signals S31 and S32, and the skip signal SKIP are depicted in order from the top.

In this figure, the AC voltage dividing voltage Vac is a sinusoidal voltage based on 0V, and the low input detection thresholds V31 and V32 are variable values (V31 = −γ / ERR, V32 = + γ / ERR, respectively, according to the error signal ERR. ).

At time t41, when the AC voltage dividing voltage Vac becomes higher than the low input detection threshold value V31, the comparison signal S31 rises to a high level. Further, at this point, since the AC voltage dividing voltage Vac is lower than the low input detection threshold value V32, the comparison signal S32 is maintained at a high level. Therefore, since the comparison signals S31 and S32 both have a high level, the skip signal SKIP falls to a low level. As a result, the AND signal S13 is fixed at a low level, so that the on-timing of the bidirectional switch 20 is skipped.

At time t42, when the AC voltage dividing voltage Vac becomes higher than the low input detection threshold value V32, the comparison signal S32 falls to a low level, so that the skip signal SKIP rises to a high level. As a result, the low-level fixation of the AND signal S13 is released, so that the soft switching (ZVS) of the bidirectional switch 20 is restarted.

After that, the AC voltage dividing voltage Vac changes from rising to falling, and when the AC voltage dividing voltage Vac becomes lower than the low input detection threshold value V32 at time t43, the comparison signal S32 rises to a high level. Further, at this point, since the AC voltage dividing voltage Vac is higher than the low input detection threshold value V31, the comparison signal S31 is maintained at a high level. Therefore, since the comparison signals S31 and S32 both have a high level, the skip signal SKIP falls to a low level. As a result, the AND signal S13 is fixed at a low level, so that the on-timing of the bidirectional switch 20 is skipped.

At time t44, when the AC voltage dividing voltage Vac becomes lower than the low input detection threshold value V31, the comparison signal S31 falls to a low level, so that the skip signal SKIP rises to a high level. As a result, the low-level fixation of the AND signal S13 is released, so that the soft switching (ZVS) of the bidirectional switch 20 is restarted.

After the time t44, when the AC voltage dividing voltage Vac changes from falling to rising, the same behavior as described above is repeated, and the skip signal SKIP generation operation by the skip control unit 750 is continued.

As described above, according to the skip control unit 750 having the above configuration, when the AC voltage dividing voltage Vac is low (for example, when V31 <Vac <V32 is satisfied), the bidirectional switch 20 is turned on. Can be skipped.

As shown by the white arrows in this figure, the low input detection thresholds V31 and V32 are variable values according to the error signal ERR (and the weight of the load). Hereinafter, the load interlocking operation of each of the low input detection thresholds V31 and V32 will be described in detail.

FIG. 22 is a timing chart showing load interlocking operations of the low input detection thresholds V31 and V32, respectively. From the top, the AC voltage dividing voltage Vac, the skip signal SKIP (H) under heavy load, and the light load. The skip signal SKIP (L) is depicted.

Regarding the low input detection thresholds V31 and V32 that fluctuate in conjunction with the load, those under heavy load are set to V31 (H) and V32 (H), and those under light load are set to V31 (L) and V32 (L). ), Each is described separately.

When the AC input voltage Vi is low, the power transmission to the secondary circuit system 1s due to the switching operation becomes poor, so that the switching loss becomes conspicuous. In particular, when the load is light, the influence of switching loss is large, and the efficiency of the AC / DC converter 1 is significantly reduced.

Therefore, in the skip control unit 750 of the present embodiment, the low input detection thresholds V31 and V32 are set so that the lighter the load, the longer the low level period (= period for skipping the on-timing of the bidirectional switch 20) of the skip signal SKIP. Each load interlocking operation is performed (see comparing skip signals SKIP (H) and SKIP (L)).

Therefore, when the load is light, the bidirectional switch 20 does not need to be turned on / off unnecessarily, so that the switching loss can be reduced. On the other hand, when the load is heavy, the high level period (= period for turning on / off the bidirectional switch 20) of the skip signal SKIP is extended, so that the power transmission to the secondary circuit system 1s can be enhanced.

As described above, by using the skip control unit 750 of this embodiment, it is possible to obtain the optimum conversion efficiency according to the load.

By the way, a technique for lowering the switching frequency to improve efficiency at a light load has been conventionally proposed, but when the AC input voltage Vi is low, the on-timing of the bidirectional switch 20 is skipped to complete the switching operation. It didn't stop at.

In addition, some conventional switching power supplies have a function to detect the AC input voltage, but whether or not the AC input voltage has reached the specified voltage value (abnormal state such as momentary power failure). It was not for determining whether or not to stop the switching operation, but for confirming whether or not the switching operation was stopped.

In this embodiment, the first embodiment (FIG. 12) is used as the base, but the second embodiment (FIG. 16) and the third embodiment (FIG. 17) may be used as the base.

<Other variants>
In addition to the above-described embodiment, the various technical features disclosed in the present specification can be modified in various ways without departing from the spirit of the technical creation. That is, it should be considered that the above-described embodiment is exemplary in all respects and is not restrictive, and the technical scope of the present invention is shown not by the description of the above-mentioned embodiment but by the scope of claims. It should be understood that it includes all changes that fall within the meaning and scope of the claims.

The AC / DC converter disclosed in the present specification can be used as a power source for, for example, general electric equipment and industrial equipment.

1 AC / DC converter 1p Primary circuit system 1s Secondary circuit system 10 Transformer 11 Primary winding 11x Leakage inductance 12 Secondary winding 20 Bidirectional switch 30, 30a, 30b Resonant capacitor 40 Full-wave rectifier circuit 41, 42 Diode 50 Smoothing Capacitor 60 Feedback circuit 70 Control circuit 710 On-timing setting unit 711, 712 Comparator 713 AND gate 714 Signal delay unit 715 Zero cross detection threshold setting unit 720 Off-timing setting unit 721 Oscillator 722 Error amplifier 723 Phase compensation unit 723a Capacitor 723b Resistance 724 OR Gate 726 Resistance 730 RS Flip Flop 740 Overcurrent Protection Unit 741 Overcurrent Detection Threshold Setting Unit 742, 743 Comparator 744 OR Gate 750 Skip Control Unit 751 Low Input Detection Threshold Setting Unit 752, 753 Comparator 754 NAND Gate 80 Sense Resistance 90 Power Fuse 100 Filter circuit 120 Coil 150 Capacitor voltage divider 151, 152 Capacitor 153 Discharge switch 170 AC voltage divider 171, 172 Resistance PW AC power supply Z load

Claims (10)

With the primary winding to which the AC input voltage is applied,
The secondary winding electromagnetically coupled to the primary winding and
A bidirectional switch connected in series with the primary winding,
A resonant capacitor connected in parallel to at least one of the bidirectional switch and the primary winding,
Resonant inductance component and
A full-wave rectifier circuit that full-wave rectifies the induced voltage generated in the secondary winding,
A smoothing capacitor that smoothes the output of the full-wave rectifier circuit,
A control circuit that turns the bidirectional switch on and off,
Have,
An AC / DC converter that directly converts the AC input voltage into a DC output voltage by extracting both the forward voltage and the flyback voltage from the secondary winding.
The control circuit includes an overcurrent protection unit that forcibly turns off the bidirectional switch when the primary current flowing through the primary winding becomes larger than the overcurrent detection threshold value.
The AC / DC converter is characterized in that the overcurrent protection unit includes an overcurrent detection threshold value setting unit that lowers the overcurrent detection threshold value as the load is lighter. The control circuit includes an off-timing setting unit that sets the off-timing of the bidirectional switch based on an error signal between a feedback signal corresponding to the DC output voltage and a predetermined reference signal.
The AC / DC converter according to claim 1, wherein the overcurrent detection threshold value setting unit sets the overcurrent detection threshold value by multiplying the error signal by a predetermined coefficient. The AC / DC converter according to claim 2, wherein the coefficient is a predetermined fixed value or a variable value according to the AC input voltage. The off-timing setting unit
An error amplifier that amplifies the difference between the feedback signal and the reference signal,
A phase compensator connected to the first output end of the error amplifier and
A resistor connected between the first output end and the second output end of the error amplifier,
Including
The AC / DC converter according to claim 2 or 3, wherein a node signal appearing at the second output terminal of the error amplifier is used as the error signal. The control circuit includes an on-timing setting unit that sets the on-timing of the bidirectional switch based on the comparison result between the voltage across the bidirectional switch or the voltage dividing voltage thereof and the zero cross detection threshold value.
The AC / DC converter according to any one of claims 1 to 4, wherein the on-timing setting unit includes a zero-cross detection threshold value setting unit that raises the zero-cross detection threshold value as the load is lighter. The control circuit includes an off-timing setting unit that sets the off-timing of the bidirectional switch based on an error signal between a feedback signal corresponding to the DC output voltage and a predetermined reference signal.
The AC / DC converter according to claim 5, wherein the zero-cross detection threshold value setting unit sets the zero-cross detection threshold value by multiplying the reciprocal of the error signal by a predetermined coefficient. The AC / DC converter according to claim 5 or 6, wherein the AC / DC converter has a capacitive voltage dividing circuit that divides the voltage between both ends of the bidirectional switch by capacitance to generate the divided voltage. The control circuit includes a skip control unit that skips the on-timing of the bidirectional switch when the AC input voltage or its divided voltage is lower than the low input detection threshold value.
The AC / DC converter according to any one of claims 1 to 7, wherein the skip control unit includes a low input detection threshold value setting unit that raises the low input detection threshold value as the load is lighter. The control circuit includes an off-timing setting unit that sets the off-timing of the bidirectional switch based on an error signal between a feedback signal corresponding to the DC output voltage and a predetermined reference signal.
The AC / DC converter according to claim 8, wherein the low input detection threshold value setting unit sets the low input detection threshold value by multiplying the reciprocal of the error signal by a predetermined coefficient. A control circuit for a switching power supply that generates an output voltage from an input voltage.
An error amplifier that amplifies the difference between the feedback signal corresponding to the output voltage and a predetermined reference signal, and
A phase compensator connected to the first output end of the error amplifier and
A resistor connected between the first output end and the second output end of the error amplifier,
Including
A control circuit characterized in that the on-duty of the switching power supply is controlled based on an error signal appearing at the second output terminal of the error amplifier.

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