JP6911349B2 - Status signal output device and erroneous output prevention method - Google Patents

Description

The present invention relates to a state signal output device and a method for preventing erroneous output.

As a system equipped with a device such as a servomotor, for example, there is a system in which a control unit that controls the entire system controls a drive circuit and supplies a drive current from the drive circuit to drive the device such as a servomotor.
In such a system, in the drive circuit, when a motor drive command signal is input from the control unit, the state of the drive circuit, that is, whether the drive circuit is in the operation ready state or an alarm output is output. It detects whether it is in a state, etc., and outputs a signal indicating the state of the drive circuit to the control unit as a state signal. As a result, the control unit recognizes the state of the drive circuit.

On the other hand, in the drive circuit, when the state of the drive circuit is in the operation ready state, a drive current corresponding to the motor drive command signal from the control unit is generated and supplied to a device such as a servomotor, and the state of the drive circuit is an alarm. The drive current is not supplied when it is in the output state.
At this time, in the drive circuit, the motor drive command signal from the control unit is input to the CPU, the state of the drive circuit is detected by the CPU, a state signal is generated, and the generated state signal is amplified by the buffer to be amplified by the control unit. It is output to.

In the drive circuit, the CPU outputs a permission signal indicating whether or not it is in an operable state, and the permission signal is output on a signal line different from the signal line of the state signal. The CPU outputs a permission signal indicating that the CPU is in an operable state only while the initial processing at the time of startup is completed and the CPU is in a state in which a predetermined operation can be performed.
The buffer is in the effective state only while the permission signal indicating that the CPU is in the operable state is input, and the state signal input from the CPU via a signal line different from the permission signal is amplified. Output to the control unit. By configuring the buffer to output the status signal to the control unit only when it receives the permission signal from the CPU and is in the valid state, the CPU does not complete the initial processing at the time of startup, etc., and the drive circuit Prevents the unstable state signal from being output to the control unit via the buffer when the state signal cannot be output according to the state, that is, when the state signal is in an unstable state. I try to do it.

As a method for the control unit or the like to recognize the state of one device such as a drive circuit, for example, the method described in Patent Document 1 has been proposed. In Patent Document 1, the state of the numerical control device (corresponding to one device) is recognized by a computer (corresponding to the output destination of the state signal) that controls the power-on of the numerical control device. When the power is turned on by the computer, a start-up signal is first output to the computer, and then a start-up completion signal is output when a predetermined initial process or the like is completed. On the other hand, in a computer, after controlling the power of the numerical control device to be turned on, when a start start signal is input from the numerical control device and then a start completion signal is input within a predetermined time, initial processing of the numerical control device, etc. Is made to recognize that is finished.

Japanese Unexamined Patent Publication No. 2016-21119

Since the CPU is not in a state where it can execute predetermined arithmetic processing or the like while the initial processing or the like is being executed at startup, various signals output from the CPU executing the initial processing or the like are generated by the CPU. It becomes an unstable signal, not a signal that has been processed.
In the drive circuit, when the initial processing of the CPU is completed, a permission signal indicating that the CPU is in an operable state is output to the buffer, and the CPU receives the permission signal only when the buffer is in the valid state. In the method of outputting the status signal to the control unit via the buffer, the status signal from the CPU is not output unless the buffer is in the valid state. However, since the CPU cannot generate the permission signal while the CPU is executing the initial processing or the like, the permission signal becomes an unstable signal. Therefore, the buffer erroneously determines that a permission signal indicating that the CPU is in the operable state has been input even though the CPU is not actually in the operable state, and the buffer becomes the valid state and outputs the status signal. There is a possibility that it will end up.

Further, even in the method described in Patent Document 1, since the numerical control device is executing the initial processing and the like until the numerical control device outputs the start completion signal, the start completion signal becomes an unstable signal. .. As a result, the computer erroneously recognizes that it is a start-up completion signal generated by the numerical control device, even though it is actually an unstable signal rather than a start-up completion signal generated by the numerical control device. , There is a possibility of erroneously recognizing that the initial processing in the numerical control device has been completed.
The present invention has been made in view of such circumstances, and a signal in which the state signal is unstable because the CPU is executing initial processing or the like at startup or the like and the CPU cannot generate a state signal. It is an object of the present invention to provide a state signal output device and a method for preventing erroneous output, which can prevent the device on the input side of the state signal from malfunctioning based on the unstable state signal.

According to one aspect of the present invention, a state signal representing the state of one device is output to another device via a signal line, and the device is in an operable state when it is in a preset operable state. The permission signal to be represented is provided so as to be located between the CPU and another device on the signal line of the state signal and the CPU that outputs the permission signal on a signal line different from the signal line of the state signal, and also via the signal line of the permission signal. By being connected to the CPU , both the status signal and the permission signal are input, and the buffer that outputs the status signal to other devices only while the permission signal indicating that it is in the operable state is input, and The permission signal stabilizing circuit provided in the signal line of the permission signal between the CPU and the buffer is provided, and the permission signal stabilization circuit determines the signal level of the signal line of the permission signal while the CPU is in an inoperable state. , The feature is to maintain the signal level indicating that the CPU is in an inoperable state.

According to one aspect of the present invention, the state signal is input in a state where the CPU is executing initial processing or the like at startup or the like and the CPU cannot generate a state signal and is an unstable state signal. It is possible to prevent the device on the other side from malfunctioning based on the unstable state signal.

It is a block diagram which shows an example of the structure of the motor control device to which the state signal output device which concerns on one Embodiment of this invention is applied. It is a block diagram which shows an example of the permission signal stabilizer.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The following detailed description describes many specific details to provide a complete understanding of the embodiments of the present invention. However, it is clear that one or more embodiments can be implemented without such specific details. Other well-known structures and devices are shown in schematics for the sake of brevity in the drawings.
The state signal output device according to the embodiment of the present invention outputs a state signal indicating the state of the drive circuit (corresponding to one device) and is in an operable state when it is in a preset operable state. The state is limited to the CPU that outputs the permission signal indicating A buffer that outputs a signal and a permission signal stabilizing circuit provided in the signal line of the permission signal between the CPU and the buffer are provided, and the permission signal stabilizing circuit is provided as a permission signal while the CPU is in an inoperable state. The signal level of the signal line of is maintained at the signal level indicating that the CPU is in an inoperable state.

FIG. 1 is a configuration diagram showing an example of a motor control device to which the state signal output device according to the embodiment of the present invention is applied.
The motor control device 100 shown in FIG. 1 includes a drive circuit (corresponding to one device) 1 and a control unit 2, and the drive circuit 1 is controlled by the control unit 2 to drive and control, for example, a servomotor M. ..
The drive circuit 1 includes a control unit 1a and a drive current supply circuit 1b.
The control unit 1a includes a CPU 11, a buffer 12, and a permission signal stabilization circuit 13, and includes a functional configuration of a state signal output device according to an embodiment of the present invention.

The CPU 11 executes initial processing or the like at startup or restart, and when the initial processing or the like is completed and the CPU 11 is ready to execute a predetermined process, the CPU 11 is in an operable state. , Outputs a permission signal indicating that the CPU 11 is in an operable state. The CPU 11 invalidates the permission signal stabilization circuit 13 when it becomes operable.
Further, when the motor drive command signal is input from the control unit 2, the CPU 11 detects the state of each part of the control unit 1a and the drive current supply circuit 1b, and outputs a state signal indicating the state of the drive circuit 1. This state signal is output to the control unit 2 via the buffer 12. The CPU 11 detects the state of the drive circuit 1, such as whether the drive circuit 1 is in the operation ready state or the alarm output state, and outputs this as a state signal. The CPU 11 drives the motor from the control unit 2 when the drive circuit 1 is in a state where it can perform predetermined operations in response to various command signals from the control unit 2, such as when the drive circuit 1 is in an operation ready state. In response to the command signal, a drive signal for driving and controlling the drive current supply circuit 1b is output. When the drive circuit 1 is in a state where it cannot operate in response to various command signals from the control unit 2, such as when the drive circuit 1 is in the alarm output state, the CPU 11 controls the drive of the drive current supply circuit 1b. Not performed.

The CPU 11 and the buffer 12 are connected by, for example, the internal bus L1, and the status signal is input to the buffer 12 via the internal bus L1. The permission signal output from the CPU 11 is input to the buffer 12 via a signal line L2 different from the internal bus L1. A permission signal stabilizing circuit 13 is interposed in the signal line L2 between the CPU 11 and the buffer 12. The permission signal stabilization circuit 13 stabilizes the permission signal input via the signal line L2 and outputs it to the buffer 12.
The drive current supply circuit 1b includes, for example, an IPM (Intelligent Power Module) element or the like, and supplies a drive current corresponding to a drive signal from the CPU 11 to the servomotor M.

FIG. 2 is a configuration diagram showing an example of the permission signal stabilization circuit 13. As shown in FIG. 2A, the permission signal stabilization circuit 13 has a resistor R1 at one end connected to, for example, a 5V power supply, and the other end of the resistor R1 is a permission signal for connecting the CPU 11 and the buffer 12. A switch SW which is connected to the signal line L2 for transmission and has a normally closed contact is inserted between the resistor R1 and the signal line L2. When the power of the drive circuit 1 is turned on, the permission signal stabilization circuit 13 maintains the signal line L2 for transmitting the permission signal at the HIGH level, and maintains the permission signal input to the buffer 12 at the HIGH level. The CPU 11 controls the switch SW to an open state when the initial processing or the like is completed and becomes an operable state, and thereafter maintains the open state until, for example, the power supply of the drive circuit 1 is cut off.

FIG. 2B shows another example of the permission signal stabilization circuit 13, and the permission signal stabilization circuit 13 has a resistor whose one end is connected to GND (0V) as shown in FIG. 2B. The other end of the resistor R2 having R2 is connected to the signal line L2 connecting between the CPU 11 and the buffer 12, and a switch SW having a normally closed contact is inserted between the resistor R1 and the signal line L2. Has been done. When the power of the drive circuit 1 is turned on, the permission signal stabilization circuit 13 maintains the signal line L2 of the permission signal at the ground potential and maintains the permission signal input to the buffer 12 at the LOW level. The CPU 11 controls the switch SW to an open state when the initial processing or the like is completed and becomes an operable state, and thereafter maintains the open state until, for example, the power supply of the drive circuit 1 is cut off.

Next, the operation of the above embodiment will be described.
The power supply of the drive circuit 1 is turned on when the power supply of the motor control device 100 is turned on, and each part of the drive circuit 1 is activated.
When the power of the drive circuit 1 is turned on, the CPU 11 performs initial processing and the like, and after the initial processing and the like are completed and a predetermined arithmetic processing can be executed (operable state), the CPU 11 is in an operable state. The permission signal indicating that the result has been obtained is output to the buffer 12. This permission signal is input to the buffer 12 via the signal line L2.
The buffer 12 is in the effective state only while the permission signal indicating the operable state is input, and the state signal input from the CPU 11 can be output to the control unit 2.

When the motor drive command signal is input from the control unit 2, the CPU 11 detects the state of the drive circuit 1 and outputs the state signal. The status signal output from the CPU 11 is output to the buffer 12 via the internal bus L1. At this point, a permission signal indicating that the CPU 11 is in an operable state is input to the buffer 12, and since the buffer 12 is in the valid state, the state signal is output from the buffer 12 to the control unit 2 to control. The unit 2 recognizes the state of the drive circuit 1 from the state signal.
On the other hand, when the drive circuit 1 is in an operable state such as an operation ready state, the CPU 11 generates a drive signal corresponding to the motor drive command signal from the control unit 2 and drives the drive current supply circuit 1b. ..
When the CPU 11 is configured to output a permission signal as a LOW level when the initial processing or the like in the CPU 11 is completed and a predetermined processing can be executed and the CPU 11 is in an operable state, the permission signal stabilization circuit 13 , As shown in FIG. 2 (a).

When the power of the drive circuit 1 is turned on and the CPU 11 is started, the CPU 11 has not completed the initial processing and the like, and the CPU 11 cannot generate the permission signal. Therefore, the permission signal becomes an unstable signal. However, the signal line L2 between the CPU 11 and the buffer 12 is provided with the permission signal stabilization circuit 13, and the permission signal input to the buffer 12 is maintained at the HIGH level by the permission signal stabilization circuit 13. That is, the permission signal is maintained at a signal level indicating that the CPU 11 is in an inoperable state in which the initial processing and the like have not been completed. Therefore, the CPU 11 cannot generate the permission signal, and even if the permission signal is unstable, the permission signal indicating that the buffer 12 is in an inoperable state is input, so that the buffer 12 operates. The buffer 12 does not erroneously recognize that the permission signal indicating that the possible state has been input, and the buffer 12 does not erroneously recognize that the initial processing or the like in the CPU 11 has been completed.

Therefore, even if the motor drive command signal is input from the control unit 2 to the drive circuit 1 when the drive circuit 1 is not in the operation ready state at the time of startup, the unstable state signal is output to the control unit 2. Is avoided. Since the state signal is not input to the control unit 2 as a response to the motor drive command signal, it can be recognized that the drive circuit 1 is not in the operable state.
When the initial processing or the like in the CPU 11 is completed and the LOW level permission signal is output from the CPU 11, the CPU 11 has, for example, a switch SW provided between the signal line L2 of the permission signal stabilization circuit 13 and the resistor R1. Is switched to the cutoff state, and the permission signal stabilization circuit 13 is invalidated. The permission signal output from the CPU 11 is input to the buffer 12 as it is, and since the permission signal is at the LOW level, the buffer 12 is switched to the valid state. After that, the state signal input to the buffer 12 is amplified by the buffer 12 and output to the control unit 2. At this point, the CPU 11 has completed the initial processing and the like, and the CPU 11 is in an operable state capable of executing a predetermined arithmetic processing. When the motor drive command signal is output from the control unit 2 at this point, the CPU 11 outputs a stable state signal according to the state of the drive circuit 1, and this state signal is output to the control unit 2. The control unit 2 can recognize the state of the drive circuit 1 from the state signal.

When the drive circuit 1 is in the operation ready state, the CPU 11 outputs a drive signal corresponding to the motor drive command signal to the drive current supply circuit 1b, and the drive current is supplied to the servomotor M from the drive current supply circuit 1b.
On the other hand, when the CPU 11 outputs the permission signal as the HIGH level when the initial processing or the like is completed and the predetermined processing can be executed, the permission signal stabilization circuit 13 is shown in FIG. 2 (b). It is configured as shown.
When the power of the drive circuit 1 is turned on, the permission signal cannot be generated by the CPU 11, so that the permission signal becomes an unstable signal, but the buffer 12 does not have the CPU 11 due to the permission signal stabilization circuit 13. A permit signal maintained at a LOW level indicating that it is in an operable state is input. Therefore, the CPU 11 cannot generate the permission signal and the permission signal is an unstable signal, but the buffer 12 does not erroneously recognize that the permission signal indicating the operable state has been input from the CPU 11. Since the buffer 12 does not output the state signal to the control unit 2 while the permission signal is a signal indicating the inoperable state, the unstable state signal output from the CPU 11 is sent to the control unit 2 via the buffer 12. It is avoided that it is output.

When the initial processing and the like in the CPU 11 are completed and the HIGH level permission signal is output from the CPU 11, the CPU 11 is provided with, for example, a switch provided between the signal line L2 and the resistor R2 of the permission signal stabilization circuit 13. The SW is switched to the cutoff state, and the permission signal stabilization circuit 13 is invalidated. The permission signal output from the CPU 11 is input to the buffer 12 as it is, and the buffer 12 is switched to the valid state. After that, the state signal input to the buffer 12 is amplified by the buffer 12 and output. At this point, the CPU 11 has completed the initial processing and the like, and is in a state where a predetermined arithmetic processing can be executed. The state signal output by the CPU 11 at this point is a state signal set according to the state of the drive circuit 1. Therefore, it is possible to prevent the control unit 2 from outputting an unstable state signal from the CPU 11, and to output only the state signal generated according to the state of the drive circuit 1. ..

In the motor control device 100, from the time when the drive circuit 1 is started until the initial processing and the like in the CPU 11 are completed and the CPU 11 is in a state where the permission signal can be generated, while the initial processing and the like in the CPU 11 are not completed. The permission signal input to the buffer 12 maintains a signal level indicating that the initial processing and the like in the CPU 11 have not been completed. In the motor control device 100, when the CPU 11 is executing initial processing and the like and the permission signal is unstable, the buffer 12 malfunctions based on the unstable permission signal, resulting in instability. A permission signal stabilization circuit 13 is provided on the signal line L2 of the permission signal between the CPU 11 and the buffer 12 in order to prevent the state signal from being output to the control unit 2.

When the initial processing and the like in the CPU 11 are completed, the CPU 11 invalidates the permission signal stabilization circuit 13 and outputs a permission signal indicating an operable state, the permission signal input to the buffer 12 is a permission indicating the operable state. Switch to a signal. The buffer 12 is in the valid state, and a state signal corresponding to the state of the drive circuit 1 generated by the CPU 11 is output from the buffer 12 to the control unit 2. The control unit 2 can recognize the state of the drive circuit 1 based on the state signal. Therefore, when the CPU 11 is in a state where the initial processing or the like has not been completed, it is possible to prevent the control unit 2 from malfunctioning based on the unstable state signal, and improve the reliability of the motor control device 100. Can be done.

In the above embodiment, the case where the state signal output device is provided in the drive circuit 1 that drives and controls the servomotor M has been described, but the present invention is not limited to this. For example, when the CPU mounted on one device transmits a status signal indicating the state of one device to another device such as a host device, the CPU transmits a status signal representing its own status to the host device or the like. In this case, the CPU outputs the status signal of one of the devices to the other device, such as when the CPU relays the status signal of the device on which it is not mounted and transmits it to a higher-level device or the like. Any CPU can be applied.

Further, in the above embodiment, the case where the CPU 11 invalidates the permission signal stabilization circuit 13 by shutting off the switch SW provided between the signal line L2 of the permission signal stabilization circuit 13 and the resistor R1 or R2 will be described. However, it is not limited to this. The configuration may be such that the permission signal stabilization circuit 13 can be invalidated after the CPU 11 is in an operable state.
Further, the permission signal stabilization circuit 13 is not limited to the configuration shown in FIGS. 2A and 2B, and the signal line L2 is in a non-operating state until the CPU 11 is in an operable state. Any configuration may be used as long as it can be maintained in the permission signal representing.

Although the present invention has been described above with reference to specific embodiments, the description does not limit the invention. By reference to the description of the present invention, other embodiments of the present invention will be apparent to those skilled in the art as well as various variations of the disclosed embodiments. Therefore, it should be understood that the scope of claims also covers these modifications or embodiments included in the scope and gist of the present invention.

1 Drive circuit 1a Control unit 1b Drive current supply circuit 2 Control unit 11 CPU
12 Buffer 13 Allow signal stabilization circuit 100 Motor controller M Servo motor SW switch

Claims (5)

A state signal indicating the state of one device is output to another device via a signal line, and a permission signal indicating that the device is in the operable state when it is in the preset operable state is transmitted as the state signal. CPU that outputs with a signal line different from the signal line of
The status signal and the permission signal are provided so as to be located between the CPU and the other device in the signal line of the state signal and connected to the CPU via the signal line of the permission signal. are both input, and a buffer for outputting the state signal to the other device only while the enabling signal indicating that it is in the operational state is entered,
The permission signal stabilizing circuit provided in the signal line of the permission signal between the CPU and the buffer is provided.
The permission signal stabilization circuit is characterized in that the signal level of the signal line of the permission signal is maintained at a signal level indicating that the CPU is in the non-operable state while the CPU is in the non-operable state. State signal output device. The permission signal indicating that the operation is possible is a LOW level signal.
The state signal output device according to claim 1, wherein the permission signal stabilization circuit includes a resistor having one end connected to the signal line and the other end connected to a power supply. The permission signal indicating that the operation is possible is a HIGH level signal.
The state signal output device according to claim 1, wherein the permission signal stabilization circuit includes a resistor having one end connected to the signal line and the other end connected to a ground potential. Included in the drive circuit as one device,
The state signal output device according to any one of claims 1 to 3, wherein the state signal representing the state of the drive circuit is output to a higher-level device of the drive circuit. It is a method of preventing erroneous output of a state signal indicating the state of one device.
The CPU outputs the state signal of the one device to another device via a signal line, and also indicates that the CPU is in the operable state when it is in the preset operable state. Is output on a signal line different from the signal line of the state signal.
A buffer is provided in the signal line of the state signal so as to be located between the CPU and the other device, and the buffer is connected to the CPU via the signal line of the permission signal.
Said buffer, said both state signal and said permission signal is inputted, and outputs the state signal only while the enable signal indicating that it is in the operational state is entered,
While the CPU is in the inoperable state, the signal level of the signal line of the permission signal between the CPU and the buffer is maintained at a signal level indicating that the CPU is in the inoperable state. Characteristic erroneous output prevention method.

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