JP6913656B2 - Arithmetic logic unit - Google Patents

Description

Embodiments of the present invention relate to arithmetic units.

For example, an arithmetic unit is used for deep learning and the like. It is desired to speed up the calculation in the arithmetic unit.

Japanese Patent No. 58646484

An embodiment of the present invention provides an arithmetic unit capable of speeding up.

According to the embodiment of the present invention, the arithmetic unit includes an element unit including the first element and the second element, and a circuit unit including the arithmetic circuit. The first element includes a first conductive layer and a first laminated body. The first conductive layer includes a first portion, a second portion, and a third portion between the first portion and the second portion. The first laminated body is formed between a first magnetic layer, a second magnetic layer provided between the third portion and the first magnetic layer, and between the first magnetic layer and the second magnetic layer. Includes a first non-magnetic layer provided in. The direction from the first portion to the second portion intersects with the direction from the third portion to the first magnetic layer. The second element includes a second conductive layer and a second laminated body. The second conductive layer includes a fourth portion, a fifth portion, and a sixth portion between the fourth portion and the fifth portion. The second laminated body is formed between a third magnetic layer, a fourth magnetic layer provided between the sixth portion and the third magnetic layer, and between the third magnetic layer and the fourth magnetic layer. Includes a second non-magnetic layer provided in. The direction from the fourth portion to the fifth portion intersects with the direction from the sixth portion to the third magnetic layer. The first element is in the first state or the second state depending on the potential of the first magnetic layer and the direction of the current flowing through the first conductive layer. The first electrical resistance of the first path including the path between the first magnetic layer and the first conductive layer in the first state is higher than the second electrical resistance of the first path in the second state. Is also low. The second element is in the third state or the fourth state depending on the potential of the third magnetic layer and the direction of the current flowing through the second conductive layer. The third electrical resistance of the second path including the path between the third magnetic layer and the second conductive layer in the third state is higher than the fourth electrical resistance of the second path in the fourth state. Is also low. The arithmetic circuit is the first when the first element is in the first state and the second element is in the third state, and when the first element is in the second state and the second element is in the fourth state. Outputs one signal. The arithmetic circuit outputs a second signal when the first element is in the second state and the second element is in the third state.

1 (a) to 1 (e) are schematic views illustrating an arithmetic unit according to the first embodiment. 2 (a) and 2 (b) are schematic views illustrating the operation of the arithmetic unit according to the first embodiment. 3 (a) to 3 (d) are schematic views illustrating the operation of the arithmetic unit according to the first embodiment. 4 (a) to 4 (d) are schematic views illustrating the operation of the arithmetic unit according to the first embodiment. 5 (a) to 5 (d) are schematic views illustrating the operation of the arithmetic unit according to the first embodiment. 6 (a) to 6 (d) are schematic views illustrating the operation of the arithmetic unit according to the first embodiment. 7 (a) to 7 (d) are schematic views illustrating the operation of the arithmetic unit according to the first embodiment. 8 (a) to 8 (d) are schematic views illustrating the operation of the arithmetic unit according to the first embodiment. FIG. 9 is a schematic diagram illustrating an arithmetic unit according to the first embodiment. 10 (a) and 10 (b) are schematic views illustrating the arithmetic unit according to the first embodiment. FIG. 11 is a schematic diagram illustrating the operation of the arithmetic unit according to the first embodiment. FIG. 12 is a schematic diagram illustrating the operation of the arithmetic unit according to the first embodiment. FIG. 13 is a schematic diagram illustrating the operation of the arithmetic unit according to the first embodiment. FIG. 14 is a schematic diagram illustrating the operation of the arithmetic unit according to the first embodiment. FIG. 15 is a schematic diagram illustrating the operation of the arithmetic unit according to the first embodiment. FIG. 16 is a schematic diagram illustrating an arithmetic unit according to the first embodiment. FIG. 17 is a schematic diagram illustrating a part of the arithmetic unit according to the first embodiment. 18 (a) to 18 (c) are schematic views illustrating a part of the arithmetic unit according to the first embodiment. FIG. 19 is a schematic diagram illustrating a part of the arithmetic unit according to the first embodiment. FIG. 20 is a schematic diagram illustrating a part of the arithmetic unit according to the first embodiment. 21 (a) and 21 (b) are schematic views illustrating a part of the arithmetic unit according to the first embodiment. FIG. 22 is a schematic diagram illustrating the operation of the arithmetic unit according to the first embodiment. FIG. 23 is a schematic diagram illustrating the operation of the arithmetic unit according to the first embodiment. FIG. 24 is a schematic diagram illustrating the operation of the arithmetic unit according to the first embodiment. FIG. 25 is a schematic diagram illustrating the operation of the arithmetic unit according to the first embodiment. FIG. 26 is a schematic diagram illustrating the operation of the arithmetic unit according to the second embodiment. FIG. 27 is a schematic diagram illustrating the operation of the arithmetic unit according to the second embodiment. FIG. 28 is a schematic diagram illustrating the operation of the arithmetic unit according to the second embodiment. FIG. 29 is a schematic diagram illustrating the operation of the arithmetic unit according to the second embodiment. FIG. 30 is a schematic diagram illustrating the operation of the arithmetic unit according to the second embodiment. FIG. 31 is a schematic diagram illustrating an arithmetic unit according to the third embodiment. 32 (a) to 32 (d) are schematic views illustrating the operation of the arithmetic unit according to the third embodiment. FIG. 33 is a schematic diagram illustrating an arithmetic unit according to the third embodiment. 34 (a) to 34 (d) are schematic views illustrating the operation of the arithmetic unit according to the third embodiment. FIG. 35 is a schematic diagram illustrating an arithmetic unit according to the third embodiment. 36 (a) to 36 (d) are schematic views illustrating the operation of the arithmetic unit according to the third embodiment. FIG. 37 is a schematic diagram illustrating an arithmetic unit according to the third embodiment. FIG. 38 is a schematic diagram illustrating an arithmetic unit according to the third embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between the parts, etc. are not always the same as the actual ones. Even if the same part is represented, the dimensions and ratios of each may be represented differently depending on the drawing.
In the specification of the present application and each figure, the same elements as those described above with respect to the above-mentioned figures are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.

(First Embodiment)
1 (a) to 1 (e) are schematic views illustrating an arithmetic unit according to the first embodiment.
FIG. 1A is a schematic perspective view. 1 (b) to 1 (e) are schematic cross-sectional views illustrating a part of the arithmetic unit.

As shown in FIG. 1A, the arithmetic unit 110 according to the embodiment includes an element unit 54 and a circuit unit 70. The circuit unit 70 includes an arithmetic circuit 71. In this example, the circuit unit 70 further includes a control circuit 72. As will be described later, the element unit 54 and the arithmetic circuit 71 may function as the XNOR arithmetic circuit 55.

The element unit 54 includes a first element 51M and a second element 52M. As will be described later, the element unit 54 may be provided with a plurality of first elements 51M and a plurality of second elements 52M.

The first element 51M includes a first conductive layer 21 and a first laminated body 51. The first conductive layer 21 includes a first portion 21a, a second portion 21b, and a third portion 21c. The third portion 21c is provided between the first portion 21a and the second portion 21b.

The first laminated body 51 includes a first magnetic layer 11, a second magnetic layer 12, and a first non-magnetic layer 11n. The second magnetic layer 12 is provided between the third portion 21c and the first magnetic layer 11. The first non-magnetic layer 11n is provided between the first magnetic layer 11 and the second magnetic layer 12.

The direction from the first portion 21a to the second portion 21b intersects the direction from the third portion 21c to the first magnetic layer 11.

The direction from the third portion 21c to the first magnetic layer 11 is the Z-axis direction. One direction perpendicular to the Z-axis direction is defined as the X-axis direction. The direction perpendicular to the Z-axis direction and the X-axis direction is defined as the Y-axis direction.

In this example, the direction from the first portion 21a to the second portion 21b is along the X-axis direction.

In one example, the second magnetic layer 12 is in contact with the third portion 21c. Another layer may be provided between the first magnetic layer 11 and the first non-magnetic layer 11n. Another layer may be provided between the second magnetic layer 12 and the first non-magnetic layer 11n.

As will be described later, a plurality of first laminated bodies 51 may be provided on one first conductive layer 21.

The second element 52M includes a second conductive layer 22 and a second laminated body 52. The second conductive layer 22 includes a fourth portion 22d, a fifth portion 22e, and a sixth portion 22f. The sixth portion 22f is provided between the fourth portion 22d and the fifth portion 22e.

The second laminated body 52 includes a third magnetic layer 13, a fourth magnetic layer 14, and a second non-magnetic layer 12n. The fourth magnetic layer 14 is provided between the sixth portion 22f and the third magnetic layer 13. The second non-magnetic layer 12n is provided between the third magnetic layer 13 and the fourth magnetic layer 14.

The direction from the fourth portion 22d to the fifth portion 22e intersects the direction from the sixth portion 22f to the third magnetic layer 13. In this example, the direction from the sixth portion 22f to the third magnetic layer 13 is along the Z-axis direction. In one example, the direction from the fourth portion 22d to the fifth portion 22e may be along the direction from the first portion 21a to the second portion 21b (for example, the X-axis direction). In embodiments, various modifications are possible in these directions.

In one example, the fourth magnetic layer 14 is in contact with the sixth portion 22f. Another layer may be provided between the third magnetic layer 13 and the second non-magnetic layer 12n. Another layer may be provided between the fourth magnetic layer 14 and the second non-magnetic layer 12n.

The first to fourth magnetic layers 11 to 14 are, for example, ferromagnetic. The first non-magnetic layer 11n and the second non-magnetic layer 12n contain, for example, a metal oxide (for example, MgO).

The magnetization 12M of the second magnetic layer 12 and the magnetization 14M of the fourth magnetic layer 14 (see FIGS. 1B to 1E) are the magnetization 11M of the first magnetic layer 11 and the third magnetic layer. It is more likely to change than the magnetization 13M of 13 (see FIGS. 1 (b) to 1 (e)). The second magnetic layer 12 and the fourth magnetic layer 14 are, for example, magnetized free layers. The first magnetic layer 11 and the third magnetic layer 13 are, for example, reference layers.

The first element 51M can be in the first state ST1 (see FIG. 1B) or the second state ST2 (see FIG. 1C). These two states are formed according to the direction of the current flowing through the first conductive layer 21.

The electrical resistance of the first path CP1 (see FIG. 1A) including the path between the first magnetic layer 11 and the first conductive layer 21 in the first state ST1 is the first electrical resistance R1 (FIG. 1 (b)). ) Refer to). The electric resistance of the first path CP1 in the second state ST2 is defined as the second electric resistance R2 (see FIG. 1C). The first electric resistance R1 is lower than the second electric resistance R2.

The second element 52M can be in the third state ST3 (see FIG. 1D) or the fourth state ST4 (see FIG. 1E). These two states are formed according to the direction of the current flowing through the second conductive layer 22.

The electrical resistance of the second path CP2 (see FIG. 1A) including the path between the third magnetic layer 13 and the second conductive layer 21 in the third state ST3 is the third electrical resistance R3 (FIG. 1 (d)). ) Refer to). The electric resistance of the second path CP2 in the fourth state ST4 is defined as the fourth electric resistance R4 (see FIG. 1 (e)).

In this way, a plurality of states (first state ST1 and second state ST2) can be formed in the first laminated body 51. A plurality of states (third state ST3 and fourth state ST4) can be formed in the second laminated body 52. The difference in electrical resistance in these states is considered to depend on the direction of magnetization in the two magnetic layers.

For example, as shown in FIG. 1B, in the first state ST1, the magnetization 12M is “parallel” to the magnetization 11M. For example, as shown in FIG. 1 (c), in the second state ST2, the magnetization 12M is “antiparallel” to the magnetization 11M. For example, in the third state ST3, as shown in FIG. 1D, the magnetization 14M is “parallel” to the magnetization 13M. For example, as shown in FIG. 1 (e), in the fourth state ST4, the magnetization 14M is “antiparallel” to the magnetization 13M. The above expressions "parallel" and "anti-parallel" are expedient expressions. These magnetizations are "parallel" when one magnetization of the two magnetic layers has a component of the other one magnetization orientation of the two magnetic layers. These magnetizations are "antiparallel" when one magnetization of the two magnetic layers has components that are opposite to the orientation of another one of the two magnetic layers.

For example, at least one of the first conductive layer 21 and the second conductive layer 22 includes at least one selected from the group consisting of Ta, W, Re, Os, Ir, Pt, Pd, Cu and Ag. By using such a material, it is easy to obtain a relatively large spin orbit torque (SOT).

It is considered that a plurality of states of the magnetization 12M of the second magnetic layer 12 are generated based on, for example, the action of SOT generated between the first conductive layer 21 and the second magnetic layer 12. It is considered that a plurality of states of the magnetization 14M of the fourth magnetic layer 14 are generated based on, for example, the action of SOT generated between the second conductive layer 22 and the fourth magnetic layer 14.

The above-mentioned plurality of states can be switched by controlling the direction of the current flowing through the conductive layer. Here, depending on the conditions of the voltage applied to the laminated body, there are cases where a plurality of states can be switched and cases where it is difficult to switch between the plurality of states.

1 (b) to 1 (e) exemplify a case where a voltage capable of switching a plurality of states is applied to the laminated body. The first magnetic layer 11 is set to the first potential V1. The first potential V1 is a potential based on the potential of the first conductive layer 21. The third magnetic layer 13 is set to the third potential V3. The third potential V3 is a potential based on the potential of the second conductive layer 22.

As shown in FIG. 1B, when the first magnetic layer 11 is set to the first potential V1 and the first current J1 flows through the first conductive layer 21, the first electric resistance R1 (first state ST1) is generated. can get. The first current J1 has an orientation from the first portion 21a to the second portion 21b. As shown in FIG. 1 (c), when the first magnetic layer 11 is set to the first potential V1 and the second current J2 flows through the first conductive layer 21, the second electric resistance R2 (first state ST2) is generated. can get. The second current J2 has an orientation from the second portion 21b to the first portion 21a.

As shown in FIG. 1D, when the third magnetic layer 13 is set to the third potential V3 and the third current J3 flows through the second conductive layer 22, the third electric resistance R3 (third state ST3) is generated. can get. The third current J3 has an orientation from the fourth portion 22d to the fifth portion 22e. As shown in FIG. 1 (e), when the third magnetic layer 13 is set to the third potential V3 and the fourth current J4 flows through the second conductive layer 22, the fourth electric resistance R4 (fourth state ST4) is generated. can get. The fourth current J4 has an orientation from the fifth portion 22e to the fourth portion 22d.

The setting of these potentials and the supply of currents are performed by, for example, the control circuit 72. For example, the potential is set by applying a pulse voltage. For example, the current is supplied by supplying the pulse current.

Even if the above current is supplied to the conductive layer, when the potential of the first magnetic layer 11 is not the first potential V1 (for example, when it is the second potential), the electric resistance is in the state before the current is supplied. maintain. Even if the above current is supplied to the conductive layer, when the potential of the third magnetic layer 13 is not the third potential V3 (for example, when it is the fourth potential), the electric resistance is in the state before the current is supplied. maintain.

As described above, depending on the potential of the first magnetic layer 11 and the direction of the current flowing through the first conductive layer 21, the first element 51M (for example, the first laminated body 51) is in the first state ST1 or the second state. It becomes ST2. The first electric resistance R1 in the first state ST1 of the first path CP1 including the path between the first magnetic layer 11 and the first conductive layer 21 is the second electric resistance in the second state ST2 of the first path CP1. Lower than R2.

The second element 52M (for example, the second laminated body 52) becomes the third state ST3 or the fourth state ST4 depending on the potential of the third magnetic layer 13 and the direction of the current flowing through the second conductive layer 22. The third electric resistance R3 in the third state ST3 of the second path CP2 including the path between the third magnetic layer 13 and the second conductive layer 22 is the fourth electric resistance in the fourth state ST4 of the second path CP2. Lower than resistance R4.

The arithmetic circuit 71 outputs signals corresponding to the above-mentioned plurality of states.
Hereinafter, a plurality of states and examples of output signals will be described. The plurality of states are determined by, for example, a plurality of inputs acquired by the arithmetic unit 110. In the following, the control circuit 72 acquires these inputs. These inputs may be acquired by another portion provided in the arithmetic unit 110. In embodiments, these inputs may be stored in the arithmetic unit 110. These inputs may be generated by some circuits included in the arithmetic unit 110. In the following, the control circuit 72 acquires the first input and the second input.

2 (a) and 2 (b) are schematic views illustrating the operation of the arithmetic unit according to the first embodiment.
These figures exemplify the first input I1 and the second input I2, the state of the element, and the signal output from the arithmetic circuit 71.

As shown in FIG. 2A, the first input I1 is one of 0 and 1 or the other of 0 and 1. The second input I2 is one of 0 and 1 or the other of 0 and 1. “0” is, for example, the first information. “1” is, for example, second information.

For example, the two states of the first input I1 correspond to the two states of the magnetization 12M of the second magnetic layer 12. The two states of the second input I2 correspond to the two states of the potential of the first magnetic layer 11 (first potential V1 or second potential). A plurality of states of the element are determined by the combination of the two states of the first input I1 and the two states of the second input I2.

FIG. 2A illustrates the first input I1, the first input I2, the state 51S of the first element 51M, the state 52S of the second element 52M, and the signal 71S output from the arithmetic circuit 71.

For example, as shown in FIG. 2A, when the first input I1 is 0 and the second input I2 is 0, the first element 51M is in the first state ST1. When the first input I1 is 0 and the second input I2 is 1, the first element 51M is in the second state ST2. When the first input I1 is 1 and the second input I2 is 0, the first element 51M is in the second state ST2. When the first input I1 is 1 and the second input I2 is 1, the first element 51M is in the second state ST2.

On the other hand, as shown in FIG. 2A, when the first input I1 is 0 and the second input I2 is 0, the second element 52M is in the third state ST3. When the first input I1 is 0 and the second input I2 is 1, the second element 52M is in the third state ST3. When the first input I1 is 1 and the second input I2 is 0, the second element 52M is in the third state ST3. When the first input I1 is 1 and the second input I2 is 1, the second element 52M is in the fourth state ST4.

As shown in FIG. 2A, when the first input I1 is 0 and the second input I2 is 0, the arithmetic circuit 71 outputs the first signal SG1. When the first input I1 is 0 and the second input I2 is 1, the arithmetic circuit 71 outputs the second signal SG2. When the first input I1 is 1 and the second input I2 is 0, the arithmetic circuit 71 outputs the second signal SG2. When the first input I1 is 1 and the second input I2 is 1, the arithmetic circuit 71 outputs the first signal SG1.

As shown in FIG. 2B, for example, the first state ST1 corresponds to "0" and the second state ST2 corresponds to "1". The third state ST3 is made to correspond to "0", and the fourth state ST4 is made to correspond to "1". The first signal SG1 is made to correspond to "1", and the second signal SG2 is made to correspond to "0".

As shown in FIG. 2B, the first element 51M (first laminated body 51) performs an "OR" operation on the first input I1 and the second input I2. The second element 52M (second laminated body 52) performs an "AND" operation on the first input I1 and the second input I2. The arithmetic circuit 71 performs an "XNOR" operation on the first input I1 and the second input I2.

As described above, in the arithmetic circuit 71, when the first element 51M is in the first state ST1 and the second element 52M is in the third state ST3, and when the first element 51M is in the second state ST2 and the second element 52M is in the fourth state. The first signal SG1 is output in the state ST4.

The arithmetic circuit 71 outputs the second signal SG2 when the first element 51M is in the second state ST2 and the second element 52M is in the third state ST3.

As described above, in the arithmetic unit 110, by using the two laminated bodies and the two conductive layers, the "XNOR" operation of the two inputs can be efficiently performed. It is possible to provide an arithmetic unit capable of speeding up. For example, even when each of these two inputs is plural and the number increases, the "XNOR" operation can be performed at high speed. The arithmetic unit 110 can be applied to deep learning and the like. In one example, the first input I1 can correspond to a "weight". The second input I2 can correspond to "activation". For example, in each element of a plurality of "weights", the product with "activation" is calculated. Furthermore, the sum of them is calculated. For example, the product-sum calculation of "weight" and "activation" can be performed at high speed.

In the embodiment, "0" and "1" may be interchanged with each other. For example, when the first input I1 is one of 0 and 1 (for example, "0") and the second input I2 is one of 0 and 1 (for example, "0"), the control circuit 72 sets the first element 51M. One state is ST1 (see FIG. 2A). When the first input I1 is one of the above 0 and 1 (for example, "0") and the second input I2 is the other of 0 and 1 (for example, "1"), the control circuit 72 sets the first element 51M to the first element 51M. Two states ST2 (see FIG. 2A). When the first input I1 is the other of 0 and 1 (for example, "1") and the second input I2 is the other of 0 and 1 (for example, "0"), the control circuit 72 sets the first element 51M to the first element 51M. Two states ST2 (see FIG. 2A). When the first input I1 is the other of 0 and 1 (for example, "1") and the second input I2 is the other of 0 and 1 (for example, "1"), the control circuit 72 is the first element 51M. Is the second state ST2 (see FIG. 2A).

When the first input I1 is one of the above 0 and 1 (for example, "0") and the second input I2 is the other of 0 and 1 (for example, "1"), the control circuit 72 is the second element 52M. Is the third state ST3 (see FIG. 2A). When the first input I1 is one of the above 0 and 1 (for example, "0") and the second input I2 is one of the above 0 and 1 (for example, "0"), the control circuit 72 is the second element 52M. Is the third state ST3 (see FIG. 2A). When the first input I1 is the other of 0 and 1 (for example, "1") and the second input I2 is the other of 0 and 1 (for example, "1"), the control circuit 72 is the second element. Let 52M be the fourth state ST4 (see FIG. 2A). When the first input I1 is the other of 0 and 1 (for example, "1") and the second input I2 is the other of 0 and 1 (for example, "0"), the control circuit 72 is the second element 52M. Is the third state ST3.

Hereinafter, an example of operation based on the first input I1 and the second input I2 will be described.

3 (a) to 3 (d) are schematic views illustrating the operation of the arithmetic unit according to the first embodiment.
These figures illustrate the first operation performed by the control circuit 72. FIG. 3A illustrates a state (initial state) of the first element 51M before the first operation. In the initial state illustrated in FIG. 3A, the magnetization 12M of the second magnetic layer 12 (see FIGS. 1B and 1C) is arbitrary. In one example, the first operation corresponds to the operation of writing the first input I1 (eg, information about the "weight") to the first element 51M.

The control circuit 72 executes the first step STP1 and the second step STP2 in the first operation. The second step STP2 is carried out after the first step STP1.

As shown in FIG. 3B, in the first step STP1, the control circuit 72 supplies the first current J1 from the first portion 21a to the second portion 21b to the first conductive layer 21 while supplying the first magnetic field. The layer 11 is set to the first potential V1. The first potential V1 is a potential based on the potential of the first conductive layer 21. At this time, the first element 51M (first laminated body 51) is in the first state ST1.

As shown in FIG. 3C, in the second step STP2, when the first input I1 is one of 0 and 1 (for example, “0”), the control circuit 72 is the second portion 21b to the first. The first magnetic layer 11 is set to the second potential V2 while supplying the second current J2 to the portion 21a to the first conductive layer 21. The second potential V2 is a potential based on the potential of the first conductive layer 21. In this case, in the first element 51M (first laminated body 51), the state after the first step STP1 (first state ST1) is maintained. For example, the magnetization 12M of the second magnetic layer 12 maintains the state after the first step STP1.

In one example, the polarity of the second potential V2 is opposite to the polarity of the first potential V1. For example, the first potential V1 may be a positive potential, and the second potential V2 may be a negative potential, for example. When the first magnetic layer 11 is set to the second potential V2, the magnetization 12M of the second magnetic layer 12 is not inverted, for example, regardless of the current flowing through the first conductive layer 21.

As shown in FIG. 3D, in the second step STP2, when the first input I1 is 0 and the other of 1 (for example, “1”), the control circuit 72 first sets the second current J2. The first magnetic layer 11 is set to the first potential V1 while being supplied to the conductive layer 21. In this case, the first element 51M (first laminated body 51) changes to the second state ST2. For example, the magnetization 12M of the second magnetic layer 12 changes from the state after the first step STP1.

In the operation of FIGS. 3B to 3D described above, the first element 51M (first laminated body 51) is set to the first state ST1, and then the first element 51M (first laminated body 51) is set to the first state ST1 according to the first input I1. The state ST1 is maintained or switching to the second state ST2 is performed. Switching to the second state ST2 is selected by supplying a second current J2 to the first conductive layer 21 and setting the potential of the first magnetic layer 11 to the first potential V1 or the second potential V2.

In the embodiment, the first portion 21a and the second portion 21b may be interchanged with each other.

4 (a) to 4 (d) are schematic views illustrating the operation of the arithmetic unit according to the first embodiment.
These figures illustrate the first operation performed by the control circuit 72. FIG. 4A illustrates a state (initial state) of the first element 51M before the first operation. Also in this case, the magnetization 12M is arbitrary in the initial state illustrated in FIG. 4A. Also in this case, the control circuit 72 executes the first step STP1 and the second step STP2 in the first operation.

The control circuit 72 executes the first step STP1 and the second step STP2 in the first operation. The second step STP2 is carried out after the first step STP1.

As shown in FIG. 4B, in the first step STP1, the control circuit 72 sets the first magnetic layer 11 to the first potential V1 while supplying the second current J2 to the first conductive layer 21. At this time, the first element 51M (first laminated body 51) is in the second state ST2.

As shown in FIG. 4C, in the second step STP2, when the first input I1 is 0 and the other of 1 (for example, “1”), the control circuit 72 first sets the first current J1. The first magnetic layer 11 is set to the second potential V2 while being supplied to the conductive layer 21. In this case, in the first element 51M (first laminated body 51), the state after the first step STP1 (second state ST2) is maintained.

As shown in FIG. 4D, in the second step STP2, when the first input I1 is one of 0 and 1 (for example, “0”), the control circuit 72 first sets the first current J1. The first magnetic layer 11 is set to the first potential V1 while being supplied to the conductive layer 21. In this case, the first element 51M (first laminated body 51) changes to the first state ST1.

In the operation of FIGS. 4 (b) to 4 (d) above, the first element 51M (first laminated body 51) is set to the second state ST2, and then the second element 51M (first laminated body 51) is set to the second state ST2, and then the second element 51M (first laminated body 51) is set to the second state ST2. The state ST2 is maintained or switching to the first state ST1 is performed. Switching to the first state ST1 is selected by supplying the first current J1 to the first conductive layer 21 and setting the potential of the first magnetic layer 11 to the first potential V1 or the second potential V2.

5 (a) to 5 (d) are schematic views illustrating the operation of the arithmetic unit according to the first embodiment.
These figures illustrate the second operation performed by the control circuit 72. FIG. 5A illustrates a state (initial state) of the second element 52M before the second operation. In the initial state illustrated in FIG. 5A, the magnetization 14M of the fourth magnetic layer 14 (see FIGS. 1D and 1E) is arbitrary. In one example, the second operation corresponds to the operation of writing the first input I1 (eg, information about the "weight") to the second element 52M.

The control circuit 72 executes the third step STP3 and the fourth step STP4 in the second operation. The fourth step STP4 is carried out after the third step STP3.

As shown in FIG. 5B, in the third step STP3, the control circuit 72 supplies the third current J3 from the fourth portion 22d to the fifth portion 22e to the second conductive layer 22, and the third magnetism. The layer 13 is set to the third potential V3. The third potential V3 is a potential based on the potential of the second conductive layer 22. At this time, the second element 52M (second laminated body 52) is in the third state ST3.

As shown in FIG. 5C, in the fourth step STP4, when the first input I1 is one of 0 and 1 (for example, “0”), the control circuit 72 has the fifth part 22e to the fourth. The third magnetic layer 13 is set to the fourth potential V4 while supplying the fourth current J4 to the portion 22d to the second conductive layer 22. The fourth potential V4 is a potential based on the potential of the second conductive layer 22. When the fourth potential V4 is applied, for example, the magnetization 14M of the fourth magnetic layer 14 does not change substantially. In the second element 52M (second laminated body 52), the state after the third step STP3 (third state ST3) is maintained.

As shown in FIG. 5D, in the fourth step STP4, when the first input I1 is the other of 0 and 1 (for example, “1”), the control circuit 72 secondizes the fourth current J4. The third magnetic layer 13 is set to the third potential V3 while being supplied to the conductive layer 22. As a result, the second element 52M (second laminated body 52) changes to the fourth state ST4. For example, the magnetization 14M of the fourth magnetic layer 14 changes from the state after the third step STP3.

In the operation of FIGS. 5B to 5D described above, the second element 52M (second laminated body 52) is set to the third state ST3, and then the third element 52M (second laminated body 52) is set to the third state ST3, and then the third element 52M (second laminated body 52) is set to the third state ST3. The state ST3 is maintained or switching to the fourth state ST4 is performed. Switching to the fourth state ST4 is selected by supplying a fourth current J4 to the second conductive layer 22 and setting the potential of the third magnetic layer 13 to the third potential V3 or the fourth potential V4.

In the embodiment, the fourth portion 22d and the fifth portion 22e may be interchanged with each other.

6 (a) to 6 (d) are schematic views illustrating the operation of the arithmetic unit according to the first embodiment.
These figures illustrate the second operation performed by the control circuit 72. FIG. 6A illustrates a state (initial state) of the second element 52M before the second operation. The control circuit 72 executes the third step STP3 and the fourth step STP4 in the second operation.

As shown in FIG. 6B, in the third step STP3, the control circuit 72 sets the third magnetic layer 13 to the third potential V3 while supplying the fourth current J4 to the second conductive layer 22. At this time, the second element 52M (second laminated body 52) is in the fourth state ST4.

As shown in FIG. 6C, in the fourth step STP4, when the first input I1 is 0 and the other of 1 (for example, “1”), the control circuit 72 sets the third current J3 to the second. The third magnetic layer 13 is set to the fourth potential V4 while being supplied to the conductive layer 22. In this case, in the second element 52M (second laminated body 52), the state after the third step STP3 (fourth state ST4) is maintained.

As shown in FIG. 6D, in the fourth step STP4, when the first input I1 is one of 0 and 1 (for example, “0”), the control circuit 72 sets the third current J3 to the second. The third magnetic layer 13 is set to the third potential V3 while being supplied to the conductive layer 22. In this case, the second element 52M (second laminated body 52) changes to the third state ST3.

In the operation of FIGS. 6 (b) to 6 (d) described above, the second element 52M (second laminated body 52) is set to the fourth state ST4, and then the fourth element 52M (second laminated body 52) is set to the fourth state ST4, and then the fourth element 52M (second laminated body 52) is set according to the first input I1. The state ST4 is maintained or switching to the third state ST3 is performed. Switching to the third state ST3 is selected by supplying a third current J3 to the second conductive layer 22 and setting the potential of the third magnetic layer 13 to the third potential V3 or the fourth potential V4.

Hereinafter, an example of the operation performed based on the second input I2 will be described. The second input I2 corresponds to, for example, information about "activation".

7 (a) to 7 (d) are schematic views illustrating the operation of the arithmetic unit according to the first embodiment.
The control circuit 72 further performs a third operation after the first operation. The third operation is performed based on, for example, the second input I2. These figures illustrate the third operation. The figure on the left side of these figures illustrates the state before the third operation (the state after the first operation). The figure on the right side of these figures illustrates the third operation and the state after the third operation.

As shown in FIG. 7A, the first input I1 is one of 0 and 1 (for example, “0”). At this time, the first element 51M is in the first state ST1. At this time, in the third operation, when the second input I2 is one of 0 and 1 (for example, “0”), the control circuit 72 supplies the second current J2 to the first conductive layer 21 while supplying the second current J2. The first magnetic layer 11 is set to the second potential V2. As a result, the first state ST1 (for example, "0") is maintained.

As shown in FIG. 7B, in this case as well, the first input I1 is one of 0 and 1 (for example, “0”). At this time, the first element 51M is in the first state ST1. At this time, in the third operation, when the second input I2 is the other of 0 and 1 (for example, "1"), the control circuit 72 supplies the second current J2 to the first conductive layer 21 while supplying the second current J2. The first magnetic layer 11 is set to the first potential V1. As a result, the second state ST2 (for example, "1") is formed.

As shown in FIG. 7 (c), the first input I1 is the other of 0 and 1 (for example, "1"). At this time, the first element 51M is in the second state ST2. At this time, in the third operation, when the second input I2 is one of 0 and 1 (for example, “0”), the control circuit 72 supplies the second current J2 to the first conductive layer 21 while supplying the second current J2. The first magnetic layer 11 is set to the second potential V2. As a result, the second state ST2 (for example, "1") is maintained.

As shown in FIG. 7D, also in this case, the first input I1 is the other of 0 and 1 (for example, “1”). At this time, the first element 51M is in the second state ST2. At this time, in the third operation, when the second input I2 is the other of 0 and 1 (for example, "1"), the control circuit 72 supplies the second current J2 to the first conductive layer 21 while supplying the second current J2. The first magnetic layer 11 is set to the first potential V1. As a result, the second state ST2 (for example, "1") is formed.

By such an operation, the operations illustrated in FIGS. 2 (a) and 2 (b) are performed in the first element 51M (and the first laminated body 51).

8 (a) to 8 (d) are schematic views illustrating the operation of the arithmetic unit according to the first embodiment.
The control circuit 72 further performs the fourth operation after the second operation. The fourth operation is performed based on, for example, the second input I2. These figures illustrate the fourth operation. The figure on the left side of these figures illustrates the state before the fourth operation (the state after the second operation). The figure on the right side of these figures illustrates the fourth operation and the state after the fourth operation.

As shown in FIG. 8A, the first input I1 is one of 0 and 1 (for example, “0”). At this time, the second element 52M is in the third state ST3. In the fourth operation, the control circuit 72 supplies the third current J3 to the second conductive layer 22 and the third magnetism when the second input I2 is the other of 0 and 1 (for example, “1”). The layer is set to the fourth potential V4. In the second element 52M, the third state ST3 (for example, "0") is maintained.

As shown in FIG. 8B, in this case as well, the first input I1 is one of 0 and 1 (for example, “0”). The second element 52M is in the third state ST3. In the fourth operation, when the second input I2 is one of 0 and 1 (for example, “0”), the control circuit 72 supplies the third current J3 to the second conductive layer 22 and the third magnetism. The layer 13 is set to the third potential V3. The second element 52M is in the third state ST3 (for example, “0”).

As shown in FIG. 8 (c), the first input I1 is the other of 0 and 1 (for example, "1"). At this time, the second element 52M is in the fourth state ST4. In the fourth operation, the control circuit 72 supplies the third current J3 to the second conductive layer 22 and the third magnetism when the second input I2 is the other of 0 and 1 (for example, “1”). The layer is set to the fourth potential V4. In the second element 52M, the fourth state ST4 (for example, "1") is maintained.

As shown in FIG. 8D, also in this case, the first input I1 is the other of 0 and 1 (for example, “1”). The second element 52M is in the fourth state ST4. In the fourth operation, when the second input I2 is one of 0 and 1 (for example, “0”), the control circuit 72 supplies the third current J3 to the second conductive layer 22 and the third magnetism. The layer 13 is set to the third potential V3. The second element 52M changes to the fourth state ST4 (for example, "1").

By such an operation, the operations illustrated in FIGS. 2 (a) and 2 (b) are performed in the second element 52M (and the second laminated body 52).

In the operations shown in FIGS. 8 (a) to 8 (d), the information of the second input I2 is inverted ("0" and "1" are mutually inverted by the operations shown in FIGS. 7 (a) to 7 (d). The operation when (replacement) is performed.

For example, the odor of the first element 51M is subjected to an "OR" operation between the first input I1 and the second input I2. In the second element 52M, the "AND" operation of the first input I1 and the inversion of the second input I2 is performed.

The inverting signal of the second input I2 may be generated by, for example, the control circuit 72. The control circuit 72 may include an inverting circuit for the second input I2.

Hereinafter, one example of the arithmetic unit 110 will be further described.

FIG. 9 is a schematic diagram illustrating an arithmetic unit according to the first embodiment.
FIG. 9 is a block diagram of the arithmetic unit 110.
As shown in FIG. 9, the arithmetic unit 110 is provided with an element unit 54 and a circuit unit 70. As described above, the element unit 54 includes the first element 51M and the second element 52M. The circuit unit 70 includes an arithmetic circuit 71 and a control circuit 72. As will be described later, a plurality of first elements 51M may be provided. The plurality of first elements 51M are included in the first element group 51MAT. A plurality of second elements 52M may be provided. The plurality of second elements 52M are included in the second element group 52MAT. For example, the number of the plurality of first elements 51M is the same as the number of the plurality of second elements 52M.

In this example, the arithmetic unit 110 is provided with a controller 63C, a WL driver 63DR, a WL decoder 63DE, a first BL driver 61DR, a second BL driver 62DR, a first BL decoder 61DE, and a second BL decoder 62DE. The controller 63C controls the WL driver 63DR, the WL decoder 63DE, the first BL driver 61DR, the second BL driver 62DR, the first BL decoder 61DE, and the second BL decoder 62DE. These drivers and decoders are included in the control circuit 72. The controller 63C may be included in the control circuit 72.

As will be described later, the first BL decoder 61DE is electrically connected to the first conductive layer 21 of the first element 51M. As will be described later, the second BL decoder 62DE is electrically connected to the second conductive layer 22 of the second element 52M. The first BL decoder 61DE supplies the first current J1 or the second current J2 to the first conductive layer 21. The second BL decoder 62DE supplies the third current J3 or the fourth current J4 to the second conductive layer 22.

The first BL decoder 61DE is electrically connected to the first element 51M. The first BL decoder 61DE is electrically connected to the first BL driver 61DR. The first BL driver 61DR is electrically connected to the first data buffer 61DB. The first BL decoder 61DE, the first BL driver 61DR, and the first data buffer 61DB are included in the control circuit 72. The potential of the first magnetic layer 11 of the first element 51M is controlled by the first BL decoder 61DE.

The second BL decoder 62DE is electrically connected to the second element 52M. The second BL decoder 62DE is electrically connected to the second BL driver 62DR. The second BL driver 62DR is electrically connected to the second data buffer 62DB. The second BL decoder 62DE, the second BL driver 62DR, and the second data buffer 62DB are included in the control circuit 72. The potential of the third magnetic layer 13 of the second element 52M is controlled by the second BL decoder 62DE.

An arithmetic circuit 71 is provided between the first element 51M and the second element 51M. The control circuit 72 performs the above operation. The calculation circuit 71 outputs the above calculation results (for example, the first signal SG1 and the second signal SG2).

10 (a) and 10 (b) are schematic views illustrating the arithmetic unit according to the first embodiment.
As shown in FIG. 10A, a current is supplied to _{the first BL decoder 61DE from the power supply WDV U via the conductive layer driver CLD.} A current is supplied to the _{first BL decoder 61DE from the power supply BWDV U} via another conductive layer driver CLD. The output of the first buffer BF1 is supplied to the first BL decoder 61DE via the BL driver BLD. Data regarding, for example, the first input I1 and the second input I2 are supplied to the first buffer BF1.

In this example, a plurality of first laminated bodies 51 are provided on one first conductive layer 21. One of the outputs of the first BL decoder 61DE is electrically connected to the first portion 21a of the first conductive layer 21 via a transistor. Another output of the first BL decoder 61DE is electrically connected to the second portion 21b of the first conductive layer 21 via a transistor. Yet another output of the first BL decoder 61DE is electrically connected to one of the plurality of first magnetic layers 11 via the transistor TR1. Each gate of these transistors is electrically connected to the WL decoder 63DE.

In this example, a plurality of first conductive layers 21 are arranged in a matrix along the X-axis direction and the Y-axis direction. For example, in the first element group 51MAT, a plurality of first elements 51M are arranged in a matrix along the X-axis direction and the Y-axis direction.

To the 2BL decoder 62DE, current from the power supply WDV _L via the conductive layer driver CLD is supplied. To the 2BL decoder 62DE, a current from the power supply BWDV _L is supplied through another conductive layer driver CLD. The output of the second buffer BF2 is supplied to the second BL decoder 62DE via the BL driver BLD. For example, data relating to the first input I1 and the second input I2 is supplied to the second buffer BF2. In this example, the second buffer BF2 includes an inverter INV (inverting circuit). For example, the second buffer BF2 outputs a signal (inverted information) inverted with respect to the output from the first buffer BF1.

In this example, a plurality of second laminated bodies 52 are provided on one second conductive layer 22. One of the outputs of the second BL decoder 62DE is electrically connected to the fourth portion 22d of the second conductive layer 22 via a transistor. Another output of the second BL decoder 62DE is electrically connected to the fifth portion 22e of the second conductive layer 22 via a transistor. Yet another output of the second BL decoder 61DE is electrically connected to one of the plurality of third magnetic layers 12 via the transistor TR2. Each gate of these transistors is electrically connected to the WL decoder 63DE.

In this example, the plurality of second conductive layers 22 are arranged in a matrix along the X-axis direction and the Y-axis direction. For example, in the second element group 52MAT, a plurality of second elements 52M are arranged in a matrix along the X-axis direction and the Y-axis direction.

The WL control signal WL is supplied to the WL decoder 63DE via the WL driver WLD.

For example, the arithmetic circuit 71 includes a plurality of sense amplifiers SA. One of the plurality of sense amplifiers SA is electrically connected to the first magnetic layer 11 via the transistor TR1. One of the plurality of sense amplifiers SA has a value corresponding to the electrical resistance of the first path CP1 (see FIG. 1A) including the path between the first magnetic layer 11 and the first conductive layer 21 (for example,). At least one of electrical resistance, current and voltage) can be detected.

One of the plurality of sense amplifiers SA is electrically connected to the third magnetic layer 13 via the transistor TR2. One of the plurality of sense amplifiers SA has a value corresponding to the electrical resistance of the second path CP2 (see FIG. 1A) including the path between the third magnetic layer 13 and the second conductive layer 22 (for example,). At least one of electrical resistance, current and voltage) can be detected.

A state corresponding to the first input I1 and the second input I2 is formed in the first element 51M. The state formed in the first element 51M is, for example, the calculation result of "OR". A state corresponding to the first input I1 and the second input I2 is formed in the second element 52M. The state formed in the second element 52M is, for example, the result of "AND" calculation of the inversion of the first input I1 and the second input I2. The calculation circuit 71 can output, for example, the calculation result of "XNOR".

The first buffer BF1 and the second buffer BF2 described above are included in, for example, the circuit unit 70. The first buffer BF1 is electrically connected to the first element 51M. The first buffer BF1 can store at least one of the first input I1 and the second input I2. The second buffer BF2 is electrically connected to the second element 52M. The second buffer BF2 can store at least one of the above of the first input I1 and the second input I2. For example, the second buffer BF2 can output a signal inverted with respect to the signal output from the first buffer BF1. For example, the second buffer BF2 may include an inverter INV.

As shown in FIG. 10B, in the arithmetic unit 110a according to the embodiment, the BL driver BLD provided between the second buffer BF2 and the second BL decoder 62DE includes an inverter INV. As a result, for example, the second BL decoder 62DE outputs a signal (inverted information) that is inverted with respect to the output from the first BL decoder 61DE.

As described above, the circuit unit 70 includes a first circuit (for example, a first BL decoder 61DE) electrically connected to the first element 51M. The first circuit can output a signal corresponding to at least one of the first input I1 and the second input I2. The circuit unit 70 further includes a second circuit (for example, a second BL decoder 62DE) electrically connected to the second element 52M. The second circuit can output a signal corresponding to at least one of the above of the first input I1 and the second input I2. For example, the second circuit described above includes an inverter INV. For example, the second circuit outputs a signal (inverted information) that is inverted with respect to the output from the first circuit.

11 to 15 are schematic views illustrating the operation of the arithmetic unit according to the first embodiment.
These figures exemplify the state of data held in the laminated body (for example, the first laminated body 51 and the second laminated body 52). In one example, the data stored in the first laminate 51 corresponds to the direction of magnetization of the magnetization 12M of the second magnetic layer 12. In one example, the data stored in the second laminate 52 corresponds to the direction of magnetization of the magnetization 14M of the fourth magnetic layer 14.

For example, in the initial state illustrated in FIG. 11, the data (for example, the value) stored in the plurality of laminated bodies (for example, the first element 51M and the second element 52M) is arbitrary.

As shown in FIG. 12, weight data Wm and _n are written in the first element 51M and the second element 52M. This operation corresponds to, for example, the first operation and the second operation. As shown in FIG. 12, for example, it is desirable that the same value is written at positions symmetrical with respect to the arithmetic circuit 71.

For example, the element unit 54 includes a plurality of first elements 51M and a plurality of second elements 52M. At least a part of the arithmetic circuit 71 (for example, a sense amplifier SA) is provided between at least a part of the plurality of first elements 51M and at least a part of the plurality of second elements 52M. Let "N" be any integer greater than or equal to 1. For example, "N" is not more than or equal to the number of the plurality of first elements 51M, and is less than or equal to the number of the plurality of second elements 52M. The Nth first element 51M is between the (N + 1) th first element 51M and the arithmetic circuit 71. For example, from the arithmetic circuit 71, the first to Nth first elements 51M are arranged in this order. The Nth second element 52M is between the (N + 1) th second element 52M and the arithmetic circuit 71. For example, from the arithmetic circuit 71, the first to Nth second elements 52M are arranged in this order. The first input I1 corresponding to the Nth first element 51M is the same as the first input I1 corresponding to the Nth second element 52M.

As shown in FIG. 13, to store the second input I2 _(such as I 1 ~I _m) to the first buffer BF1. On the other hand, the inversion of the second input I2 (xI _{1 to xI m,} etc.) is stored in the second buffer BF2. For example, by providing the second buffer BF2 with an inverter INV (see FIG. 10A), inverted data can be stored.

As shown in FIG. 14, by performing the calculation, the calculation results (values O _{1, 1} to values O _{m, n} ) of "OR" regarding the first input I1 and the second input I2 are stored in the first element 51M. Will be done. In the calculation, for example, in the first element 51M, while supplying the second current J2 to the first conductive layer 21, the first magnetic layer 11 is subjected to the first potential V1 or the second potential V2 according to the second input I2. (See FIGS. 7 (a) to 7 (d)).

On the other hand, as shown in FIG. 14, by performing the calculation, the calculation result of "AND" regarding the inversion of the first input I1 and the second input I2 (values A _{1, 1} to value A) is performed on the second element 52M. _{m, n} ) is saved. In the calculation, for example, in the second element 52M, while supplying the third current J3 to the second conductive layer 22, the third magnetic layer 13 is subjected to the third potential V3 or the fourth potential V4 according to the second input I2. (See FIGS. 8 (a) to 8 (d)).

As shown in FIG. 15, in the arithmetic circuit 71, the first signal SG1 or the second signal SG2 (signals F _{1, 1 to} F _{m) is based on the state of the first element 51M and the state of the second element 52M. , 1} ) is output.

For example, as described above, in the arithmetic circuit 71, when the first element 51M is in the first state ST1 and the second element 52M is in the third state ST3, and when the first element 51M is in the second state ST2, the second element The first signal SG1 (for example, "1") is output when the 52M is in the fourth state ST4. For example, the arithmetic circuit 71 outputs a second signal SG2 (for example, “0”) when the first element 51M is in the second state ST2 and the second element 52M is in the third state ST3.

For example, as described with respect to FIG. 2B, when the difference between the value of the first element 51M and the value of the second element 52M is small (or when there is no difference), the value is output from the arithmetic circuit 71. The signal 71S is the first signal SG1 (for example, “1”). When the difference between the value of the first element 51M and the value of the second element 52M is large, the signal 71S output from the arithmetic circuit 71 is the second signal SG2 (for example, “0”). Such an calculation is performed, for example, by detecting the difference between the signal obtained from the first element 51M and the signal obtained from the second element 52M by the sense amplifier SA provided in the calculation circuit 71.

Further, by providing an offset between the electric resistance of the first element 51M and the electric resistance of the second element 52M, the above calculation becomes easier.

FIG. 16 is a schematic diagram illustrating an arithmetic unit according to the first embodiment.
The horizontal axis of FIG. 16 is the electric resistance Re1. The vertical axis is the distribution Ds1. As shown in FIG. 16, for example, the third electric resistance R3 may be between the first electric resistance R1 and the second electric resistance R2. For example, the second electric resistance R2 may be between the third electric resistance R3 and the fourth electric resistance R4.

For example, the area of the first laminated body 51 (for example, see FIG. 1 (a)) in the XY plane and the area of the second laminated body 52 (for example, see FIG. 1 (a)) in the XY plane. The above-mentioned electrical resistance relationship can be obtained by differentiating each other.

In the example shown in FIG. 16, when the electric resistance obtained from the first element 51M is higher than the electric resistance obtained from the second element 52M, the arithmetic circuit 71 outputs the second signal SG2 (for example, “0”). .. For example, when the electric resistance obtained from the first element 51M is the same as the electric resistance obtained from the second element 52M, or when it is lower than the electric resistance obtained from the second element 52M, the arithmetic circuit 71 performs the first signal. Outputs SG1 (for example, "1").

By imparting an offset to the electrical resistance of the plurality of elements in this way, it becomes easy to generate the output of the first signal SG1 or the second signal SG2 in the arithmetic circuit 71.

The above offset may be made in the arithmetic circuit 71. Hereinafter, some examples of offsets will be described.
FIG. 17 is a schematic diagram illustrating a part of the arithmetic unit according to the first embodiment.
These figures show an example of the arithmetic circuit 71.

As shown in FIG. 17, in the arithmetic unit 111, the arithmetic circuit 71 reads, for example, the difference between the current flowing through the first input terminal IN1 and the current flowing through the second input terminal IN2. The first input terminal IN1 is electrically connected to the first path CP1 (see FIG. 1A). The second input terminal IN2 is electrically connected to the second path CP2 (see FIG. 1A). In this example, the resistor RO is connected to the second input terminal IN2. As a result, an offset is generated between the current obtained from the first element 51M and the current obtained from the second element 52M.

As described above, in this example, the arithmetic circuit 71 has a first sense circuit SEN1 electrically connected to the first path CP1 and a second sense circuit SEN2 electrically connected to the second path CP2. include. The resistance of the circuit included in the first sense circuit SEN1 is different from the resistance of the circuit included in the second sense circuit SEN2. In this example, the resistors RO are provided so that the resistors in these circuits are different from each other. For example, the relationship corresponding to the electrical resistance described with respect to FIG. 16 can be obtained.

In this example, the read voltage Voltage is supplied to the sense circuit SEN. The first sense circuit SEN1 and the second sense circuit SEN2 are electrically connected to the ground potential (or, for example, voltage Vss). For example, a signal corresponding to the difference between the current flowing through the first input terminal IN1 and the current flowing through the second input terminal IN2 is output to the output OUT or the output OUTB.

18 (a) to 18 (c) are schematic views illustrating a part of the arithmetic unit according to the first embodiment.
As shown in FIG. 18A, in the arithmetic unit 112, the arithmetic circuit 71 includes a first sense circuit SEN1 and a second sense circuit SEN2. The first sense circuit SEN1 includes the circuit SENA1 and the first transistor M1. The second sense circuit SEN2 includes the circuit SENA2 and the second transistor M2.

The first transistor M1 is connected to the gate of the circuit SENA1. The second transistor M2 is connected to the gate of the circuit SENA2. The other end of the first transistor M1 is electrically connected to the ground potential (or, for example, voltage Vss) via the first element 51M (first path CP1). The first read current Iread1 flows through the first transistor M1. The other end of the second transistor M2 is electrically connected to the ground potential (or, for example, voltage Vss) via the second element 52M (second path CP2). The second read current Iread2 flows through the second transistor M2. A clamp voltage Vlamp is supplied to the gate of the first transistor M1 and the gate of the second transistor M2.

FIG. 18B illustrates the first transistor M1. The first transistor M1 includes a first source S1 and a first drain D1 provided in the first semiconductor layer SL1, a first insulating film IL1, and a first gate G1. The first transistor M1 has a first gate width w1. The first gate width w1 corresponds to, for example, the length of the first gate G1 along the direction intersecting the direction from the first source S1 to the first drain D1.

FIG. 18C illustrates the second transistor M2. The second transistor M2 includes a second source S2 and a second drain D2 provided in the second semiconductor layer SL2, a second insulating film IL2, and a second gate G2. The second transistor M2 has a second gate width w2. The second gate width w2 corresponds to, for example, the length of the second gate G2 along the direction intersecting the direction from the second source S2 to the second drain D2.

In the embodiment, the first gate width w1 is wider than the second gate width w2. As a result, the resistance (on resistance) of the second transistor M2 becomes higher than the resistance (on resistance) of the first transistor M1. For example, the resistance of the second path CP2 becomes higher than the resistance of the first path CP1, and an offset occurs. This provides, for example, the relationship corresponding to the electrical resistance described with respect to FIG.

FIG. 19 is a schematic diagram illustrating a part of the arithmetic unit according to the first embodiment.
As shown in FIG. 19, in the arithmetic unit 113, the arithmetic circuit 71 includes a first sense circuit SEN1 and a second sense circuit SEN2. The first sense circuit SEN1 includes the circuit SENA1 and the first transistor M1. The second sense circuit SEN2 includes the circuit SENA2 and the second transistor M2.

In this example, the first clamp voltage Vlamp1 applied to the first gate G1 of the first transistor M1 is different from the second clamp voltage Vlamp2 applied to the second gate G2 of the second transistor M2. For example, the first clamp voltage Vlamp1 is higher than the second clamp voltage Vlamp2. As a result, for example, the resistance of the second path CP2 becomes higher than the resistance of the first path CP1, and an offset occurs. This provides, for example, the relationship corresponding to the electrical resistance described with respect to FIG.

As described above, the arithmetic circuit 71 includes a first sense circuit SEN1 electrically connected to the first path CP1, a second sense circuit SEN2 electrically connected to the second path CP2, and an offset voltage circuit (first). It includes at least one of a circuit for one clamp voltage Vlamp1 and a circuit for a second clamp voltage Vlamp2). The offset voltage circuit is connected to at least one of the 1-sense circuit SEN1 and the 2nd sense circuit SEN2. The voltage due to the offset voltage circuit (at least one of the circuit for the first clamp voltage Vlamp1 and the circuit for the second clamp voltage Vlamp2) is different from each other.

FIG. 20 is a schematic diagram illustrating a part of the arithmetic unit according to the first embodiment.
As shown in FIG. 20, in the arithmetic unit 114, a voltage sense type lead circuit may be used as the arithmetic circuit 71.

21 (a) and 21 (b) are schematic views illustrating a part of the arithmetic unit according to the first embodiment.
As shown in FIG. 21 (a), in the arithmetic unit 115, a voltage sense type sense amplifier SA is used as the arithmetic circuit 71. In this example, the sense amplifier SA is electrically connected to the first path CP1 and the second path CP2. In this example, the first capacitor C1 is electrically connected to the first path CP1. The second capacitor C2 is electrically connected to the second path CP2. These capacitors hold the voltage read by the sense amplifier SA. In this example, the capacitances of these capacitors differ from each other. For example, the electric capacity of the first capacitor C1 is larger than the electric capacity of the second capacitor C2. This provides, for example, the relationship corresponding to the electrical resistance described with respect to FIG.

In this case, as shown in FIG. 21B, a circuit without an offset may be used for the sense amplifier SA.

In the operations described with reference to FIGS. 13 to 15, calculations are collectively performed by the plurality of first elements 51M and the plurality of second elements 52M as a whole. In this case, for example, the current supplied from the light driver to the element unit 54 is large.

In the embodiment, the calculation may be performed by a part group of the plurality of first elements 51M and a part group of the plurality of second elements 52M. For example, the current supplied from the light driver to the element unit 54 can be reduced. An example of such an operation will be described below.

22 to 25 are schematic views illustrating the operation of the arithmetic unit according to the first embodiment.
FIG. 22 illustrates the operation after the _{weight data Wm and n} are written to the first element 51M and the second element 52M. As shown in FIG. 22, to store the second input I2 _(such as I 1 ~I _m) to the first buffer BF1. On the other hand, the inversion of the second input I2 (xI _{1 to xI m,} etc.) is stored in the second buffer BF2.

As shown in FIG. 23, the row in the first row is activated, and the “OR” operation is performed in the first row of the first element 51M. On the other hand, the row in the first row is activated, and the "AND" operation is performed in the first row of the second element 52M.

As shown in FIG. 24, the row in the second row is activated, and the “OR” operation is performed in the second row of the first element 51M. On the other hand, the row in the second row is activated, and the "AND" operation is performed in the second row of the second element 52M.

After that, the row to be activated is sequentially changed to perform the calculation. As shown in FIG. 25, the row in the last line is activated to perform the calculation. As a result, the calculation of the plurality of first elements 51M and the plurality of second elements 52M as a whole is completed. In this method, the current can be reduced.

For example, in the examples described with respect to FIGS. 11 to 15, the first input I1 corresponds to a "weight". The second input I2 corresponds to "activation". These inputs may be interchanged as described below.

(Second Embodiment)
In this embodiment, the first input I1 corresponds to "activation" and the second input I2 corresponds to "wait".

26 to 30 are schematic views illustrating the operation of the arithmetic unit according to the second embodiment.
These figures exemplify the state of data held in the laminated body (for example, the first laminated body 51 and the second laminated body 52). For example, in the initial state illustrated in FIG. 26, the data (for example, the value) stored in the plurality of laminated bodies (for example, the first element 51M and the second element 52M) is arbitrary.

As shown in FIG. 27, activation data Im _{, n} (input data) are written in the first element 51M and the second element 52M. This operation corresponds to, for example, the first operation and the second operation. As shown in FIG. 27, for example, it is desirable that the same value is written at positions symmetrical with respect to the arithmetic circuit 71.

As shown in FIG. 28, the second input I2 (W _{1 to} W _m, etc.) is stored in the first buffer BF1. On the other hand, the inversion of the second input I2 (xW _{1 to xW m,} etc.) is stored in the second buffer BF2.

As shown in FIG. 29, by performing the calculation, the calculation results (values O _{1, 1} to values O _{m, n} ) of "OR" regarding the first input I1 and the second input I2 are stored in the first element 51M. Will be done. In the calculation, for example, in the first element 51M, while supplying the second current J2 to the first conductive layer 21, the first magnetic layer 11 is set to the first potential V1 or the second potential V2 according to the second input I2. do.

On the other hand, as shown in FIG. 29, by performing the calculation, the calculation result of "AND" regarding the inversion of the first input I1 and the second input I2 (values A _{1, 1} to value A) is performed on the second element 52M. _{m, n} ) is saved. In the calculation, for example, in the second element 52M, while supplying the third current J3 to the second conductive layer 22, the third magnetic layer 13 is subjected to the third potential V3 or the fourth potential V4 according to the second input I2. And.

As shown in FIG. 30, in the arithmetic circuit 71, the first signal SG1 or the second signal SG2 (signals F _{1, 1 to} F _{m) is based on the state of the first element 51M and the state of the second element 52M. , 1} ) is output.

In this case as well, in the arithmetic circuit 71, when the first element 51M is in the first state ST1 and the second element 52M is in the third state ST3, and when the first element 51M is in the second state ST2 and the second element 52M is in the fourth state. The first signal SG1 (for example, "1") is output in the state ST4. For example, the arithmetic circuit 71 outputs the second signal SG2 (for example, “0”) when the first element 51M is in the second state ST2 and the second element 52M is in the third state ST3.

(Third Embodiment)
Hereinafter, some examples of the arithmetic unit according to the third embodiment will be described.
FIG. 31 is a schematic diagram illustrating an arithmetic unit according to the third embodiment.
As shown in FIG. 31, the arithmetic unit 130 includes an XNOR arithmetic circuit 55. The XNOR arithmetic circuit 55 has, for example, the configurations described with respect to the first embodiment and the second embodiment. The XNOR calculation circuit 55 includes the element unit 54 and the calculation circuit 71. The XNOR arithmetic circuit 55 can carry out the above operation.

The arithmetic unit 130 is one of the examples of the computer system. For example, the arithmetic unit 130 includes a plurality of arithmetic elements PE (for example, Processor Element). For example, the memory controller 56 controls the XNOR arithmetic circuit 55 and the arithmetic element PE.

In this example, the plurality of arithmetic elements PE, the memory controller 56, and the XNOR arithmetic circuit 55 are provided on one chip. This chip is, for example, a processor chip. In this processor chip, for example, DNN (Deep Neural Network) and the like can be calculated.

In this example, the arithmetic unit 130 further includes a memory 57 (eg DRAM). The memory 57 (for example, DRAM) can store, for example, data related to weights, data related to activation (input), output data, and the like.

The arithmetic element PE, for example, performs at least one of a sum operation, an activation operation, and a Batch Normalization process other than the product operation in the "convolution operation" (Convolution) in DNN.

32 (a) to 32 (d) are schematic views illustrating the operation of the arithmetic unit according to the third embodiment.
These figures illustrate the operation in the arithmetic unit 130. As shown in FIG. 32 (a), the weight data W is supplied to the XNOR calculation circuit 55 from the memory 57.

As shown in FIG. 32 (b), data I regarding activation (for example, input) is supplied from the memory 57 to the XNOR calculation circuit 55.

As shown in FIG. 32 (c), the calculation result (for example, product calculation) by the XNOR calculation circuit 55 is supplied to a plurality of calculation element PEs via, for example, the memory controller 56. In the calculation element PE, a sum calculation, an activation calculation, a Batch Normalization process, and the like are performed.

As shown in FIG. 32 (d), the calculation result is stored in the memory 57.

FIG. 33 is a schematic diagram illustrating an arithmetic unit according to the third embodiment.
As shown in FIG. 33, the arithmetic unit 131 further includes a buffer circuit 55B in addition to a plurality of arithmetic elements PE, a memory controller 56, an XNOR arithmetic circuit 55 and a memory 57 (for example, DRAM). The buffer circuit 55B can store, for example, data regarding activation (eg, input).

For example, in the DNN calculation, a calculation using a plurality of weight data (for example, "convolution calculation") may be performed on the same activation data (for example, input data). For example, the input data can be reused. By storing the input data in the buffer circuit 55B, for example, the amount of data transferred between the memory 57 and the processor can be reduced.

34 (a) to 34 (d) are schematic views illustrating the operation of the arithmetic unit according to the third embodiment.
These figures illustrate the operation in the arithmetic unit 131. As shown in FIG. 34 (a), the weight data W is supplied to the XNOR calculation circuit 55 from the memory 57. On the other hand, data I regarding activation (for example, input) is supplied from the memory 57 to the buffer circuit 55B.

As shown in FIG. 34 (b), the data I regarding activation (for example, input) is transferred from the buffer circuit 55B to the XNOR calculation circuit 55. Then, the XNOR calculation circuit 55 performs the XNOR calculation.

As shown in FIG. 34 (c), the calculation result (for example, product calculation) by the XNOR calculation circuit 55 is supplied to a plurality of calculation element PEs via, for example, the memory controller 56. In the calculation element PE, a sum calculation, an activation calculation, a Batch Normalization process, and the like are performed.

As shown in FIG. 34 (d), at least a part of the calculation result is stored in the memory 57. When the buffer circuit 55B has free space, at least a part of the calculation result may be stored in the buffer circuit 55B. At least a part of the calculation result stored in the buffer circuit 55B may be used for the later calculation.

FIG. 35 is a schematic diagram illustrating an arithmetic unit according to the third embodiment.
As shown in FIG. 35, in the arithmetic unit 132, a buffer unit 58 is provided in addition to a plurality of arithmetic element PEs, a plurality of XNOR arithmetic circuits 55, and a memory controller 56. In this example, a memory 57 (eg DRAM) is further provided.

In this example, the XNOR arithmetic circuit 55 is provided corresponding to each of the plurality of arithmetic elements PE. The buffer unit 58 can store at least one of weight data, activation data (for example, input data), and output data, for example. The buffer portion 58 can be formed by, for example, an SRAM based on a semiconductor (for example, silicon). The buffer portion 58 can be formed by, for example, a magnetic memory based on a magnetic layer. The buffer unit 58 may include, for example, a memory element having the same configuration as the first laminated body 51 described above.

36 (a) to 36 (d) are schematic views illustrating the operation of the arithmetic unit according to the third embodiment.
These figures illustrate the operation in the arithmetic unit 132. As shown in FIG. 36 (a), the wait data W is supplied to the XNOR calculation circuit 55 from the buffer unit 58.

As shown in FIG. 36 (b), the data I regarding activation (for example, input) is transferred from the buffer unit 58 to the XNOR calculation circuit 55. Then, the XNOR calculation circuit 55 performs the XNOR calculation.

As shown in FIG. 36 (c), the calculation result (for example, product calculation) by the XNOR calculation circuit 55 is supplied to, for example, the calculation element PE. In the calculation element PE, a sum calculation, an activation calculation, a Batch Normalization process, and the like are performed.

As shown in FIG. 36 (d), at least a part of the calculation result is stored in the buffer unit 58. At least a part of the calculation result may be stored in the memory 57.

FIG. 37 is a schematic diagram illustrating an arithmetic unit according to the third embodiment.
As shown in FIG. 37, in the arithmetic unit 133, in addition to the plurality of arithmetic element PEs, the plurality of XNOR arithmetic circuits 55, and the memory controller 56, a first buffer unit 58a and a second buffer unit 58b are provided.

For example, weight data is stored in the first buffer unit 58a. For example, activation data (for example, input data) or input / output data is stored in the second buffer unit 58b. For example, the amount of DNN weight data is greater than the amount of input / output data. The first buffer portion 58a may include, for example, a magnetic memory based on a magnetic layer. The second buffer portion 58b may include, for example, an SRAM based on a semiconductor (for example, silicon).

FIG. 38 is a schematic diagram illustrating an arithmetic unit according to the third embodiment.
As shown in FIG. 38, in the arithmetic unit 134, a controller 56a for the first buffer unit 58a and a controller 56b for the second buffer unit 58b are provided. Further, the controller 56a is provided with a prefetch buffer 58c.

For example, when a magnetic memory is used as the first buffer unit 58a and SRAM is used as the second buffer unit 58b, the operating speed of the first buffer unit 58a may be slower than the operating speed of the second buffer unit 58b. ..

For example, in an operation such as DNN, the operation may be regular. For example, the address of the data used in the later calculation may be specified in advance. In such a case, the data of the first buffer unit 58a is stored in advance in the prefetch buffer 58c. For example, prefetch the output data. As a result, even when the operation of the first buffer unit 58a is slow, it is possible to prevent the total calculation time from becoming long.

For example, a deep neural network in which neural network operations are multi-layered improves the accuracy of recognition by a computer. Research and development on learning or inference by deep neural networks will be carried out. In deep learning, a large amount of operations are performed using a large amount of weight data. Delays occur in such operations. The energy increases.

According to the embodiment, for example, the calculation in deep learning can be speeded up. For example, energy can be reduced.

For example, a neural network using "convolution operation" shows excellent performance in an image recognition task. In the "convolution operation", the product-sum operation is sequentially executed using the weight data and the feature map data. As a technique for reducing the amount of calculation of the product-sum operation, it is considered effective to reduce the bit of the weight data or the intermediate data of the operation. For example, the value is usually represented by a 32-bit floating point number. By reducing the number of bits, the amount of data or the amount of calculation can be reduced. For example, a method of reducing the data to 1 bit can be considered. By making the data 1 bit, the product operation of the product-sum operation can be executed at the XNOR gate.

In the embodiment, for example, the present invention relates to an arithmetic unit using a magnetic memory. For example, a Neural Network arithmetic unit using 1 bit of weight data and 1 bit of input data is used. For example, the same weight data W is written in two magnetic memories (stacks). While applying data I (input data) to one of the two magnetic memories to the bit line, a current in one direction is supplied to the conductive layer. As a result, W (OR) I is calculated. While applying data I to the bit line in another one of the two magnetic memories, a current in the other direction is supplied to the conductive layer. As a result, W (AND) I is calculated. Further, (XOR) of W (OR) I and W (AND) I is calculated.

In the embodiment, a plurality of rows may be activated at the same time. For example, a large number of XNOR operations may be performed in parallel.

In a plurality of magnetic memory read circuits (for example, arithmetic circuit 71), A (OR) I data is input to one input, and A (AND) I data is input to the other input. One of the resistance states of one input may be between the two resistance states of the other input. For example, an offset may be provided.

For example, when writing weight data to a plurality of magnetic memories, the same data may be written at symmetrical positions when viewed from the read circuit.

A plurality of XNOR arithmetic circuits 55 may be provided. An arithmetic element PE that performs a sum operation and an activation operation of the outputs of the XNOR arithmetic circuit 55 may be provided. A plurality of arithmetic elements PE may be provided.

A buffer may be provided in the arithmetic unit. The buffer may include, for example, a magnetic memory. The buffer may include, for example, a semiconductor memory (eg, SRAM).

The arithmetic unit may include a prefetch buffer 58c. The prefetch buffer 58c may store, for example, the data read from the buffer by the magnetic memory.

The embodiment may include the following configurations (eg, technical proposals).
(Structure 1)
The element unit including the first element and the second element,
The circuit part including the arithmetic circuit and
With
The first element includes a first conductive layer and a first laminated body, and the first conductive layer is a third portion between a first portion, a second portion, and the first portion and the second portion. The first laminated body includes a portion, a second magnetic layer provided between the first magnetic layer, the third portion and the first magnetic layer, the first magnetic layer, and the first magnetic layer. A first non-magnetic layer provided between the two magnetic layers is included, and the direction from the first portion to the second portion intersects the direction from the third portion to the first magnetic layer.
The second element includes a second conductive layer and a second laminated body, and the second conductive layer is a sixth portion between a fourth portion, a fifth portion, and the fourth portion and the fifth portion. The second laminated body includes a portion, a third magnetic layer, a fourth magnetic layer provided between the sixth portion and the third magnetic layer, the third magnetic layer, and the third magnetic layer. A second non-magnetic layer provided between the four magnetic layers is included, and the direction from the fourth portion to the fifth portion intersects with the direction from the sixth portion to the third magnetic layer.
The first element is in the first state or the second state depending on the potential of the first magnetic layer and the direction of the current flowing through the first conductive layer, and the first magnetic layer and the first conductive layer are combined. The first electrical resistance of the first path including the intervening path in the first state is lower than the second electrical resistance of the first path in the second state.
The second element is in the third state or the fourth state depending on the potential of the third magnetic layer and the direction of the current flowing through the second conductive layer, and the third magnetic layer and the second conductive layer are combined. The third electrical resistance of the second path including the intervening path in the third state is lower than the fourth electrical resistance of the second path in the fourth state.
The arithmetic circuit is the first when the first element is in the first state and the second element is in the third state, and when the first element is in the second state and the second element is in the fourth state. Output one signal,
The arithmetic circuit is an arithmetic unit that outputs a second signal when the first element is in the second state and the second element is in the third state.

(Structure 2)
The circuit unit further includes a control circuit.
The control circuit acquires the first input and the second input, and obtains the first input and the second input.
When the first input is 0 and 1 and the second input is one of 0 and 1, the control circuit puts the first element in the first state.
When the first input is 0 and 1 and the second input is 0 and 1, the control circuit puts the first element in the second state.
When the first input is the other of 0 and 1 and the second input is the one of 0 and 1, the control circuit puts the first element in the second state.
When the first input is 0 and 1 and the second input is 0 and 1, the control circuit puts the first element in the second state.
When the first input is 0 and 1 and the second input is 0 and 1, the control circuit puts the second element in the third state.
When the first input is 0 and 1 and the second input is 0 and 1, the control circuit puts the second element in the third state.
When the first input is 0 and 1 and the second input is 0 and 1, the control circuit puts the second element in the fourth state.
The arithmetic unit according to the configuration 1, wherein the control circuit puts the second element in the third state when the first input is 0 and 1 and the second input is 0 and 1.

(Structure 3)
The control circuit carries out the first operation and
In the first operation, the control circuit performs a first step and a second step after the first step.
In the first step, the control circuit supplies the first magnetic layer with the potential of the first conductive layer while supplying the first current from the first portion to the second portion to the first conductive layer. Set to the first potential based on
In the second step, the control circuit supplies the first conductive layer with a second current from the second portion to the first portion when the first input is one of 0 and 1. , The first magnetic layer is set to a second potential based on the potential of the first conductive layer.
In the second step, when the first input is 0 and the other of 1, the control circuit supplies the second current to the first conductive layer and transfers the first magnetic layer to the first magnetic layer. The arithmetic unit according to the configuration 2, which is set to one potential.

(Structure 4)
The control circuit carries out the first operation and
In the first operation, the control circuit performs a first step and a second step after the first step.
In the first step, the control circuit supplies the first conductive layer with a second current from the second portion to the first portion, and supplies the first magnetic layer to the potential of the first conductive layer. Set to the first potential based on
In the second step, the control circuit supplies the first current from the first portion to the second portion to the first conductive layer when the first input is 0 and the other of 1. , The first magnetic layer is set to a second potential based on the potential of the first conductive layer.
In the second step, when the first input is one of 0 and 1, the control circuit supplies the first current to the first conductive layer and transfers the first magnetic layer to the first magnetic layer. The arithmetic unit according to the configuration 2, which is set to one potential.

(Structure 5)
The control circuit carries out the second operation and
In the second operation, the control circuit performs a third step and a fourth step after the third step.
In the third step, the control circuit supplies the second conductive layer with a third current from the fourth portion to the fifth portion, and causes the third magnetic layer to have the potential of the second conductive layer. Set to the third potential based on
In the fourth step, the control circuit supplies the second conductive layer with a fourth current from the fifth portion to the fourth portion when the first input is one of 0 and 1. , The third magnetic layer is set to a fourth potential based on the potential of the second conductive layer.
In the fourth step, the control circuit supplies the third magnetic layer to the second conductive layer while supplying the fourth current to the second conductive layer when the first input is 0 and the other of 1. The arithmetic unit according to configuration 3 or 4, which is set to three potentials.

(Structure 6)
The control circuit carries out the second operation and
In the second operation, the control circuit performs a third step and a fourth step after the third step.
In the third step, the control circuit supplies the second conductive layer with a fourth current from the fifth portion to the second portion, and supplies the third magnetic layer to the potential of the second conductive layer. Set to the third potential based on
In the fourth step, the control circuit supplies the second conductive layer with a third current from the fourth portion to the fifth portion when the first input is 0 and the other of 1. , The third magnetic layer is set to a fourth potential based on the potential of the second conductive layer.
In the fourth step, when the first input is one of 0 and 1, the control circuit supplies the third current to the second conductive layer and transfers the third magnetic layer to the third magnetic layer. The arithmetic unit according to configuration 3 or 4, which is set to three potentials.

(Structure 7)
The control circuit further performs a third operation after the first operation,
In the third operation, when the second input is one of 0 and 1, the control circuit supplies the second current to the first conductive layer and transfers the first magnetic layer to the first magnetic layer. Set to 2 potentials
In the third operation, when the second input is 0 and the other of 1, the control circuit supplies the second current to the first conductive layer and transfers the first magnetic layer to the first magnetic layer. The arithmetic unit according to configuration 6, which is set to one potential.

(Structure 8)
The control circuit performs a fourth operation after the second operation,
In the fourth operation, when the second input is the other of 0 and 1, the control circuit supplies the third current to the second conductive layer and transfers the third magnetic layer to the third magnetic layer. Set to 4 potentials,
In the fourth operation, when the second input is one of 0 and 1, the control circuit supplies the third current to the second conductive layer and transfers the third magnetic layer to the third magnetic layer. The arithmetic unit according to the configuration 7, which is set to three potentials.

(Structure 9)
The element unit includes a plurality of the first element and a plurality of the second elements.
At least a part of the arithmetic circuit is provided between at least a part of the plurality of first elements and at least a part of the plurality of second elements.
In N, which is an arbitrary integer of 1 or more, the Nth first element is located between the (N + 1) th first element and the arithmetic circuit.
The Nth second element is located between the (N + 1) th second element and the arithmetic circuit.
The operation according to any one of configurations 1 to 8, wherein the first input corresponding to the Nth first element is the same as the first input corresponding to the Nth second element. Device.

(Structure 10)
The third electric resistance is between the first electric resistance and the second electric resistance, and the second electric resistance is between the third electric resistance and the fourth electric resistance. 9. The arithmetic unit according to any one of 9.

(Structure 11)
The arithmetic circuit
A first sense circuit electrically connected to the first path,
A second sense circuit electrically connected to the second path,
Including
The arithmetic unit according to any one of configurations 1 to 9, wherein the resistance of the circuit included in the first sense circuit is different from the resistance of the circuit included in the second sense circuit.

(Structure 12)
The arithmetic circuit
A first sense circuit electrically connected to the first path,
A second sense circuit electrically connected to the second path,
Including
The arithmetic unit according to any one of configurations 1 to 9, wherein the gate width of the transistor included in the first sense circuit is different from the gate width of the transistor of the second sense circuit.

(Structure 13)
The arithmetic circuit
A first sense circuit electrically connected to the first path,
A second sense circuit electrically connected to the second path,
An offset voltage circuit connected to at least one of the first sense circuit and the second sense circuit, and
The arithmetic unit according to any one of configurations 1 to 9, comprising the above.

(Structure 14)
The first element includes a plurality of the first laminated bodies.
The arithmetic unit according to any one of configurations 1 to 12, wherein the second element includes a plurality of the second laminated bodies.

(Structure 15)
The arithmetic unit according to the configuration 14, wherein the number of the plurality of first laminated bodies is the same as the number of the plurality of said second laminated bodies.

(Structure 16)
At least one of the first conductive layer and the second conductive layer comprises at least one selected from the group consisting of Ta, W, Re, Os, Ir, Pt, Pd, Cu and Ag, configurations 1 to 15 The arithmetic unit according to any one of the above.

(Structure 17)
The circuit unit further includes a buffer unit capable of storing at least one of the first input and the second input.
The arithmetic unit according to any one of configurations 2 to 8, wherein the buffer unit includes a semiconductor.

(Structure 18)
The circuit unit
A first buffer that is electrically connected to the first element and can store at least one of the first input and the second input.
A second buffer that is electrically connected to the second element and can store at least one of the first input and the second input.
Including
The arithmetic unit according to any one of configurations 2 to 8, wherein the second buffer can output a signal inverted with respect to the signal output from the first buffer.

(Structure 19)
The circuit unit
A first buffer that is electrically connected to the first element and can store at least one of the first input and the second input.
A second buffer that is electrically connected to the second element and can store at least one of the first input and the second input.
Including
The arithmetic unit according to any one of configurations 2 to 8, wherein the second buffer includes an inverter.

(Structure 20)
The circuit unit
A first circuit that is electrically connected to the first element and can output a signal corresponding to at least one of the first input and the second input.
A second circuit that is electrically connected to the second element and can output a signal corresponding to at least one of the first input and the second input.
With more
The arithmetic unit according to any one of configurations 2 to 8, wherein the second circuit includes an inverter.

According to the embodiment, it is possible to provide an arithmetic unit capable of increasing the speed.

In the present specification, the "electrically connected state" includes a state in which a plurality of conductors are physically in contact with each other and a current flows between the plurality of conductors. The "electrically connected state" includes a state in which another conductor is inserted between the plurality of conductors and a current flows between the plurality of conductors. The "electrically connected state" is a state in which an electric element (such as a switch element such as a transistor) is inserted between a plurality of conductors and a current flows between the plurality of conductors. Includes formable states.

In the present specification, "vertical" and "parallel" include not only strict vertical and strict parallel, but also variations in the manufacturing process, for example, and may be substantially vertical and substantially parallel. ..

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, specific configurations of each element such as a conductive layer, a magnetic layer, a non-magnetic layer, an element, an element unit, an arithmetic circuit, a control circuit, and a circuit unit included in an arithmetic device can be appropriately determined from a range known to those skilled in the art. The present invention is included in the scope of the present invention as long as the present invention can be carried out in the same manner by selection and the same effect can be obtained.

Further, a combination of any two or more elements of each specific example to the extent technically possible is also included in the scope of the present invention as long as the gist of the present invention is included.

In addition, all arithmetic units that can be appropriately designed and implemented by those skilled in the art based on the arithmetic unit described above as an embodiment of the present invention also belong to the scope of the present invention as long as the gist of the present invention is included. ..

In addition, within the scope of the idea of the present invention, those skilled in the art can come up with various modified examples and modified examples, and it is understood that these modified examples and modified examples also belong to the scope of the present invention. ..

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

11-14 ... 1st to 4th magnetic layers, 11M to 14M ... magnetized, 11n, 12n ... 1st and 2nd non-magnetic layers, 21, 22 ... 1st and 2nd conductive layers, 21a to 21c ... 1st to 1st 3rd part, 22d to 22f ... 4th to 6th parts, 51, 52 ... 1st and 2nd laminates, 51M, 52M ... 1st and 2nd elements, 51MAT, 52MAT ... 1st and 2nd element groups, 51S, 52S ... state, 54 ... element section, 55 ... XNOR arithmetic circuit, 55B ... buffer circuit, 56 ... memory controller, 56a, 56b ... controller, 57 ... memory, 58 ... buffer section, 58a, 58b ... first, first 2 buffers, 58c ... prefetch buffer, 61DB, 62DB ... 1st and 2nd data buffers, 61DE, 62DE ... 1st and 2nd BL decoders, 61DR, 62DR ... 1st and 2nd BL drivers, 62C, 63C ... controllers, 63DE ... WL decoder, 63DR ... WL driver, 70 ... circuit unit, 71 ... arithmetic circuit, 71S ... signal, 72 ... control circuit, 110-115, 110a, 130-134 ... arithmetic device, A _{1,1 to Am, n} ... value, BF1, BF2 ... 1st, 2nd buffer, BLD ... driver, BWDV _L , BWDV _U ... power supply, C1, C2 ... 1st, 2nd capacitor, CLD ... conductive layer driver, CP1, CP2 ... 1st, 2nd path, D1, D2 ... 1st, 2nd drain, Ds1 ... distribution, F _{1,1 to} F _{m, 1} ... signal, G1, G2 ... 1st, 2nd gate, I ... data, I1, I2 ... 1st, 2nd input, IL1, IL2 ... 1st, 2nd insulating film, IN1, IN2 ... 1st, 2nd input terminal _{, Im, n} ... Activation data, INV ... Inverter, Iread1, Iread2 ... 1st , 2nd read current, J1 to J4 ... 1st to 4th currents, M1, M2 ... 1st and 2nd transistors, O _{1,1 to Om, n} ... value, OUT, OUTB ... output, PE ... arithmetic element , R1 to R4 ... 1st to 4th electric resistance, RO ... resistance, Re1 ... electric resistance, S1, S2 ... 1st and 2nd sources, SA ... sense amplifier, SEN ... sense circuit, SEN1, SEN2 ... 1st, 2nd sense circuit, SENA1, SENA2 ... circuit, SG1, SG2 ... 1st and 2nd signals, SL1, SL2 ... 1st and 2nd semiconductor layers, ST1 to ST4 ... 1st to 4th states, STP1 to STP4 ... 1st 1st to 4th steps, TR1, TR2 ... Transistor, V1 to V4 ... 1st to 4th potentials, Vclamp ... Clamp voltage, Vclamp1, Vclamp2 ... 1st and 2nd clamp voltage, Voltage ... Read voltage, W ... Weight data, WDV _L , WDV _U ... Power supply, WL ... WL control signal, WLD ... WL driver, W _{m, n} ... Wait data, w1, w2 ... 1st and 2nd gate width

Claims (10)

The element unit including the first element and the second element,
A circuit unit including an arithmetic circuit and a control circuit,
With
The first element includes a first conductive layer and a first laminated body, and the first conductive layer is a third portion between a first portion, a second portion, and the first portion and the second portion. The first laminated body includes a portion, a second magnetic layer provided between the first magnetic layer, the third portion and the first magnetic layer, the first magnetic layer, and the first magnetic layer. A first non-magnetic layer provided between the two magnetic layers is included, and the direction from the first portion to the second portion intersects the direction from the third portion to the first magnetic layer.
The second element includes a second conductive layer and a second laminated body, and the second conductive layer is a sixth portion between a fourth portion, a fifth portion, and the fourth portion and the fifth portion. The second laminated body includes a portion, a third magnetic layer, a fourth magnetic layer provided between the sixth portion and the third magnetic layer, the third magnetic layer, and the third magnetic layer. A second non-magnetic layer provided between the four magnetic layers is included, and the direction from the fourth portion to the fifth portion intersects with the direction from the sixth portion to the third magnetic layer.
The first element is in the first state or the second state depending on the potential of the first magnetic layer and the direction of the current flowing through the first conductive layer, and the first magnetic layer and the first conductive layer are combined. The first electrical resistance of the first path including the intervening path in the first state is lower than the second electrical resistance of the first path in the second state.
The second element is in the third state or the fourth state depending on the potential of the third magnetic layer and the direction of the current flowing through the second conductive layer, and the third magnetic layer and the second conductive layer are combined. The third electrical resistance of the second path including the intervening path in the third state is lower than the fourth electrical resistance of the second path in the fourth state.
The arithmetic circuit is the first when the first element is in the first state and the second element is in the third state, and when the first element is in the second state and the second element is in the fourth state. Output one signal,
The arithmetic circuit outputs a second signal when the first element is in the second state and the second element is in the third state.
The control circuit acquires the first input and the second input, and obtains the first input and the second input.
When the first input is 0 and 1 and the second input is one of 0 and 1, the control circuit puts the first element in the first state.
When the first input is 0 and 1 and the second input is 0 and 1, the control circuit puts the first element in the second state.
When the first input is the other of 0 and 1 and the second input is the one of 0 and 1, the control circuit puts the first element in the second state.
When the first input is 0 and 1 and the second input is 0 and 1, the control circuit puts the first element in the second state.
When the first input is 0 and 1 and the second input is 0 and 1, the control circuit puts the second element in the third state.
When the first input is 0 and 1 and the second input is 0 and 1, the control circuit puts the second element in the third state.
When the first input is 0 and 1 and the second input is 0 and 1, the control circuit puts the second element in the fourth state.
An arithmetic unit in which the control circuit puts the second element in the third state when the first input is 0 and 1 and the second input is 0 and 1. The control circuit carries out the first operation and
In the first operation, the control circuit performs a first step and a second step after the first step.
In the first step, the control circuit supplies the first magnetic layer with the potential of the first conductive layer while supplying the first current from the first portion to the second portion to the first conductive layer. Set to the first potential based on
In the second step, the control circuit supplies the first conductive layer with a second current from the second portion to the first portion when the first input is one of 0 and 1. , The first magnetic layer is set to a second potential based on the potential of the first conductive layer.
In the second step, when the first input is 0 and the other of 1, the control circuit supplies the second current to the first conductive layer and transfers the first magnetic layer to the first magnetic layer. set to 1 potential calculation device according to claim 1. The control circuit carries out the first operation and
In the first operation, the control circuit performs a first step and a second step after the first step.
In the first step, the control circuit supplies the first conductive layer with a second current from the second portion to the first portion, and supplies the first magnetic layer to the potential of the first conductive layer. Set to the first potential based on
In the second step, the control circuit supplies the first current from the first portion to the second portion to the first conductive layer when the first input is 0 and the other of 1. , The first magnetic layer is set to a second potential based on the potential of the first conductive layer.
In the second step, when the first input is one of 0 and 1, the control circuit supplies the first current to the first conductive layer and transfers the first magnetic layer to the first magnetic layer. set to 1 potential calculation device according to claim 1. The control circuit carries out the second operation and
In the second operation, the control circuit performs a third step and a fourth step after the third step.
In the third step, the control circuit supplies the second conductive layer with a third current from the fourth portion to the fifth portion, and causes the third magnetic layer to have the potential of the second conductive layer. Set to the third potential based on
In the fourth step, the control circuit supplies the second conductive layer with a fourth current from the fifth portion to the fourth portion when the first input is one of 0 and 1. , The third magnetic layer is set to a fourth potential based on the potential of the second conductive layer.
In the fourth step, the control circuit supplies the third magnetic layer to the second conductive layer while supplying the fourth current to the second conductive layer when the first input is 0 and the other of 1. The arithmetic unit according to claim 2 or 3 , which is set to three potentials. The control circuit carries out the second operation and
In the second operation, the control circuit performs a third step and a fourth step after the third step.
In the third step, the control circuit supplies the second conductive layer with a fourth current from the fifth portion to the second portion, and supplies the third magnetic layer to the potential of the second conductive layer. Set to the third potential based on
In the fourth step, the control circuit supplies the second conductive layer with a third current from the fourth portion to the fifth portion when the first input is 0 and the other of 1. , The third magnetic layer is set to a fourth potential based on the potential of the second conductive layer.
In the fourth step, when the first input is one of 0 and 1, the control circuit supplies the third current to the second conductive layer and transfers the third magnetic layer to the third magnetic layer. The arithmetic unit according to claim 2 or 3 , which is set to three potentials. The control circuit further performs a third operation after the first operation,
In the third operation, when the second input is one of 0 and 1, the control circuit supplies the second current to the first conductive layer and transfers the first magnetic layer to the first magnetic layer. Set to 2 potentials
In the third operation, when the second input is 0 and the other of 1, the control circuit supplies the second current to the first conductive layer and transfers the first magnetic layer to the first magnetic layer. The arithmetic unit according to claim 5 , which is set to one potential. The control circuit performs a fourth operation after the second operation,
In the fourth operation, when the second input is the other of 0 and 1, the control circuit supplies the third current to the second conductive layer and transfers the third magnetic layer to the third magnetic layer. Set to 4 potentials,
In the fourth operation, when the second input is one of 0 and 1, the control circuit supplies the third current to the second conductive layer and transfers the third magnetic layer to the third magnetic layer. The arithmetic unit according to claim 6 , which is set to 3 potentials. The third electric resistance is between the first electric resistance and the second electric resistance, and the second electric resistance is between the third electric resistance and the fourth electric resistance. The arithmetic unit according to any one of 1 to 7. The arithmetic circuit
A first sense circuit electrically connected to the first path,
A second sense circuit electrically connected to the second path,
Including
The arithmetic unit according to any one of claims 1 to 7 , wherein the gate width of the transistor included in the first sense circuit is different from the gate width of the transistor of the second sense circuit. The arithmetic circuit
A first sense circuit electrically connected to the first path,
A second sense circuit electrically connected to the second path,
An offset voltage circuit connected to at least one of the first sense circuit and the second sense circuit, and
The arithmetic unit according to any one of claims 1 to 7, further comprising.

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