Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JP6921708B2 - Ceramic substrate - Google Patents
[go: Go Back, main page]

JP6921708B2 - Ceramic substrate - Google Patents

Ceramic substrate Download PDF

Info

Publication number
JP6921708B2
JP6921708B2 JP2017203016A JP2017203016A JP6921708B2 JP 6921708 B2 JP6921708 B2 JP 6921708B2 JP 2017203016 A JP2017203016 A JP 2017203016A JP 2017203016 A JP2017203016 A JP 2017203016A JP 6921708 B2 JP6921708 B2 JP 6921708B2
Authority
JP
Japan
Prior art keywords
substrate
view
ceramic
plan
via conductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2017203016A
Other languages
Japanese (ja)
Other versions
JP2019079835A (en
Inventor
貴広 林
貴広 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niterra Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP2017203016A priority Critical patent/JP6921708B2/en
Publication of JP2019079835A publication Critical patent/JP2019079835A/en
Application granted granted Critical
Publication of JP6921708B2 publication Critical patent/JP6921708B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Description

本発明は、セラミックからなる基板本体の表面の平面視における中央側に複数のビア導体が比較的密集して配設されたセラミック基板に関する。 The present invention relates to a ceramic substrate in which a plurality of via conductors are relatively densely arranged on the central side in a plan view of the surface of a substrate body made of ceramic.

一般に、セラミック基板は、複数のセラミックグリーンシートの表面やこれに設けた貫通穴に金属粉末を含む導電性ペーストを印刷あるいは充填した後、これらのグリーンシートを積層し、更に焼成することで製造されている。しかし、前記焼成時において、セラミックと金属との間における収縮量の差に起因して、得られるセラミック基板に不用意な反りが生じることが知られている。
例えば、複数のセラミック層を積層してなり、外部配線パターン、内部配線パターン、およびこれらの間を接続するビア(ビア導体)が形成された複数の配線部と、該配線部の周囲に沿って配置された矩形枠状の非配線部とからなり、該非配線部にダミービア(ダミービア導体)を設けることによって、不用意な反りの発生を抑制して、電子部品の実装工程における歩留まりを改善するようにしたセラミック多層基板が提案されている(例えば、特許文献1参照)。
Generally, a ceramic substrate is manufactured by printing or filling a conductive paste containing a metal powder on the surfaces of a plurality of ceramic green sheets or through holes provided therein, laminating these green sheets, and further firing them. ing. However, it is known that the obtained ceramic substrate is inadvertently warped due to the difference in the amount of shrinkage between the ceramic and the metal during the firing.
For example, a plurality of wiring portions formed by laminating a plurality of ceramic layers to form an external wiring pattern, an internal wiring pattern, and vias (via conductors) connecting the external wiring patterns, and along the periphery of the wiring portions. It consists of an arranged rectangular frame-shaped non-wiring portion, and by providing a dummy via (dummy via conductor) in the non-wiring portion, it is possible to suppress the occurrence of inadvertent warpage and improve the yield in the mounting process of electronic components. A ceramic multilayer substrate has been proposed (see, for example, Patent Document 1).

ところで、セラミックからなる基板本体の表面の中央側には、該表面上に追って電子部品を実装するための複数のパッドが形成され、且つ該パッドごとの真下には、上記基板本体の厚み方向に沿って配設された複数のビア導体が個別に接続されている。該複数のビア導体が比較的密集して配設された基板本体の表面における中央側と周辺側との間では、製造時の焼成工程における収縮量の差に起因して、平面視で中央側の表面が周辺側の表面よりも上記複数のビア導体全体の収縮により一層厚み方向に沿って収縮する。その結果、上記ビア導体の収縮量がセラミックの収縮量よりも大きい場合には、前記表面の中央側には、対向する裏面側に凸となる凹部が、平面視で上記複数のビア導体を含む実装領域に沿って形成される。該凹部が生じると、追って上記複数のパッド上に実装される電子部品の底面の周辺部が、当該凹部の周辺側の傾斜面あるいは湾曲面に接触あるいは接近し過ぎることにより、上記電子部品を所要の姿勢および位置に実装できず、電気的な接続が不安定になり得る。更に、上記凹部が湾曲面で形成されていることにより、該凹部の端に近い周辺側のパッドと、中央側のパッドとの間では、両者の接続高さが異なるため、周辺側のパッドにおける接続信頼性が低下する、という問題点があった。 By the way, on the central side of the surface of the substrate body made of ceramic, a plurality of pads for mounting electronic components are formed on the surface, and directly below each pad, in the thickness direction of the substrate body. A plurality of via conductors arranged along the line are individually connected. The central side in a plan view between the central side and the peripheral side on the surface of the substrate body in which the plurality of via conductors are relatively densely arranged is due to the difference in the amount of shrinkage in the firing process during manufacturing. The surface of the above-mentioned is further contracted along the thickness direction due to the contraction of the entire plurality of via conductors than the surface on the peripheral side. As a result, when the shrinkage amount of the via conductor is larger than the shrinkage amount of the ceramic, a recess that is convex toward the opposite back surface side is included on the center side of the front surface, and includes the plurality of via conductors in a plan view. It is formed along the mounting area. When the recess is generated, the peripheral portion of the bottom surface of the electronic component mounted on the plurality of pads is in contact with or too close to the inclined surface or the curved surface on the peripheral side of the recess, so that the electronic component is required. It cannot be mounted in the posture and position of, and the electrical connection can become unstable. Further, since the recess is formed of a curved surface, the connection height between the pad on the peripheral side near the end of the recess and the pad on the center side are different. There was a problem that the connection reliability was lowered.

特開2012−114183号公報(第1〜13頁、図1〜5)Japanese Unexamined Patent Publication No. 2012-114183 (pages 1 to 13, FIGS. 1 to 5)

本発明は、背景技術で説明した問題点を解決し、セラミックからなる基板本体の表面における平面視の中央側に複数のビア導体が比較的密集して配設されていても、該複数のビア導体の上方に追って電子部品を精度良く、且つ電気的に確実に実装できるセラミック基板を提供する、ことを課題とする。 The present invention solves the problems described in the background art, and even if a plurality of via conductors are relatively densely arranged on the central side in a plan view on the surface of a substrate body made of ceramic, the plurality of vias are arranged. An object of the present invention is to provide a ceramic substrate capable of accurately and electrically mounting electronic components on the upper side of a conductor.

課題を解決するための手段および発明の効果Means for Solving Problems and Effects of Invention

本発明は、前記課題を解決するため、セラミックからなる基板本体の表面において、複数のビア導体が配設された実装領域の外側に沿ってダミービア導体を配設することで、平面視で追って実装される電子部品の底面よりも広い凹部を形成する、ことに着想して成されたものである。
即ち、本発明のセラミック基板(請求項1)は、セラミックからなり、平面視の外形が矩形状で且つ対向する表面および裏面を有する基板本体と、該基板本体の表面の平面視における中央側に位置し、平面視の外形が矩形状で且つ上記基板本体の厚み方向に沿って配設された複数のビア導体を有する実装領域と、を備えたセラミック基板であって、上記基板本体の表面において、平面視で上記実装領域の外側に沿って前記基板本体の厚み方向に沿って形成された複数のダミービア導体を配設してなると共に、平面視で上記基板本体の表面における上記実装領域および複数のダミービア導体を含み、且つ側面視で上記基板本体の裏面側に凸となる凹部を有し、複数の上記ダミービア導体は、平面視で上記実装領域における四隅の近傍のみに沿って平面視でL字状に配設されている、ことを特徴とする。
In order to solve the above problems, the present invention is mounted in a plan view by arranging dummy via conductors along the outside of a mounting region in which a plurality of via conductors are arranged on the surface of a substrate body made of ceramic. It was conceived to form a recess wider than the bottom surface of the electronic component to be formed.
That is, the ceramic substrate (claim 1) of the present invention is made of ceramic and has a rectangular outer shape in a plan view and has a front surface and a back surface facing each other. A ceramic substrate that is located, has a rectangular outer shape in a plan view, and has a mounting region having a plurality of via conductors arranged along the thickness direction of the substrate body, and is provided on the surface of the substrate body. A plurality of dummy via conductors formed along the thickness direction of the substrate main body are arranged along the outside of the mounting region in a plan view, and the mounting region and a plurality of the mounting regions on the surface of the substrate main body in a plan view. The dummy via conductors are included, and have concave portions that are convex on the back surface side of the substrate body in a side view, and the plurality of dummy via conductors are L in a plan view along only the vicinity of the four corners in the mounting region. It is characterized in that it is arranged in a character shape.

前記セラミック基板によれば、以下の効果(1),(1′)が得られる。
(1)前記基板本体の表面において、平面視で該表面の中央側に複数の前記ビア導体が比較的密集して配設された実装領域を有し、且つ該実装領域の外側に沿って複数のダミービア導体が配設されている。そのため、製造時における焼成工程で、上記複数のビア導体と共に上記複数のダミービア導体も、これらの軸方向に沿って収縮するため、上記基板本体の表面には、平面視で前記実装領域とこれらの外側に位置する複数のダミービア導体とを含み、且つ側面視で上記基板本体の裏面側に凸となる比較的扁平で、且つ追って実装される電子部品の実装領域よりも広い面積の凹部が形成されている。従って、上記複数のビア導体の上端面ごと対し、あるいは、該ビア導体ごとの上端面に接合された複数のパッドなどを介して、ロウ付けなどにより上記電子部品を実装した際に、該電子部品を所要の姿勢および位置に精度良く容易に実装できるので、前記各ビア導体と上記電子部品との電気的な接続を確実に得ることが可能となる。
(1′)前記実装領域は、平面視で矩形(正方形あるいは長方形)状を呈し、且つ該実装領域内に配設される複数の前記ビア導体の外形も平面視で実装領域の外形とほぼ相似形となっている。そのため、製造時の焼成工程で、実装領域の四隅付近は、ビア導体が比較的密集しており、且つビア導体が存在する領域(即ち、収縮の大きい領域)と、ビア導体が存在していない領域(即ち、収縮の小さい領域)との境界となっている。その結果、上記四隅付近は、他の部位よりも、比較的収縮しにくく、前記のように、複数の前記ダミービア導体を、平面視で前記実装領域における四隅の近傍のみに沿ってL字状に配設することにより、前記同様の電子部品の実装領域よりも比較的広い凹部を基板本体の表面に有するセラミック基板となる。従って、前記効果(1)を奏することが可能である。
According to the ceramic substrate, the following effects (1) and (1') can be obtained.
(1) On the surface of the substrate main body, there is a mounting region in which a plurality of the via conductors are relatively densely arranged on the center side of the surface in a plan view, and a plurality of mounting regions are arranged along the outside of the mounting region. Dummy via conductor is arranged. Therefore, in the firing step at the time of manufacturing, the plurality of dummy via conductors as well as the plurality of via conductors also shrink along their axial directions. A relatively flat recess that includes a plurality of dummy via conductors located on the outside and is convex on the back surface side of the substrate body in a side view and has a larger area than the mounting area of the electronic component to be mounted later is formed. ing. Therefore, when the electronic component is mounted by brazing or the like with respect to the upper end surfaces of the plurality of via conductors or through a plurality of pads joined to the upper end surfaces of the via conductors, the electronic component is used. Can be accurately and easily mounted in a required posture and position, so that it is possible to reliably obtain an electrical connection between each via conductor and the electronic component.
(1') The mounting area has a rectangular (square or rectangular) shape in a plan view, and the outer shapes of the plurality of via conductors arranged in the mounting area are substantially similar to the outer shape of the mounting area in a plan view. It is in shape. Therefore, in the firing process during manufacturing, the via conductors are relatively dense in the vicinity of the four corners of the mounting region, and the region where the via conductor exists (that is, the region where the shrinkage is large) and the via conductor do not exist. It is a boundary with a region (that is, a region with small contraction). As a result, the vicinity of the four corners is relatively less likely to shrink than the other portions, and as described above, the plurality of dummy via conductors are formed into an L shape along only the vicinity of the four corners in the mounting region in a plan view. By disposing of the ceramic substrate, the ceramic substrate has a recess on the surface of the substrate body that is relatively wider than the mounting area of the same electronic component. Therefore, it is possible to achieve the effect (1).

尚、前記セラミックは、例えば、アルミナや窒化アルミニウムなどの高温焼成セラミック、あるいは、ガラス−セラミックなどの低温焼成セラミックである。
また、前記実装領域は、平面視で矩形(正方形または長方形)状を呈する。
更に、前記ビア導体は、基板本体が上記高温焼成セラミックの場合には、タングステン(以下、単にWと記載する)またはモリブデン(以下、単にMoと記載する)からなり、上記低温焼成セラミックの場合には、銅または銀からなる。
また、上記ダミービア導体は、同じ基板本体において、異なる深さに位置するセラミック層ごとに形成されていても良い。
更に、上記ビア導体は、その上端面に基板本体の表面上に突出するパッドが接合されていても良い。
また、前記ダミービア導体は、上記ビア導体と同じ金属か同種の金属からなる。
更に、前記凹部は、側面視で扁平状の円弧形または扁平な逆台形状を呈する。
加えて、前記セラミック基板は、複数の該セラミック基板を平面視で縦横に隣接して併設した製品領域を含む多数個取りの形態からなるものであっても良い。
The ceramic is, for example, a high-temperature fired ceramic such as alumina or aluminum nitride, or a low-temperature fired ceramic such as glass-ceramic.
Further, the mounting area has a rectangular shape (square or rectangular shape) in a plan view.
Further, the via conductor is made of tungsten (hereinafter, simply referred to as W) or molybdenum (hereinafter, simply referred to as Mo) when the substrate body is the high temperature co-fired ceramic, and when the substrate body is the high temperature co-fired ceramic, the via conductor is made of molybdenum (hereinafter, simply referred to as Mo). Consists of copper or silver.
Further, the dummy via conductor may be formed for each ceramic layer located at different depths in the same substrate body.
Further, the via conductor may have a pad protruding on the surface of the substrate body bonded to the upper end surface thereof.
Further, the dummy via conductor is made of the same metal as the via conductor or a metal of the same type.
Further, the recess has a flat arc shape or a flat inverted trapezoidal shape when viewed from the side.
In addition, the ceramic substrate may be in the form of a large number of pieces including a product area in which a plurality of the ceramic substrates are arranged vertically and horizontally adjacent to each other in a plan view.

更に、本発明には、前記基板本体は、複数のセラミック層を積層したものであり、前記ダミービア導体は、その上端面が上記基板本体の表面に露出している、セラミック基板(請求項)も含まれる。
これによれば、複数の上記ダミービア導体の上端面が上記基板本体の表面に露出しているので、製造時の焼成工程で上記複数のダミービア導体が位置している基板本体の表面側を含めた位置に前記凹部が形成されている。その結果、追って実装領域内に位置する複数のビア導体の上端面ごとに導体のボール(例えば、ハンダボール)を介して、あるいは、予め接合したパッドを介して、電子部品を精度良く実装することができる。従って、前記効果(1)を確実に奏することが可能である。
尚、前記複数のダミービア導体は、基板本体の表面を有する最上層のセラミック層、あるいは該セラミック層とこれに隣接する中層のセラミック層とを貫通するものであっても良い。
Further, in the present invention, the substrate body is a laminate of a plurality of ceramic layers, and the upper end surface of the dummy via conductor is exposed on the surface of the substrate body (claim 2 ). Is also included.
According to this, since the upper end surfaces of the plurality of dummy via conductors are exposed on the surface of the substrate main body, the surface side of the substrate main body in which the plurality of dummy via conductors are located is included in the firing step at the time of manufacturing. The recess is formed at the position. As a result, the electronic components can be accurately mounted via the conductor balls (for example, solder balls) or through the pads previously joined to each of the upper end surfaces of the plurality of via conductors located in the mounting region. Can be done. Therefore, it is possible to surely achieve the effect (1).
The plurality of dummy via conductors may be those that penetrate the uppermost ceramic layer having the surface of the substrate main body, or the ceramic layer and the ceramic layer of the middle layer adjacent thereto.

また、本発明には、前記ダミービア導体の上端面は、アライメントマークを兼ねている、セラミック基板(請求項)も含まれる。
これによれば、例えば、平面視で前記実装領域が矩形である場合、該実装領域における2つの対角線ごとの延長線上となる四隅に、上端面がアライメントマークを兼ねる4つのダミービア導体を配設したり、あるいは、上記該実装領域の外形において、対向する一対ずつの辺の中間点を縦横に直交して通過する一対の中間線ごとの延長線上に、アライメントマークを兼ねる4つのダミービア導体を配設することが例示される。その結果、追ってなされる電子部品の実装時に、上記各ダミービア導体の位置をCCDカメラなどを用いる画像処理によって確認することで、一層正確な実装が可能となる。従って、アライメントマークを兼ねるダミービア導体を併用することで、前記効果(1)を一層顕著に得ることが可能となり、更に画像処理による実装も可能となる(以下、効果(2)と称する)。
尚、前記アライメントマークを兼ねるダミービア導体は、前記ビア導体と同じでも良いし、その上端面にメッキまたは塗装により色彩を付加したものでも良い。
The present invention also includes a ceramic substrate (claim 3 ) in which the upper end surface of the dummy via conductor also serves as an alignment mark.
According to this, for example, when the mounting area is rectangular in a plan view, four dummy via conductors whose upper end surface also serves as an alignment mark are arranged at four corners which are extension lines of each of the two diagonal lines in the mounting area. Alternatively, in the outer shape of the mounting area, four dummy via conductors that also serve as alignment marks are arranged on the extension line of each pair of intermediate lines that pass through the intermediate points of the pair of opposing sides at right angles in the vertical and horizontal directions. Is exemplified. As a result, more accurate mounting is possible by confirming the position of each of the dummy via conductors by image processing using a CCD camera or the like at the time of mounting the electronic component to be performed later. Therefore, by using a dummy via conductor that also serves as an alignment mark, the effect (1) can be obtained more prominently, and further mounting by image processing becomes possible (hereinafter, referred to as the effect (2)).
The dummy via conductor that also serves as the alignment mark may be the same as the via conductor, or may have a color added to the upper end surface thereof by plating or painting.

加えて、本発明には、前記基板本体は、複数のセラミック層を積層したものであり、前記ダミービア導体は、上記基板本体における中層のセラミック層に形成されている、セラミック基板(請求項)も含まれる。
これによれば、複数の上記ダミービア導体が、上記基板本体における中層のセラミック層に形成されていることで、焼成時の収縮が基板本体の表面側や裏面側では健在化しにくくなっている。その結果、平面視で前記実装領域よりも広く、且つ周辺側に位置する傾斜面の傾斜度あるいは湾曲面の急峻度を抑制した前記凹部を、基板本体の表面における中央側に有したセラミック基板とされている。従って、前記効果(1)を一層確実に得ることが可能なセラミック基板となる。
また、前記形態によれば、実装用のパッドと混同して、電子部品を誤った領域に実装する事態を確実に予防することができる(以下、効果(3)とする)。
更に、前記形態によれば、ビア導体が外部に露出しないので、後述する電解メッキによるニッケル膜や金膜の使用量を削減できる(以下、効果(4)とする)。
尚、上記ダミービア導体は、例えば、実装領域の四隅近傍では、最上層のセラミックおよび中層のセラミック層を貫通する比較的縦長の形態とし、且つ上記実装領域の四辺ごとにおける中間位置には、中層のセラミック層のみを貫通する比較的短い形態としても良い。
In addition, in the present invention, the substrate body is a laminate of a plurality of ceramic layers, and the dummy via conductor is formed on the middle ceramic layer in the substrate body (claim 4 ). Is also included.
According to this, since the plurality of dummy via conductors are formed in the ceramic layer of the middle layer in the substrate main body, shrinkage during firing is less likely to be alive on the front surface side and the back surface side of the substrate main body. As a result, the ceramic substrate has the recess, which is wider than the mounting region in a plan view and suppresses the inclination of the inclined surface or the steepness of the curved surface located on the peripheral side, on the central side of the surface of the substrate main body. Has been done. Therefore, the ceramic substrate can obtain the effect (1) more reliably.
Further, according to the above-described embodiment, it is possible to reliably prevent a situation in which an electronic component is mounted in an erroneous region by being confused with a mounting pad (hereinafter, referred to as effect (3)).
Further, according to the above-described embodiment, since the via conductor is not exposed to the outside, the amount of nickel film or gold film used by electrolytic plating described later can be reduced (hereinafter, referred to as effect (4)).
The dummy via conductor has, for example, a relatively vertically long form penetrating the ceramic layer of the uppermost layer and the ceramic layer of the middle layer in the vicinity of the four corners of the mounting region, and the middle layer is placed at an intermediate position on each of the four sides of the mounting region. It may be in a relatively short form that penetrates only the ceramic layer.

(A)は本発明の前提となる一参考形態のセラミック基板を示す平面図、(B)は(A)中のX−X線の矢視に沿った垂直断面図、(C)は電子部品を実装した状態を示す前記と同様な垂直断面図。(A) is a plan view showing a premise and name Ru one reference embodiment of the ceramic substrate of the present invention, (B) is a vertical sectional view taken along the arrow line X-X in (A), (C) an electron A vertical cross-sectional view similar to the above showing a state in which components are mounted. (A)は異なる配列のダミービア導体を含む実施形態のセラミック基板の部分平面図、(B)は応用形態のダミービア導体を含む上記セラミック基板の部分平面図。 (A) is a partial plan view of the ceramic substrate of the embodiment including the dummy via conductors of different arrangements, and (B) is a partial plan view of the ceramic substrate including the dummy via conductors of the application embodiment. 異なる形態の配列のダミービア導体を含む実施形態または参考形態の上記セラミック基板の垂直断面図。FIG. 3 is a vertical cross-sectional view of the ceramic substrate of the embodiment or reference embodiment comprising dummy via conductors of different forms of arrangement. (A)は異なる参考形態のダミービア導体を含む上記セラミック基板の部分平面図、(B)は更に異なる参考形態のダミービア導体を含む上記セラミック基板の平面図。(A) is a partial plan view of the ceramic substrate including a dummy via conductor of a different reference form, and (B) is a plan view of the ceramic substrate including a dummy via conductor of a further different reference form.

以下において、本発明を実施するための形態について説明する。
図1(A)は、本発明の前提となる一参考形態のセラミック基板1を示す平面図、図1(B)は、(A)中のX−X線の矢視に沿った垂直断面図である。
上記セラミック基板1は、図1(A),(B)に示すように、平面視の外形が正方形(矩形)状で且つ対向する表面3および裏面4を有する基板本体2と、該基板本体2の表面3における平面視で中央側に位置し、前記基板本体2の厚み方向に沿って配設された複数のビア導体7を有する実装領域5と、を備えている。
上記基板本体2は、3層(複数)のセラミック層(セラミック)c1〜c3を一体に積層してなり、該セラミック層c1〜c3は、例えば、主にアルミナからなる。
Hereinafter, embodiments for carrying out the present invention will be described.
Figure 1 (A) is a plan view showing assumption and the ceramic substrate 1 one reference embodiment ing of the present invention, FIG. 1 (B), a vertical cross section along the arrow line X-X in (A) It is a figure.
As shown in FIGS. 1 (A) and 1 (B), the ceramic substrate 1 has a substrate main body 2 having a square (rectangular) outer shape in a plan view and having a front surface 3 and a back surface 4 facing each other, and the substrate main body 2. A mounting region 5 having a plurality of via conductors 7 arranged along the thickness direction of the substrate main body 2 and located on the central side in a plan view of the surface 3 of the substrate 3 is provided.
The substrate main body 2 is formed by integrally laminating three (plural) ceramic layers (ceramics) c1 to c3, and the ceramic layers c1 to c3 are mainly made of, for example, alumina.

また、前記実装領域5は、追って基板本体2の表面3に実装される後述する電子部品を配置するための仮想のエリアであり、該電子部品の底面とほぼ同じ広さである。該実装領域5内の表面3には、平面視で格子状に配列された複数のビア導体7の上端面が露出している。該ビア導体7は、WあるいはMoからなり、基板本体2の最上層および中層のセラミック層c1,c2を貫通している。
上記複数のビア導体7は、平面視で基板本体2の表面3における周辺側に比べて、比較的密集して配設されている。該複数のビア導体7は、平面視で市松模様(千鳥状)のパターンで配列されていても良い。
更に、図1(A),(B)に示すように、上記複数のビア導体7の上端面ごとには、前記基板本体2の表面3上に突出する円盤形状のパッド9が予め個別に接合されている。該パッド9もWあるいはMoからなり、外部に露出する表面には、電解メッキによるニッケル膜および金膜(何れも図示せず)が被覆されている。
Further, the mounting area 5 is a virtual area for arranging an electronic component described later to be mounted on the surface 3 of the substrate main body 2, and has substantially the same size as the bottom surface of the electronic component. The upper end surfaces of the plurality of via conductors 7 arranged in a grid pattern in a plan view are exposed on the surface 3 in the mounting region 5. The via conductor 7 is made of W or Mo and penetrates the ceramic layers c1 and c2 of the uppermost layer and the middle layer of the substrate main body 2.
The plurality of via conductors 7 are arranged relatively densely as compared with the peripheral side of the surface 3 of the substrate main body 2 in a plan view. The plurality of via conductors 7 may be arranged in a checkered pattern (staggered pattern) in a plan view.
Further, as shown in FIGS. 1A and 1B, disk-shaped pads 9 projecting on the surface 3 of the substrate main body 2 are individually joined in advance to each of the upper end surfaces of the plurality of via conductors 7. Has been done. The pad 9 is also made of W or Mo, and the surface exposed to the outside is coated with a nickel film and a gold film (neither shown) by electroplating.

尚、前記セラミックc1〜c3間には、図示しない内層配線が適宜形成され、該内層配線は、前記ビア導体7の何れかと接続されると共に、中層および最下層のセラミック層c2,c3を貫通する図示しないビア導体を介して、基板本体2の裏面4に形成された複数の外部接続端子(図示せず)とも電気的に接続されている。上記内層配線、ビア導体、および外部接続端子も、WまたはMoからなる。
また、図1(A),(B)に示すように、前記基板本体2の表面3において、平面視で前記実装領域5の外側に沿って、複数のダミービア導体8が矩形枠形状で且つほぼ等間隔に配設されている。該ダミービア導体8も、WあるいはMoからなり、且つ何れも前記セラミック層c1,c2を貫通している。尚、当該ダミービア導体8は、製造時において、前記ビア導体7と同様に、同じ打ち抜き加工によりセラミックグリーンシートに形成された複数のビアホール内ごとに、充填されたW粉末またはMo粉末を含む導電性ペーストを焼成したものである。
An inner layer wiring (not shown) is appropriately formed between the ceramics c1 to c3, and the inner layer wiring is connected to any of the via conductors 7 and penetrates the ceramic layers c2 and c3 of the middle layer and the bottom layer. It is also electrically connected to a plurality of external connection terminals (not shown) formed on the back surface 4 of the substrate main body 2 via a via conductor (not shown). The inner layer wiring, via conductor, and external connection terminal are also made of W or Mo.
Further, as shown in FIGS. 1A and 1B, on the surface 3 of the substrate main body 2, a plurality of dummy via conductors 8 have a rectangular frame shape and substantially along the outside of the mounting region 5 in a plan view. They are evenly spaced. The dummy via conductor 8 is also made of W or Mo, and both penetrate the ceramic layers c1 and c2. At the time of manufacture, the dummy via conductor 8 is conductive, containing W powder or Mo powder filled in each of a plurality of via holes formed in the ceramic green sheet by the same punching process, as in the via conductor 7. It is a baked paste.

加えて、図1(A),(B)に示すように、前記基板本体2の表面3には、平面視で前記実装領域5および前記複数のダミービア導体8を含む矩形状を呈し、且つ側面視で基板本体2の裏面4側に浅い凸となる凹部10を有している。該凹部10は、前記基板本体2となる3層のセラミックグリーンシート積層体を焼成した際に、未焼成であった前記複数のビア導体7および複数のダミービア導体8が焼成後において、それらの軸方向に沿って収縮した結果、形成されたものである。尚、該収縮の具合などによっては、基板本体2の裏面4の中央側にも平面視が相似形で、且つ更に小さくて浅い凹部(図示せず)がほぼ線対称で形成されていても良い。 In addition, as shown in FIGS. 1A and 1B, the surface 3 of the substrate body 2 has a rectangular shape including the mounting region 5 and the plurality of dummy via conductors 8 in a plan view, and has side surfaces. Visually, it has a recess 10 that is shallowly convex on the back surface 4 side of the substrate body 2. The recess 10 is a shaft of the plurality of via conductors 7 and the plurality of dummy via conductors 8 which were not fired when the three-layer ceramic green sheet laminate serving as the substrate main body 2 was fired. It is formed as a result of contraction along the direction. Depending on the degree of contraction and the like, a smaller and shallow recess (not shown) may be formed substantially line-symmetrically on the central side of the back surface 4 of the substrate main body 2 as well as having a similar figure in plan view. ..

図1(C)は、前記基板本体2の表面3における実装領域5上に電子部品12を実装した状態を示す前記同様の垂直断面図である。
図示のように、全体が扁平状の直方体を呈する電子部品12は、前記実装領域5内に位置する複数のビア導体7の上端ごとに接合された複数のパッド9の上方に、図示しないハンダなどを介して実装される。しかも、上記基板本体2の表面3における前記複数のダミービア導体8を含む領域にも前記凹部10が形成されており、且つ該凹部10は、平面視の中央側が比較的平坦で、且つ該中央側よりも周辺側が比較的急峻な湾曲面を有している。その結果、図1(C)に示すように、前記電子部品12は、その底面の全周辺が上記凹部10の内側に位置すると共に、該電子部品12の底面に設けられた図示しない複数の外部電極は、上記ハンダなどやパッド9を介して、前記複数のビア導体7と個別に導通可能とされる。
従って、前記のようなセラミック基板1によれば、上記電子部品12を所定の位置および姿勢にして精度良く実装するこが容易となる(前記効果(1))。
FIG. 1C is a similar vertical cross-sectional view showing a state in which the electronic component 12 is mounted on the mounting region 5 on the surface 3 of the substrate main body 2.
As shown in the drawing, the electronic component 12 having a rectangular parallelepiped as a whole is formed by solder or the like (not shown) above a plurality of pads 9 joined at each upper end of the plurality of via conductors 7 located in the mounting region 5. It is implemented via. Moreover, the recess 10 is also formed in the region of the surface 3 of the substrate main body 2 including the plurality of dummy via conductors 8, and the recess 10 is relatively flat on the central side in a plan view and is on the central side. The peripheral side has a relatively steep curved surface. As a result, as shown in FIG. 1C, the electronic component 12 has a plurality of external surfaces (not shown) provided on the bottom surface of the electronic component 12, while the entire periphery of the bottom surface of the electronic component 12 is located inside the recess 10. The electrodes can be individually conducted with the plurality of via conductors 7 via the solder or the like or the pads 9.
Therefore, according to the ceramic substrate 1 as described above, it becomes easy to mount the electronic component 12 in a predetermined position and orientation with high accuracy (the effect (1)).

図2(A)は、前記とは異なる配列のダミービア導体8を含む実施形態の前記セラミック基板1を示す部分平面図である。
図2(A)に示すように、基板本体2の表面3における平面視の中央側には、前記同様に配設された複数のビア導体7を有する実装領域5が位置しており、該実装領域5の四隅の外側には、その近傍にのみ沿って複数のダミービア導体8がほぼ等間隔に配設されている。前述した焼成時における収縮は、平面視が矩形状を呈する実装領域5において、該実装領域5の各辺における中間側よりも2つの辺が隣接する四隅付近において、比較的生じにくい傾向にある。
従って、実装領域5の外側における四隅の近傍にのみ複数のダミービア導体8を配設する上記の形態によっても、前記効果(1)を得ることが可能である。
尚、図2(A)中において、平面視がL字形状を呈する四隅の5個ずつのダミービア導体8のうち、角部ごとに位置するダミービア導体8を省略しても良い。
FIG. 2A is a partial plan view showing the ceramic substrate 1 of the embodiment including the dummy via conductors 8 having an arrangement different from the above.
As shown in FIG. 2A, a mounting region 5 having a plurality of via conductors 7 arranged in the same manner is located on the central side of the surface 3 of the substrate main body 2 in a plan view, and the mounting region 5 is located. A plurality of dummy via conductors 8 are arranged at substantially equal intervals on the outside of the four corners of the region 5 only in the vicinity thereof. The shrinkage during firing tends to be relatively unlikely to occur in the mounting region 5 having a rectangular shape in a plan view, in the vicinity of the four corners where the two sides are adjacent to each other than the intermediate side in each side of the mounting region 5.
Therefore, the effect (1) can also be obtained by the above-described embodiment in which the plurality of dummy via conductors 8 are arranged only in the vicinity of the four corners outside the mounting region 5.
In FIG. 2A, of the five dummy via conductors 8 at each of the four corners having an L-shaped plan view, the dummy via conductors 8 located at each corner may be omitted.

図2(B)は、前記図2(A)に示した形態の応用形態を示す前記セラミック基板1の部分平面図である。
図2(B)に示すように、基板本体2の表面3の中央側には、前記同様の実装領域5が位置し、且つ該実装領域5の四隅の外側に近傍のみに沿って、複数のダミービア導体8が平面視でL字形状にして配設されている。そとて、該平面視でL字形状を呈する四隅ごとの5個のダミービア導体8のうち、角部ごとに位置するものを平面視で画像認識が容易なアライメントマークを兼ねたダミービア導体8aとしたものである。該ダミービア導体8aは、他のダミービア導体8と同じく、上端面の最外層にメッキによる金膜を被覆した形態のほか、例えば、白色などの明色系の色彩を有する塗膜(何れも図示せず)を塗布したものでも良い。
図示のように、4個の上記ダミービア導体8aは、平面視で実装領域5における2つの対角線(仮想線)が、該実装領域5の中心を個別に通過する位置にある。そのため、前記電子部品12を実装領域5上に実装する際に、予め、図示しないCCDカメラなどにより、上記4個のダミービア導体8aの位置を認識しておくことにより、上記電子部品12の実装精度をより顕著に高めることが可能となる。
従って、上記形態によれば、前記効果(1),(2)を得ることが可能となる。
FIG. 2B is a partial plan view of the ceramic substrate 1 showing an application form of the form shown in FIG. 2A.
As shown in FIG. 2B, a plurality of similar mounting regions 5 are located on the central side of the surface 3 of the substrate main body 2, and a plurality of the same mounting regions 5 are located outside the four corners of the mounting region 5 only in the vicinity. The dummy via conductor 8 is arranged in an L shape in a plan view. Then, among the five dummy via conductors 8 for each of the four corners that exhibit an L-shape in the plan view, the ones located at each corner are combined with the dummy via conductor 8a that also serves as an alignment mark for easy image recognition in the plan view. It was done. Like the other dummy via conductors 8, the dummy via conductor 8a has a form in which the outermost layer of the upper end surface is coated with a gold film by plating, or a coating film having a bright color such as white (both are shown in the figure). It may be coated with (1).
As shown in the figure, the four dummy via conductors 8a are located at positions where two diagonal lines (virtual lines) in the mounting region 5 individually pass through the center of the mounting region 5 in a plan view. Therefore, when the electronic component 12 is mounted on the mounting region 5, the mounting accuracy of the electronic component 12 is achieved by recognizing the positions of the four dummy via conductors 8a in advance by a CCD camera or the like (not shown). Can be increased more remarkably.
Therefore, according to the above-described embodiment, the above-mentioned effects (1) and (2) can be obtained.

図3は、異なる形態の配列のダミービア導体8bを含む実施形態または参考形態の前記セラミック基板1の垂直断面図である。
図3に示すように、本セラミック基板1では、基板本体2の表面3の平面視における中央側に、前記同様の実装領域5が位置し、且つ該実装領域5の外側に沿って、中層のセラミック層c2のみを貫通する複数のダミービア導体8bを配設している。基板本体2の表面3および裏面4に露出しない該ダミービア導体8bは、平面視で実装領域5の外側の全周に沿って形成しても良いし、前記実装領域5の四隅の近傍付近にのみ配設した形態としても良い。
上記ダミービア導体8bを用いることで、図3に示すように、基板本体2の表面3側に形成される凹部10は、その周辺部の曲面おける急峻度がより緩和されるので、前記効果(1)をより確実に得ることが可能となる。
加えて、前記効果(3),(4)を併せて奏することもできる。
FIG. 3 is a vertical cross-sectional view of the ceramic substrate 1 of the embodiment or the reference embodiment including the dummy via conductors 8b having different arrangements.
As shown in FIG. 3, in the present ceramic substrate 1, the same mounting region 5 is located on the central side of the surface 3 of the substrate main body 2 in a plan view, and the middle layer is formed along the outside of the mounting region 5. A plurality of dummy via conductors 8b penetrating only the ceramic layer c2 are arranged. The dummy via conductor 8b, which is not exposed on the front surface 3 and the back surface 4 of the substrate main body 2, may be formed along the entire outer circumference of the mounting region 5 in a plan view, or may be formed only in the vicinity of the four corners of the mounting region 5. It may be arranged.
By using the dummy via conductor 8b, as shown in FIG. 3, the concave portion 10 formed on the surface 3 side of the substrate main body 2 has a more relaxed steepness on the curved surface of the peripheral portion thereof, and thus the above effect (1). ) Can be obtained more reliably.
In addition, the effects (3) and (4) can be combined.

図4(A)は、異なる参考形態のダミービア導体8,8bを含む前記セラミック基板1の部分平面図である。
図4(A)に示すように、本セラミック基板1でも、基板本体2の表面3の平面視における中央側に、前記同様の実装領域5が位置している。平面視で該実装領域5の外側に沿って、その四隅ごとの近傍に前記セラミック層c1,c2を貫通し且つ基板本体2の表面3に上端面が露出する複数のダミービア導体8を配設している共に、上記実装領域5の各辺の中程ごとに前記セラミック層c2のみを貫通し且つ上記表面3に露出しない複数のダミービア導体8bを配設している。
FIG. 4A is a partial plan view of the ceramic substrate 1 including dummy via conductors 8 and 8b having different reference forms.
As shown in FIG. 4A, also in the present ceramic substrate 1, the same mounting region 5 is located on the central side of the surface 3 of the substrate main body 2 in a plan view. A plurality of dummy via conductors 8 are arranged along the outside of the mounting region 5 in a plan view, penetrating the ceramic layers c1 and c2 in the vicinity of each of the four corners, and exposing the upper end surface on the surface 3 of the substrate main body 2. In addition, a plurality of dummy via conductors 8b that penetrate only the ceramic layer c2 and are not exposed on the surface 3 are arranged in the middle of each side of the mounting region 5.

前記のように、実装領域5の四隅の近傍に複数の前記ダミービア導体8を配設し、且つこれらの間である実装領域の各辺の中間に複数の前記ダミービア導体8bを配設することにより、焼成後の収縮過程において、上記実装領域5の四隅の近傍において、前記凹部10のコーナー付近ごとに前記基板本体2の厚み方向に沿った急峻な曲面を形成すると共に、上記実装領域5の各辺の中間位置ごとに隣接して比較的緩やかな曲面の周辺部を有する凹部10を形成することができる。
従って、上記形態のセラミック基板1も前記効果(1)を有している。
尚、図4(A)中において、凹部10の四隅付近にアライメントマークを兼ねる前記ダミービア導体8aを個別に追加して配設しても良い。
As described above, by disposing the plurality of dummy via conductors 8 in the vicinity of the four corners of the mounting region 5, and disposing the plurality of dummy via conductors 8b in the middle of each side of the mounting region between them. In the shrinking process after firing, a steep curved surface is formed in the vicinity of the four corners of the mounting region 5 at each corner of the recess 10 along the thickness direction of the substrate body 2, and each of the mounting regions 5 is formed. It is possible to form a recess 10 having a relatively gentle curved surface peripheral portion adjacent to each intermediate position of the side.
Therefore, the ceramic substrate 1 of the above-described form also has the above-mentioned effect (1).
In FIG. 4A, the dummy via conductor 8a, which also serves as an alignment mark, may be individually added and arranged near the four corners of the recess 10.

図4(B)は、更に異なる参考形態のダミービア導体8,8aを含む前記セラミック基板1の平面図である。
図4(B)に示すように、本セラミック基板1でも、基板本体2の表面3の平面視における中央側に、前記同様の実装領域5が位置している。平面視で該実装領域5の外側に沿って、その四隅ごとの近傍に内外2列で且つ千鳥状に複数のダミービア導体8を配設すると共に、これらの間ごとである上記実装領域5の各辺の中程ごとに該実装領域5寄りの内側に沿って複数のダミービア導体8を1列にして配設している。
FIG. 4B is a plan view of the ceramic substrate 1 including dummy via conductors 8 and 8a having a different reference form.
As shown in FIG. 4B, also in the present ceramic substrate 1, the same mounting region 5 is located on the central side of the surface 3 of the substrate main body 2 in a plan view. Along the outside of the mounting area 5 in a plan view, a plurality of dummy via conductors 8 are arranged in two rows inside and outside and in a staggered manner in the vicinity of each of the four corners, and each of the mounting areas 5 is located between them. A plurality of dummy via conductors 8 are arranged in a row along the inside of the mounting area 5 in the middle of each side.

更に、図示のように、前記実装領域5の各角(コーナー)部の外側には、アライメントマークを兼ねる前記ダミービア導体8aを1個ずつ配設している。
前記のような形態によれば、前記基板本体2の表面3における平面視の中央側に、比較的広い面積の凹部10を有するセラミック基板1とすることができると共に、前記効果(1),(2)を奏することができる。
尚、平面視で前記実装領域5の外側の全周に沿って、複数のダミービア導体8を内外2列以上にして配設した形態としても良い。この場合、該複数のダミービア導体8は、平面視で千鳥状に限らず、格子状の位置ごとに配列しても良い。
また、前記前記ダミービア導体8aを、通常のダミービア導体8にしても良い。
Further, as shown in the drawing, one dummy via conductor 8a also serving as an alignment mark is arranged outside each corner portion of the mounting region 5.
According to the above-described form, the ceramic substrate 1 having a recess 10 having a relatively large area on the central side of the surface 3 of the substrate main body 2 in a plan view can be formed, and the effects (1), (1). 2) can be played.
It should be noted that a plurality of dummy via conductors 8 may be arranged in two or more rows inside and outside along the entire outer circumference of the mounting region 5 in a plan view. In this case, the plurality of dummy via conductors 8 are not limited to the staggered shape in a plan view, and may be arranged at each grid-like position.
Further, the dummy via conductor 8a may be replaced with a normal dummy via conductor 8.

本発明は、以上において説明した各形態に限定されるものではない。
例えば、前記基板本体2を構成するセラミックは、例えば、窒化アルミニウムやムライトなどの高温焼成セラミックとしたり、ガラス−セラミックなどの低温焼成セラミックとしても良い。後者の場合、前記ビア導体7、ダミービア導体8,8a,8b、およびパッド9などの導体には、銅あるいは銀が適用される。
また、前記基板本体2は、2層のセラミック層あるいは4層以上のセラミック層を積層したものでも良い。例えば、4層のセラミック層からなる基板本体2の場合、前記ビア導体7およびダミービア導体8,8aは、前記表面3を有する最上層のセラミック層のみ、あるいは該最上層のセラミック層とこれに隣接するセラミック層とを貫通する形態とし、前記ダミービア導体8bは、中層の2つのセラミック層の一方あるいは双方を貫通する形態としても良い。
The present invention is not limited to each of the forms described above.
For example, the ceramic constituting the substrate main body 2 may be, for example, a high-temperature fired ceramic such as aluminum nitride or mullite, or a low-temperature fired ceramic such as glass-ceramic. In the latter case, copper or silver is applied to the conductors such as the via conductor 7, the dummy via conductors 8, 8a, 8b, and the pad 9.
Further, the substrate main body 2 may be a laminate of two ceramic layers or four or more ceramic layers. For example, in the case of the substrate main body 2 composed of four ceramic layers, the via conductor 7 and the dummy via conductors 8 and 8a are only the uppermost ceramic layer having the surface 3 or adjacent to the uppermost ceramic layer. The dummy via conductor 8b may be formed to penetrate one or both of the two ceramic layers in the middle layer.

更に、前記基板本体2の表面3および裏面4は、平面視で互いに対向する長方形状を呈する形態であっても良い。
また、前記基板本体2の表面3における中央側に、平面視の外形が長方形状を呈する実装領域5を設けた形態としても良い。かかる形態の場合、前記ダミービア導体8(前記ダミービア導体8a,8bを含む)は、上記長方形状を構成する各辺のうち、対向する一対の短辺の外側に沿ってのみ配設するか、あるいは、一対の短辺の外側に沿って配設するピッチを、対向する一対の長辺の外側に沿って配設するピッチよりも小さくする形態が推奨される。
更に、前記パッド9を省略し、前記ビア導体7の上端面を基板本体2の表面に露出させた形態としても良い。
Further, the front surface 3 and the back surface 4 of the substrate main body 2 may have a rectangular shape facing each other in a plan view.
Further, a mounting region 5 having a rectangular outer shape in a plan view may be provided on the central side of the surface 3 of the substrate main body 2. In the case of such a form, the dummy via conductor 8 (including the dummy via conductors 8a and 8b) is arranged only along the outside of the pair of short sides facing each other among the sides constituting the rectangular shape. , It is recommended that the pitch arranged along the outside of the pair of short sides be smaller than the pitch arranged along the outside of the pair of long sides facing each other.
Further, the pad 9 may be omitted, and the upper end surface of the via conductor 7 may be exposed on the surface of the substrate main body 2.

また、前記アライメントマークを兼ねるダミービア導体8aは、平面視が矩形状を呈する前記実装領域5の各辺における中間位置の外側ごとの4カ所に配設した形態、あるいは、上記実装領域5の角部ごとにおける何れか3カ所に配設した形態としも良い。
加えて、前記凹部10は、平面視が矩形状である前記実装領域5を囲むほぼ相似形を呈すると共に、各辺の中程が前記表面3の周辺側あるいは中心側に緩くカーブしている形態であっても良い。
Further, the dummy via conductor 8a also serving as the alignment mark is arranged at four locations outside the intermediate position on each side of the mounting region 5 having a rectangular shape in a plan view, or a corner portion of the mounting region 5. The form may be arranged in any three places in each case.
In addition, the recess 10 has a substantially similar shape surrounding the mounting region 5 having a rectangular shape in a plan view, and the middle of each side is gently curved toward the peripheral side or the central side of the surface 3. It may be.

本発明によれば、セラミックからなる基板本体の表面における中央側に複数のビア導体が比較的密集して配設されていても、該複数のビア導体の上方に追って電子部品を精度良く、且つ電気的に確実に実装できるセラミック基板を確実に提供できる。 According to the present invention, even if a plurality of via conductors are relatively densely arranged on the central side of the surface of the substrate body made of ceramic, the electronic component can be accurately and accurately arranged above the plurality of via conductors. It is possible to reliably provide a ceramic substrate that can be reliably mounted electrically.

1………………セラミック基板
2………………基板本体
3………………表面
4………………裏面
5………………実装領域
7………………ビア導体
8,8a,8b…ダミービア導体
10……………凹部
c1〜c3……セラミック層(セラミック)
1 ……………… Ceramic substrate 2 ……………… Substrate body 3 ……………… Front side 4 ……………… Back side 5 ……………… Mounting area 7 ……………… Via conductors 8,8a, 8b ... Dummy via conductors 10 ............... Recesses c1 to c3 ... Ceramic layer (ceramic)

Claims (4)

セラミックからなり、平面視の外形が矩形状で且つ対向する表面および裏面を有する基板本体と、
上記基板本体の表面の平面視における中央側に位置し、平面視の外形が矩形状で且つ上記基板本体の厚み方向に沿って配設された複数のビア導体を有する実装領域と、を備えたセラミック基板であって、
上記基板本体の表面において、平面視で上記実装領域の外側に沿って前記基板本体の厚み方向に沿って形成された複数のダミービア導体を配設してなると共に、
平面視で上記基板本体の表面における上記実装領域および複数のダミービア導体を含み、且つ側面視で上記基板本体の裏面側に凸となる凹部を有し
複数の上記ダミービア導体は、平面視で上記実装領域における四隅の近傍のみに沿って平面視でL字状に配設されている、
ことを特徴とするセラミック基板。
A substrate body made of ceramic, having a rectangular outer shape in a plan view and having opposite front and back surfaces.
It is located on the central side of the surface of the substrate body in a plan view, has a rectangular outer shape in a plan view, and has a mounting region having a plurality of via conductors arranged along the thickness direction of the board body. It ’s a ceramic substrate.
On the surface of the substrate body, a plurality of dummy via conductors formed along the thickness direction of the substrate body are arranged along the outside of the mounting region in a plan view, and also.
It includes the mounting area and a plurality of dummy via conductors on the surface of the substrate body in a plan view, and has a concave portion that is convex on the back surface side of the substrate body in a side view.
The plurality of dummy via conductors are arranged in an L shape in a plan view along only the vicinity of the four corners in the mounting region in a plan view .
A ceramic substrate characterized by that.
前記基板本体は、複数のセラミック層を積層したものであり、前記ダミービア導体は、その上端面が上記基板本体の表面に露出している、
ことを特徴とする請求項1に記載のセラミック基板。
The substrate main body is obtained by laminating a plurality of ceramic layers, and the upper end surface of the dummy via conductor is exposed on the surface of the substrate main body.
The ceramic substrate according to claim 1.
前記ダミービア導体の上端面は、アライメントマークを兼ねている、
ことを特徴とする請求項に記載のセラミック基板。
The upper end surface of the dummy via conductor also serves as an alignment mark.
The ceramic substrate according to claim 2.
前記基板本体は、複数のセラミック層を積層したものであり、前記ダミービア導体は、上記基板本体における中層のセラミック層に形成されている、
ことを特徴とする請求項に記載のセラミック基板。
The substrate main body is formed by laminating a plurality of ceramic layers, and the dummy via conductor is formed on a middle ceramic layer in the substrate main body.
The ceramic substrate according to claim 1.
JP2017203016A 2017-10-20 2017-10-20 Ceramic substrate Active JP6921708B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2017203016A JP6921708B2 (en) 2017-10-20 2017-10-20 Ceramic substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017203016A JP6921708B2 (en) 2017-10-20 2017-10-20 Ceramic substrate

Publications (2)

Publication Number Publication Date
JP2019079835A JP2019079835A (en) 2019-05-23
JP6921708B2 true JP6921708B2 (en) 2021-08-18

Family

ID=66628133

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017203016A Active JP6921708B2 (en) 2017-10-20 2017-10-20 Ceramic substrate

Country Status (1)

Country Link
JP (1) JP6921708B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6873447B1 (en) * 2020-06-26 2021-05-19 山佐株式会社 Pachinko machine

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3169254B2 (en) * 1992-03-18 2001-05-21 株式会社日立製作所 Multilayer wiring board
JP4239530B2 (en) * 2002-09-04 2009-03-18 株式会社村田製作所 Multilayer ceramic substrate
JP2004288660A (en) * 2003-01-29 2004-10-14 Kyocera Corp Wiring board
JP2007234662A (en) * 2006-02-27 2007-09-13 Kyocera Corp Multiple wiring board
JP2012114183A (en) * 2010-11-24 2012-06-14 Panasonic Corp Ceramic multilayer substrate
WO2015102107A1 (en) * 2014-01-06 2015-07-09 株式会社村田製作所 Stacked wiring substrate, and inspection device provided with same
JP2017017081A (en) * 2015-06-29 2017-01-19 日本特殊陶業株式会社 Multi-piece wiring board

Also Published As

Publication number Publication date
JP2019079835A (en) 2019-05-23

Similar Documents

Publication Publication Date Title
CN100553413C (en) Multilayer ceramic substrate
US20180324950A1 (en) Substrate apparatus and method of manufacturing the same
JP6151572B2 (en) Electronic device mounting substrate and electronic device
JP6921708B2 (en) Ceramic substrate
JP6819603B2 (en) Multilayer ceramic substrate and its manufacturing method
JP2010258189A (en) Manufacturing method of electronic component mounting substrate and manufacturing method of electronic component mounting mother substrate
JP3988250B2 (en) Multilayer circuit board manufacturing method
JP4560099B2 (en) Multi-chip substrate
JP2014236134A (en) Multilayer wiring board and probe card including the same
CN106879163B (en) Circuit board
JP2007048844A (en) Ceramic electronic component and manufacturing method thereof
JP2000049038A (en) Multilayer ceramic capacitors
JP6121860B2 (en) Wiring board and electronic device
JP7011563B2 (en) Circuit boards and electronic components
JP3894841B2 (en) Multiple wiring board
JP7698600B2 (en) Multi-piece ceramic substrate and its manufacturing method
JPH07221433A (en) Ceramic circuit board and manufacturing method thereof
JPS5999794A (en) Thick film circuit device
JP2021012896A (en) Multi-piece ceramic substrate, manufacturing method of the same, and manufacturing method of ceramic substrate
JP3466398B2 (en) Wiring board and its manufacturing method
JP2007234662A (en) Multiple wiring board
JP3894810B2 (en) Multiple wiring board
JP2005210041A (en) Wiring board
JP4285751B2 (en) Wiring board and manufacturing method thereof
JP2022149755A (en) Multi-cavity substrate, wiring substrate, and electronic component

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20191125

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20200210

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20200630

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200707

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20210202

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210426

C60 Trial request (containing other claim documents, opposition documents)

Free format text: JAPANESE INTERMEDIATE CODE: C60

Effective date: 20210426

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20210507

C21 Notice of transfer of a case for reconsideration by examiners before appeal proceedings

Free format text: JAPANESE INTERMEDIATE CODE: C21

Effective date: 20210511

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20210713

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20210728

R150 Certificate of patent or registration of utility model

Ref document number: 6921708

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250