JP6923614B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device.

For example, a semiconductor device in which a semiconductor element such as a transistor is sealed with a resin package has been proposed. Patent Document 1 discloses a semiconductor device including a semiconductor element having three electrodes, three leads conducting on these electrodes, the semiconductor element, and a resin package covering a part of each of the three leads. The three electrodes are formed on the same surface of the semiconductor element. The semiconductor element is bonded to one of the three leads. The three electrodes are separately conductively connected to the three leads via three wires. The resin package covers the entire semiconductor element, all of the three wires, and a part of each of the three leads. Of the three leads, the portion protruding from the resin package is a terminal portion for mounting the semiconductor device.

In a conventional semiconductor device, in a plan view, the lead on which the semiconductor element is arranged is larger than the semiconductor element. This large lead determines the size of the resin package. Therefore, the large lead hinders the miniaturization of the semiconductor device.

The above three wires generally have a loop shape. Therefore, in order to properly cover the three wires, the resin package needs to have an appropriate height. As a result, the height of the semiconductor device becomes high. At the same time, in order to properly bond the above three wires, it is necessary to secure a certain distance between the so-called first bonding portion and the second bonding portion. Further, the terminal portions of the three leads project from the resin package. These increase the plan view dimension of the semiconductor device. As described above, the semiconductor device has a problem that it is difficult to reduce the size.

Japanese Unexamined Patent Publication No. 2012-190936

The present invention has been conceived under the above circumstances, and its main object is to provide a semiconductor device capable of miniaturization.

According to the first aspect of the present invention, the semiconductor element, the main lead on which the semiconductor element is arranged, and the semiconductor element and the resin package covering the main lead are provided, and the main lead is from the resin package. Provided is a semiconductor device in which the semiconductor element is exposed and has a portion that does not overlap the main lead in the thickness direction of the semiconductor element.

Preferably, the main lead has a main lead main surface and a main lead back surface facing opposite sides, the semiconductor element is arranged on the main lead main surface, and the main lead back surface is the resin. Exposed from the package.

Preferably, the main lead includes a main full thickness portion and a main eaves portion, the main total thickness portion is a portion extending from the main lead main surface to the back surface of the main lead, and the main eaves portion is the semiconductor. It protrudes from the main total thickness portion in a direction perpendicular to the thickness direction of the element.

Preferably, the semiconductor element overlaps the main total thickness portion in the thickness direction of the semiconductor element as a whole.

Preferably, it further comprises a primary and secondary lead that conducts to the semiconductor device, the primary and secondary lead being separated from the main lead and exposed from the resin package.

Preferably, the main eaves portion has a main front portion, and the main front portion projects from the main total thickness portion toward the first sub-lead.

Preferably, the main eaves portion has a main side portion, and the main side portion protrudes from the main total thickness portion in a direction perpendicular to the projecting direction of the main front portion. ..

Preferably, the main lead comprises a main side connecting portion that projects from the main side portion, and the main side connecting portion has an end face that is exposed from the resin package.

Preferably, the main eaves portion has a main rear portion, and the main rear portion protrudes from the main total thickness portion in a direction opposite to the direction in which the main front portion protrudes.

Preferably, the main lead includes a main rear connecting portion that projects from the main rear portion, and the main rear connecting portion has an end face that is exposed from the resin package.

Preferably, the main total thickness portion is surrounded by the main eaves portion in the thickness direction of the semiconductor element as a whole.

Preferably, the main eaves portion overlaps the semiconductor element in the thickness direction of the semiconductor element as a whole.

Preferably, a main surface plating layer formed on the main lead and interposed between the semiconductor element and the main lead is further provided.

Preferably, the main surface plating layer overlaps the entire main eaves portion.

Preferably, a first sublead conducting the semiconductor element is further provided, the first sublead is separated from the main lead, and is outside the resin package in the thickness direction of the semiconductor element. Is exposed from the resin package.

Preferably, the first secondary lead includes a first and second full thickness portion and a first secondary eaves portion, and the first secondary lead has a main surface of the first secondary lead and a back surface of the first secondary lead facing opposite sides. The back surface of the first sub-lead is exposed from the resin package, and the first sub-total thickness portion is a portion extending from the main surface of the first sub-lead to the back surface of the first sub-lead. The primary sub-hedge portion protrudes from the first secondary full-thickness portion in a direction perpendicular to the thickness direction of the semiconductor element, and constitutes the first secondary lead main surface.

Preferably, the first sub-eaves portion has a first sub-front portion, and the first sub-front portion projects from the first sub-total thickness portion toward the main lead.

Preferably, the first sub-total thickness portion is exposed from the resin package toward the outside of the resin package in the thickness direction of the semiconductor element.

Preferably, the first sub-lead includes the first sub-extending portion, extends from the first sub-extended portion in a direction perpendicular to the thickness direction of the semiconductor element, and extends from the first sub-extended portion. The back surface of the first sub-lead is formed, and the first sub-extending portion is exposed from the resin package toward the outside of the resin package in the thickness direction of the semiconductor element.

Preferably, the first sublead has a first sublead main surface and a first sublead back surface facing opposite sides, and the first sublead back surface is exposed from the resin package.

Preferably, the resin package has a resin back surface that faces in the same direction as the back surface of the first sub-lead, and the back surface of the resin is flush with the back surface of the first sub-lead.

Preferably, the first secondary lead has a first secondary lead end face connected to the back surface of the first secondary lead, and the first secondary lead end face faces the side opposite to the side where the main lead is located. ..

Preferably, the first secondary lead end face is exposed from the resin package.

Preferably, the resin package has a first resin end face that faces in the same direction as the first secondary lead end face, and the first resin end face is flush with the first secondary lead end face. ..

Preferably, the first sublead has a first sublead side surface connected to the back surface of the first sublead, and the first sublead side surface is the direction in which the first sublead end face faces and the thickness of the semiconductor element. It faces in a direction that is perpendicular to any of the vertical directions.

Preferably, the first secondary lead side surface is exposed from the resin package.

Preferably, the resin package has a first resin side surface that faces in the same direction as the first secondary lead side surface, and the first secondary lead side surface is flush with the first resin side surface. ..

Preferably, a first wire that is directly connected to the semiconductor element and conducts the semiconductor element and the first sublead is further provided.

Preferably, a first sub-plating layer interposed between the first sub lead and the first wire is further provided.

Preferably, a second sublead conducting the semiconductor element is further provided, the second sublead is separated from the main lead and the first sublead, and in the thickness direction of the semiconductor element. It is exposed from the resin package to the outside of the resin package.

Preferably, a second wire that is directly connected to the semiconductor element and conducts the semiconductor element and the second sublead is further provided.

Preferably, a second secondary plating layer interposed between the second secondary lead and the second wire is further provided.

Preferably, the semiconductor element has a semiconductor layer laminated with each other, a eutectic layer of a semiconductor and a metal, and a metal single layer constituting the back electrode, and the metal single layer is directly bonded to the main lead. Has been done.

Preferably, the eutectic layer is composed of a eutectic of Si and Au.

Preferably, the simple metal layer is thinner than the eutectic layer.

Preferably, the semiconductor device further comprises a first wire, the semiconductor device includes a first surface electrode to which the first wire is bonded, and the first surface electrode is the main component in the thickness direction of the semiconductor device. It overlaps the thick part.

Preferably, the semiconductor element further comprises a second wire, the semiconductor element includes a second surface electrode to which the second wire is bonded, and the second surface electrode is the main component in the thickness direction of the semiconductor element. It overlaps the thick part.

Preferably, the first wire and the second wire are further provided, and the semiconductor element includes a first surface electrode to which the first wire is bonded and a second surface electrode to which the second wire is bonded. At least one of the first surface electrode and the second surface electrode overlaps the main total thickness portion in the thickness direction of the semiconductor element.

According to the second side surface of the present invention, it has a front surface and a back surface facing in opposite directions in the thickness direction, a first surface electrode and a second surface electrode formed on the front surface, and a back surface electrode formed on the back surface. A semiconductor element, a main lead having a die pad portion to which the back surface electrode is conductively connected and a main back surface terminal portion facing the opposite side of the die pad portion, and a first wire connected to the first front surface electrode via a first wire. A first sub-lead having a 1-wire bonding portion and a first sub-back surface terminal portion facing the opposite side of the first wire bonding portion, and a second wire bonding connected to the second surface electrode via a second wire. A second sub-lead having a portion and a second sub-back surface terminal portion facing the side opposite to the second wire bonding portion, the semiconductor element, the main lead, the first sub-lead, and a part of the second sub-lead. It is provided with a resin package that covers each of the main back surface terminals, the first sub back surface terminal portion, and the second sub back surface terminal portion to be exposed on the same side, and the main lead is the die pad portion. It has a main total thickness portion extending from the main back surface terminal portion to the main back surface terminal portion, and a main head portion protruding from the die pad portion side portion of the main total thickness portion in a direction perpendicular to the thickness direction. The die pad portion and the semiconductor element overlap both the main total thickness portion and the main eaves portion in the thickness direction, and at least one of the first surface electrode and the second surface electrode is on the main eaves portion. The first wire overlaps and has a first bonding portion bonded to the first wire bonding portion and a second bonding portion bonded to the first surface electrode via a first bump. The second wire is characterized by having a first bonding portion bonded to the second wire bonding portion and a second bonding portion bonded to the second surface electrode via a second bump. , Semiconductor devices are provided.

Preferably, the first surface electrode is a gate electrode, the second surface electrode is a source electrode, the back surface electrode is a drain electrode, and the semiconductor element is configured as a transistor. The electrodes are farther away from the first sublead and the second sublead than the second surface electrode.

Preferably, the first surface electrode overlaps the main total thickness portion in the thickness direction, and the second surface electrode overlaps the main eaves portion in the thickness direction.

Preferably, the first surface electrode overlaps both the main total thickness portion and the main eaves portion in the thickness direction.

Preferably, the first bump of the first wire and the second bonding portion of the first wire overlap both the main total thickness portion and the main eaves portion in the thickness direction.

Preferably, the main eaves portion has a main front portion that protrudes from the main total thickness portion toward the first sub-lead and the second sub-lead.

Preferably, the main eaves portion has a main lateral portion that protrudes in a direction perpendicular to the direction in which the main front portion protrudes.

Preferably, the main lead has a main side connecting portion that projects from the main side portion and one end surface is exposed from the resin package.

Preferably, the main eaves portion has a main rear portion that protrudes to the side opposite to the main front portion.

Preferably, the main lead has a main rear connecting portion that projects from the main rear portion and one end surface is exposed from the resin package.

Preferably, all of the main total thickness portion is surrounded by the main eaves portion.

Preferably, a main surface plating layer is formed on the die pad portion.

Preferably, the main surface plating layer overlaps all of the main eaves.

Preferably, the first sub-lead is from the first sub-total thickness portion extending from the first wire bonding portion to the first sub-back surface terminal portion and the first wire bonding portion side portion of the first sub-total thickness portion. It has a first secondary eaves portion that protrudes in a direction perpendicular to the thickness direction.

Preferably, the first sub-eaves portion has a first sub-front portion projecting from the first sub-total thickness portion toward the main lead.

Preferably, the first sub-eaves portion has a first sub-side portion projecting in a direction perpendicular to the direction in which the first sub-front portion projects.

Preferably, the first sub-lead has a first sub-side connection that projects from the first sub-side and one end surface is exposed from the resin package.

Preferably, the first sub-eaves portion has a first sub-rear portion projecting to the side opposite to the first sub-front portion.

Preferably, the first sub-lead has a first sub-rear connecting portion that protrudes from the first sub-rear portion and one end surface is exposed from the resin package.

Preferably, all of the first sub-total thickness portion is surrounded by the first sub-eaves.

Preferably, the first sub-surface plating layer is formed on the first wire bonding portion.

Preferably, the first sub-surface plating layer overlaps all of the first sub-eaves.

Preferably, the second sub-lead is from the second sub-total thickness portion extending from the second wire bonding portion to the second sub-back surface terminal portion and the second sub-wire bonding portion side portion of the second sub-total thickness portion. It has a second secondary eaves portion that protrudes in a direction perpendicular to the thickness direction.

Preferably, the second sub-eaves have a second sub-front portion that projects from the second sub-total thickness portion toward the main lead.

Preferably, the second sub-eaves portion has a second sub-side portion projecting in a direction perpendicular to the direction in which the second sub-front portion projects.

Preferably, the second sub-lead has a second sub-side connecting portion that protrudes from the second sub-side portion and one end surface is exposed from the resin package.

Preferably, the second sub-eaves have a second sub-rear portion that projects to the opposite side of the second sub-front.

Preferably, the second sub-lead has a second sub-rear connecting portion that projects from the second sub-rear portion and one end surface of which is exposed from the resin package.

Preferably, all of the second sub-total thickness portion is surrounded by the second sub-eaves.

Preferably, a second sub-surface plating layer is formed on the second wire bonding portion.

Preferably, the second sub-surface plating layer overlaps all of the second sub-eaves.

Preferably, the semiconductor element has a semiconductor layer laminated with each other, a eutectic layer of a semiconductor and a metal, and a metal single layer constituting the back electrode, and the metal single layer is directly bonded to the die pad portion. Has been done.

Preferably, the eutectic layer is composed of a eutectic of Si and Au.

Preferably, the simple metal layer is thinner than the eutectic layer.

Other features and advantages of the present invention will become more apparent with the detailed description given below with reference to the accompanying drawings.

It is a perspective view of the semiconductor device which concerns on 1st Embodiment of this invention. It is a top view of the semiconductor device shown in FIG. It is a bottom view of the semiconductor device shown in FIG. It is sectional drawing which follows the IV-IV line of FIG. It is sectional drawing which follows the VV line of FIG. It is a partially enlarged sectional view of the semiconductor device shown in FIG. FIG. 3 is a cross-sectional view taken along the line VII-VII of FIG. FIG. 3 is a cross-sectional view taken along the line VIII-VIII of FIG. It is sectional drawing which follows the IX-IX line of FIG. It is an enlarged image which shows the second bonding part of the semiconductor device shown in FIG. It is sectional drawing which shows one step in the manufacturing method of the semiconductor device shown in FIG. It is a perspective view of the semiconductor device which concerns on 2nd Embodiment of this invention. It is a top view of the semiconductor device shown in FIG. It is an enlarged plan view of the main part which shows the semiconductor element of the semiconductor device of FIG. It is a top view of the modification of the semiconductor device of this invention. It is a perspective view which shows an example of the semiconductor device based on 3rd Embodiment of this invention. It is a perspective view which shows the semiconductor device of FIG. It is a top view which shows the semiconductor device of FIG. It is sectional drawing which follows the XIX-XIX line of FIG. FIG. 3 is a cross-sectional view taken along the line XX-XX of FIG. FIG. 6 is an enlarged cross-sectional view of a main part showing the semiconductor device of FIG. FIG. 8 is a cross-sectional view taken along the line XXII-XXII of FIG. FIG. 3 is a cross-sectional view taken along the line XXIII-XXIII of FIG. FIG. 8 is a cross-sectional view taken along the line XXIV-XXIV of FIG. FIG. 6 is an enlarged plan view of a main part showing a semiconductor element of the semiconductor device of FIG. It is sectional drawing which shows an example of the manufacturing process of the semiconductor device of FIG. It is sectional drawing which shows an example of the manufacturing process of the semiconductor device of FIG. It is sectional drawing which shows an example of the manufacturing process of the semiconductor device of FIG. It is sectional drawing which shows an example of the manufacturing process of the semiconductor device of FIG. It is sectional drawing which shows an example of the manufacturing process of the semiconductor device of FIG. It is sectional drawing which shows an example of the manufacturing process of the semiconductor device of FIG. It is an enlarged image which shows the 2nd bonding part formed in the example of the manufacturing process of the semiconductor device of FIG. It is a main part plan view which shows the cutting process in an example of the manufacturing process of the semiconductor device of FIG. It is an X-ray image which shows the semiconductor device of FIG. It is a top view which shows an example of the semiconductor device based on 4th Embodiment of this invention.

Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.

The first embodiment of the present invention will be described with reference to FIGS. 1 to 11.

FIG. 1 is a perspective view of a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a plan view of the semiconductor device shown in FIG. FIG. 3 is a bottom view of the semiconductor device shown in FIG. FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. FIG. 5 is a cross-sectional view taken along the line VV of FIG. FIG. 6 is a partially enlarged cross-sectional view of the semiconductor device shown in FIG. FIG. 7 is a cross-sectional view taken along the line VII-VII of FIG. FIG. 8 is a cross-sectional view taken along the line VIII-VIII of FIG. FIG. 9 is a cross-sectional view taken along the line IX-IX of FIG.

The semiconductor device 101 of the present embodiment includes a semiconductor element 200, a main lead 300, a first sub-lead 400, a second sub-lead 500, a first wire 600, a second wire 700, and a resin package 800. In FIGS. 1 and 2, the resin package 800 is shown by a chain double-dashed line. The semiconductor device 101 is configured as a so-called surface mountable relatively small semiconductor device. To give an example of the size of the semiconductor device 101, the x-direction dimension is about 0.4 to 0.8 mm, the y-direction dimension is about 0.2 to 0.6 mm, and the thickness direction z-dimension is 0.3 to 0. It is about 4 mm.

In the present embodiment, the semiconductor element 200 is configured as a so-called transistor. The semiconductor element 200 has a front surface 201 and a back surface 202, and a first front surface electrode 211, a second front surface electrode 212, and a back surface electrode 220 are formed. The front surface 201 and the back surface 202 are oriented in opposite directions in the z direction. To give an example of the size of the semiconductor element 200, the x-direction dimension is about 300 μm and the y-direction dimension is about 300 μm.

As shown in FIG. 14, the first surface electrode 211 and the second surface electrode 212 are formed on the surface 201, and are composed of, for example, a part of an electrode layer 213 made of an Au plating layer. In the present embodiment, the first surface electrode 211 is a gate electrode and the second surface electrode 212 is a source electrode. In the present embodiment, in FIG. 14, the first surface electrode 211 is located on the left side in the x direction, and the second surface electrode 212 is located on the right side in the x direction. Further, the first surface electrode 211 is located on the lower side in the y-direction diagram, and the second surface electrode 212 is located on the upper side in the y-direction diagram. The back surface electrode 220 is formed on the back surface 202. In the present embodiment, the back surface electrode 220 is a drain electrode.

The removal region 214 is formed by removing a part of the electrode layer 231. The removal region 214 has a shape surrounding the first surface electrode 211. More specifically, the removal region 214 has a portion extending parallel to each other along the four sides of the semiconductor element 200 and a portion located with a relatively large area surrounding the first surface electrode 211. There is. The first surface electrode 211 and the second surface electrode 212 are insulated by such an annular removal region 214.

The peripheral region of the second surface electrode 212 is the active region 216. In the active region 216, the MOSFET 217 is built in a portion located inward in the z direction from the surface 201. The MOSFET 217 is composed of a plurality of unit cells 218 arranged in a matrix. The arrangement form of the plurality of unit cells 218 is not limited to the matrix shape, and may be, for example, a striped shape or a staggered shape.

In the present embodiment, one second surface electrode 212 is provided as the source electrode, but the present invention is not limited to this, and a plurality of second surface electrodes 212 may be provided.

A semiconductor element 200 is arranged on the main lead 300. As shown in FIGS. 2 and 3, in the present embodiment, the semiconductor element 200 has a portion that does not overlap with the main lead 300 in the thickness direction z-view. That is, the semiconductor element 200 has a portion that protrudes to the outside of the main lead 300 in the z-view in the thickness direction. As will be described in detail later, the main lead 300 is exposed from the resin package 800. The main lead 300 is derived from the lead frame. The main lead 300 is formed by performing patterning such as etching on a metal plate made of Cu, for example.

As shown in FIGS. 4 and 5, the main lead 300 has a main lead main surface 310 and a main lead back surface 320 facing opposite sides. Both the main lead main surface 310 and the main lead back surface 320 are flat.

The main lead main surface 310 faces upward in the thickness direction z. A semiconductor element 200 is arranged on the main lead main surface 310. Further, in the present embodiment, the main surface plating layer 311 is formed on the main lead main surface 310 of the main lead 300. The main surface plating layer 311 is interposed between the semiconductor element 200 and the main lead 300. The main surface plating layer 311 is formed over the entire area of the main lead main surface 310. The main surface plating layer 311 is made of Ag having a thickness of, for example, about 2 μm.

In FIG. 3, the back surface 320 of the main lead is shown by hatching. The main lead back surface 320 faces downward in the thickness direction z on the side opposite to the main lead main surface 310, and is used for surface mounting the semiconductor device 101. The back surface 320 of the main lead has a rectangular shape. All of the main lead back surface 320 overlaps the main lead main surface 310 in the thickness direction z, and is included in the main lead main surface 310.

The main lead 300 includes a main total thickness portion 330 and a main eaves portion 340.

The main total thickness portion 330 is a portion extending from the main lead main surface 310 to the main lead back surface 320 in the thickness direction z. In the present embodiment, the main total thickness portion 330 overlaps the semiconductor element 200 in the thickness direction z-view throughout. At least one of the first surface electrode 211 and the second surface electrode 212 overlaps the main total thickness portion 330 in the thickness direction z. In the present embodiment, both the first surface electrode 211 and the second surface electrode 212 overlap the main total thickness portion 330 in the thickness direction z. That is, in the thickness direction z, the first surface electrode 211 and the second surface electrode 212 are arranged closer to the center of the semiconductor element 200. Unlike the present embodiment, only the first surface electrode 211 overlaps the main total thickness portion 330 in the thickness direction z, and the second surface electrode 212 overlaps the main total thickness portion 330 in the thickness direction z. It does not have to be. Similarly, unlike the present embodiment, only the second surface electrode 212 overlaps the main total thickness portion 330 in the thickness direction z, and the first surface electrode 211 overlaps the main total thickness portion 330 in the thickness direction z. It does not have to overlap in. In the present embodiment, the thickness of the main total thickness portion 330 is about 0.9 to 1.1 mm. The main total thickness portion 330 constitutes the main lead back surface 320.

The main eaves portion 340 protrudes from the main total thickness portion 330 in a direction perpendicular to the thickness direction z. In the present embodiment, the main eaves portion 340 protrudes from the main total thickness portion 330 in the x direction and the y direction which are perpendicular to the thickness direction z. Further, in the present embodiment, the main eaves portion 340 protrudes from the main lead main surface 310 side portion of the main total thickness portion 330 in the x direction and the y direction which are perpendicular to the thickness direction z. The thickness of the main eaves portion 340 is, for example, half that of the main total thickness portion 330, and is about 0.05 mm. The main eaves portion 340 and the main total thickness portion 330 constitute the main lead main surface 310 described above. On the other hand, the main eaves portion 340 does not form the main lead back surface 320. The main eaves portion 340 surrounds the main total thickness portion 330 in the z-view in the thickness direction. Further, in the present embodiment, the main eaves portion 340 overlaps the semiconductor element 200 in the thickness direction z-viewing as a whole.

In the present embodiment, the main eaves portion 340 has a main front portion 341, a main side portion 342, and a main rear portion 343.

The main front portion 341 projects from the main total thickness portion 330 toward the first sub-lead 400. Further, in the present embodiment, the main front portion 341 projects from the main total thickness portion 330 toward the second sub lead 500.

The main side portion 342 projects from the main total thickness portion 330 in a direction perpendicular to the projecting direction of the main front portion 341. Specifically, the main side portion 342 projects from the main total thickness portion 330 in the y direction. In this embodiment, two main side portions 342 are formed. Further, in the present embodiment, the main lead 300 has two main side connecting portions 351. The main side connecting portion 351 extends from the main side portion 342 of the main eaves portion 340 and has the same thickness as the main side portion 342. The y-direction end face of the main side connecting portion 351 is exposed from the resin package 800.

The main rear portion 343 projects from the main total thickness portion 330 in the direction opposite to the direction in which the main front portion 341 protrudes. In this embodiment, the main lead 300 has a main rear connecting portion 352. The main rear connecting portion 352 extends from the main rear portion 343 of the main eaves portion 340 and has the same thickness as the main rear portion 343. The x-direction end face of the main rear connecting portion 352 is exposed from the resin package 800.

As shown in FIG. 6, in the semiconductor element 200, the back surface electrode 220 is bonded to the main lead main surface 310 (main surface plating layer 311). Specifically, the back electrode 220 as a single metal layer is directly bonded to the main lead main surface 310 (main surface plating layer 311) by, for example, a thermal pressure bonding method. In this thermal crimping, no vibration is applied, only heat and pressure are applied.

The first sub-lead 400 is separated from the main lead 300. Specifically, the first and secondary leads 400 are arranged apart from the main lead 300 in the x direction. Further, the first secondary lead 400 is separated from the second secondary lead 500. The first sub-lead 400 is exposed from the resin package 800 to the outside of the resin package 800 in the z-view in the thickness direction. In the present embodiment, the first sublead 400 is exposed from the resin package 800 in the direction x and the direction y from the resin package 800. The first sublead 400 is derived from the lead frame. The first secondary lead 400 is formed by, for example, patterning a metal plate made of Cu by etching or the like.

The first sub-lead 400 has a first sub-lead main surface 410, a first sub-lead back surface 420, a first sub-lead end surface 481, and a first sub-lead side surface 482. The first sub-lead main surface 410, the first sub-lead back surface 420, the first sub-lead end surface 481, and the first sub-lead side surface 482 are all flat.

The first secondary lead main surface 410 faces upward in the thickness direction z. The first wire 600 is bonded to the first secondary lead main surface 410. In the present embodiment, the first sub-surface plating layer 411 is formed on the first sub-lead main surface 410. The first secondary surface plating layer 411 is interposed between the first secondary lead main surface 410 and the first wire 600. The first sub-surface plating layer 411 is formed over the entire area of the first sub-lead main surface 410. The first secondary surface plating layer 411 is made of Ag having a thickness of, for example, about 2 μm. In FIG. 1, for convenience of understanding, a halftone is applied to the first secondary surface plating layer 411.

The back surface 420 of the first sub-lead faces the side opposite to the direction of the main surface 410 of the first sub-lead. Specifically, the back surface 420 of the first sub-lead faces downward in the thickness direction z on the side opposite to the main surface 410 of the first sub-lead. The back surface 420 of the first secondary lead is exposed from the resin package 800. The first secondary lead back surface 420 is used for surface mounting the semiconductor device 101. In FIG. 3, the back surface 420 of the first secondary lead is shown by hatching.

The first sub-lead end face 481 faces the side opposite to the side where the main lead 300 is located. Specifically, the first sublead end face 481 faces the right side of FIG. The first sub-lead end face 481 is connected to the first sub-lead back surface 420. The first sub-lead end face 481 is exposed from the resin package 800.

The first sub-lead side surface 482 faces a direction perpendicular to both the direction in which the first sub-lead end surface 481 faces and the thickness direction z of the semiconductor element 200. Specifically, the first secondary lead side surface 482 faces the lower side of FIG. The first sub-lead side surface 482 is connected to the first sub-lead back surface 420. The first sub-lead side surface 482 is exposed from the resin package 800.

The first sub lead 400 includes a first sub total thickness portion 430 and a first sub eaves portion 440.

The first sub-total thickness portion 430 is a portion extending from the first sub-lead main surface 410 to the first sub-lead back surface 420 in the thickness direction z. In the present embodiment, the thickness of the first sub-total thickness portion 430 is about 0.1 mm. The first sub full thickness portion 430 constitutes the first sub lead main surface 410 and the first sub lead back surface 420. In the present embodiment, the first sub-total thickness portion 430 is exposed from the resin package 800. Therefore, the first sub-total thickness portion 430 constitutes the first sub-lead end face 481 and the first sub-lead side surface 482.

The first sub-eaves portion 440 protrudes from the first sub-total thickness portion 430 in a direction perpendicular to the thickness direction z. In the present embodiment, the first secondary eaves portion 440 protrudes in the x direction and the y direction. The thickness of the first sub-eaves portion 440 is, for example, half that of the first sub-total thickness portion 430, and is about 0.05 mm. The first sub-eaves portion 440 constitutes the first sub-lead main surface 410. On the other hand, the first secondary eaves portion 440 does not form the first secondary lead back surface 420.

In the present embodiment, the first deputy eaves portion 440 has a first deputy front portion 441 and a first deputy inner portion 442.

The first sub-front portion 441 projects from the first sub-total thickness portion 430 toward the main lead 300. The first sub-inner portion 442 projects from the first sub-total thickness portion 430 toward the second sub lead 500.

The second sub-lead 500 is separated from the main lead 300. Specifically, the second secondary lead 500 is arranged so as to be separated from the main lead 300 in the x direction. Further, the second secondary lead 500 is separated from the first secondary lead 400. The second secondary lead 500 is exposed from the resin package 800 to the outside of the resin package 800 in the z-view in the thickness direction. In the present embodiment, the second secondary lead 500 is exposed from the resin package 800 in the direction x and the direction y from the resin package 800. The second secondary lead 500 is derived from the lead frame. The second secondary lead 500 is formed by performing patterning such as etching on a metal plate made of Cu, for example.

The second sub-lead 500 has a second sub-lead main surface 510, a second sub-lead back surface 520, a second sub-lead end surface 581, and a second sub-lead side surface 582. The second sub-lead main surface 510, the second sub-lead back surface 520, the second sub-lead end surface 581, and the second sub-lead side surface 582 are all flat.

The second secondary lead main surface 510 faces upward in the thickness direction z. The second wire 700 is bonded to the second secondary lead main surface 510. In the present embodiment, the second sub-surface plating layer 511 is formed on the second sub-lead main surface 510. The second secondary surface plating layer 511 is interposed between the second secondary lead main surface 510 and the second wire 700. The second secondary surface plating layer 511 is formed over the entire area of the second secondary lead main surface 510. The second secondary surface plating layer 511 is made of Ag having a thickness of, for example, about 2 μm. In FIG. 1, for convenience of understanding, a halftone is applied to the second secondary surface plating layer 511.

The back surface 520 of the second sub-lead faces the side opposite to the direction of the main surface 510 of the second sub-lead. Specifically, the second secondary lead back surface 520 faces downward in the thickness direction z on the side opposite to the second secondary lead main surface 510. The back surface 520 of the second secondary lead is exposed from the resin package 800. The second secondary lead back surface 520 is used for surface mounting the semiconductor device 101. In FIG. 3, the back surface 520 of the second secondary lead is shown by hatching.

The second secondary lead end face 581 faces the side opposite to the side where the main lead 300 is located. Specifically, the second secondary lead end face 581 faces the right side of FIG. The second sub-lead end face 581 is connected to the second sub-lead back surface 520. The second secondary lead end face 581 is exposed from the resin package 800.

The second sub-lead side surface 582 faces a direction perpendicular to both the direction in which the second sub-lead end face 581 faces and the thickness direction z of the semiconductor element 200. Specifically, the second secondary lead side surface 582 faces the upper side of FIG. The second secondary lead side surface 582 is connected to the second secondary lead back surface 520. The second secondary lead side surface 582 is exposed from the resin package 800.

The second sub lead 500 includes a second sub full thickness portion 530 and a second sub eaves portion 540.

The second sub-total thickness portion 530 is a portion extending from the second sub-lead main surface 510 to the second sub-lead back surface 520 in the thickness direction z. In the present embodiment, the thickness of the second sub-total thickness portion 530 is about 0.1 mm. The second sub-total thickness portion 530 constitutes a second sub-lead main surface 510 and a second sub-lead back surface 520. In the present embodiment, the second sub-total thickness portion 530 is exposed from the resin package 800. Therefore, the second sub-total thickness portion 530 constitutes the second sub-lead end face 581 and the second sub-lead side surface 582.

The second sub-eaves portion 540 protrudes from the second sub-total thickness portion 530 in a direction perpendicular to the thickness direction z. In the present embodiment, the second secondary eaves portion 540 protrudes in the x direction and the y direction. The thickness of the second sub-eaves portion 540 is, for example, half that of the second sub-total thickness portion 530, and is about 0.05 mm. The second secondary eaves portion 540 constitutes the second secondary lead main surface 510. On the other hand, the second secondary eaves portion 540 does not form the second secondary lead back surface 520.

In the present embodiment, the second sub-eaves portion 540 has a second sub-front portion 541 and a second sub-inner portion 542.

The second sub-front portion 541 projects from the second sub-total thickness portion 530 toward the main lead 300. The second sub inner portion 542 projects from the second sub total thickness portion 530 toward the first sub lead 400.

The first wire 600 is directly connected to the semiconductor element 200 and conducts the semiconductor element 200 and the first sublead 400. Specifically, the first wire 600 is bonded to the first surface electrode 211 of the semiconductor element 200 and the first sub-surface plating layer 411.

The first wire 600 has a first bonding portion 610 and a second bonding portion 620. The first wire 600 is made of Au having a diameter of about 20 μm.

The first bonding portion 610 is bonded to the first secondary surface plating layer 411 and has a coronal lump portion.

The second bonding portion 620 is bonded to the first surface electrode 211 of the semiconductor element 200 via the first bump 630. The second bonding portion 620 has a tapered shape in which the z-thickness in the thickness direction becomes smaller toward the tip.

The first bump 630 is a portion similar to the above-mentioned mass portion of the first bonding portion 610. In the present embodiment, the volume of the first bump 630 is slightly smaller than that of the mass portion of the first bonding portion 610. The first bump 630 overlaps the main total thickness portion 330 in the z-view in the thickness direction. Note that FIG. 10 shows an enlarged image of the second bonding portion 620 of the semiconductor device shown in FIG.

The second wire 700 is directly connected to the semiconductor element 200 and conducts the semiconductor element 200 and the second sublead 500. Specifically, the second wire 700 is bonded to the second surface electrode 212 of the semiconductor element 200 and the second secondary surface plating layer 511.

The second wire 700 has a first bonding portion 710 and a second bonding portion 720. The second wire 700 is made of Au having a diameter of about 20 μm.

The first bonding portion 710 is bonded to the second secondary surface plating layer 511 and has a coronal lump portion.

The second bonding portion 720 is bonded to the second surface electrode 212 of the semiconductor element 200 via the second bump 730. The second bonding portion 720 has a tapered shape in which the z-thickness in the thickness direction becomes smaller toward the tip.

The second bump 730 is a portion similar to the above-mentioned mass portion of the first bonding portion 710. The second bump 730 overlaps the main total thickness portion 330 in the z-view in the thickness direction. In the present embodiment, the volume of the second bump 730 is slightly smaller than that of the mass portion of the first bonding portion 710.

The resin package 800 covers the semiconductor element 200, the main lead 300, the first sub-lead 400, the second sub-lead 500, the first wire 600, and the second wire 700. The resin package 800 is made of, for example, a black epoxy resin. Further, in the resin package 800, all of the main lead back surface 320 of the main lead 300, the first sub lead back surface 420 of the first sub lead 400, and the second sub lead back surface 520 of the second sub lead 500 are z downward in the thickness direction. It is exposed to the side.

The resin package 800 has a resin main surface 801, a resin back surface 802, a first resin side surface 803, a second resin side surface 804, a first resin end surface 805, and a second resin end surface 806.

The resin main surface 801 faces the same direction as the main lead main surface 310. In this embodiment, the resin main surface 801 is flat.

The resin back surface 802 faces the same direction as the main lead back surface 320. That is, the resin back surface 802 faces in the direction opposite to the direction in which the resin main surface 801 faces. The resin back surface 802 is flat. The main lead 300, the first sub lead 400, and the second sub lead 500 are exposed from the resin back surface 802. In the present embodiment, the resin back surface 802 is flush with each of the main lead back surface 320, the first sub lead back surface 420, and the second sub lead back surface 520.

The first resin side surface 803 faces the same direction as the first sub-lead side surface 482 of the first sub-lead 400. The first resin side surface 803 is flat. The first secondary lead 400 is exposed from the first resin side surface 803. In the present embodiment, the first sub-total thickness portion 430 is exposed from the second resin side surface 804. The first resin side surface 803 is flush with the first sub lead side surface 482. Further, in the present embodiment, the main lead 300 is exposed on the first resin side surface 803. Specifically, on the first resin side surface 803, the main side connecting portion 351 of the main lead 300 is exposed. The first resin side surface 803 is flush with the end surface of the main side connecting portion 351.

The second resin side surface 804 faces the same direction as the second sub lead side surface 582 of the second sub lead 500. The second resin side surface 804 is flat. The second secondary lead 500 is exposed from the second resin side surface 804. The second resin side surface 804 is flush with the second secondary lead side surface 582. In the present embodiment, the second sub-total thickness portion 530 is exposed from the second resin side surface 804. Further, in the present embodiment, the main lead 300 is exposed on the second resin side surface 804. Specifically, the main side connecting portion 351 of the main lead 300 is exposed on the second resin side surface 804. The second resin side surface 804 is flush with the end surface of the main side connecting portion 351.

The first resin end face 805 faces the same direction as the first sub-lead end face 481 of the first sub-lead 400. The first resin end face 805 is flat. The first sub-lead 400 is exposed from the first resin end face 805. The first resin end face 805 is flush with the first sub lead end face 481. In the present embodiment, the first sub-total thickness portion 430 is exposed from the first resin end face 805. Similarly, the first resin end face 805 faces the same direction as the second sub lead end face 581 of the second sub lead 500. The second secondary lead 500 is exposed from the first resin end face 805. The first resin end face 805 is flush with the second secondary lead end face 581. In the present embodiment, the second sub-total thickness portion 530 is exposed from the first resin end face 805.

The second resin end face 806 faces in the direction opposite to the direction in which the first resin end face 805 faces. The second resin end face 806 is flat. The main lead 300 is exposed from the second resin end face 806. In the present embodiment, the main rear connecting portion 352 is exposed from the second resin end face 806. The second resin end face 806 is flush with the end face of the main rear connecting portion 352.

It should be noted that the surface of the resin and the surface of the lead (main lead 300, first sub-lead 400, or second sub-lead 500) are flush with each other when the semiconductor device 101 is manufactured. This is because the resin members that form the resin package are diced together. FIG. 11 shows a cross-sectional view of one step in the method for manufacturing the semiconductor device shown in FIG. The figure shows the vicinity of the first secondary lead 400. In this embodiment, the lead and the resin member are diced along the line Ct1 in the figure.

Next, the action and effect of this embodiment will be described.

In the present embodiment, the semiconductor element 200 has a portion that does not overlap the main lead 300 in the thickness direction z-view of the semiconductor element 200. According to such a configuration, the size of the main lead 300 can be made relatively smaller than the size of the semiconductor element 200 in the z-view in the thickness direction. As a result, the size of the resin package 800 in the thickness direction z-view is determined not by the main lead 300 but by the semiconductor element 200. As a result, the size of the semiconductor device 101 in the thickness direction z-view can be reduced.

In this embodiment, the main lead 300 includes a main total thickness portion 330 and a main eaves portion 340. According to such a configuration, the bonding area between the semiconductor element 200 and the main lead 300 can be increased. As a result, the semiconductor element 200 can be reliably joined by the main lead 300.

Then, the second bonding portion 620 of the first wire 600 is bonded to the first surface electrode 211 via the first bump 630, and the second bonding portion 720 of the second wire 700 is bonded to the second surface electrode 212 via the second bump 730. The z-height in the thickness direction of the first wire 600 and the second wire 700 can be reduced by adopting the configuration joined to. This contributes to lowering the z-height in the thickness direction of the semiconductor device 101. Therefore, according to the present embodiment, the semiconductor device 101 can be miniaturized.

The length of the first wire 600 is due to the fact that the first surface electrode 211 as the gate electrode is more distant from the first secondary lead 400 and the second secondary lead 500 than the second surface electrode 212 as the source electrode. Can be longer than the second wire 700. The longer first wire 600 tends to increase the bonding strength particularly in the second bonding portion 620. Generally, the first surface electrode 211 as a gate electrode is formed on a relatively smooth surface of the semiconductor layer 231 via an insulating layer (not shown). Such a first surface electrode 211 is relatively difficult to improve the bonding strength of wire bonding. On the other hand, the second surface electrode 212 as the source electrode is often connected to a metal portion filled in a plurality of trenches (pits) formed in the semiconductor layer 231. With such a configuration, the second surface electrode 212 tends to relatively improve the bonding strength of wire bonding. Therefore, joining the first wire 600, which tends to increase the bonding strength, to the first surface electrode 211 as the gate electrode, which is relatively concerned about insufficient bonding strength, is advantageous for avoiding problems such as wire peeling. ..

Since the main eaves portion 340 has the main front portion 341, the bonding strength between the main lead 300 and the resin package 800 can be increased. Further, while keeping the semiconductor element 200 and the first sub-lead 400 and the second sub-lead 500 close to each other, it is possible to prevent the main lead back surface 320, the first sub-lead back surface 420, and the second sub-lead back surface 520 from being unreasonably approached. can do.

Since the main eaves portion 340 has the main side portion 342 and the main rear portion 343, the bonding strength between the main lead 300 and the resin package 800 can be increased. The configuration in which all of the main total thickness portions 330 are surrounded by the main eaves portions 340 is suitable for increasing the bonding strength between the main lead 300 and the resin package 800.

The main side connecting portion 351 and the main rear connecting portion 352 appropriately hold the main lead 300 in the manufacturing process of the semiconductor device 101. The y-direction end face of the main side connecting portion 351 and the x-direction end face of the main rear connecting portion 352 are exposed from the resin package 800 but are separated from the main lead back surface 320. Therefore, there is little possibility that the solder for surface-mounting the semiconductor device 101 accidentally spreads on the y-direction end face of the main side connecting portion 351 and the x-direction end face of the main rear connecting portion 352.

Since the main surface plating layer 311 is formed on the main lead main surface 310, the bonding strength between the back electrode 220 of the semiconductor element 200 and the main lead main surface 310 can be increased. By overlapping the main surface plating layer 311 on all of the main eaves 340, the area that can be used as the main lead main surface 310 can be expanded.

Since the first secondary lead 400 has the first secondary eaves portion 440, the bonding strength between the first secondary lead 400 and the resin package 800 can be increased. Since the first sub-eaves portion 440 has the first sub-front portion 441, the distance between the first sub-lead back surface 420 and the main lead back surface 320 becomes unreasonably close while increasing the bonding strength with the resin package 800. It is possible to avoid it. This is because even when the entire semiconductor device 101 is miniaturized, the first sub-lead back surface 420 and the main lead back surface 320 adhere to the solder adhering to the first sub-lead back surface 420 and the main lead back surface 320. This means that it is possible to prevent a problem of conduction through the solder.

Since the first sub-eaves portion 440 has the first sub-inner portion 442, the bonding strength between the first sub-lead 400 and the resin package 800 can be increased. Since the first sub-eaves portion 440 has the first sub-inner portion 442, the distance between the first sub-lead back surface 420 and the second sub-lead back surface 520 is unreasonable while increasing the bonding strength with the resin package 800. It is possible to avoid getting close to. This is because even when the entire semiconductor device 101 is miniaturized, the solder on the back surface 420 of the first sub-lead and the back surface 520 of the second sub-lead adhere to the back surface 420 of the first sub-lead and the second sub-lead. This means that it is possible to prevent a problem of conduction via the solder adhering to the back surface 520.

In the present embodiment, the first sub-lead 400 has a first sub-lead end face 481 connected to the back surface 420 of the first sub-lead. The first sub-lead end face 481 is exposed from the resin package 800. Therefore, the back surface 420 of the first secondary lead can be made wider. As a result, the tape 901 (see FIG. 11) used in the resin molding for forming the resin package 800 and the back surface 420 of the first secondary lead can be more firmly bonded. Therefore, it is possible to prevent the resin material from entering between the tape 901 and the back surface 420 of the first secondary lead during the resin molding. As a result, it is possible to prevent resin burrs from being generated on the back surface 420 of the first secondary lead. Similarly, the same effect can be obtained by exposing the first secondary lead side surface 482 from the resin package 800. Further, the effect on the first sub-lead 400 is also due to the fact that the second sub-lead end face 581 of the second sub-lead 500 is exposed from the resin package 800 and that the second sub-lead side surface 582 is exposed. And the same effect as described above is achieved.

Since the first secondary surface plating layer 411 is formed on the first secondary lead main surface 410, the bonding strength between the first wire 600 and the first secondary lead main surface 410 can be increased.

Since the second secondary lead 500 has the second secondary eaves portion 540, the bonding strength between the second secondary lead 500 and the resin package 800 can be increased. Since the second sub-eaves portion 540 has the second sub-front portion 541, the distance between the second sub-lead back surface 520 and the main lead back surface 320 becomes unreasonably close while increasing the bonding strength with the resin package 800. It is possible to avoid it.

Since the second sub-eaves portion 540 has the second sub-inner portion 542, the bonding strength between the second sub-lead 500 and the resin package 800 can be increased. Since the second sub-eaves portion 540 has the second sub-inner portion 542, the distance between the second sub-lead back surface 520 and the first sub-lead back surface 420 is unreasonable while increasing the bonding strength with the resin package 800. It is possible to avoid getting close to. This is because even when the entire semiconductor device 101 is miniaturized, the solder on the back surface 420 of the first sub-lead and the back surface 520 of the second sub-lead adhere to the back surface 420 of the first sub-lead and the second sub-lead. This means that it is possible to prevent a problem of conduction via the solder adhering to the back surface 520.

Since the second secondary surface plating layer 511 is formed on the second secondary lead main surface 510, the bonding strength between the second wire 700 and the second secondary lead main surface 510 can be increased.

In the bonding between the semiconductor element 200 and the main lead main surface 310 of the main lead 300, the back electrode 220 made of a single metal layer is directly bonded to the main lead main surface 310, and vibration is applied during the bonding. No. With such a configuration, it is not necessary to set a margin region in consideration of vibration in the region of the main lead 300 located around the semiconductor element 200. This is advantageous for miniaturization of the semiconductor device 101.

A second embodiment of the present invention will be described with reference to FIGS. 12 and 13.

FIG. 12 is a perspective view of the semiconductor device according to the second embodiment of the present invention. FIG. 13 is a plan view of the semiconductor device shown in FIG.

In the semiconductor device 102 shown in these figures, the shapes of the first sublead 400 and the second sublead 500 are different from those of the semiconductor device 101. Since the configurations other than those described below are the same as those of the semiconductor device 101, the same reference numerals as those in the first embodiment will be added and the description thereof will be omitted.

In the present embodiment, the first sub lead 400 includes a first sub full thickness portion 430, a first sub eaves portion 440, and a first sub extension portion 460.

In the present embodiment, the first sub-total thickness portion 430 is not exposed from the resin package 800.

The first sub-extending portion 460 extends from the first sub-total thickness portion 430 in a direction perpendicular to the thickness direction z. The thickness of the first sub-extending portion 460 is, for example, half that of the first sub-total thickness portion 430, and is about 0.05 mm. The first sub-extending portion 460 constitutes the first sub-lead back surface 420. On the other hand, the first sub-extending portion 460 does not constitute the first sub-lead main surface 410. The first sub-extending portion 460 is exposed from the resin package 800 toward the outside of the resin package 800 in the z-view in the thickness direction. Specifically, the first sub-extending portion 460 is exposed from the resin package 800 in the direction x and the direction y from the resin package 800. Therefore, the first sub-extending portion 460 constitutes the first sub-lead end face 481 and the first sub-lead side surface 482.

In the present embodiment, the first sub-extending portion 460 has a first sub-rear portion 461 and a first sub-side portion 462.

The first sub-rear portion 461 projects from the first sub-total thickness portion 430 toward the side opposite to the side where the main lead 300 is located. The first sub-rear portion 461 constitutes the first sub-lead end face 481. The first sub-side portion 462 projects from the first sub-total thickness portion 430 toward the side opposite to the side where the second sub lead 500 is located. The first sub-side portion 462 constitutes the first sub-lead side surface 482.

In the present embodiment, the second sub-total thickness portion 530 is not exposed from the resin package 800.

The second sub-extending portion 560 extends from the second sub-total thickness portion 530 in a direction perpendicular to the thickness direction z. The thickness of the second sub-extending portion 560 is, for example, half that of the second sub-total thickness portion 530, and is about 0.05 mm. The second sub-extending portion 560 constitutes the second sub-lead back surface 520. On the other hand, the second sub-extending portion 560 does not constitute the second sub-lead main surface 510. The second sub-extending portion 560 is exposed from the resin package 800 toward the outside of the resin package 800 in the z-view in the thickness direction. Specifically, the second sub-extending portion 560 is exposed from the resin package 800 in the direction x and the direction y from the resin package 800. Therefore, the second sub-extending portion 560 constitutes the second sub-lead end face 581 and the second sub-lead side surface 582.

In the present embodiment, the second sub-extending portion 560 has a second sub-rear portion 561 and a second sub-side side portion 562.

The second sub-rear portion 561 projects from the second sub-total thickness portion 530 toward the side opposite to the side where the main lead 300 is located. The second sub-rear portion 561 constitutes the second sub-lead end face 581. The second sub-side portion 562 projects from the second sub-total thickness portion 530 toward the side opposite to the side where the first sub-lead 400 is located. The second secondary side portion 562 constitutes the second secondary lead side surface 582.

When manufacturing the semiconductor device 102, the lead and the resin member are diced along the line Ct2 of FIG. 11 used in the description of the semiconductor device 101.

Next, the action and effect of this embodiment will be described.

According to the present embodiment, in addition to the same effects as described with respect to the semiconductor device 101, the following effects are exhibited.

According to the present embodiment, when cutting the first sub-lead 400 of the lead frame, it is not necessary to dic the first sub-total thickness portion 430, and a relatively thin portion may be diced. The generation of burrs is proportional to the thickness of the lead frame to be cut. Therefore, it is possible to suppress the generation of metal burrs that can be formed by cutting the portion of the lead frame that should be the first secondary lead 400. Similarly, it is possible to suppress the generation of metal burrs that can be formed by cutting the portion of the lead frame that should be the second secondary lead 500.

As a matter of fact, when the main lead 300, the first sub-lead 400 and the second sub-lead 500 are patterned by etching, the boundary between the main total thickness portion 330 and the main eaves portion 340 is shown in FIGS. 1 to 13 and the like. The clear corners shown in are not formed and can be curved surfaces. Similarly, in the first sub lead 400, the boundary between the first sub total thickness portion 430 and the first sub eaves portion 440, the boundary between the first sub eaves portion 440 and the first sub extension portion 460, and the second sub lead 500. The boundary between the second sub-total thickness portion 530 and the second sub-hasp portion 540, the boundary between the second sub-hashi portion 540 and the second sub-extending portion 560, and the like can also be curved surfaces. This is because even if the design is intended for the form shown in FIGS. 1 to 13, the above-mentioned curved surface is inevitably formed in the etching process when the semiconductor devices 101 and 102 have the above-mentioned extremely small configuration. This is because it may occur.

FIG. 15 shows a modified example of the semiconductor device. As shown in the figure, the positions of the first surface electrode 211 as the gate electrode, the second surface electrode 212 as the source electrode, the second bonding portions 620 and 720, the first bump 630, and the second bump 730 are located. , It is different from the semiconductor device shown in FIG. Since the description regarding the semiconductor device 101 other than these positions can be applied to the description of the semiconductor device shown in FIG. 15, the description other than the position will be omitted. In FIG. 2, the first surface electrode 211, which is the gate electrode, is located to the left of the semiconductor element 200, and the second surface electrode 212, which is the source electrode, is located to the right of the semiconductor element 200. Further, the second bonding portion 620 and the first bump 630 were located on the left side of the second bonding portion 720 and the second bump 730. On the other hand, in FIG. 15, the first surface electrode 211, which is a gate electrode, is located to the right of the semiconductor element 200, and the second surface electrode 212, which is a source electrode, is located to the left of the semiconductor element 200. Further, the second bonding portion 620 and the first bump 630 are located on the right side of the second bonding portion 720 and the second bump 730. In this way, the positions of the first surface electrode 211, which is the gate electrode, and the second surface electrode 212, which is the source electrode, in the plan view can be freely changed.

The present invention is not limited to the above-described embodiments. The specific configuration of each part of the present invention can be freely redesigned. The semiconductor element is not limited to a transistor, and may be a diode, for example.

16 to 24 show an example of the semiconductor device according to the third embodiment of the present invention.

The semiconductor device 101 of the present embodiment includes a semiconductor element 200, a main lead 300, a first sub-lead 400, a second sub-lead 500, a first wire 600, a second wire 700, and a resin package 800. The semiconductor device 101 is configured as a so-called surface-mountable relatively small semiconductor device. To give an example of the size, the x-direction dimension is about 0.8 mm, the y-direction dimension is about 0.6 mm, and z. The directional dimension is about 0.36 mm. The z direction is the thickness direction of the semiconductor element, the main lead, the first sub-lead, and the second sub-lead referred to in the present invention. FIG. 16 is a perspective view of the semiconductor device 101 as viewed from above in the z direction. FIG. 17 is a perspective view of the semiconductor device 101 as viewed from below in the z direction. FIG. 18 is a plan view of the semiconductor device 101. FIG. 19 is a cross-sectional view taken along the line XIX-XIX of FIG. 18 in the zx plane. FIG. 20 is a cross-sectional view taken along the line XX-XX of FIG. 18 in the zx plane. FIG. 21 is an enlarged cross-sectional view of a main part in the zx plane that crosses the semiconductor element 200. FIG. 22 is a cross-sectional view taken along the line XXII-XXII of FIG. 18 in the yz plane. FIG. 23 is a cross-sectional view taken along the line XXIII-XXIII of FIG. 18 in the yz plane. FIG. 24 is a cross-sectional view taken along the line XXIV-XXIV of FIG. 18 in the yz plane.

In the present embodiment, the semiconductor element 200 is configured as a so-called transistor. The semiconductor element 200 has a front surface 201 and a back surface 202, and a first front surface electrode 211, a second front surface electrode 212, and a back surface electrode 220 are formed. The front surface 201 and the back surface 202 are oriented in opposite directions in the z direction. To give an example of the size of the semiconductor element 200, the x-direction dimension is about 300 μm and the y-direction dimension is about 300 μm.

As shown in FIG. 25, the first surface electrode 211 and the second surface electrode 212 are formed on the surface 201, and are composed of, for example, a part of an electrode layer 213 made of an Au plating layer. In the present embodiment, the first surface electrode 211 is a gate electrode and the second surface electrode 212 is a source electrode. In the present embodiment, in FIGS. 18 and 25, the first surface electrode 211 is located on the left side in the x direction, and the second surface electrode 212 is located on the right side in the x direction. Further, the first surface electrode 211 is located on the lower side in the y-direction diagram, and the second surface electrode 212 is located on the upper side in the y-direction diagram. The back surface electrode 220 is formed on the back surface 202. In the present embodiment, the back surface electrode 220 is a drain electrode.

The removal region 214 is formed by removing a part of the electrode layer 231. The removal region 214 has a shape surrounding the first surface electrode 211. More specifically, the removal region 214 has a portion extending parallel to each other along the four sides of the semiconductor element 200 and a portion located with a relatively large area surrounding the first surface electrode 211. There is. The first surface electrode 211 and the second surface electrode 212 are insulated by such an annular removal region 214.

The peripheral region of the second surface electrode 212 is the active region 216. In the active region 216, the MOSFET 217 is built in a portion located inward in the z direction from the surface 201. The MOSFET 217 is composed of a plurality of unit cells 218 arranged in a matrix. The arrangement form of the plurality of unit cells 218 is not limited to the matrix shape, and may be, for example, a striped shape or a staggered shape.

In the present embodiment, one second surface electrode 212 is provided as the source electrode, but the present invention is not limited to this, and a plurality of second surface electrodes 212 may be provided.

FIG. 21 shows the vicinity of the back electrode 220 of the semiconductor element 200. The semiconductor element 200 of this embodiment has a semiconductor layer 231 and a eutectic layer 232. The semiconductor layer 231 is a layer in which each part that functions as a transistor is formed, and is made of, for example, Si. The eutectic layer 232 is composed of a eutectic body of a semiconductor and a metal constituting the semiconductor layer 231. In this embodiment, the eutectic layer 232 is composed of a eutectic of Si as a semiconductor and Au as a metal. The eutectic layer 232 is formed by an alloying treatment by laminating a layer made of Au on a semiconductor layer 231 and then heating the layers. A back surface electrode 220 is laminated below the eutectic layer 232 in the z direction. The back electrode 220 is, for example, an Au layer formed by vapor deposition on a eutectic layer 232, and is an example of a simple metal layer referred to in the present invention. The eutectic layer 232 has a thickness of, for example, about 1200 nm. The back electrode 220 as a single metal layer has a thickness of, for example, about 600 nm, and is thinner than the eutectic layer 232. In the present embodiment, the surface of the eutectic layer 232 facing downward in the z direction is defined as the back surface 202 of the semiconductor element 200.

The main lead 300 has a die pad portion 310, a main back surface terminal portion 320, a main total thickness portion 330, and a main eaves portion 340. The main lead 300 is formed by performing patterning such as etching on a metal plate made of Cu, for example.

The die pad portion 310 faces upward in the z direction and is a portion on which the semiconductor element 200 is mounted. In the present embodiment, the die pad portion 310 has a rectangular shape having a dimension in the x direction of about 0.4 mm and a dimension in the y direction of about 0.5 mm. Further, in the present embodiment, the main surface plating layer 311 is formed on the die pad portion 310. The main surface plating layer 311 is formed over the entire area of the die pad portion 310. The main surface plating layer 311 is made of Ag having a thickness of, for example, about 2 μm. In FIG. 16, for convenience of understanding, the main surface plating layer 311 is halftone.

The main back surface terminal portion 320 faces downward in the z direction on the side opposite to the die pad portion 310, and is used for surface mounting the semiconductor device 101. The main back surface terminal portion 320 has a rectangular shape having a dimension in the x direction of about 0.18 mm and a dimension in the y direction of about 0.48 mm. All of the main back surface terminal portion 320 overlaps the die pad portion 310 in the z-direction view, and is included in the die pad portion 310. In the present embodiment, the main back surface plating layer 321 is formed on the main lead 300. The main back surface plating layer 321 is laminated on a portion of the main lead 300 for forming the main back surface terminal portion 320, and is made of, for example, Ni, Sn or an alloy thereof having a thickness of about 0.06 mm. In the present embodiment, for convenience, the lower surface of the main back surface plating layer 321 in the z direction is defined as the main back surface terminal portion 320. The terminal portion 320 may be configured.

The main total thickness portion 330 is a portion extending from the die pad portion 310 to the main back surface terminal portion 320 in the z direction. In the present embodiment, the main total thickness portion 330 refers to a portion made of Cu excluding the main back surface plating layer 321 and has a thickness of about 0.1 mm. Like the main back surface terminal portion 320, the main total thickness portion 330 has a dimension in the x direction of about 0.18 mm and a dimension in the y direction of about 0.48 mm.

The main eaves portion 340 protrudes from the die pad portion 310 side portion of the main total thickness portion 330 in the x direction and the y direction which are perpendicular to the z direction. The upper end surface of the main eaves portion 340 in the z direction is flush with the main total thickness portion 330. In the present embodiment, the main eaves portion 340 has a main front portion 341, a main side portion 342, and a main rear portion 343. The thickness of the main eaves portion 340 is, for example, half that of the main total thickness portion 330, and is about 0.05 mm.

The main front portion 341 projects from the main total thickness portion 330 in the x direction toward the first sub-lead 400 and the second sub-lead 500. In the present embodiment, the main front portion 341 has a rectangular shape having a dimension in the x direction of about 0.21 mm and a dimension in the y direction of about 0.5 mm.

The main side portion 342 projects from the main total thickness portion 330 in the y direction. In this embodiment, two main side portions 342 are formed. The main side portion 342 has a dimension in the x direction of about 0.18 mm and a dimension in the y direction of about 0.01 mm. Further, in the present embodiment, the main lead 300 has two main side connecting portions 351. The main side connecting portion 351 extends from the main side portion 342 of the main eaves portion 340 and has the same thickness as the main side portion 342. The y-direction end face of the main side connecting portion 351 is exposed from the resin package 800. The main side connecting portion 351 has a dimension in the x direction of about 0.1 mm and a dimension in the y direction of about 0.04 mm.

The main rear portion 343 projects from the main total thickness portion 330 to the side opposite to the main front portion 341. The main rear portion 343 has a dimension in the x direction of about 0.01 mm and a dimension in the y direction of about 0.5 mm. In this embodiment, the main lead 300 has two main rear connecting portions 352. The main rear connecting portion 352 extends from the main rear portion 343 of the main eaves portion 340 and has the same thickness as the main rear portion 343. The x-direction end face of the main rear connecting portion 352 is exposed from the resin package 800. The main rear connecting portion 352 has a dimension in the x direction of about 0.04 mm and a dimension in the y direction of about 0.1 mm.

With the above-described configuration, in the present embodiment, all of the main total thickness portions 330 are surrounded by the main eaves portions 340 in the z-direction view. Further, the upper surface of the main total thickness portion 330 and the main eaves portion 340 in the z direction is the die pad portion 310, and the main surface plating layer 311 overlaps all of the main total thickness portion 330 and the main eaves portion 340. Further, as is clearly shown in FIG. 18, about half of the semiconductor element 200 overlaps the main total thickness portion 330 in the z-direction view, and about the other half overlaps the main front portion 341 of the main eaves portion 340. There is. The first surface electrode 211 as a gate electrode overlaps the main total thickness portion 330, and the second surface electrode 212 as a source electrode overlaps the main front portion 341 of the main eaves portion 340.

As shown in FIG. 21, in the semiconductor element 200, the back surface electrode 220 is bonded to the die pad portion 310 (main surface plating layer 311). Specifically, the back surface electrode 220 as a single metal layer is directly bonded to the die pad portion 310 (main surface plating layer 311) by, for example, a thermal pressure bonding method. In this thermal crimping, no vibration is applied, only heat and pressure are applied.

The first sub lead 400 is arranged so as to be separated from the main lead 300 in the x direction, and the first wire bonding portion 410, the first sub back surface terminal portion 420, the first sub total thickness portion 430, and the first sub. It has a canopy portion 440. The first sub-lead 400 is formed by, for example, patterning a metal plate made of Cu by etching or the like.

The first wire bonding portion 410 faces upward in the z direction and is a portion to which the first wire 600 is bonded. In the present embodiment, the first wire bonding portion 410 has a rectangular shape having a dimension in the x direction of about 0.2 mm and a dimension in the y direction of about 0.2 mm. Further, in the present embodiment, the first sub-surface plating layer 411 is formed on the first wire bonding portion 410. The first sub-surface plating layer 411 is formed over the entire area of the first wire bonding portion 410. The first sub-surface plating layer 411 is made of, for example, Ag having a thickness of about 2 μm. In FIG. 16, for convenience of understanding, the first sub-surface plating layer 411 is halftone.

The first sub-back surface terminal portion 420 faces downward in the z direction on the side opposite to the first wire bonding portion 410, and is used for surface mounting the semiconductor device 101. The first sub-back surface terminal portion 420 has a rectangular shape having a dimension in the x direction of about 0.18 mm and a dimension in the y direction of about 0.13 mm. All of the first sub-back surface terminal portion 420 overlaps the first wire bonding portion 410 in the z-direction view, and is included in the first wire bonding portion 410. In the present embodiment, the first sub-lead 400 is formed with the first sub-back surface plating layer 421. The first sub-back surface plating layer 421 is laminated on a portion of the first sub-lead 400 for forming the first sub-back surface terminal portion 420, for example, Ni, Sn having a thickness of about 0.06 mm or these. It consists of an alloy. In the present embodiment, for convenience, the lower surface of the first sub-back surface plating layer 421 in the z direction is defined as the first sub-back surface terminal portion 420. For example, in a configuration without the first sub-back surface plating layer 421, the above-mentioned Cu The first sub-back surface terminal portion 420 may be configured by the portion made of.

The first sub-total thickness portion 430 is a portion extending from the first wire bonding portion 410 to the first sub-back surface terminal portion 420 in the z direction. In the present embodiment, the first sub-total thickness portion 430 refers to a portion made of Cu excluding the first sub-back surface plating layer 421, and the thickness thereof is about 0.1 mm. The first sub-total thickness portion 430 has a x-direction dimension of about 0.18 mm and a y-direction dimension of about 0.13 mm, similarly to the first sub-back surface terminal portion 420.

The first sub-eaves portion 440 protrudes from the first wire bonding portion 410 side portion of the first sub-total thickness portion 430 in the x-direction and the y-direction, which are perpendicular to the z-direction. The upper end surface of the first sub-eaves portion 440 in the z direction is flush with the first sub-total thickness portion 430. In the present embodiment, the first sub-eaves portion 440 has a first sub-front portion 441, a first sub-side portion 442, and a first sub-rear portion 443. The thickness of the first sub-eaves portion 440 is, for example, half that of the first sub-total thickness portion 430, and is about 0.05 mm.

The first sub-front portion 441 projects from the first sub-total thickness portion 430 toward the main lead 300 in the x direction. In the present embodiment, the first sub-front portion 441 has a dimension in the x direction of about 0.01 mm and a dimension in the y direction of about 0.2 mm.

The first sub-side portion 442 protrudes from the first sub-total thickness portion 430 in the y direction. In this embodiment, two first sub-side portions 442 are formed. The first sub-side portion 442 located above in the y-direction diagram in FIG. 18 projects toward the second sub-lead 500, and has a x-direction dimension of about 0.2 mm and a y-direction dimension of about 0.06 mm. be. The first sub-side portion 442 located at the lower side in the y-direction diagram has a y-direction x-direction dimension of about 0.2 mm and a y-direction dimension of about 0.01 mm. Further, in the present embodiment, the first sub-lead 400 has a first sub-side connecting portion 451. The first sub-side connection portion 451 extends downward in the y-direction diagram in FIG. 18 from the first sub-side portion 442 of the first sub-eaves portion 440, and has the same thickness as the first sub-side portion 442. ing. The y-direction end face of the first sub-side connecting portion 451 is exposed from the resin package 800. The first sub-side connecting portion 451 has a dimension in the x direction of about 0.1 mm and a dimension in the y direction of about 0.04 mm.

The first sub-rear portion 443 projects from the first sub-total thickness portion 430 to the side opposite to the first sub-front portion 441. The first sub-rear portion 443 has a dimension in the x direction of about 0.01 mm and a dimension in the y direction of about 0.14 mm. In the present embodiment, the first sub-lead 400 has a first sub-rear connecting portion 452. The first sub-rear connecting portion 452 extends from the first sub-rear portion 443 of the first sub-eaves portion 440 and has the same thickness as the first sub-rear portion 443. The x-direction end face of the first sub-rear connecting portion 452 is exposed from the resin package 800. The first sub-rear connecting portion 452 has a dimension in the x direction of about 0.04 mm and a dimension in the y direction of about 0.1 mm.

With the above-described configuration, in the present embodiment, all of the first sub-total thickness portions 430 are surrounded by the first sub-eaves portion 440 in the z-direction view. Further, the upper surface of the first sub-total thickness portion 430 and the first sub-eaves portion 440 in the z direction is the first wire bonding portion 410, and the first sub-surface plating layer 411 is the first sub-total thickness portion 430 and the first sub-total thickness portion 430. It overlaps all of the first sub-eaves 440.

The second sub-lead 500 is arranged at a position alongside the first sub-lead 400 in the y direction so as to be separated from the main lead 300 in the x direction, and the second wire bonding portion 510 and the second sub-back surface terminal portion. It has 520, a second sub-total thickness portion 530, and a second sub-eaves portion 540. The second sub-lead 500 is formed by, for example, performing patterning such as etching on a metal plate made of Cu.

The second wire bonding portion 510 faces upward in the z direction and is a portion to which the second wire 700 is bonded. In the present embodiment, the second wire bonding portion 510 has a rectangular shape having a dimension in the x direction of about 0.2 mm and a dimension in the y direction of about 0.2 mm. Further, in the present embodiment, the second sub-surface plating layer 511 is formed on the second wire bonding portion 510. The second sub-surface plating layer 511 is formed over the entire area of the second wire bonding portion 510. The second sub-surface plating layer 511 is made of Ag having a thickness of, for example, about 2 μm. In FIG. 16, for convenience of understanding, the second sub-surface plating layer 511 is halftone.

The second secondary back surface terminal portion 520 faces downward in the z direction on the side opposite to the second wire bonding portion 510, and is used for surface mounting the semiconductor device 101. The second sub-back surface terminal portion 520 has a rectangular shape having a dimension in the x direction of about 0.18 mm and a dimension in the y direction of about 0.13 mm. All of the second sub-back surface terminal portion 520 overlaps the second wire bonding portion 510 in the z-direction view, and is included in the second wire bonding portion 510. In the present embodiment, the second sub-lead 500 is formed with the second sub-back surface plating layer 521. The second sub-back surface plating layer 521 is laminated on a portion of the second sub-lead 500 for forming the second sub-back surface terminal portion 520, for example, Ni, Sn having a thickness of about 0.06 mm or these. It consists of an alloy. In the present embodiment, for convenience, the lower surface of the second secondary back surface plating layer 521 in the z direction is defined as the second secondary back surface terminal portion 520. For example, in a configuration without the second secondary back surface plating layer 521, the above-mentioned Cu The second sub-back surface terminal portion 520 may be configured by the portion made of.

The second sub-total thickness portion 530 is a portion extending from the second wire bonding portion 510 to the second sub-back surface terminal portion 520 in the z direction. In the present embodiment, the second sub-total thickness portion 530 refers to a portion made of Cu excluding the second sub-back surface plating layer 521, and the thickness thereof is about 0.1 mm. The second sub-total thickness portion 530 has a x-direction dimension of about 0.18 mm and a y-direction dimension of about 0.13 mm, similarly to the second sub-back surface terminal portion 520.

The second sub-eaves portion 540 protrudes from the second wire bonding portion 510 side portion of the second sub-total thickness portion 530 in the x-direction and the y-direction, which are perpendicular to the z-direction. The upper end surface of the second sub-eaves portion 540 in the z direction is flush with the second sub-total thickness portion 530. In the present embodiment, the second sub-eaves portion 540 has a second sub-front portion 541, a second sub-side side portion 542, and a second sub-rear portion 543. The thickness of the second sub-eaves portion 540 is, for example, half that of the second sub-total thickness portion 530, and is about 0.05 mm.

The second sub-front portion 541 projects from the second sub-total thickness portion 530 toward the main lead 300 in the x direction. In the present embodiment, the second sub-front portion 541 has a dimension in the x direction of about 0.01 mm and a dimension in the y direction of about 0.2 mm.

The second sub-side portion 542 projects from the second sub-total thickness portion 530 in the y direction. In this embodiment, two second sub-side portions 542 are formed. The second sub-side portion 542 located at the lower side in the y-direction diagram in FIG. 18 projects toward the first sub-lead 400, and has a x-direction dimension of about 0.2 mm and a y-direction dimension of about 0.06 mm. be. The second sub-side portion 542 located above in the y-direction diagram has a x-direction dimension of about 0.2 mm and a y-direction dimension of about 0.01 mm. Further, in the present embodiment, the second sub-lead 500 has a second sub-side connecting portion 551. The second sub-side connection portion 551 extends upward in the y-direction diagram in FIG. 18 from the second sub-side portion 542 of the second sub-eaves portion 540, and has the same thickness as the second sub-side portion 542. ing. The y-direction end face of the second secondary side connecting portion 551 is exposed from the resin package 800. The second sub-side connecting portion 551 has a dimension in the x direction of about 0.1 mm and a dimension in the y direction of about 0.04 mm.

The second sub-rear portion 543 projects from the second sub-total thickness portion 530 to the side opposite to the second sub-front portion 541. The second sub-rear portion 543 has a dimension in the x direction of about 0.01 mm and a dimension in the y direction of about 0.14 mm. In the present embodiment, the second sub-lead 500 has a second sub-rear connecting portion 552. The second sub-rear connecting portion 552 extends from the second sub-rear portion 543 of the second sub-eaves portion 540 and has the same thickness as the second sub-rear portion 543. The x-direction end face of the second sub-rear connecting portion 552 is exposed from the resin package 800. The second sub-rear connecting portion 552 has a dimension in the x direction of about 0.04 mm and a dimension in the y direction of about 0.1 mm.

With the above-described configuration, in the present embodiment, all of the second sub-total thickness portion 530 is surrounded by the second sub-eaves portion 540 in the z-direction view. Further, the upper surface of the second sub-total thickness portion 530 and the second sub-eaves portion 540 in the z direction is the second wire bonding portion 510, and the second sub-surface plating layer 511 is the second sub-total thickness portion 530 and the second sub-total thickness portion 530. It overlaps all of the second sub-eaves 540.

The first wire 600 is bonded to the first surface electrode 211 of the semiconductor element 200 and the first wire bonding portion 410 of the first sublead 400, and has a first bonding portion 610 and a second bonding portion 620. The first wire 600 is made of Au having a diameter of about 20 μm.

The first bonding portion 610 is bonded to the first wire bonding portion 410 of the first secondary lead 400, and has a coronal lump portion. The second bonding portion 620 is bonded to the first surface electrode 211 of the semiconductor element 200 via the first bump 630. The second bonding portion 620 has a tapered shape in which the thickness in the z direction decreases toward the tip. The first bump 630 is a portion similar to the above-mentioned mass portion of the first bonding portion 610. In the present embodiment, the volume of the first bump 630 is slightly smaller than that of the mass portion of the first bonding portion 610.

The second wire 700 is bonded to the second surface electrode 212 of the semiconductor element 200 and the second wire bonding portion 510 of the second sublead 500, and has a first bonding portion 710 and a second bonding portion 720. The second wire 700 is made of Au having a diameter of about 20 μm.

The first bonding portion 710 is bonded to the second wire bonding portion 510 of the second secondary lead 500, and has a coronal lump portion. The second bonding portion 720 is bonded to the second surface electrode 212 of the semiconductor element 200 via the second bump 730. The second bonding portion 720 has a tapered shape in which the thickness in the z direction decreases toward the tip. The second bump 730 is a portion similar to the above-mentioned mass portion of the first bonding portion 710. In the present embodiment, the volume of the second bump 730 is slightly smaller than that of the lump portion of the first bonding portion 710.

The resin package 800 covers the semiconductor element 200 and a part of each of the main lead 300, the first sub-lead 400, and the second sub-lead 500, and is made of, for example, a black epoxy resin. Further, in the resin package 800, all of the main back surface terminal portion 320 of the main lead 300, the first sub back surface terminal portion 420 of the first sub lead 400, and the second sub back surface terminal portion 520 of the second sub lead 500 are in the z direction. It is exposed to the lower side. Further, in the present embodiment, the distance between the upper end of the first wire 600 and the second wire 700 in the z direction and the upper end of the resin package 800 in the z direction is about 50 μm.

Next, an example of the manufacturing method of the semiconductor device 101 will be described below with reference to FIGS. 26 to 33.

In FIGS. 26 to 32, the step of bonding the first wire 600 will be mainly described, but the second wire 700 is also bonded by the same step. First, as shown in FIG. 26, the semiconductor element 200 is bonded to the main lead 300. At this time, if a lead frame in which a plurality of main leads 300, first sub-leads 400, and second sub-leads 500 are connected is used, the manufacturing efficiency can be improved. A capillary Cp is prepared, and the wire 601 is exposed from the tip thereof. The wire 601 is made of Au having a diameter of about 20 μm. Then, a ball 602 is formed at the tip of the wire 601 by generating a spark immediately above the first surface electrode 211 of the semiconductor element 200.

Next, as shown in FIG. 27, the ball 602 is joined to the first surface electrode 211 of the semiconductor element 200 by lowering the capillary Cp. Then, the capillary Cp is raised while the wire 601 is fixed to the capillary Cp. As a result, as shown in FIG. 28, the first bump 630 is formed on the first surface electrode 211.

Next, as shown in FIG. 29, the ball 602 is formed again at the tip of the wire 601 by generating a spark directly above the first wire bonding portion 410 of the first sub-lead 400. Next, as shown in FIG. 30, the ball 602 is bonded to the first wire bonding portion 410 of the first secondary lead 400 by lowering the capillary Cp.

Next, the capillary Cp is moved as shown in FIG. 31 without fixing the wire 601 to the capillary Cp. As a result, the first bonding portion 610 is first formed. Further, the tip of the capillary Cp is pressed against the first bump 630. At this time, the wire 601 is sandwiched between the capillary Cp and the first bump 630. Further, for example, heat and vibration may be applied via a support base (not shown) that holds the main lead 300. Then, the capillary Cp is separated from the semiconductor element 200 in a state where the wire 601 is fixed to the capillary Cp. As a result, the second bonding portion 620 is formed. FIG. 32 is an enlarged image of the second bonding portion 620 and the first bump 630 taken from above in the z direction. As is clearly shown in the figure, the second bonding portion 620 having a slightly widened shape is bonded to the first bump 630 having a circular shape in a plan view.

After that, the bonding step of the second wire 700 is performed together with the bonding step of the first wire 600. Further, for example, a black epoxy resin is used so as to cover the semiconductor element 200, a part of each of the main lead 300, the first sub-lead 400, and the second sub-lead 500, and the first wire 600 and the second wire 700. A plate-shaped resin member is formed. FIG. 33 shows the lead frame, the semiconductor element 200, the first wire 600, and the second wire 700 described above, and these are covered with the resin member (not shown). Then, the semiconductor device 101 shown in FIGS. 16 to 24 can be obtained by collectively cutting the resin member and the lead frame along the cutting line CL in the drawing.

Next, the operation of the semiconductor device 101 will be described.

According to the present embodiment, the die pad portion 310 and the semiconductor element 200 overlap both the main total thickness portion 330 and the main eaves portion 340 in the z-direction view. The main eaves portion 340 exerts a function of increasing the bonding strength between the main lead 300 and the resin package 800. While improving the bonding strength, it is possible to prevent the main lead 300 from excessively protruding from the semiconductor element 200. This contributes to reducing the z-direction visual dimension of the semiconductor device 101. Further, it is advantageous to reduce the z-direction visual dimension of the semiconductor device 101 that at least one of the first surface electrode 211 and the second surface electrode 212 overlaps the main eaves portion 340. Then, the second bonding portion 620 of the first wire 600 is bonded to the first surface electrode 211 via the first bump 630, and the second bonding portion 720 of the second wire 700 is bonded to the second surface electrode 212 via the second bump 730. The height of the first wire 600 and the second wire 700 in the z direction can be reduced by adopting the configuration joined to. This contributes to lowering the height of the semiconductor device 101 in the z direction. Therefore, according to the present embodiment, the semiconductor device 101 can be miniaturized.

The length of the first wire 600 is due to the fact that the first surface electrode 211 as the gate electrode is farther from the first sublead 400 and the second sublead 500 than the second surface electrode 212 as the source electrode. Can be longer than the second wire 700. The first wire 600 having a longer length tends to increase the bonding strength particularly in the second bonding portion 620. Generally, the first surface electrode 211 as a gate electrode is formed on a relatively smooth surface of the semiconductor layer 231 via an insulating layer (not shown). Such a first surface electrode 211 is relatively difficult to improve the bonding strength of wire bonding. On the other hand, the second surface electrode 212 as the source electrode is often connected to a metal portion filled in a plurality of trenches (pits) formed in the semiconductor layer 231. With such a configuration, the second surface electrode 212 can easily improve the bonding strength of wire bonding. Therefore, joining the first wire 600, which tends to increase the bonding strength, to the first surface electrode 211 as the gate electrode, which is relatively concerned about insufficient bonding strength, is advantageous for avoiding problems such as wire peeling. ..

As shown in FIGS. 27 and 31, when the first surface electrode 211 overlaps with the main total thickness portion 330 in the z-direction view, the first surface electrode 211 as a gate electrode is relatively concerned about insufficient bonding strength. On the other hand, the capillary Cp can be pressed more reliably. On the other hand, by arranging the second surface electrode 212 as a source electrode whose bonding strength is relatively easy to improve at a position overlapping the main eaves portion 340 in the z-direction view, the z-direction view dimension of the semiconductor device 101 is reduced. be able to.

Since the main eaves portion 340 has the main front portion 341, the bonding strength between the main lead 300 and the resin package 800 can be increased. Further, while the semiconductor element 200 and the first sub-lead 400 and the second sub-lead 500 are brought close to each other, the main back surface terminal portion 320, the first sub back surface terminal portion 420, and the second sub back surface terminal portion 520 are brought close to each other unreasonably. Can be avoided.

Since the main eaves portion 340 has the main side portion 342 and the main rear portion 343, the bonding strength between the main lead 300 and the resin package 800 can be increased. The configuration in which all of the main total thickness portions 330 are surrounded by the main eaves portions 340 is suitable for increasing the bonding strength between the main lead 300 and the resin package 800.

The main side connecting portion 351 and the main rear connecting portion 352 appropriately hold the main lead 300 in the manufacturing process of the semiconductor device 101. The y-direction end face of the main side connecting portion 351 and the x-direction end face of the main rear connecting portion 352 are exposed from the resin package 800 but are separated from the main back surface terminal portion 320. Therefore, there is little possibility that the solder for surface-mounting the semiconductor device 101 accidentally spreads on the y-direction end face of the main side connecting portion 351 and the x-direction end face of the main rear connecting portion 352.

Since the main surface plating layer 311 is formed on the die pad portion 310, the bonding strength between the back electrode 220 of the semiconductor element 200 and the die pad portion 310 can be increased. By overlapping the main surface plating layer 311 on all of the main eaves portion 340, the area that can be used as the die pad portion 310 can be expanded.

Since the first sub-lead 400 has the first sub-eaves portion 440, the bonding strength between the first sub-lead 400 and the resin package 800 can be increased. Since the first sub-eaves portion 440 has the first sub-front portion 441, the distance between the first sub-back surface terminal portion 420 and the main back surface terminal portion 320 is unreasonably increased while increasing the bonding strength with the resin package 800. It is possible to avoid getting close.

Since the first sub-eaves portion 440 has the first sub-side portion 442 and the first sub-rear portion 443, the bonding strength between the first sub-lead 400 and the resin package 800 can be increased. The configuration in which all of the first sub-total thickness portion 430 is surrounded by the first sub-eaves portion 440 is suitable for increasing the bonding strength between the first sub lead 400 and the resin package 800. Since the first sub-side portion 442 on the second sub-lead 500 side is relatively large, the joint strength is improved, and the first sub-back surface terminal portion 420 and the second sub-back surface terminal portion 520 are unreasonable. It is possible to avoid getting close to.

The first sub-side connecting portion 451 and the first sub-rear connecting portion 452 appropriately hold the first sub-lead 400 in the manufacturing process of the semiconductor device 101. The y-direction end face of the first sub-side connecting portion 451 and the x-direction end face of the first sub-rear connecting portion 452 are exposed from the resin package 800 but separated from the first sub-back surface terminal portion 420. Therefore, there is little possibility that the solder for surface-mounting the semiconductor device 101 accidentally spreads on the y-direction end face of the first sub-side side connecting portion 451 and the x-direction end face of the first sub-rear connecting portion 452.

Since the first sub-surface plating layer 411 is formed on the first wire bonding portion 410, the bonding strength between the first wire 600 and the first wire bonding portion 410 can be increased.

Since the second sub-lead 500 has the second sub-eaves portion 540, the bonding strength between the second sub-lead 500 and the resin package 800 can be increased. Since the second sub-eaves portion 540 has the second sub-front portion 541, the distance between the second sub-back surface terminal portion 520 and the main back surface terminal portion 320 is unreasonably increased while increasing the bonding strength with the resin package 800. It is possible to avoid getting close.

Since the second sub-eaves portion 540 has the second sub-side portion 542 and the second sub-rear portion 543, the bonding strength between the second sub-lead 500 and the resin package 800 can be increased. The configuration in which all of the second sub-total thickness portion 530 is surrounded by the second sub-eaves portion 540 is suitable for increasing the bonding strength between the second sub lead 500 and the resin package 800. Since the second sub-side side portion 542 on the first sub-lead 400 side is relatively large, the joint strength is improved, and the second sub-back surface terminal portion 520 and the first sub-back surface terminal portion 420 are unreasonable. It is possible to avoid getting close to.

The second sub-side connecting portion 551 and the second sub-rear connecting portion 552 appropriately hold the second sub-lead 500 in the manufacturing process of the semiconductor device 101. The y-direction end face of the second sub-side connecting portion 551 and the x-direction end face of the second sub-rear connecting portion 552 are exposed from the resin package 800 but separated from the second sub-back surface terminal portion 520. Therefore, there is little possibility that the solder for surface-mounting the semiconductor device 101 accidentally spreads on the y-direction end face of the second sub-side side connecting portion 551 and the x-direction end face of the second sub-rear connecting portion 552.

Since the second sub-surface plating layer 511 is formed on the second wire bonding portion 510, the bonding strength between the second wire 700 and the second wire bonding portion 510 can be increased.

In the bonding between the semiconductor element 200 and the die pad portion 310 of the main lead 300, the back surface electrode 220 made of a single metal layer is directly bonded to the die pad portion 310, and no vibration is applied during the bonding. With such a configuration, it is not necessary to set a margin region in consideration of vibration in the region of the main lead 300 located around the semiconductor element 200. This is advantageous for miniaturization of the semiconductor device 101.

FIG. 34 is an X-ray image of the semiconductor device 101. As is well shown in the figure, when the main lead 300, the first sub-lead 400 and the second sub-lead 500 are patterned by etching, the boundary between the main total thickness portion 330 and the main eaves portion 340 is shown in FIG. -The clear corners shown in FIG. 24 are not formed, but are curved surfaces. Similarly, the boundary between the first sub-total thickness portion 440 and the first sub-eaves portion 440 in the first sub-lead 400, or the second sub-total thickness portion 540 and the second sub-eaves portion 540 in the second sub-lead 500. The boundary is also a curved surface. This is because the above-mentioned curved surface is inevitably generated in the etching process when the semiconductor device 101 has the above-mentioned extremely small configuration even if the design is intended for the forms shown in FIGS. 16 to 24. ..

FIG. 35 shows a semiconductor device based on the fourth embodiment of the present invention. In the figure, the same or similar elements as those in the above embodiment are designated by the same reference numerals as those in the above embodiment.

In the present embodiment, the first surface electrode 211 overlaps both the main total thickness portion 330 and the main eaves portion 340 in the z-direction view. Then, the first bump 630 and the second bonding portion 620 of the first wire 600 overlap both the main total thickness portion 330 and the main eaves portion 340 in the z-direction view. In the figure, a broken line extending in the y direction overlaps the first bump 630 and the second bonding portion 620 of the first wire 600. This broken line is the boundary between the main total thickness portion 330 and the main eaves portion 340 in the z-direction view. The semiconductor device 102 can also be miniaturized according to such an embodiment.

The semiconductor device according to the present invention is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present invention can be freely redesigned.

The semiconductor element referred to in the present invention is not limited to a transistor, and various semiconductor elements having a first surface electrode and a second surface electrode can be used.

101 Semiconductor device 102 Semiconductor device 200 Semiconductor element 201 Front surface 202 Back surface 211 First surface electrode 212 Second surface electrode 220 Back surface electrode 231 Semiconductor layer 232 Co-crystal layer 300 Main lead 310 Main lead Main surface 311 Main surface Plating layer 320 Main lead back surface 330 Main total thickness 340 Main eaves 341 Main front 342 Main side 343 Main rear 351 Main side connection 352 Main rear connection 400 First secondary lead 410 First secondary lead Main surface 411 First secondary surface Plating layer 420 1st sub-lead back surface 430 1st sub-total thickness part 440 1st deputy eaves part 441 1st sub-front part 442 1st sub-inner part 460 1st sub-extending part 461 1st sub-rear part 462 1st Sub-side 481 1st sub-lead end face 482 1st sub-lead side surface 500 2nd sub-lead 510 2nd sub-lead main surface 511 2nd sub-surface plating layer 520 2nd sub-lead back surface 530 2nd sub-total thickness part 540th 2 Deputy eaves 541 2nd deputy front part 542 2nd deputy inner part 560 2nd deputy extension part 561 2nd deputy rear part 562 2nd deputy side part 581 2nd sub lead end face 582 2nd sub lead side surface 600 First wire 610 First bonding part 620 Second bonding part 630 First bump 700 Second wire 710 First bonding part 720 Second bonding part 730 Second bump 800 Resin package 801 Resin main surface 802 Resin back surface 803 First resin side surface 804 Second resin Side surface 805 First resin end face 806 Second resin end face 901 Tape Ct1 line Ct2 line x direction y direction z Thickness direction 101,102 Semiconductor device 200 Semiconductor element 201 Surface 202 Back surface 211 First surface electrode 212 Second surface electrode 213 Electrode layer 214 Removal area 216 Active area 217 MOSFET
218 Unit cell 220 Back electrode (metal single layer)
231 Semiconductor layer 232 Co-crystal layer 300 Main lead 310 Die pad part 311 Main surface plating layer 320 Main back surface terminal part 321 Main back surface plating layer 330 Main total thickness part 340 Main eaves part 341 Main front part 342 Main side part 343 Main rear part 351 Main side connecting part 352 Main rear connecting part 400 1st sub lead 410 1st wire bonding part 411 1st sub front surface plating layer 420 1st sub back surface terminal part 421 1st sub back surface plating layer 430 1st sub total thickness part 440 1st sub-plating part 441 1st sub-front part 442 1st sub-side side part 443 1st sub-rear part 451 1st sub-side connection part 452 1st sub-rear connection part 500 2nd sub-lead 510 2nd wire bonding Part 511 Second sub front surface plating layer 520 Second sub back surface terminal part 521 Second sub back surface plating layer 530 Second sub total thickness part 540 Second sub eaves part 541 Second sub front part 542 Second sub side side part 543 Second 2 Sub-rear part 551 Second sub-side connection part 552 Second sub-rear connection part 600 First wire 610 First bonding part 620 Second bonding part 630 First bump 700 Second wire 710 First bonding part 720 Second bonding part 730 Second bonding part 730 Second Bump 800 Resin Package Cp Capillary 601 Wire

Claims (7)

With semiconductor elements
A main lead on which the semiconductor element is arranged and conducting with the semiconductor element,
A first sublead that is separated from the main lead and conducts with the semiconductor element,
A second sub-lead that is separated from the main lead and the first sub-lead and conducts to the semiconductor element,
A resin package that covers the semiconductor element, the main lead, the first sublead, and the second sublead and has a rectangular shape in the thickness direction of the semiconductor element is provided.
The resin package has a first surface, a second surface orthogonal to the closed and and the first surface perpendicular direction normal to the thickness direction, the thickness direction having a normal direction parallel to the thickness direction A third surface having a normal direction perpendicular to the second surface and facing the opposite side to the second surface, having a normal direction perpendicular to the thickness direction, and orthogonal to the first surface to the third surface. It has a fourth surface and a fifth surface that has a normal direction perpendicular to the thickness direction and faces the opposite side of the fourth surface.
The main lead, the first sub-lead, and the second sub-lead are exposed from the first surface of the resin package.
The main lead has a main lead main surface and a main lead back surface facing opposite sides of each other.
The semiconductor element is arranged on the main lead surface.
The back surface of the main lead is exposed from the first surface of the resin package.
The first sub-lead has a first sub-lead main surface and a first sub-lead back surface facing opposite sides, and the first sub-lead back surface is exposed from the first surface of the resin package.
The second sub-lead has a second sub-lead main surface and a second sub-lead back surface facing opposite sides, and the second sub-lead back surface is exposed from the first surface of the resin package.
As the conductor portion conducting to the semiconductor element, only the back surface of the main lead, the back surface of the first sub lead, and the back surface of the second sub lead are exposed from the first surface.
The semiconductor element is configured as a transistor having a gate electrode, a source electrode, and a drain electrode.
The drain electrode conducts with the main lead, the gate electrode conducts with the first sub lead, and the source electrode conducts with the second sub lead.
The main lead has a first part exposed from the second surface of the resin package, a third part exposed from the third surface, and a fifth part exposed from the fourth surface .
The first sublead has a second portion exposed from the second surface of the resin package.
The second secondary lead has a fourth portion exposed from the third surface of the resin package.
The maximum dimension of the second part in the thickness direction is larger than the maximum dimension of the first part in the thickness direction, and on the second surface, the first part is separated from the first surface. The second part reaches the first surface, and a part of the second surface is located between the first part and the first surface.
The maximum dimension of the fourth part in the thickness direction is larger than the maximum dimension of the third part in the thickness direction, and on the third surface, the third part is separated from the first surface. The fourth part reaches the first surface, and a part of the third surface is located between the third part and the first surface.
The maximum dimension of the fifth part in the thickness direction is smaller than the maximum dimension of the second part and the fourth part in the thickness direction, and the fifth part is the first surface of the fourth surface. Separated, a part of the fourth surface is located between the fifth part and the first surface.
The main lead is a semiconductor device that is not exposed from the fifth surface. The semiconductor device according to claim 1, wherein the first part is located between one end and the other end of the back surface of the main lead in a direction in which the main lead and the first sub lead are separated from each other. The first part and the second part are rectangular and have a rectangular shape.
The semiconductor device according to claim 1 or 2 , wherein the dimensions of the first part and the second part in the thickness direction are different from each other. The semiconductor according to any one of claims 1 to 3, wherein the third part is located between one end and the other end of the back surface of the main lead in a direction in which the main lead and the second sub lead are separated from each other. Device. The third part and the fourth part are rectangular and have a rectangular shape.
The semiconductor device according to any one of claims 1 to 4 , wherein the dimensions of the third part and the fourth part in the thickness direction are different from each other. The semiconductor device according to any one of claims 1 to 5 , further comprising a first wire that is directly connected to the semiconductor element and conducts the semiconductor element and the first sublead. The semiconductor device according to any one of claims 1 to 6 , further comprising a second wire that is directly connected to the semiconductor element and conducts the semiconductor element and the second sublead.

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