JP6929624B2 - Display driver and semiconductor device - Google Patents

Description

The present invention relates to a display driver that drives a display device in response to a video signal and a semiconductor device in which the display driver is formed.

For example, a liquid crystal display device that displays an image according to a video signal is provided with a liquid crystal display panel as a display device and drivers for driving a plurality of source lines of the display panel. The driver includes a plurality of decoders that individually convert a plurality of gradation data pieces for each pixel based on a video signal into analog gradation voltages, and amplifies the gradation voltage with a gain of 1 and supplies it to the source line. A plurality of differential amplifier circuits (hereinafter referred to as amplifiers) are included (see, for example, Patent Document 1). Further, such a driver is provided with a bias circuit that generates a bias signal for setting an operating current flowing inside each amplifier.

Japanese Unexamined Patent Publication No. 2004-301946

By the way, when the voltage value of the gradation voltage input to each amplifier transitions from a low voltage state to a high voltage state suddenly, noise is generated that the voltage value of the bias signal is temporarily increased due to this.

Therefore, when a large number of amplifiers are simultaneously supplied with a gradation voltage that transitions from a low voltage to a high voltage state, the bias circuit side cannot suppress the increase in the voltage value of the bias signal, and the output voltage of each amplifier becomes high. The problem of distortion has arisen.

Therefore, the present invention suppresses the influence of noise generated in the bias signal and suppresses waveform distortion even when a plurality of amplifiers are simultaneously supplied with a gradation voltage that transitions from a low voltage state to a high voltage state. It is an object of the present invention to provide a display driver and a semiconductor device capable of generating a suppressed display drive voltage.

Further, the display driver according to the present invention individually amplifies each of the gradation voltages having voltage values corresponding to the brightness level of each pixel, and applies a plurality of display drive voltages obtained by individually amplifying the plurality of display drive voltages to a plurality of data lines of the display device. A display driver including a plurality of supplied amplifiers, which has a bias voltage generating unit for generating first and second bias voltages, and each of the plurality of amplifiers receives a supply of a power supply voltage and said the first. A first bias transistor that generates a current having a magnitude corresponding to the bias voltage of the above, and a second bias transistor that outputs the current generated by the first bias transistor as an operating current according to the second bias voltage. The operating current is divided into first and second currents based on the ratio of the voltage values of the bias transistor, the first and second lines, and the gradation voltage and the display drive voltage, and the first and second currents are divided. The bias voltage generation unit includes a first transistor connected to a diode and an output unit that generates the display drive voltage based on the voltage of the first line. A first bias voltage generation circuit including a first constant current source connected to the drain end of the first transistor and generating a voltage at the drain end of the first transistor as the first bias voltage. , A second transistor that receives a second constant current source and a bias setting voltage that sets the voltage value of the second bias voltage at the gate end, and receives a current sent from the second constant current source at the source end. It is characterized by having a second bias voltage generation circuit that generates the voltage at the source end of the second transistor as the second bias voltage.

Further, in the semiconductor device according to the present invention, a plurality of display drive voltages obtained by individually amplifying each of the gradation voltages having a voltage value corresponding to the brightness level of each pixel are applied to a plurality of data lines of the display device. A semiconductor device in which a display driver including a plurality of supplied amplifiers is formed, the display driver has a bias voltage generator for generating first and second bias voltages, and each of the plurality of amplifiers has a bias voltage generator. Is a first bias transistor that receives a supply of a power supply voltage and generates a current having a magnitude corresponding to the first bias voltage, and a current generated by the first bias transistor is used as the second bias voltage. The operating current is calculated by the ratio of the voltage values of the second bias transistor, the first and second lines, and the gradation voltage and the display drive voltage, which are output as the operating current. The bias voltage generation includes a differential pair divided into the currents of 1 and sent to the first and second lines, respectively, and an output unit that generates the display drive voltage based on the voltage of the first line. The unit includes a first transistor connected by a diode and a first constant current source connected to the drain end of the first transistor, and biases the voltage at the drain end of the first transistor to the first bias. The first bias voltage generation circuit generated as a voltage, the second constant current source, and the bias setting voltage for setting the voltage value of the second bias voltage at the gate end are received, and the second constant is received at the source end. It is characterized by having a second bias voltage generation circuit including a second transistor that receives a current sent from a current source and generating a voltage at the source end of the second transistor as the second bias voltage. There is.

In the display driver according to the present invention, the bias voltage is used to supply an operating current having a magnitude corresponding to the bias voltage to the differential pair included in the amplifier that supplies the display drive voltage obtained by amplifying the gradation voltage to the display device. The source follower circuit is adopted as the bias voltage generation part which generates. As a result, even if noise occurs in the bias voltage due to the transition from the high voltage value (or low voltage value) state to the low voltage value (or high voltage value) state at the same time for a plurality of gradation voltages. Since the amount of noise is suppressed by the source follower circuit, it is possible to generate a display drive voltage in which distortion is suppressed.

It is a block diagram which shows the structure of the display device 10 including the display driver which concerns on this invention. It is a block diagram which shows the internal structure of a data driver 13. It is a block diagram which shows an example of the internal structure of an output amplifier part 133. FIG. 5 is a waveform diagram showing a waveform of a bias voltage VBH2 when gradation voltages B _{1 to} B _{n simultaneously transition from a low voltage value state to a high voltage value state.} It is a circuit diagram which shows the other structure of the 2nd vise voltage generation part. It is a block diagram which shows another example of the internal structure of an output amplifier part 133.

Hereinafter, examples of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a display device 10 including a display driver according to the present invention. As shown in FIG. 1, the display device 10 includes a drive control unit 11, a scanning driver 12, a data driver 13, and a display device 20 including a liquid crystal display or an organic EL panel.

_{The display device 20 has m horizontal scanning lines S 1 to} S _m each extending in the horizontal direction of the 2D screen (m is a natural number of 2 or more) and n each extending in the vertical direction of the 2D screen. _{The number of data lines D 1 to} D _n (n is a natural number of 2 or more) is formed. Further, a display cell PX that bears pixels is formed in the region of each intersection of the horizontal scanning line and the data line, that is, the region surrounded by the broken line in FIG.

Based on the input video signal VS, the drive control unit 11 generates a series of pixel data PDs that represent the brightness level of the pixels for each pixel, for example, as 6-bit data, and the video data signal VD including the series of the pixel data PDs. Is supplied to the data driver 13. Further, the drive control unit 11 detects a horizontal synchronization signal from the input video signal VS and supplies the horizontal synchronization signal to the scanning driver 12.

Scan driver 12 in synchronism with the horizontal synchronizing signal supplied from the drive control unit 11 generates a horizontal scanning pulse sequentially to this scan line S ₁ to S _m, each of the display devices 20, alternatively applied do.

FIG. 2 is a block diagram showing an internal configuration of the data driver 13 as a display driver. The data driver 13 is formed by being divided into a single semiconductor chip or a plurality of semiconductor chips.

As shown in FIG. 2, the data driver 13 includes a data latch unit 131, a gradation voltage conversion unit 132, and an output amplifier unit 133.

The data latch unit 131 sequentially captures a series of pixel data PDs included in the video data signal VD supplied from the drive control unit 11. At this time, the data latch unit 131, every time one horizontal scanning line of the pixel data PD (n number of) incorporation is made, the gradation voltage converting the n pixel data PD as pixel data Q ₁ to Q _n It is supplied to the unit 132.

The gradation voltage conversion unit 132 uses the pixel data Q _{1 to} Q _{n supplied from the data latch unit 131 to have a gradation voltage B 1 to} B _n having a voltage value corresponding to the brightness level represented by each pixel data Q. Is converted to and supplied to the output amplifier unit 133.

The output amplifier unit 133 _{supplies the gradation voltages B 1 to} B _n individually amplified by the gain 1 to _{the data lines D 1 to} D _n of the display device 20 as display _{drive voltages G 1 to} G _n.

FIG. 3 is a block diagram showing an internal configuration of the output amplifier unit 133. As shown in FIG. 3, the output amplifier unit 133 includes a bias voltage generation unit BSC and amplifiers AM _{1 to} AM _n .

The bias voltage generation unit BSC includes a first bias generation circuit including a p-channel MOS (metal oxide semiconductor) type transistor P1 and a constant current source MG1, and a second bias generation circuit including a p-channel MOS type transistor P2 and a constant current source MG2. It has a bias generation circuit of.

A power supply voltage VDD is applied to the source end of the transistor P1 of the first bias generation circuit, and its gate end and drain end are connected to each other. The gate end and drain end of the transistor P1 are connected to one end of the constant current source MG1. That is, the transistor P1 is diode-connected to the constant current source MG1. A ground potential VSS is applied to the other end of the constant current source MG1. The constant current source MG1 allows a predetermined constant current to flow from the drain end of the transistor P1 toward the supply line (not shown) of the ground potential VSS. As a result, a voltage having a constant voltage value is generated at the gate end and the drain end of the transistor P1. The first bias generation circuit supplies a voltage having a constant voltage value as a bias voltage VBH1 to each of the _{amplifiers AM 1 to} AM _n.

The constant current source MG2 of the second bias generation circuit receives the supply of the power supply voltage VDD to generate a predetermined constant current, and supplies this to the source end of the transistor P2. A ground potential VSS is applied to the drain end of the transistor P2, and a bias setting voltage BST is applied to the gate end thereof. As a result, a voltage having a voltage value corresponding to the bias setting voltage BST is generated at the source end of the transistor P2.

That is, the second bias generation circuit includes a source follower circuit including the transistor P2 and the constant current source MG2, generates a voltage having a voltage value corresponding to the bias set voltage BST, and uses this as the bias voltage VBH2 for the amplifier AM _1. Supply to each of ~ AM _n.

Amplifiers AM _{1 to} AM _n have the same internal configuration. Therefore, an excerpt of the amplifier AM ₁ below, describes the internal structure of the amplifier AM _{1-Am n} respectively.

As shown in FIG. 3, each of the amplifiers AM _{1 to} AM _n has a differential unit including p-channel MOS type transistors P11 to P14, n-channel MOS type transistors N11 and N12, and a p-channel MOS type transistor P21. And an output unit including an n-channel MOS type transistor N21.

A power supply voltage VDD is applied to the source end of the transistor P11 as the first bias transistor, and a bias voltage VBH1 is supplied to the gate end. The drain end of the transistor P11 is connected to the source end of the transistor P12. With this configuration, the transistor P11 receives the supply of the power supply voltage VDD to generate a current having a magnitude corresponding to the bias voltage VBH1 and supplies this to the source end of the transistor P12.

Further, a bias voltage VBH2 is supplied to the gate end of the transistor P12 as the second bias transistor, and the drain end thereof is connected to the source end of each of the transistors P13 and P14 forming a differential pair. With this configuration, the transistor P12 supplies the current supplied from the transistor P12 as an operating current to the source ends of each of the transistors P13 and P14 according to the bias voltage VBH2.

_{A gradation voltage B 1} is supplied to the gate end of the transistor P13, and the drain end thereof is connected to the drain end of the transistor N11 and the gate end of the transistor N21 via a line L1.

_{The display drive voltage G 1} is supplied to the gate end of the transistor P14 via the output line L0, and the drain end thereof is connected to the drain end of the transistor N12 via the line L2. The drain end and the gate end of the transistor N11 are connected to each other, and the gate end is further connected to the gate end of the transistor N11. A ground potential VSS is applied to the source ends of the transistors N11 and N12.

A power supply voltage VDD is applied to the source end of the transistor P21, and a predetermined fixed voltage VT is applied to the gate end thereof. The drain end of the transistor P21 is connected to the drain end of the transistor N21 via the output line L0. A ground potential VSS is applied to the source end of the transistor N21.

According to the configuration shown in FIG. 3, in the amplifier AV ₁ , the transistors P11 and P12 as the operating current generator supply the operating currents having a magnitude corresponding to the bias voltages VBH1 and VBH2 to the transistors P13 and P14 forming the differential pair. do. In reality, the transistor P11 generates a current that is a source of the operating current, and supplies this to the differential pair (P13, P14) via the transistor P12. The transistor P12 functions as a filter for preventing noise due to steep current fluctuations in the differential pair from leaking into the bias voltage VBH1.

The transistor P13 _{causes a current corresponding to the gradation voltage B 1} to flow through the line L1. The transistor M2 causes a current corresponding to the _{display drive voltage G 1} supplied via the output line L0 to flow through the line L2. That is, the transistors P13 and P14 as the differential pair have the operating current supplied from the bias transistors (P11, P12) first and first by the ratio of the voltage values of _{the gradation voltage B 1} and the display drive voltage G _1. It is divided into two currents, the first current is sent to the line L1 and the second current is sent to the line L2.

With this configuration, the differential unit _{supplies an output voltage drive signal having a level corresponding to the difference value between the gradation voltage B 1} and the display drive voltage G ₁ to the gate end of the transistor N21 of the output unit via the line L1. do. Then, the transistor N21 draws out the output current Io based on the output voltage drive signal from the output line L0. On the other hand, the transistor P21 of the output unit pulls up the voltage of the output line L0 to a voltage value corresponding to the power supply voltage VDD by passing a current corresponding to the fixed voltage VT through the output line L0. Therefore, due to the operation of the transistor N21 described above, the voltage of the output line L0 is lowered by the amount corresponding to the difference value between the _{gradation voltage B 1} and the display drive voltage G _1, and as a result, is equal to the _{gradation voltage B 1.} It reaches the voltage value. As a result, the _{display drive voltage G 1} having a voltage value equal _{to the gradation voltage B 1} is output via the output line L0.

The following is an example in which each of the gradation voltages B _{1 to} B _n simultaneously transitions _{from the low voltage value VL} state to the high voltage value V _H state at the time point t0, as shown in FIG. 4, for example. The operation performed by the bias voltage generation unit BSC and the amplifiers AM _{1 to} AM _n will be described.

First, when each of the gradation voltages B _{1 to} B _n steeply transitions to a _{high voltage value V H} as shown in FIG. 4, the voltage value of the node PTAIL in _{each amplifier AM 1 to} AM _{n is changed accordingly.} To increase. Then, due to the influence of the parasitic capacitance parasitic between the gate and drain of the transistor P12 connected to the node PTAIL, the voltage at the gate end of the transistor P12, that is, the voltage value of the bias voltage VBH2 is temporarily changed as shown in FIG. There is a noise of increasing. At this time, when a large number of gradation voltages, for example, all of the _{gradation voltages B 1 to} B _{n , transition from the low voltage value V L} state to the high voltage value V _H state at the same time, the amount of noise increases and the bias voltage. It takes time for the voltage value of VBH2 to return to the original voltage value. During this period, if the voltage value of the bias voltage VBH2 becomes higher than the predetermined voltage value, the transistor P12 is turned off, a malfunction occurs in which the operating current temporarily stops flowing to the differential pair (P13, P14), and the display drive voltage G Distortion occurs in the waveform of _1.

Therefore, the bias voltage generation unit BSC employs a source follower circuit (P2, MG2) as shown in FIG. 3 as a second bias generation circuit that generates the bias voltage VBH2. In the source follower circuit, the voltage value of the bias voltage VBH2 is if it becomes higher than the voltage value V _R as shown in the the Figure 4 example corresponding to the bias setting voltage BST is following this, the transistor P2 The gate-source voltage is low. Therefore, at this time, the source-drain current of the transistor P2 becomes large, and the voltage value of the bias voltage VBH2 is lowered. As a result, even if the voltage of the node PTAIL temporarily increases, the transistor P12 as a bias transistor can be kept in the ON state.

Therefore, even when the gradation voltages B _{1 to} B _n simultaneously transition from the low voltage value state to the high voltage value state, the above-mentioned malfunction that the differential unit temporarily falls into the stopped state is avoided. The amplifiers AM _{1 to} AM _n can suppress the influence of noise generated in the bias voltage and generate display drive voltages G _{1 to} G _n with suppressed waveform distortion.

In the above embodiment, p-channel MOS type transistors are used as the transistors P11 to P14 of the differential units of the _{amplifiers AM 1 to} AM _{n and the transistors P1 and P2 of the bias voltage generation unit BSC.} A channel MOS type transistor may be adopted. For example, as the second bias generation circuit of the bias voltage generation unit BSC, instead of the source follower circuit including the p-channel MOS type transistor P2 as shown in FIG. 3, the n-channel MOS type as shown in FIG. 5 A source follower circuit including the transistor P2a of the above may be adopted.

In the configuration shown in FIG. 5, the power supply voltage VDD is applied to the drain end of the transistor P2a, and the bias setting voltage BST is supplied to the gate end thereof. The source end of the transistor P2a is connected to one end of the constant current source MG2a. A ground potential VSS is applied to the other end of the constant current source MG2a. The constant current source MG2a flows a predetermined constant current toward the supply line (not shown) of the ground potential VSS. As a result, a voltage having a constant voltage value having a magnitude corresponding to the bias setting voltage BST is generated at the source end of the transistor P2a. The second bias generation circuit supplies the voltage at the source end of the transistor P2a as a bias voltage VBH2 to each of the _{amplifiers AM 1 to} AM _n.

In the second bias generation circuit shown in FIGS. 3 and 5, a source follower circuit including a constant current source (MG2, MG2a) is adopted, but a source including a resistance element instead of the constant current source. A follower circuit may be adopted.

Further, in the above embodiment, as shown in FIG. 4 _{, the bias voltage generation unit BSC determines the case where all the gradation voltages B 1 to} B _n simultaneously transition from the low voltage value state to the high voltage value state. The malfunction avoidance process was explained. However, even when the gradation voltages B _{1 to} B _n simultaneously transition from the high voltage value state to the low voltage value state, the bias voltage generation unit BSC similarly performs the above-mentioned malfunction avoidance processing. .. The voltage value of the bias voltage VBH2 is higher than the voltage value corresponding to the bias set voltage BST regardless of the number of gradation voltages that simultaneously transition from the low voltage value to the high voltage value or from the high voltage value to the low voltage value. When the voltage becomes high or low, the bias voltage generation unit BSC performs the malfunction avoidance process in the same manner.

Further, in the example shown in FIG. 3, although the bias voltage generation unit BSC to be provided by one system with respect to the amplifier AM _{1-Am n,} then partition the amplifier AM _{1-Am n} into a plurality of groups, the group The bias voltage generation unit BSC may be provided individually for each.

For example, as shown in FIG. 6, the amplifiers AM _{1 to} AM _n belong to the first group to which AM _{1 to} AM _k (k is an integer of 2 or more) and the second group to which AM _{k + 1 to} AM _n belong. Divide into groups. Then, the bias voltage generation unit BSCa having the same internal configuration as the bias voltage generation unit BSC shown in FIG. 3 supplies the bias voltages VBH1 and VBH2 _{to the amplifiers AM 1 to} AM _{k belonging to the first group.} Further, the bias voltage generation unit BSCb having the same internal configuration as the bias voltage generation unit BSC shown in FIG. 3 supplies the bias voltages VBH1 and VBH2 _{to the amplifiers AM k + 1 to} AM _{n belonging to the second group.}

Further, in the above embodiment, as the first bias generation circuit of the bias voltage generation unit BSC, a cascode circuit including the transistor P1 and the constant current source MG1 as shown in FIG. 3 or FIG. 5 is adopted, and the second bias is adopted. A cascode circuit including the transistor P2 and the constant current source MG2 is adopted as the generation circuit, but the circuit configuration is not limited to this. That is, if the source follower is adopted as the second bias generation circuit, various circuits can be adopted for the actual circuit of the source follower and the first bias generation circuit.

In short, the bias voltage generation unit (BSC, BSCa, BSCb) and the plurality of amplifiers (AM _{1 to} AM _n ) included in the output amplifier unit 133 may have the following configurations. _{That is, the plurality of amplifiers individually amplify each of the gradation voltages (B 1 to} B _n ) corresponding to the brightness level of each pixel to generate a plurality of display drive voltages (G _{1 to} G _n). At this time, each amplifier determines the operating current by the ratio of the voltage value of the gradation voltage and the display drive voltage to the operating current generating unit (P12) that generates the operating current having a magnitude corresponding to the bias voltage (VBH2). Display drive based on the differential pairs (P13, P14) that are divided into the first and second currents and sent to the first line (L1) and the second line (L2), respectively, and the voltage of the first line. Includes output units (P21, N21) that generate voltage. The bias voltage generator (BSC, BSCa, BSCb) receives a bias setting voltage (BST) at its own gate end and supplies the voltage at its source end as a bias voltage (VBH2) to each of a plurality of amplifiers (P2). ) Is included in the source follower circuit.

According to such a configuration, the bias voltage suddenly changes due to the fact that a plurality of gradation voltages simultaneously transition from a high voltage value (or low voltage value) state to a low voltage value (or high voltage value) state. Even if a large voltage fluctuation occurs, the amount of the voltage fluctuation is suppressed by the source follower circuit. As a result, it is possible to prevent a malfunction of the operating current generating unit that generates an operating current corresponding to the bias voltage, so that it is possible to generate a display drive voltage in which distortion is suppressed.

13 data driver 20 display device 133 output amplifier section AM _{1-Am n} amplifier BSC bias voltage generator MG1, MG2 constant current source P1, P2, P11-P14 transistor

Claims (5)

A display driver that includes multiple amplifiers that supply multiple display drive voltages obtained by individually amplifying each of the gradation voltages having voltage values corresponding to the brightness levels of each pixel to multiple data lines of the display device. There,
It has a bias voltage generator that generates the first and second bias voltages.
Each of the plurality of amplifiers
A first bias transistor that receives the supply of a power supply voltage and generates a current of a magnitude corresponding to the first bias voltage.
A second bias transistor that outputs the current generated by the first bias transistor as an operating current according to the second bias voltage, and
The first and second lines and
A differential pair that divides the operating current into first and second currents based on the ratio of the voltage values of the gradation voltage and the display drive voltage and sends them to the first and second lines, respectively.
Includes an output unit that generates the display drive voltage based on the voltage of the first line.
The bias voltage generator
A diode-connected first transistor and a first constant current source connected to the drain end of the first transistor are included, and the voltage at the drain end of the first transistor is generated as the first bias voltage. The first bias voltage generation circuit and
A second constant current source and a second transistor that receives a bias setting voltage that sets the voltage value of the second bias voltage at the gate end and receives a current sent from the second constant current source at the source end. A display driver comprising, and a second bias voltage generation circuit that generates a voltage at the source end of the second transistor as the second bias voltage. The second transistor, the display driver of claim 1, wherein it is a p-channel MOS transistor which has a ground potential is applied to the drain terminal of itself. The second transistor, the display driver of claim 1, wherein the n-channel MOS transistor which supply voltage to the drain terminal of its own is applied. The display driver according to any one of claims 1 to 3 , wherein the bias voltage generation unit is individually provided for each group in which the plurality of amplifiers are divided into a plurality of groups. A display driver that includes multiple amplifiers that supply a plurality of display drive voltages obtained by individually amplifying each of the gradation voltages having a voltage value corresponding to the brightness level of each pixel to a plurality of data lines of the display device. It is a semiconductor device that is formed,
The display driver has a bias voltage generator that generates first and second bias voltages.
Each of the plurality of amplifiers
A first bias transistor that receives the supply of a power supply voltage and generates a current of a magnitude corresponding to the first bias voltage.
A second bias transistor that outputs the current generated by the first bias transistor as an operating current according to the second bias voltage, and
The first and second lines and
A differential pair that divides the operating current into first and second currents based on the ratio of the voltage values of the gradation voltage and the display drive voltage and sends them to the first and second lines, respectively.
Includes an output unit that generates the display drive voltage based on the voltage of the first line.
The bias voltage generator
A diode-connected first transistor and a first constant current source connected to the drain end of the first transistor are included, and the voltage at the drain end of the first transistor is generated as the first bias voltage. The first bias voltage generation circuit and
A second constant current source and a second transistor that receives a bias setting voltage that sets the voltage value of the second bias voltage at the gate end and receives a current sent from the second constant current source at the source end. A semiconductor device comprising a second bias voltage generation circuit that generates a voltage at the source end of the second transistor as the second bias voltage.

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