JP6929752B2 - Focus detection device and focus detection method - Google Patents

Description

The present invention relates to a focus detection device and a focus detection method.

Conventionally, a focus detection device that performs a phase difference type focus detection using a pixel signal generated by an image sensor is known. Among this type of focus detection device, a focus detection device that enables focus detection even during live view display is also known. For example, the image pickup apparatus proposed in Patent Document 1 generates an image by changing the exposure time of a row required for performing a phase difference type focus detection on an image pickup element with the exposure time of another row. The pixel signal required for this purpose and the pixel signal required for performing the focus detection by the phase difference method are generated.

Japanese Unexamined Patent Publication No. 2015-161906

The image pickup apparatus of Patent Document 1 changes the exposure time for each row of the image pickup element, and is basically configured on the premise of detecting a phase difference in the horizontal direction. Therefore, even if the method of the image pickup apparatus of Patent Document 1 is used as it is, it tends to take time to detect the phase difference in the vertical direction. Therefore, if an attempt is made to detect the phase difference in both the horizontal direction and the vertical direction in order to secure the focus detection performance, there is a possibility that a sufficient time for the live view display cannot be secured during continuous shooting or the like.

The present invention has been made in view of the above circumstances, and provides a focus detection device and a focus detection method capable of securing time for live view display while ensuring the focus detection performance of the phase difference method. The purpose is to do.

In order to achieve the above object, the focus detection device of the first aspect of the present invention photoelectrically converts each light beam passing through different ejection pupil regions of the imaging optical system to one microlens to obtain a pixel. An imaging unit having a pixel unit in which a plurality of light receiving units divided in a first pupil division direction and a second pupil division direction different from the first pupil division direction so as to generate a signal are arranged, and the image pickup unit. Display for display generated based on pixel signal An image processing circuit that performs processing for displaying an image based on a pixel signal, and a focus detection pixel signal for focus detection generated based on the pixel signal. The image pickup unit is controlled so that the focus detection circuit that performs the process for focus detection based on the above and the first operation and the second operation including the generation and reading of the pixel signal are alternately performed. The control circuit includes a control circuit, and the control circuit controls the imaging unit so that the focus detection pixel signal relating to the first pupil division direction is generated in the first operation, and the second operation. In, the imaging unit is controlled so that the display pixel signal and the focus detection pixel signal relating to the second pupil division direction are generated.

In order to achieve the above object, in the focus detection method of the second aspect of the present invention, each light beam passing through different ejection pupil regions of the imaging optical system is photoelectrically converted into a pixel for one microlens. An imaging unit having a pixel unit in which a plurality of light receiving units divided in a first pupil division direction and a second pupil division direction different from the first pupil division direction are arranged so as to generate a signal was used. In the focus detection method, processing for displaying an image based on a display pixel signal for display generated based on the pixel signal, and focus detection generated based on the pixel signal are performed. Focus detection for the purpose The imaging is performed so that the process for focusing detection is performed based on the pixel signal, and the first operation and the second operation including the generation and reading of the pixel signal are alternately performed. Controlling the imaging unit includes controlling the unit, and controlling the imaging unit controls the imaging unit so that the focus detection pixel signal relating to the first pupil division direction is generated in the first operation. This includes controlling the imaging unit so that the display pixel signal and the focus detection pixel signal related to the second pupil division direction are generated in the second operation.

According to the present invention, it is possible to provide a focus detection device and a focus detection method that can secure time for live view display while ensuring the focus detection performance of the phase difference method.

FIG. 1 is a block diagram showing an example of a configuration of an image pickup apparatus including a focus detection apparatus according to an embodiment of the present invention. FIG. 2 is a diagram showing a configuration of an image sensor of an example. FIG. 3 is a diagram showing a detailed configuration of the pixel portion. FIG. 4A is a diagram showing addition of pixel signals when the pixels are treated as left and right opening pixels. FIG. 4B is a diagram showing addition of pixel signals when the pixels are treated as upper and lower opening pixels. FIG. 5A is a flowchart showing the operation of the image pickup apparatus according to the embodiment. FIG. 5B is a flowchart showing the operation of the image pickup apparatus according to the embodiment. FIG. 6 is a timing chart for explaining imaging and readout processing for AF and LV display. FIG. 7 is a diagram showing an example of setting pixel addition in the first operation. FIG. 8 is a diagram showing pixel data stored in the DRAM by the first operation. FIG. 9 is a diagram showing an example of setting pixel addition in the second operation. FIG. 10 is a diagram showing pixel data stored in the DRAM by the second operation. FIG. 11 is a flowchart showing the operation of the image pickup apparatus when the AF mode is the single AF mode. FIG. 12 is a diagram showing a modified example of reading out a pixel signal. FIG. 13 is a diagram showing pixel data stored in the DRAM by reading out FIG. FIG. 14A is a diagram for explaining the modified example 3. FIG. 14B is a diagram for explaining the modified example 3.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an example of a configuration of an image pickup apparatus including a focus detection apparatus according to an embodiment of the present invention. In FIG. 1, the solid line with an arrow indicates the flow of data, and the broken line with an arrow indicates the flow of a control signal.

As shown in FIG. 1, the image pickup apparatus 1 includes an interchangeable lens 100 and a camera body 200. The interchangeable lens 100 is configured so that it can be attached to and detached from the camera body 200. The interchangeable lens 100 and the camera body 200 are connected so that they can communicate with each other when the interchangeable lens 100 is attached to the camera body 200. The image pickup device 1 does not necessarily have to be an interchangeable lens type image pickup device. For example, the image pickup device 1 may be a lens-integrated image pickup device.

The interchangeable lens 100 includes an imaging optical system 102, a driving unit 104, a lens CPU 106, and a lens-side storage unit 108. Here, each block of the interchangeable lens 100 is composed of, for example, hardware. However, it does not necessarily have to be configured by hardware, and a part may be configured by software. Further, each block of the interchangeable lens 100 does not have to be composed of a single hardware or software, and may be composed of a plurality of hardware or software.

The image pickup optical system 102 is an optical system for forming a luminous flux from a subject on the image pickup element 208 of the camera body 200. The imaging optical system 102 includes a focus lens 1021 and an aperture 1022. The focus lens 1021 is configured so that the focal position of the imaging optical system 102 can be adjusted by moving in the optical axis direction.

The diaphragm 1022 is arranged on the optical axis of the focus lens 1021. The aperture 1022 has a variable aperture. The aperture 1022 adjusts the amount of light flux from the subject that passes through the focus lens 1021 and is incident on the image sensor 208. The drive unit 104 drives the focus lens 1021 and the aperture 1022 based on the control signal output from the lens CPU 106. Here, the imaging optical system 102 may be configured as a zoom lens. In this case, the drive unit 104 also performs zoom drive.

The lens CPU 106 is configured to be able to communicate with the CPU 212 of the camera body 200 via the interface (I / F) 110. The lens CPU 106 controls the drive unit 104 according to the control of the CPU 212 of the camera body 200. Further, the lens CPU 106 transmits information such as the aperture value (F value) of the aperture 1022 and the lens information stored in the lens side storage unit 108 to the CPU 212 via the I / F 110. The lens CPU 106 does not necessarily have to be configured as a CPU. That is, the same function as the lens CPU 106 may be realized by an ASIC, FPGA, or the like. Further, the same function as the lens CPU 106 may be realized by software.

The lens-side storage unit 108 stores lens information regarding the interchangeable lens 100. The lens information includes, for example, information on the focal length of the imaging optical system 102 and information on aberrations.

The camera body 200 includes a mechanical shutter 202, a drive unit 204, an operation unit 206, an image sensor 208, an image stabilization circuit 210, a CPU 212, an image processing circuit 214, an image compression expansion unit 216, and a focus detection circuit. It has 218, an exposure control circuit 220, a display unit 222, a bus 224, a DRAM 226, a main body side storage unit 228, and a recording medium 230. Here, each block of the camera body 200 is composed of, for example, hardware. However, it does not necessarily have to be configured by hardware, and a part may be configured by software. Further, each block of the camera body 200 does not have to be composed of a single hardware or software, and may be composed of a plurality of hardware or software.

The mechanical shutter 202 is configured to be openable and closable, and adjusts the incident time of the light flux from the subject on the image sensor 208 (exposure time of the image sensor 208). As the mechanical shutter 202, for example, a focal plane shutter is adopted. The drive unit 204 drives the mechanical shutter 202 based on the control signal from the CPU 212.

The operation unit 206 includes various operation buttons such as a power button, a release button, a moving image button, a play button, and a menu button, and various operation members such as a touch panel. The operation unit 206 detects the operation state of various operation members and outputs a signal indicating the detection result to the CPU 212.

The image sensor 208 is arranged on the optical axis of the image pickup optical system 102, behind the mechanical shutter 202, and at a position where a light flux from the subject is imaged by the image pickup optical system 102. The image pickup device 208 takes an image of the subject and generates a pixel signal related to the subject. The image sensor 208 will be described in detail later.

The camera shake correction circuit 210 moves the image sensor 208 in a direction parallel to the light receiving surface thereof so that the camera shake generated in the camera body 200 is suppressed. By moving the image sensor 208 according to the camera shake, the blurring of the subject image generated in the image data due to the camera shake is suppressed. The camera shake correction circuit may be provided in the interchangeable lens 100. The camera shake correction circuit in this case is configured to move the camera shake correction optical system included in the image pickup optical system 102.

The CPU 212 controls the entire camera main body 200 according to a program stored in the main body side storage unit 228. The CPU 212 controls, for example, imaging by the image sensor 208. Further, the CPU 212 outputs a control signal for driving the focus lens 1021 to the lens CPU 106 according to the focus state of the focus lens 1021 detected by the focus detection circuit 218. Further, the CPU 212 outputs the exposure set value calculated by the exposure control circuit 220 to the lens CPU 106 and the image sensor 208. Here, the CPU 212 does not necessarily have to be configured as a CPU. That is, the same function as the CPU 212 may be realized by an ASIC, FPGA, or the like. Further, the same function as the CPU 212 may be realized by software.

The image processing circuit 214 performs various image processing on the pixel data. For example, when shooting a still image, the image processing circuit 214 performs image processing for recording a still image to generate still image data. Similarly, the image processing circuit 214 performs image processing for moving image recording to generate moving image data at the time of moving image shooting. Further, the image processing circuit 214 performs display image processing to generate display image data at the time of live view display.

When recording the image data, the image compression expansion unit 216 compresses the image data (still image data or moving image data) generated by the image processing circuit 214. Further, when the image data is reproduced, the image data recorded on the recording medium 230 in a compressed state is decompressed.

The focus detection circuit 218 detects the focus of the focus lens 1021 by a known phase difference method using the focus detection pixel data output from the image sensor 208.

The exposure control circuit 220 as a photometric unit calculates an exposure set value based on the pixel data of the image sensor 208. The exposure control circuit 220 measures the subject brightness from the pixel data of the image sensor 208, and calculates the exposure setting value necessary for adjusting the brightness of the subject at the time of shooting to an appropriate value from the measured subject brightness. The exposure set value includes the aperture amount (aperture value) of the aperture 1022 and the exposure time (shutter speed) of the image sensor 208.

The display unit 222 is a display unit such as a liquid crystal display or an organic EL display, and is arranged on the back surface of the camera body 200, for example. The display unit 222 displays an image under the control of the CPU 212. The display unit 222 is used for live view display, display of recorded images, and the like.

The bus 224 is connected to an image sensor 208, a CPU 212, an image processing circuit 214, an image compression expansion unit 216, a focus detection circuit 218, an exposure control circuit 220, a display unit 222, a DRAM 226, a main body side storage unit 228, and a recording medium 230. It operates as a transfer path for transferring various data generated in these blocks.

The DRAM 226 is an electrically rewritable memory, and temporarily stores various data such as pixel data, still image data, moving image data, display image data, and processing data in the CPU 212 output from the image sensor 208. Note that SDRAM may be used for temporary storage.

The main body side storage unit 228 stores various data such as a program used by the CPU 212 and adjustment values of the camera main body 200. The recording medium 230 is configured to be built in or loaded in the camera body 200, and records image data for recording as an image file in a predetermined format. The DRAM 226, the main body side storage unit 228, and the recording medium 230 may each be configured by one memory or the like, or may be configured by combining a plurality of memories or the like.

Next, the image sensor 208 will be described. FIG. 2 is a diagram showing a configuration of an example image sensor 208. As shown in FIG. 2, the image sensor 208 includes an input circuit 301, a control circuit 302, a pixel unit 303, a vertical scanning circuit 304, an analog processing circuit 305, an analog-to-digital conversion (ADC) processing circuit 306, and the like. It has a memory circuit 307, a horizontal scanning circuit 308, and an output circuit 309. Here, the imaging unit in the present embodiment is configured to include the pixel unit 303. The imaging unit may further include a vertical scanning circuit 304, an analog processing circuit 305, an ADC processing circuit 306, and a memory circuit 307. Further, the analog processing circuit 305 and the ADC processing circuit 306 may be provided outside the image pickup device 208.

The input circuit 301 receives a control signal related to the operation of the image sensor 208 from the CPU 212 and inputs the control signal to the control circuit 302. The control signal related to this operation includes a synchronization signal (vertical synchronization signal and horizontal synchronization signal), a reference clock, and a signal for setting the operation of the image sensor 208.

The control circuit 302 is composed of, for example, a CPU or an ASIC, and controls the operation of each part of the image pickup device 208 based on the control signal input from the input circuit 301.

A plurality of pixel units 303 are arranged two-dimensionally, and incident light is photoelectrically converted to generate a pixel signal. FIG. 3 is a diagram showing a detailed configuration of the pixel unit 303. Here, the left side of FIG. 3 shows a view of the pixel portion 303 as viewed from the front, and the right side of FIG. 3 shows a view of the pixel portion 303 as viewed from the side surface. As shown in FIG. 3, the pixel unit 303 includes a microlens 303a, a color filter 303b, and a pixel 303c.

The microlens 303a collects the light flux that has passed through the imaging optical system 102 on the light receiving portion of the corresponding pixel 303c. As will be described later, one pixel 303c is composed of four light receiving portions whose pupils are divided into two horizontal × two vertical. The microlens 303a concentrates the light flux that has passed through the different exit pupil regions of the imaging optical system 102 on different light receiving units.

The color filter 303b is, for example, a color filter having a Bayer array of primary colors. In the primary color system bayer arrangement, rows in which red (R) filters and green (Gr) filters are alternately arranged and rows in which blue (B) filters and green (Gb) filters are alternately arranged are alternately arranged in the column direction. It is an arranged array. As shown in FIG. 3, one color of the color filter 303b corresponds to one pixel 303c. Therefore, light of the same color is incident on the four light receiving portions constituting the pixel 303c. The color filter 303b does not necessarily have to be a color filter having a Bayer array of primary colors.

The pixel 303c is composed of four light receiving portions lt, rt, lb, and rb which are divided and arranged in the horizontal direction which is the first pupil division direction and the vertical direction which is the second pupil division direction. ing. In the figure, the notation of "lt", "rt", "lb", and "rb" is attached to "R", "Gr", "Gb", and "B" indicating the color of the color filter. .. The light receiving units lt, rt, lb, and rb receive the light flux emitted from the same portion of the subject. Each of the light receiving units lt, rt, lb, and rb is composed of, for example, a photodiode, and outputs a pixel signal based on the accumulated charge according to the received light flux. Here, the light receiving unit lt receives the light flux that has passed through the exit pupil region at the lower right of the imaging optical system 102 among the emitted light flux. The light receiving unit rt receives the light flux that has passed through the exit pupil region at the lower left of the imaging optical system 102 among the emitted light flux. The light receiving unit lb receives the light flux that has passed through the exit pupil region on the upper right of the imaging optical system 102 among the emitted light flux. The light receiving unit rb receives the light flux that has passed through the exit pupil region on the upper left of the imaging optical system 102 among the emitted light flux.

Due to the structure in which the pixel 303c is divided into four light receiving units lt, rt, lb, and rb, the pixel 303c can be treated as either a left-right opening pixel or a top-bottom opening pixel for phase difference detection. The left and right aperture pixels are a pair of a pixel that receives a light flux that has passed through the exit pupil region on the left side of the imaging optical system and a pixel that receives a light flux that has passed through the exit pupil region on the right side of the imaging optical system. The upper and lower aperture pixels are a pair of a pixel that receives a light flux that has passed through the upper exit pupil region of the imaging optical system and a pixel that receives a light flux that has passed through the lower exit pupil region of the imaging optical system. Whether the pixel 303c is treated as a left-right opening pixel or a top-bottom opening pixel is switched by a control signal from the control circuit 302.

When the pixel 303c is treated as a left and right opening pixel, the control circuit 302 is a pixel signal and a light receiving part of a light receiving part lt (Rlt, Grlt, Gblt, Blt) which is a light receiving part of the left half as shown on the left side of FIG. 4A. The pixel signals of lb (Rlb, Grlb, Gblb, Blb) are added (mixed) and output, and the pixel signals of the light receiving part rt (Rrt, Grrt, Gbrt, Brt) and the light receiving part, which are the light receiving parts of the right half, are output. The pixel signals of rb (Rrb, Grrb, Gbrb, Brb) are added and output. As a result, as shown on the right side of FIG. 4A, the left aperture pixel signal l (Rl, Grl, Gbl, Bl) having the information of the luminous flux passing through the exit pupil region on the right side of the imaging optical system and the left side of the imaging optical system. Right aperture pixel signals r (Rr, Grr, Gbr, Br) having information on the luminous flux passing through the exit pupil region of the above are output, respectively.

When the pixel 303c is treated as the upper and lower opening pixels, the control circuit 302 has a pixel signal and a light receiving part of the light receiving part lt (Rlt, Grlt, Gblt, Blt) which is the light receiving part of the upper half as shown on the left side of FIG. 4B. The pixel signals of rt (Rrt, Grrt, Gbrt, Brt) are added (mixed) and output, and the pixel signals of the light receiving part lb (Rlb, Grlb, Gblb, Blb), which is the light receiving part of the lower half, and the light receiving part The pixel signals of rb (Rrb, Grrb, Gbrb, Brb) are added and output. As a result, as shown on the right side of FIG. 4B, the upper aperture pixel signal t (Rt, Grt, Gbt, Bt) having the information of the luminous flux passing through the exit pupil region on the lower side of the imaging optical system and the imaging optical system Lower aperture pixel signals b (Rb, Grb, Gbb, Bb) having information on the luminous flux passing through the upper exit pupil region are output, respectively.

Further, the pixel unit 303 of the present embodiment may be configured so that pixel signals can be added and output even between different pixel units 303. For example, the pixel unit 303 adds and outputs pixel signals of a plurality of left-opening pixels or right-opening pixels existing in the horizontal or vertical direction, or a plurality of upper openings existing in the horizontal or vertical direction or It may be configured to add and output the pixel signals of the lower aperture pixels. The addition number of pixel signals is set by, for example, the control circuit 302. The read time can be shortened by adding the pixel signals and then reading. When there is a margin in the read time, the pixel signals may not be added between the pixel units 303.

Each time the vertical scanning circuit 304 receives a storage start signal as a control signal from the control circuit 302, the vertical scanning circuit 304 resets the electric charge accumulated in the pixel 303c of the pixel unit 303 one line at a time, and then starts accumulating the electric charge in the pixel unit 303. Let me. Further, the vertical scanning circuit 304 ends the accumulation of electric charges in the pixel 303c of the pixel unit 303 one line at a time each time it receives an accumulation end signal as a control signal from the control circuit 302, and the accumulated electric charge is analog as a pixel signal. It is transferred to the processing circuit 305.

The analog processing circuit 305 performs analog processing on the pixel signals sequentially transferred from the pixel unit 303. The analog processing circuit 305 includes, for example, a preamplifier that amplifies the pixel signal in an analog manner, a correlated double sampling (CDS) processing circuit that removes reset noise from the pixel signal, and the like.

The ADC processing circuit 306 converts the pixel signal output from the analog processing circuit 305 into pixel data which is a digital signal according to the control signal from the control circuit 302. The ADC processing circuit 306 is configured as, for example, a column-type ADC processing circuit.

The memory circuit 307 temporarily stores the pixel data output from the ADC processing circuit 306 according to the control signal from the control circuit 302. The memory circuit 307 is composed of a volatile memory or the like. The memory circuit 307 may be configured to perform digital addition of pixel data. In this case, the memory circuit 307 is configured to store the added value of the pixel data output from the ADC processing circuit 306.

The horizontal scanning circuit 308 receives the control signal from the control circuit 302 and transfers the pixel data stored in the memory circuit 307 to the output circuit 309 in column order.

The output circuit 309 arranges the pixel data transferred by the horizontal scanning circuit 308 to generate a pixel data string. Further, the output circuit 309 converts the pixel data string into a predetermined output signal format such as a serial signal and a differential signal and outputs the signal.

Hereinafter, the operation of the image pickup apparatus 1 according to the present embodiment will be described. 5A and 5B are flowcharts showing the operation of the image pickup apparatus according to the present embodiment. Here, FIGS. 5A and 5B show the operation when the AF mode of the image pickup apparatus 1 is the continuous AF mode. The continuous AF mode is an AF mode suitable for a moving subject, and is an AF mode that keeps focusing so as to follow the subject.

The operations of FIGS. 5A and 5B are started when the user's power-on operation of the image pickup apparatus 1 is detected. When the power-on operation is detected, in step S101, the CPU 212 determines whether or not the 1st release switch of the release button is in the on state. The 1st release switch is, for example, a switch that is turned on in response to a half-press operation of the release button by the user. When it is determined in step S101 that the 1st release switch is in the ON state, the process proceeds to step S104. When it is determined in step S101 that the 1st release switch is not in the ON state, the process proceeds to step S102.

In step S102, the CPU 212 captures display pixel data for live view (LV) display. At this time, the CPU 212 outputs a control signal to the drive unit 204 so that the mechanical shutter 202 is fully opened, and controls the lens CPU 106 to drive the aperture 1022 by a predetermined amount (for example, an open aperture). Output a signal. After that, the CPU 212 outputs a control signal to the image pickup device 208 to start imaging for LV display by the image pickup device 208. Then, each time the imaging for LV display is completed, the control circuit 302 starts reading the pixel signal from the pixel unit 303. When reading out the pixel signal, the control circuit 302 may add the pixel signals of the same aperture (same color) output from the pixel 303c of the pixel unit 303. The display pixel data output from the image sensor 208 is stored in the DRAM 226.

In step S103, the CPU 212 displays the LV. At this time, the CPU 212 causes the image processing circuit 214 to generate display image data. In response to this, the image processing circuit 214 performs necessary processing on the display pixel data to generate display image data for display. The display image data is obtained by adding and averaging the pixel data of the light receiving units lt, rt, lb, and rb belonging to the same pixel unit 303. The CPU 212 causes the display unit 222 to display the LV image based on the display image data generated by the image processing circuit 214. After that, the process proceeds to step S126.

In step S104, the CPU 212 performs imaging and reading for autofocus (AF) and LV display. The imaging and readout processing for AF and LV display in step S104 will be described in detail later. Here, it is assumed that the focus detection pixel data for AF is stored in the DRAM 226 by imaging and readout for AF, and the display pixel data for display is stored in the DRAM 226 by imaging and readout for LV. continue.

In step S105, the CPU 212 displays the LV.

In step S106, the CPU 212 causes the focus detection circuit 218 to execute the focus detection operation. The focus detection circuit 218 performs a correlation calculation using a pair of focus detection pixel data among the focus detection pixel data stored in the DRAM 226. The paired focus detection pixel data in the case of horizontal phase difference detection is the left aperture pixel data l and the right aperture pixel data r, and the paired focus detection pixel data in the case of vertical phase difference detection is above. The opening pixel data t and the lower opening pixel data b. After the correlation calculation, the focus detection circuit 218 determines the reliability of the focus detection. The reliability determination is determined based on, for example, the contrast obtained from the pixel data and the correlation value calculated as a result of the correlation calculation.

In step S107, the focus detection circuit 218 calculates the amount of focus shift. That is, the focus detection circuit 218 is focused on the focus lens 1021 from the two image spacing values (the amount of image shift corresponding to the extreme value of the correlation value) in the focus detection region determined to be highly reliable as a result of the reliability determination in step S106. Calculate the amount of focus shift with respect to the in-focus position of. After that, the process proceeds to step S108.

In step S108, the focus detection circuit 218 performs an area selection process for selecting a focus detection region corresponding to the focus lens position used to drive the focus lens 1021. After the area selection process, the process proceeds to step S109. The area selection process is performed, for example, by selecting a focus detection area that indicates the amount of focus shift corresponding to the (that is, the closest) focus lens position corresponding to the closest subject distance.

In step S109, the CPU 212 determines whether or not the focus lens 1021 is in focus. In the determination in step S109, for example, the amount of focus shift (corresponding to the difference between the current focus lens position and the selected focus lens position) in the focus detection area selected in the area selection process is within a predetermined allowable range. It is done by determining whether or not there is. When the out-of-focus amount is within the permissible range, it is determined that the subject is in focus. When it is determined in step S109 that the focus lens 1021 is not in the focused state, the process proceeds to step S110. When it is determined in step S109 that the focus lens 1021 is in the focused state, the process proceeds to step S111.

In step S110, the CPU 212 outputs a control signal to the lens CPU 106 so that the focus lens 1021 is driven according to the focus lens position calculated for the focus detection region selected in step S108. The lens CPU 106 receives this control signal and drives the focus lens 1021 via the drive unit 104. After that, the process proceeds to step S126.

In step S111, the CPU 212 performs imaging and reading for autofocus (AF) and LV display in the same manner as in step S104. Here, the description will be continued assuming that the focus detection pixel data is stored in the DRAM 226 by imaging and reading for AF, and the display pixel data is stored in the DRAM 226 by imaging and reading for LV.

In step S112, the CPU 212 displays the LV.

In step S113, the CPU 212 causes the focus detection circuit 218 to execute the focus detection operation. The focus detection circuit 218 performs a correlation calculation using a pair of focus detection pixel data among the focus detection pixel data stored in the DRAM 226. After the correlation calculation, the focus detection circuit 218 determines the reliability of the focus detection. In step S114, the focus detection circuit 218 calculates the amount of focus shift. In step S115, the focus detection circuit 218 performs an area selection process.

In step S116, the focus detection circuit 218 stores the information related to the focus detection as history information in, for example, DRAM 226. The information related to focus detection includes, for example, information on the amount of focus shift calculated in step S114 and information on the focus detection region selected in step S115.

In step S117, the CPU 212 determines whether or not the 2nd release switch is turned on. The 2nd release switch is, for example, a switch that is turned on in response to a user's full press operation of the release button. When it is determined in step S117 that the 2nd release switch is not in the ON state, the process proceeds to step S118. When it is determined in step S117 that the 2nd release switch is in the ON state, the process proceeds to step S120.

In step S118, the CPU 212 determines whether or not the focus lens 1021 is in focus. When it is determined in step S118 that the focus lens 1021 is not in the focused state, the process proceeds to step S119. When it is determined in step S118 that the focus lens 1021 is in the focused state, the process proceeds to step S125.

In step S119, the CPU 212 outputs a control signal to the lens CPU 106 so that the focus lens 1021 is driven according to the focus lens position calculated for the focus detection region selected in step S115. The lens CPU 106 receives this control signal and drives the focus lens 1021 via the drive unit 104. After that, the process proceeds to step S125.

In step S120, the CPU 212 causes the moving object prediction calculation by the focus detection circuit 218 to be executed. In response to this, the focus detection circuit 218 performs a moving object prediction calculation. The moving object prediction calculation is a process of predicting the position to be driven of the focus lens 1021 this time from the history of the result (focus lens position) of the past focus shift amount calculation stored in step S116.

In step S121, the CPU 212 starts the operation of the mechanical shutter 202 in order to perform imaging (main exposure) for acquiring a still image. The operation of the mechanical shutter 202 includes an opening / closing operation of the mechanical shutter 202 before and after the main exposure, and a fully opening operation of the mechanical shutter 202 for starting imaging for live view and AF after the main exposure. First, the CPU 212 switches the control signal of the drive unit 204 so that the mechanical shutter 202 is fully closed. Then, after performing the main exposure in step S123, the CPU 212 controls the drive unit 204 so that the mechanical shutter 202 is fully opened.

In step S122, the CPU 212 instructs the lens CPU 106 to simultaneously drive the focus lens 1021 and the aperture 1022 to start the operation. Here, the drive position of the focus lens 1021 is the position predicted in the moving object prediction calculation in step S120. Further, the opening amount of the aperture 1022 is an opening amount according to the aperture value calculated based on the subject brightness measured by the immediately preceding photometric calculation.

In step S123, the CPU 212 starts the main exposure. This exposure is an imaging for acquiring image data for recording. In this exposure, the CPU 212 starts imaging of the image sensor 208. After the end of the exposure period, the control circuit 302 reads out the pixel signals from each light receiving unit of the image sensor 208. After reading out the pixel signal, the CPU 212 causes the image processing circuit 214 to perform a process for generating still image data for recording. In response to this, the image processing circuit 214 performs processing necessary for generating image data for recording to generate still image data for recording. After the image processing is completed, the CPU 212 compresses the still image data for recording by the image compression expansion unit 216. After the compression is completed, the CPU 212 records the compressed still image data for recording as an image file on the recording medium 230.

In step S124, the CPU 212 instructs the lens CPU 106 to open the aperture 1022.

In step S125, the CPU 212 determines whether or not the 1st release switch is in the ON state. When it is determined in step S125 that the 1st release switch is in the ON state, the process returns to step S111. When it is determined in step S125 that the 1st release switch is not in the ON state, the process proceeds to step S126.

In step S126, the CPU 212 determines whether or not to turn off the power of the camera body 200. For example, it is determined that the power is turned off when the power is instructed to be turned off by the operation of the user's operation unit 206 or when the user's operation unit 206 is not operated for a predetermined time. When it is determined in step S126 that the power of the camera body 200 is not turned off, the process returns to step S101. When it is determined in step S126 that the power of the camera body 200 is turned off, the process ends.

Next, the processing of step S104 and step S111 will be described. FIG. 6 is a timing chart for explaining the imaging and readout processing for AF and LV display in steps S104 and S111. Here, “VD” in FIG. 6 indicates the timing of the synchronization signal (vertical synchronization signal) input to the control circuit 302. VD (1) is a vertical synchronization signal indicating the timing of the first operation including imaging and readout for AF, and VD (2) is a second operation including imaging and readout for LV display. It is a vertical synchronization signal indicating the timing. The VD (1) and the VD (2) are input to the control circuit 302 once during one frame. In this case, the process of step S104 is performed every frame. The length of one frame is determined according to the update interval of the LV display screen, the continuous shooting speed indicating the continuous shooting interval at the time of continuous shooting, and the like. Hereinafter, each of the first operation and the second operation will be described in detail.

First, the first operation will be described. The first operation shown by AF (rl) in FIG. 6 is an operation for generating and reading a focus detection pixel signal with respect to the first pupil division direction. The first pupil division direction is, for example, the horizontal direction of the pixel unit 303. Prior to the first operation, the control circuit 302 outputs a left-opening pixel signal l (Rl, Grl, Gbl, Bl) and a right-opening pixel signal r (Rr, Grr, Gbr, Br) from the pixel unit 303. The setting of the pixel unit 303 is switched so as to be. Further, the control circuit 302 sets the pixel addition between the pixel units 303 in order to shorten the pixel signal reading time. FIG. 7 shows an example of setting the pixel addition in the first operation. As shown in FIG. 7, in the first operation, addition is not performed in the horizontal direction, which is the first pupil division direction, and addition is performed only in the vertical direction, which is the second pupil division direction. Will be done. In the example of FIG. 7, it is set to add 6 pixel signals of the same aperture (left openings or right openings) arranged in the vertical direction. The number of pixel signal additions is appropriately set according to, for example, the frame rate.

By the setting of FIG. 7, the number of lines of the pixel signal is compressed to 1/6. By reducing the number of rows of the pixel signal, the read time of the pixel signal is shortened. On the other hand, since the number of columns of pixel signals does not change, the detection accuracy of the phase difference in the horizontal direction is ensured.

After the settings as shown in FIG. 7, the CPU 212 outputs a control signal to the image pickup device 208 so as to perform imaging at the exposure time required to generate the focus detection pixel signal. This exposure time is set based on the subject brightness and the like.

Upon receiving the input of the control signal from the CPU 212, the control circuit 302 starts imaging (accumulation of electric charge) for each row of the pixel unit 303. Then, the control circuit 302 controls the vertical scanning circuit 304 to sequentially output pixel signals from the pixel unit 303 of the row in which imaging is completed.

Here, the detection of the phase difference in the horizontal direction is performed using, for example, a pair of Gr's left-opening pixel signal Gr and right-opening pixel signal Grr and a pair of Gb's left-opening pixel signal Gbl and right-opening pixel signal Gbr. That is, the pair of the left opening pixel signal Rl of R and the right opening pixel signal Rr and the pair of the left opening pixel signal Bl of B and the right opening pixel signal Br do not necessarily have to be read out. Therefore, at the time of reading, only the pair of the left opening pixel signal Grl and the right opening pixel signal Grr and the pair of the left opening pixel signal Gbl and the right opening pixel signal Gbr are packed and read as shown in FIG. May be good. Of course, the pair of the left opening pixel signal Rl and the right opening pixel signal Rr and the pair of the left opening pixel signal Gbl and the right opening pixel signal Gbr may also be read together.

The pixel signal read from the pixel unit 303 is analog-processed in the analog processing circuit 305. The analog-processed pixel signal is converted into pixel data which is a digital signal in the ADC processing circuit 306. The pixel data is stored in the memory circuit 307. As described above, the addition shown in FIG. 7 may be performed in the memory circuit 307.

The horizontal scanning circuit 308 receives the control signal from the control circuit 302 and transfers the pixel data stored in the memory circuit 307 to the output circuit 309 in column order. The output circuit 309 arranges the pixel data transferred by the horizontal scanning circuit 308 to generate a pixel data string, converts the generated pixel data string into a predetermined output signal format such as a serial signal and a differential signal, and outputs the data. do. This pixel data string is stored in the DRAM 226 as shown in FIG. 8, for example. In this way, the first operation is completed.

The pixel data string stored in the DRAM 226 by the first operation is used for the correlation calculation for calculating the out-of-focus amount. The focus detection circuit 218 performs the correlation calculation using the pair of the left aperture pixel data Grl and the right aperture pixel data Grr and the pair of the left aperture pixel data Gbl and the right aperture pixel data Gbr stored in the DRAM 226.

Next, the second operation will be described. The second operation shown by LV + AF (tb) in FIG. 6 is an operation mainly for generating and reading (LV) a display pixel signal. However, in the present embodiment, the generation and reading (AF (tb)) of the focus detection pixel signal regarding the second pupil division direction are also performed in the second operation. Prior to the second operation, the control circuit 302 outputs the upper opening pixel signal t (Rt, Grt, Gbt, Bt) and the lower opening pixel signal b (Rb, Grb, Gbb, Bb) from the pixel unit 303. The setting of the pixel unit 303 is switched so as to be. Further, the control circuit 302 sets the pixel addition between the pixel units 303 in order to shorten the pixel signal reading time. FIG. 9 shows an example of setting the pixel addition in the second operation. As shown in FIG. 9, in the second operation, the addition is set so that the addition is performed in both the horizontal direction which is the first pupil division direction and the vertical direction which is the second pupil division direction. In the example of FIG. 9, the pixel signals of three identical openings (upper openings or lower openings) arranged in the horizontal direction are added, and three identical openings (upper openings or lower openings) arranged in the vertical direction are added. It is set to add the pixel signals of. In the example of FIG. 9, addition is not performed for the second row, the third and fourth columns. This is a remainder caused simply because the number of rows and the number of columns of the pixel unit 303 is not a multiple of 3.

By the setting of FIG. 9, the number of rows and the number of columns of the pixel signal are each compressed to about one-third. By reducing the number of rows and columns of the pixel signal, the read time of the pixel signal is shortened. The number of pixel signals to be added is not limited to this. However, in the second operation, the image quality at the time of display deteriorates as the number of additions of the pixel signals increases. Further, as the number of additions of the pixel signals in the vertical direction increases, the accuracy of detecting the phase difference in the vertical direction also decreases. Therefore, it is desirable that the number of pixel signal additions is appropriately determined by a trade-off between the readout time, the image quality at the time of display, and the detection accuracy of the phase difference in the vertical direction.

After the settings as shown in FIG. 9, the CPU 212 outputs a control signal to the image pickup device 208 so as to perform imaging at the exposure time required to generate the focus detection pixel signal. This exposure time is set based on the subject brightness and the like.

Upon receiving the input of the control signal from the CPU 212, the control circuit 302 starts imaging (accumulation of electric charge) for each row of the pixel unit 303. Then, the control circuit 302 controls the vertical scanning circuit 304 to sequentially output pixel signals from the pixel unit 303 of the row in which imaging is completed.

The pixel signal read from the pixel unit 303 is analog-processed in the analog processing circuit 305. The analog-processed pixel signal is converted into pixel data which is a digital signal in the ADC processing circuit 306. The pixel data is stored in the memory circuit 307. In the second operation, pixel signals of R, Gr, Gb, and B are required for the display image data. Therefore, the upper aperture pixel signals Rt, Grt, Gbt, and Bt and the lower aperture pixel signals Rb, Grb, Gbb, and Bb are stored in the memory circuit 307 without being packed.

The horizontal scanning circuit 308 receives the control signal from the control circuit 302 and transfers the pixel data stored in the memory circuit 307 to the output circuit 309 in column order. The output circuit 309 arranges the pixel data transferred by the horizontal scanning circuit 308 to generate a pixel data string, converts the generated pixel data string into a predetermined output signal format such as a serial signal and a differential signal, and outputs the data. do. This pixel data string is stored in the DRAM 226 as shown in FIG. 10, for example. In this way, the second operation is completed.

The pixel data string stored in the DRAM 226 by the second operation is used for the LV display. As described above, the display image data is obtained by adding and averaging the pixel data of the light receiving units lt, rt, lb, and rb belonging to the same pixel unit 303. Therefore, the image processing circuit 214 generates display image data by adding and averaging the upper aperture pixel data t (Rt, Grt, Gbt, Bt) and the lower aperture pixel data b (Rb, Grb, Gbb, Bb).

Further, the pixel data string stored in the DRAM 226 by the second operation is used for the correlation calculation for calculating the out-of-focus amount. The focus detection circuit 218 performs the correlation calculation using the pair of the upper aperture pixel data Grt and the lower aperture pixel data Grb stored in the DRAM 226. Further, the focus detection circuit 218 performs the correlation calculation using the pair of the upper aperture pixel data Gbt and the lower aperture pixel data Gbb stored in the DRAM 226. That is, the upper and lower opening pixel data Grt, Grb, Gbt, and Gbb are read out twice from the DRAM 226.

As described above, in the present embodiment, the pixel signal is read out so that the focus detection pixel data relating to the first pupil division direction is generated in the first operation for the phase difference AF. Further, the pixel signal is read out so that the display pixel data read in the second operation for LV display can also be used as the focus detection pixel data related to the second pupil division direction. That is, in the present embodiment, the pixel signals of the upper and lower openings are output from the pixel portion so that the phase difference related to the second pupil division direction can be detected, and the pixel signals of the upper and lower openings are used for LV display. The display pixel data and the focus detection pixel data for AF regarding the second pupil division direction are generated. As a result, both the phase difference detection regarding the first pupil division direction and the phase difference detection regarding the second pupil division direction can be performed while shortening the pixel signal reading time. In this way, in the present embodiment, it is possible to secure the time for the live view display while ensuring the focus detection performance of the phase difference method.

Further, in the present embodiment, the pixel signal reading time is further shortened by adding and then reading the pixel signals of the same aperture. At this time, in the first operation, the phase difference detection performance in the horizontal direction can be ensured by not adding the pixel signals of the same aperture in the first pupil division direction. Further, in the second operation, both the read time and the phase difference detection performance in the vertical direction can be ensured by reducing the number of additions of the pixel signals of the same aperture in the second pupil division direction.

[Modification 1]
Hereinafter, a modified example of the present embodiment will be described. The examples shown in FIGS. 5A and 5B show the operation when the AF mode of the image pickup apparatus is the continuous AF mode. The technique of the present embodiment described above can be applied when the LV display and AF are repeated in a short period of time even when the AF mode of the image pickup apparatus is not the continuous AF mode. For example, the technique of the present embodiment can be applied even when the AF mode of the image pickup apparatus is a single AF mode. The single AF mode is an AF mode in which after the 1st release switch is turned on, AF is performed until the subject is in focus, and after focusing, the AF operation is stopped. FIG. 11 is a flowchart showing the operation of the image pickup apparatus 1 when the AF mode is the single AF mode. In FIG. 11, the description of the portion overlapping with FIGS. 5A and 5B will be omitted as appropriate.

The operation of FIG. 11 is started when a user's power-on operation of the image pickup apparatus 1 is detected. When the power-on operation is detected, in step S201, the CPU 212 determines whether or not the 1st release switch of the release button is in the on state. When it is determined in step S201 that the 1st release switch is in the ON state, the process proceeds to step S204. When it is determined in step S201 that the 1st release switch is not in the ON state, the process proceeds to step S202.

In step S202, the CPU 212 captures display pixel data for live view (LV) display. In step S203, the CPU 212 displays the LV. After that, the process proceeds to step S218.

In step S204, the CPU 212 performs imaging and reading for AF and LV display. The process of step S204 is performed in the same manner as in the above-described embodiment. In step S205, the CPU 212 displays the LV.

In step S206, the CPU 212 causes the focus detection circuit 218 to execute the focus detection operation. The focus detection circuit 218 performs a correlation calculation using a pair of focus detection pixel data among the focus detection pixel data stored in the DRAM 226. After the correlation calculation, the focus detection circuit 218 determines the reliability of the focus detection. In step S207, the focus detection circuit 218 calculates the amount of focus shift. In step S208, the focus detection circuit 218 performs an area selection process.

In step S209, the CPU 212 determines whether or not the focus lens 1021 is in the focused state. When it is determined in step S209 that the focus lens 1021 is not in the focused state, the process proceeds to step S210. When it is determined in step S209 that the focus lens 1021 is in the focused state, the process proceeds to step S211.

In step S210, the CPU 212 outputs a control signal to the lens CPU 106 so that the focus lens 1021 is driven according to the focus lens position calculated for the focus detection region selected in step S208. The lens CPU 106 receives this control signal and drives the focus lens 1021 via the drive unit 104. After that, the process proceeds to step S218.

In step S211 the CPU 212 acquires display pixel data for LV display. In step S212, the CPU 212 displays the LV.

In step S213, the CPU 212 determines whether or not the 2nd release switch is turned on. When it is determined in step S213 that the 2nd release switch is not in the ON state, the process proceeds to step S217. When it is determined in step S213 that the 2nd release switch is in the ON state, the process proceeds to step S214.

In step S214, the CPU 212 instructs the lens CPU 106 to drive the diaphragm 1022 and starts the operation. Here, the aperture amount of the aperture 1022 is an aperture amount corresponding to the aperture value calculated based on the subject brightness measured by the immediately preceding photometric calculation.

In step S215, the CPU 212 starts the main exposure. In the main exposure, the CPU 212 controls the drive unit 204 so as to open and close the mechanical shutter 202 for a predetermined exposure period. Then, the CPU 212 starts imaging of the image pickup device 208 during the exposure period. After the end of the exposure period, the control circuit 302 reads out the pixel signals from each light receiving unit of the image sensor 208. After reading out the pixel signal, the CPU 212 causes the image processing circuit 214 to perform a process for generating still image data for recording. In response to this, the image processing circuit 214 performs processing necessary for generating image data for recording to generate still image data for recording. After the image processing is completed, the CPU 212 compresses the still image data for recording by the image compression expansion unit 216. After the compression is completed, the CPU 212 records the compressed still image data for recording as an image file on the recording medium 230.

In step S216, the CPU 212 instructs the lens CPU 106 to open the aperture 1022.

In step S217, the CPU 212 determines whether or not the 1st release switch is in the ON state. When it is determined in step S217 that the 1st release switch is in the ON state, the process returns to step S211. When it is determined in step S217 that the 1st release switch is not in the ON state, the process proceeds to step S218.

In step S218, the CPU 212 determines whether or not to turn off the power of the camera body 200. When it is determined in step S218 that the power of the camera body 200 is not turned off, the process returns to step S201. When it is determined in step S218 that the power of the camera body 200 is turned off, the process ends.

In this way, in the single AF mode, the LV display and AF are repeated from the time when the 1st release switch is turned on until the subject is in focus. Therefore, the technique of this embodiment is effective.

[Modification 2]
In the second operation described above, the display image data is the sum of the upper and lower opening pixel data t and b read from the light receiving units lt, rt, lb and rb belonging to the same pixel unit 303 stored in the DRAM 226. Generated by averaging. This is so that the upper and lower aperture pixel data t and b stored in the DRAM 226 can also be read as focus detection pixel data related to the second pupil division direction.

On the other hand, as shown in FIG. 12, for example, the upper and lower opening pixel signals t and b (pixel signals connected by “+” in the figure) which are not necessary for detecting the phase difference in the second pupil division direction It is added and output from the pixel unit 303 without adding only the upper and lower opening pixel signals t and b (pixel signals not connected by "+" in the figure) required for detecting the phase difference in the second pupil division direction. The image pickup device 208 may be configured to allow the image sensor 208 to be set. In this case, the pixel data is stored in the DRAM 226 as shown in FIG. By adding what can be added in the pixel unit 303 in advance in this way, the number of pixel data stored in the DRAM 226 is reduced. Further, the addition averaging process for generating the display image data in the image processing circuit 214 is also omitted. On the other hand, the detection of the phase difference with respect to the second pupil division direction can be appropriately performed.

[Modification 3]
In the first operation, the read-out time is shortened by adding pixel signals of the same aperture arranged in the vertical direction, which is the second pupil division direction, and then outputting them from the pixel unit 303. On the other hand, the read time can be shortened by thinning out the pixel signals and reading them. For example, when the frame rate set according to the continuous shooting speed or the like is faster than the predetermined value, the pixel signal is read out by 50% of the rows as shown in FIG. 14A, and the frame rate is slower than the predetermined value. When is, it is possible to perform processing such as reading out a pixel signal of 100% of rows as shown in FIG. 14B. Pixel addition reading and thinning reading may be used together. Further, when it is difficult to maintain the frame rate only by the thinning-out reading for the first operation, the thinning-out reading may be performed in the second operation as well.

[Other variants]
In the above-described embodiment, the first pupil division direction is the horizontal direction and the second pupil division direction is the vertical direction. On the contrary, the first pupil division direction may be the vertical direction and the second pupil division direction may be the horizontal direction. In this case, the pixel unit 303 is set so that the upper and lower opening pixel signals are output in the first operation, and the pixel unit 303 is set so that the left and right opening pixel signals are output in the second operation. Is done.

Further, in the above-described embodiment, the pixel addition setting and the like in the pixel unit 303 are performed by the control circuit 302 provided inside the image pickup device 208. The control circuit 302 may be provided outside the image pickup device 208. In this case, for example, the CPU 212 may be configured to perform the same processing as the control circuit 302.

Although the present invention has been described above based on the embodiments, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications and applications are possible within the scope of the gist of the present invention.

Further, in the explanation of each operation flowchart described above, the operation is described using "first", "next", etc. for convenience, but it does not mean that it is essential to perform the operation in this order. No.

Further, each process according to the above-described embodiment can be stored as a program that can be executed by the CPU 212 or the control circuit 302, which is a computer. In addition, it can be stored and distributed in a storage medium of an external storage device such as a magnetic disk, an optical disk, or a semiconductor memory. Then, the CPU 212 or the control circuit 302 reads the program stored in the storage medium of the external storage device, and the operation is controlled by the read program, so that the above-described processing can be executed.

The present invention is not limited to the above-described embodiment, and can be variously modified at the implementation stage without departing from the gist thereof. In addition, each embodiment may be carried out in combination as appropriate, in which case the combined effect can be obtained. Further, the above-described embodiment includes various inventions, and various inventions can be extracted by a combination selected from a plurality of disclosed constituent requirements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, if the problem can be solved and the effect is obtained, the configuration in which the constituent requirements are deleted can be extracted as an invention.

1 Image sensor, 100 interchangeable lens, 102 image sensor, 104 drive unit, 106 lens CPU, 108 lens side storage unit, 110 interface (I / F), 200 camera body, 202 mechanical shutter, 204 drive unit, 206 operation Unit, 208 image sensor, 210 camera shake correction circuit, 212 CPU, 214 image processing circuit, 216 image compression expansion unit, 218 focus detection circuit, 220 exposure control circuit, 222 display unit, 224 bus, 226 DRAM, 228 main unit side storage unit , 230 Recording medium, 301 input circuit, 302 control circuit, 303 pixel section, 303a microlens, 303b color filter, 303c pixel, 304 vertical scanning circuit, 305 analog processing circuit, 306 analog-to-digital conversion (ADC) processing circuit, 307 memory Circuit, 308 horizontal scanning circuit, 309 output circuit, 1021 focus lens, 1022 aperture.

Claims (7)

It is different from the first pupil division direction and the first pupil division direction so as to generate a pixel signal by photoelectric conversion of each light flux passing through different exit pupil regions of the imaging optical system for one microlens. An imaging unit having a pixel unit in which a plurality of light receiving units divided in the second pupil division direction are arranged, and an imaging unit.
Display for display generated based on the pixel signal An image processing circuit that performs processing for displaying an image based on the pixel signal, and an image processing circuit.
Focus detection for focus detection generated based on the pixel signal A focus detection circuit that performs processing for focus detection based on the pixel signal, and
A control circuit that controls the imaging unit so that the first operation and the second operation including the generation and reading of the pixel signal are alternately performed, respectively.
Equipped with
The control circuit controls the imaging unit so that the focus detection pixel signal relating to the first pupil division direction is generated in the first operation, and the display pixel signal and the display pixel signal in the second operation. A focus detection device that controls the imaging unit so that the focus detection pixel signal with respect to the second pupil division direction is generated. In the first operation, the control circuit adds the pixel signal from the light receiving unit divided in the second pupil division direction, and in the second operation, the pixel signal is added in the first pupil division direction. The focus detection device according to claim 1, wherein the imaging unit is controlled so that the pixel signals from the divided light receiving units are added. In the first operation, the control circuit does not add the pixel signals output from the plurality of pixel units in the first pupil division direction, but adds them in the second pupil division direction. The focus detection device according to claim 1 or 2, wherein the imaging unit is controlled so as to. In the second operation, the control circuit performs the imaging so that the pixel signals output from the plurality of pixel units are added in both the first pupil division direction and the second pupil division direction. The focus detection device according to claim 1 or 2, which controls a unit. The focus detection device according to claim 1 or 2, wherein the control circuit controls the imaging unit so that in the first operation, only a part of the pixel signals are read out in the second pupil division direction. .. The control circuit controls the imaging unit so that only a part of the pixel signals are read out in the second pupil division direction when the frame rate related to the first operation is faster than a predetermined value. The focus detection device according to claim 5. It is different from the first pupil division direction and the first pupil division direction so as to generate a pixel signal by photoelectric conversion of each light flux passing through different exit pupil regions of the imaging optical system for one microlens. A focus detection method using an imaging unit having a pixel unit in which a plurality of light receiving units divided in the second pupil division direction are arranged.
Display for display generated based on the pixel signal Processing for displaying an image based on the pixel signal and
Focus detection for focus detection generated based on the pixel signal Processing for focus detection based on the pixel signal and
Controlling the imaging unit so that the first operation and the second operation including the generation and reading of the pixel signal are alternately performed, respectively.
Equipped with
Controlling the imaging unit means controlling the imaging unit so that the focus detection pixel signal with respect to the first pupil division direction is generated in the first operation, and controlling the imaging unit in the second operation. A focus detection method including controlling the imaging unit so that a display pixel signal and the focus detection pixel signal with respect to the second pupil division direction are generated.

Images