JP6931572B2 - How to form the gate insulating film and the gate insulating film - Google Patents

Description

The present invention relates to a method for forming a gate insulating film and a gate insulating film.

A field effect transistor having a compound semiconductor layer containing gallium and a group 15 element is one of the semiconductor elements, and the field effect transistor is provided between the compound semiconductor layer and the gate electrode. A MISFET structure (Metal Insulator Semiconductor FET), which is a structure having a gate insulating film, is known. As a gate insulating film having a MISFET structure, an insulating film formed of aluminum oxide has been proposed (see, for example, Patent Document 1).

JP-A-2010-98141

By the way, when a repeated voltage is applied to the gate electrode of the MOSFET structure, the threshold voltage at the gate electrode fluctuates as the voltage is repeatedly applied due to the fluctuation of the defect in the film of the aluminum oxide film. As a gate insulating film capable of suppressing fluctuations in the threshold voltage, a gate insulating film composed of an aluminum oxide layer in contact with a semiconductor layer and a silicon oxide layer located on the aluminum oxide layer has been studied. In such a gate insulating film, studies on a suitable configuration when used as a gate insulating film are not yet sufficient.

An object of the present invention is to provide a method for forming a gate insulating film having a suitable configuration when used as a gate insulating film in a laminated film in which a silicon oxide layer is laminated on an aluminum oxide layer, and to provide a gate insulating film. And.

The method for forming the gate insulating film for solving the above problems is to form an aluminum oxide layer on the surface included in the film formation target, which includes a region formed of a semiconductor containing gallium and Group 15 elements. This includes forming a silicon oxide layer on the surface of the aluminum oxide layer opposite to the surface in contact with the surface. Forming the silicon oxide layer is a transition region containing oxygen, aluminum, and silicon at the boundary between the aluminum oxide layer and the silicon oxide layer, and the aluminum oxide layer and the silicon oxide layer are formed. The silicon oxide layer is formed so that the transition region having a thickness of 4 nm or more and 10 nm or less in the stacking direction is formed.

The gate insulating film for solving the above problems is formed on an aluminum oxide layer located on the surface of a semiconductor layer containing gallium and Group 15 atoms and a surface of the aluminum oxide layer opposite to the surface in contact with the surface. It has a silicon oxide layer located. The region including the boundary between the aluminum oxide layer and the silicon oxide layer is a transition region containing oxygen, aluminum, and silicon, and the width of the transition region in the direction in which the aluminum oxide layer and the silicon oxide layer are stacked. However, it is 4 nm or more and 10 nm or less.

The inventor of the present application has found the following in his diligent research on a gate insulating film composed of an aluminum oxide layer and a silicon oxide layer. That is, in the present invention, the region including the boundary between the aluminum oxide layer and the silicon oxide layer is the transition region, and the width of the transition region is 4 nm or more and 10 nm or less in the direction in which the aluminum oxide layer and the silicon oxide layer are stacked. As a result, it was found that the absolute value of the threshold voltage at the gate electrode can be suppressed from becoming large in the negative range.

In this respect, according to the above configuration, in the gate insulating film in which the silicon oxide layer is formed on the aluminum oxide layer, the thickness of the transition region in the direction in which the aluminum oxide layer and the silicon oxide layer are stacked is 4 nm or more and 10 nm or less. Is. Therefore, it is possible to prevent the absolute value of the threshold voltage at the gate electrode from becoming large in the negative range. As described above, in a laminated film in which an aluminum oxide layer and a silicon oxide layer are laminated, a suitable configuration can be obtained when used as a gate insulating film.

In the method for forming the gate insulating film, forming the aluminum oxide layer is to form the aluminum oxide layer by using the ALD method, and forming the silicon oxide layer is to form the oxidation by using the plasma CVD method. A silicon layer may be formed.

According to the above configuration, when the silicon oxide layer is formed, the semiconductor layer located under the gate insulating film is covered with the aluminum oxide layer, so that even if the silicon oxide layer is formed by the plasma CVD method, the semiconductor layer is formed. Damage is suppressed.

In the method for producing the gate insulating film, forming the silicon oxide layer ^{may supply electric power of 0.2 W / cm 2} or less to the electrode.
According to the above configuration, when the power supplied to the electrodes is 0.2 W / cm ² or less, the certainty that the thickness of the transition region becomes 4 nm or more is increased.

In the gate insulating film, the transition region is at least one of a region including an uneven surface as a boundary between the aluminum oxide layer and the silicon oxide layer and a mutual diffusion region between the aluminum oxide layer and the silicon oxide layer. It may be.

According to the above configuration, since the transition region is at least one of the region including the uneven surface and the mutual diffusion region, the thickness of the transition region is within the above-mentioned range in the direction in which the aluminum oxide layer and the silicon oxide layer are stacked. It becomes easy to exceed the lower limit value in.

The block diagram which shows the structure of the ALD apparatus used for forming the aluminum oxide film in the method of forming a gate insulating film. The block diagram which shows the structure of the plasma CVD apparatus used for forming the silicon oxide film in the method of forming a gate insulating film. The process drawing which shows one step in the manufacturing method of a MISFET including the method of forming a gate insulating film. The process drawing which shows one step in the manufacturing method of a MISFET including the method of forming a gate insulating film. The process drawing which shows one step in the manufacturing method of a MISFET including the method of forming a gate insulating film. The graph which shows the relationship between the gate voltage and the drain current in Test Example 1. The graph which shows the relationship between the gate voltage and the drain current in Test Example 2. The graph which shows the relationship between the gate voltage and the drain current in Test Example 3. The graph which shows the relationship between the gate voltage and the drain current in Test Example 4. TEM image of a partial cross-sectional structure of the MISFET of Test Example 5. The graph which shows each intensity of the oxygen atom, the silicon atom, and the aluminum atom in the MISFET of Test Example 5. TEM image of a partial cross-sectional structure of the MISFET of Test Example 6. The graph which shows each intensity of the oxygen atom, the silicon atom, and the aluminum atom in the MISFET of Test Example 6. A graph showing the relationship between high-frequency power and the width of the transition region. The graph which shows the relationship between the high frequency power and the threshold voltage.

With reference to FIGS. 1 to 15, as an embodiment in which the gate insulating film is formed and the gate insulating film is embodied, a method for forming a gate insulating film composed of an aluminum oxide layer and a silicon oxide layer and gate insulation are used. The film will be described. In the following, a schematic configuration of an ALD apparatus used for forming an aluminum oxide layer, a schematic configuration of a plasma CVD apparatus used for forming a silicon oxide layer, a method for manufacturing a MISFET including a method for forming a gate insulating film, and a test example. explain.

[Outline configuration of ALD device]
The schematic configuration of the ALD apparatus will be described with reference to FIG. The ALD apparatus described below is an apparatus for forming an aluminum oxide layer by using an atomic layer deposition method (Atomic Layer Deposition).

As shown in FIG. 1, the ALD device 10 includes a vacuum chamber 11 having a box shape. A support portion 12 that supports the film formation target S is located inside the vacuum chamber 11, and the support portion 12 is, for example, a stage. The film-forming target S includes a surface Sa on which an aluminum oxide layer is formed. A heating portion 13 is located inside the support portion 12. The heating unit 13 heats the temperature of the film forming target S supported by the support unit 12 to a predetermined temperature of 200 ° C. or higher, and more preferably to a predetermined temperature included in 250 ° C. or higher and 500 ° C. or lower.

An exhaust unit 14 that exhausts the inside of the vacuum chamber 11 is connected to the vacuum chamber 11. The exhaust unit 14 exhausts the inside of the vacuum chamber 11 to a predetermined pressure. The exhaust section 14 includes, for example, an exhaust pump and a valve.

The first pipe 21, the second pipe 22, the third pipe 23, and the fourth pipe 24 are connected to the vacuum tank 11. A cylinder for storing the purge gas is connected to the first pipe 21, and the purge gas is, for example, nitrogen (N ₂ ) gas. A first valve 21a is installed in the middle of the first pipe 21, and with the first valve 21a open, purge gas is supplied to the vacuum tank 11 through the first pipe 21, and the first valve 21a In the closed state, the supply of purge gas to the vacuum chamber 11 through the first pipe 21 is stopped.

The second pipe 22, a cylinder for storing the first oxidizing gas is connected, the first oxidizing gas, for example ozone (O ₃₎ gas. A second valve 22a is installed in the middle of the second pipe 22, and in a state where the second valve 22a is open, the first oxide gas is supplied to the vacuum tank 11 through the second pipe 22, and the second With the valve 22a closed, the supply of the first oxide gas to the vacuum tank 11 through the second pipe 22 is stopped.

A first storage unit 25 is connected to the third pipe 23, and a third valve 23a is installed in the middle of the third pipe 23. A second storage unit 26 is connected to the fourth pipe 24, and a fourth valve 24a is installed in the middle of the fourth pipe 24.

The first storage unit 25 stores the second oxide gas. The second oxidizing gas is, for example, water _(H 2 O). The first storage unit 25 is covered with the first temperature control unit 27. The first temperature control unit 27 adjusts the temperature of the second oxidation gas stored inside the first storage unit 25 to a predetermined temperature. As a result, the first temperature control unit 27 adjusts the vapor pressure of the second oxide gas in the first storage unit 25 to a predetermined value.

In the third pipe 23, the second oxide gas is supplied to the vacuum tank 11 through the third pipe 23 with the third valve 23a open, and the third valve 23a is closed. 3 The supply of the second oxide gas to the vacuum chamber 11 through the pipe 23 is stopped.

The second storage unit 26 stores the first film-forming material M1 for forming the aluminum oxide layer. The first film-forming material M1 is, for example, trimethylaluminum (TMA) (Al (CH ₃ ) ₃ ). The first film-forming material M1 is a liquid at normal temperature and pressure. The first film-forming material M1 is not limited to trimethylaluminum, and for example, triethylaluminum (TEA) (Al (C ₂ H ₅ ) ₃ ) or the like can be used.

The second storage unit 26 is covered by the second temperature control unit 28. The second temperature control unit 28 adjusts the temperature of the first film-forming material M1 stored inside the second storage unit 26 to a predetermined temperature. As a result, the second temperature control unit 28 adjusts the vapor pressure of the first film-forming material M1 in the second storage unit 26 to a predetermined value.

In the fourth pipe 24, the first film-forming material M1 is supplied to the vacuum chamber 11 through the fourth pipe 24 in a state where the fourth valve 24a is open, and the fourth valve 24a is closed. , The supply of the first film-forming material M1 to the vacuum chamber 11 through the fourth pipe 24 is stopped.

In such an ALD device 10, the amount of each gas supplied to the vacuum chamber 11 is controlled by the time for opening the first valve 21a, the second valve 22a, the third valve 23a, and the fourth valve 24a. Further, in the ALD apparatus 10, the first film-forming material M1, the second oxide gas, and the first oxide gas are supplied to the surface Sa of the film-forming target S in this order, and the first film-forming material M1 and the second After each of the oxygen gas and the first oxygen gas is supplied to the surface Sa, the purge gas is supplied to the surface Sa. As a result, the first film-forming material M1 adhering to the surface Sa of the film-forming target S heated to a predetermined temperature is oxidized by the first oxide gas and the second oxide gas on the surface Sa of the film-forming target S.

One cycle is composed of the supply of the first film-forming material M1, the supply of the purge gas, the supply of the second oxide gas, the supply of the purge gas, the supply of the first oxide gas, and the supply of the purge gas. When the aluminum oxide layer is formed on one film forming target S, such a cycle is repeated tens to hundreds of times. As a result, an aluminum oxide (Al ₂ O ₃ ) layer having a predetermined thickness is formed on the surface Sa of the film formation target S.

[Rough configuration of plasma CVD equipment]
The configuration of the plasma CVD apparatus will be described with reference to FIG. The plasma CVD apparatus described below is an apparatus for forming a silicon oxide layer by using plasma-enhanced chemical vapor deposition (PECVD).

As shown in FIG. 2, the plasma CVD apparatus 30 includes a vacuum chamber 31 having a box shape, and the vacuum chamber 31 is an introduction unit for projecting from the vacuum chamber 31 and introducing various gases into the vacuum chamber 31. 32 are connected. A support portion 33 that supports the film formation target S is located inside the vacuum chamber 31. The support portion 33 is, for example, a stage. The film-forming target S includes a surface formed of aluminum oxide as a surface on which a silicon oxide layer is formed.

A heating unit 34 is located inside the support unit 33. The heating unit 34 heats the temperature of the film forming target S supported by the support unit 33 to a predetermined temperature of 200 ° C. or higher, and more preferably to a predetermined temperature included in 250 ° C. or higher and 500 ° C. or lower.

The diffusion portion 35 is located inside the vacuum chamber 31 at a position facing the support portion 33. The diffusion unit 35 diffuses the gas supplied to the vacuum chamber 31 via the introduction unit 32 into the inside of the vacuum chamber 31. The diffuser 35 is, for example, a metal shower plate. A high-frequency power supply 36 is connected to the diffuser 35, and the diffuser 35 is also an example of an electrode to which the high-frequency power output from the high-frequency power supply 36 is supplied. The high-frequency power supply 36 supplies high-frequency power having a frequency of, for example, 27.12 MHz, to the diffuser 35. When the high-frequency power supply 36 supplies high-frequency power to the diffuser 35, plasma is generated from the gas supplied inside the vacuum chamber 31. The plasma CVD apparatus 30 may have an electrode separate from the diffusion unit 35 inside the vacuum chamber 31, and in a configuration including such an electrode, the diffusion unit 35 may be omitted.

An exhaust unit 37 that exhausts the inside of the vacuum tank 31 is connected to the vacuum tank 31. The exhaust unit 37 exhausts the inside of the vacuum chamber 31 to a predetermined pressure. The exhaust unit 37 includes, for example, an exhaust pump and a valve.

The first pipe 41 is connected to the introduction portion 32. The first pipe 41 is branched into two at a position away from the introduction unit 32, and the silicon source gas supply unit 42 is connected to one side and the oxygen-containing gas supply unit 43 is connected to the other side. The silicon source gas supply unit 42 is _{a mass flow controller that flows silane (SiH 4} ) gas to the first pipe 41 at a predetermined flow rate. As the silicon source gas, for example, tetraethoxysilane (Si (OC ₂ H ₅ ) ₄ ) (TEOS), triethoxysilane (SiH (OC ₂ H ₅ ) ₃ ) (TRIES), or the like may be used. .. Oxygen-containing gas supply unit 43 is a mass flow controller flow nitrous oxide gas (N 2 _O) in the first pipe 41 at a predetermined flow rate. As the oxygen-containing gas, for example, oxygen gas (O ₂ ), carbon monoxide gas (CO), carbon dioxide gas (CO ₂ ), or the like may be used.

In such a plasma CVD apparatus 30, silane gas is supplied into the vacuum chamber 31, and nitrous oxide gas is supplied into the vacuum chamber 31. Next, the high-frequency power supply 36 supplies high-frequency power to the diffusion unit 35, so that plasma is generated from the gas in the vacuum chamber 31. As a result, decomposition and oxidation of silane occur, so that a silicon oxide film is formed on the aluminum oxide film of the film-forming target S.

[Manufacturing method of MISFET]
A method for manufacturing a MISFET will be described with reference to FIGS. 3 to 5.
The method for forming the gate insulating film includes forming an aluminum oxide layer and forming a silicon oxide layer. Forming the aluminum oxide layer is the surface Sa included in the film formation target S, and the aluminum oxide layer is formed on the surface Sa including the region formed from the semiconductor containing gallium and the element of Group 15. To form the silicon oxide layer, the silicon oxide layer is formed on the surface of the aluminum oxide layer opposite to the surface of the film-forming target S in contact with the surface Sa. Further, forming the silicon oxide layer forms the silicon oxide layer so that a transition region containing oxygen, aluminum, and silicon is formed at the boundary between the aluminum oxide layer and the silicon oxide layer. In the transition region, the thickness in the direction in which the aluminum oxide layer and the silicon oxide layer are stacked is 4 nm or more and 10 nm or less.

That is, as shown in FIG. 3, in the method of forming the gate insulating film, first, the film formation target S including the surface Sa is prepared. The surface of the film-forming target S includes a region formed from a semiconductor containing gallium and a group 15 element. The film formation target S includes the substrate 51, the buffer layer 52 located on the substrate 51, and the gallium nitride (i-GaN) layer 53 located on the side of the buffer layer 52 opposite to the surface in contact with the substrate 51. I have.

Further, the film-forming target S is an aluminum nitride (AlN) layer 54 located on the surface of the gallium nitride layer 53 opposite to the surface in contact with the buffer layer 52, and the gallium nitride layer 53 of the aluminum nitride layer 54. It is provided with an _{aluminum gallium nitride (i-Al 0.26} GaN) layer 55 located on a surface opposite to the surface in contact with the aluminum nitride gallium nitride (i-Al 0.26 GaN).

The substrate 51 is formed of, for example, silicon, and the buffer layer 52 is formed of, for example, a gallium nitride layer and an aluminum gallium nitride layer in order from a layer in contact with the substrate 51.

Aluminum gallium nitride is a compound semiconductor containing gallium and nitrogen, which is an example of a group 15 element, and the aluminum gallium nitride layer 55 includes a region of the surface Sa formed from the semiconductor. That is, the region formed from the semiconductor contains aluminum, gallium, and nitrogen.

The region of the surface Sa formed from the semiconductor is not limited to aluminum gallium nitride, and may be formed from a semiconductor further containing either aluminum or indium in addition to gallium and Group 15 elements. Examples of such semiconductors include indium gallium nitride (InGaN) and indium gallium arsenide (InGaAs). Further, as the semiconductor, either gallium nitride (GaN) or gallium arsenide (GaAs) can be mentioned.

Further, the film formation target S includes a source electrode 56 formed in a part of the aluminum nitride gallium layer 55 and a drain electrode 57. As a material for forming the source electrode 56 and the drain electrode 57, a metal or a conductive metal compound can be used. The source electrode 56 and the drain electrode 57 are composed of, for example, a titanium (Ti) layer, an aluminum (Al) layer, a nickel (Ni) layer, and a gold (Au) layer in order from the layer in contact with the aluminum nitride gallium layer 55. ing. The outer surface of the source electrode 56 and the outer surface of the drain electrode 57 are included in the surface Sa of the film formation target S.

The aluminum oxide layer 61 is formed on the surface Sa of the film forming target S. When forming the aluminum oxide layer 61, the aluminum oxide layer 61 is formed by using the ALD method in the above-mentioned ALD device 10. The aluminum oxide layer 61 is formed so as to cover, in addition to the surface Sa of the film formation target S, the side surface of the aluminum nitride layer 54 exposed to the outside and the side surface of the aluminum nitride gallium layer 55 exposed to the outside. Will be done.

In the step of forming the aluminum oxide layer 61, a cycle composed of the following six steps is repeated as many times as the thickness of the aluminum oxide layer 61. In each cycle, the first step is a step of supplying the first film-forming material M1 to the vacuum chamber 11, the second step is a step of supplying the purge gas to the vacuum chamber 11, and the third step is the second step. This is a step of supplying the oxidation gas to the vacuum chamber 11. Further, the fourth step is a step of supplying the purge gas to the vacuum tank 11, the fifth step is a step of supplying the first oxidation gas to the vacuum tank 11, and the sixth step is a step of supplying the purge gas to the vacuum tank 11. It is a step to supply.

In the step of forming the aluminum oxide layer 61, it is preferable to form the aluminum oxide layer 61 having a thickness of 25 nm or less, which is larger than 2 nm. It is more preferable to form the aluminum oxide layer 61 having a thickness of 3 nm or more and 25 nm or less.

In the step of forming the aluminum oxide layer 61, the temperature of the film forming target S is preferably 250 ° C. or higher and 500 ° C. or lower, and the pressure in the vacuum chamber 11 is preferably 10 Pa or higher and 50 Pa or lower. Further, in the second step, the fourth step, and the sixth step, the flow rate of nitrogen gas is preferably 5 sccm or more and 50 sccm or less.

As shown in FIG. 4, the silicon oxide layer 62 is formed on the entire surface of the aluminum oxide layer 61 opposite to the surface of the film-forming target S in contact with the surface Sa. When forming the silicon oxide layer 62, the silicon oxide layer 62 is formed by using the plasma CVD method in the plasma CVD apparatus 30 described above. As a result, the gate insulating film 60 composed of the aluminum oxide layer 61 and the silicon oxide layer 62 can be obtained.

When the silicon oxide layer 62 is formed on the aluminum oxide layer 61, a transition region including at least one of the following is formed at the interface between the aluminum oxide layer 61 and the silicon oxide layer 62. That is, the transition region is a region containing oxygen, aluminum, and silicon, and is at least one of a region including an uneven surface as an interface and a mutual diffusion region between the aluminum oxide layer 61 and the silicon oxide layer 62. .. As described above, the transition region is a region containing both aluminum and silicon.

Since the transition region is at least one of the region including the uneven surface and the mutual diffusion region, the thickness of the transition region tends to exceed the lower limit value in the above range in the direction in which the aluminum oxide layer and the silicon oxide layer are stacked. Become.

The mutual diffusion region is a region including the interface between the aluminum oxide layer 61 and the silicon oxide layer 62 and the vicinity of the interface. The mutual diffusion region is a region in which silicon derived from the silicon oxide layer 62 is diffused from the silicon oxide layer 62 toward the aluminum oxide layer 61 in the aluminum oxide layer 61, and aluminum oxide in the silicon oxide layer 62. The aluminum derived from the layer 61 includes a region diffused from the aluminum oxide layer 61 toward the silicon oxide layer 62. When the transition region is a mutual diffusion region, the thickness of the transition region is the thickness of the mutual diffusion region.

On the other hand, when the transition region is a region including an uneven surface, the thickness of the transition region is the portion of the uneven surface that protrudes from the aluminum oxide layer 61 toward the silicon oxide layer 62 and the silicon oxide. This is the maximum value of the difference from the portion protruding from the layer 62 toward the aluminum oxide layer 61. Further, when the transition region is a mutual diffusion region and is a region including an uneven surface, a larger value among the thicknesses of the transition regions defined by each region can be set as the thickness of the transition region. ..

As described above, the thickness of the transition region is preferably 4 nm or more and 10 nm or less, and preferably 4 nm or more and 7 nm or less. Electron energy loss spectroscopy (EELS) is used to determine the types of atoms contained in the transition region, the proportion of each atom in the transition region, and the thickness of the transition region in the direction in which the aluminum oxide layer 61 and the silicon oxide layer 62 are stacked. Can be analyzed.

To form the silicon oxide layer 62, ^{it is preferable to supply electric power of 0.2 W / cm 2} or less to the diffusion unit 35, which is an example of the electrode. When the electric power supplied to the diffusion unit 35 is 0.2 W / cm ² or less, the certainty that the thickness of the transition region becomes 4 nm or more is increased.

Since the aluminum oxide layer 61 and the silicon oxide layer 62 having smaller defects in the film per unit volume than the aluminum oxide layer 61 are laminated, the thickness of the aluminum oxide layer 61 is larger than that when the aluminum oxide layer 61 is used alone. Even if the size is reduced, the desired insulating strength can be obtained by the gate insulating film 60. As a result, the defects in the film of the aluminum oxide layer 61 can be reduced by the amount that the volume of the aluminum oxide layer 61 is reduced, and as a result, the voltage is repeatedly applied to the film-forming target S via the gate insulating film 60. At that time, the fluctuation of the threshold voltage can be suppressed.

The defects in the film of the aluminum oxide layer 61 and the insulating film formed on the aluminum oxide layer 61 are caused by the defect structure due to impurities in the film such as carbon (C) and hydrogen (H). Defects in the membrane in each membrane can be evaluated by analytical methods such as SIMS, XPS, and FTIR.

In the step of forming the silicon oxide layer 62, it is preferable to form the silicon oxide layer 62 having a thickness of 10 nm or more and 50 nm or less.
In the step of forming the silicon oxide layer 62, the temperature of the film forming target S is preferably 250 ° C. or higher and 500 ° C. or lower, and the pressure in the vacuum chamber 11 is preferably 50 Pa or higher and 300 Pa or lower, and a high-frequency power source. 36 standard value of the power supplied to the spreading section 35 is preferably 0.024W / cm ² or more 0.2 W / cm ² or less. The flow rate of silane gas is preferably 5 sccm or more and 100 sccm or less. The flow rate of nitrous oxide gas is preferably 50 sccm or more and 1000 sccm or less.

As described above, when the gate insulating film 60 is formed, the aluminum oxide layer 61 is formed by using the ALD method, and the silicon oxide layer 62 is formed by using the plasma CVD method. Therefore, the aluminum oxide layer 61 with suppressed variation in thickness can be formed on the surface Sa of the film formation target S, and the film formation target is compared with the case where plasma is used to form the aluminum oxide layer 61. Damage to the surface Sa of S is suppressed. When the silicon oxide layer 62 is formed, the surface Sa of the film forming target S is covered with the aluminum oxide layer 61. Therefore, when the silicon oxide layer 62 is formed, the film forming target S is exposed to plasma. , The interface between the gate insulating film 60 and the surface Sa formed of the semiconductor is prevented from being damaged.

As shown in FIG. 5, the gate electrode 63 is formed on the gate insulating film 60 between the source electrode 56 and the drain electrode 57 in a plan view facing the surface Sa of the film forming target S. As the material for forming the gate electrode 63, a metal or a conductive metal compound can be used. The gate electrode 63 is composed of, for example, a gold (Au) layer, a titanium (Ti) layer, and a platinum (Pt) layer in order from the layer in contact with the gate insulating film 60. Next, in the thickness direction of the film formation target S, the portion of the gate insulating film 60 that overlaps with the source electrode 56 and the portion that overlaps with the drain electrode 57 are removed.

Then, the source wiring pad 64 is formed in the portion of the source electrode 56 exposed from the gate insulating film 60, and the gate wiring pad 65 is provided on the surface of the gate electrode 63 opposite to the surface in contact with the gate insulating film 60. The drain wiring pad 66 is formed in the portion of the drain electrode 57 exposed from the gate insulating film 60. As the material for forming each wiring pad, a metal or a conductive metal compound can be used. Each wiring pad is composed of, for example, a gold layer and a titanium layer in order from a layer in contact with each electrode. As a result, the MISFET 70 can be obtained.

In such a MISFET 70, the gate insulating film 60 includes an aluminum oxide layer 61 and a silicon oxide layer 62. The aluminum oxide layer 61 is located on the surface of the aluminum nitride gallium layer 55 containing gallium and Group 15 atoms. The silicon oxide layer 62 is located in the aluminum oxide layer 61 on a surface opposite to the surface in contact with the aluminum nitride gallium layer 55. The region including the boundary between the aluminum oxide layer 61 and the silicon oxide layer 62 is a transition region containing oxygen, aluminum, and silicon. The width of the transition region in the direction in which the aluminum oxide layer 61 and the silicon oxide layer 62 are stacked is 4 nm or more and 10 nm or less. The transition region includes at least one of a region including an uneven surface as a boundary between the aluminum oxide layer 61 and the silicon oxide layer 62 and a mutual diffusion region between the aluminum oxide layer 61 and the silicon oxide layer 62.

[Test example]
A test example will be described with reference to FIGS. 6 to 15.
[Test Example 1]
In order to form the MISFET of Test Example 1, a film forming object having the following configuration was prepared. That is, a buffer layer, an i-type gallium nitride layer, an aluminum nitride layer, and an i-type aluminum gallium nitride layer are laminated in this order on one surface of the silicon substrate, and the source electrode is placed on the aluminum gallium nitride layer. A film-forming object having a drain electrode and a drain electrode was prepared. As the buffer layer, a gallium nitride layer and an aluminum gallium nitride layer were formed in order from the layer in contact with the silicon substrate. Further, as each of the source electrode and the drain electrode, an electrode composed of a titanium layer, an aluminum layer, a nickel layer, and a gold layer was formed in order from the layer in contact with the aluminum nitride gallium layer.

A silicon substrate having a thickness of 500 μm was prepared, and the buffer layer was formed so that the total thickness of the laminated body of the gallium nitride layer and the aluminum gallium nitride layer, which are the buffer layers, was 5 μm. Further, the i-type gallium nitride layer was formed with a thickness of 1 μm, the aluminum nitride layer was formed with a thickness of 1 nm, and the i-type aluminum gallium nitride layer was formed with a thickness of 25 nm.

Then, by repeating the cycle consisting of the following six steps 210 times, an aluminum oxide film having a thickness of 20 nm was formed by using the ALD method. The duration of each step was set as follows.

[ALD cycle]
・ 1st step 1st film formation material M1 supply 0.02 seconds ・ 2nd step purge gas supply 5 seconds ・ 3rd step 2nd oxide gas supply 0.02 seconds ・ 4th step purge gas supply 5 seconds ・ 4th step 5 steps 1st oxidation gas supply 0.2 seconds ・ 6th step purge gas supply 10 seconds

In the second step, the fourth step, and the sixth step, the flow rate of the purge gas was set to 20 sccm. Further, from the first step to the sixth step, the pressure in the vacuum chamber was set to 30 Pa, and the temperature of the film forming target was set to 300 ° C.

Next, a gate insulating film composed of the aluminum oxide layer and the silicon oxide layer was formed by forming a silicon oxide layer having a thickness of 20 nm on the aluminum oxide layer by using the plasma CVD method. At this time, the flow rate of silane gas was set to 10 sccm, and the flow rate of nitrous oxide gas was set to 500 sccm. Further, the pressure in the vacuum chamber was set to 100 Pa, the temperature of the film forming target was set to 350 ° C, and the output of the high frequency power supply was set to 0.48 W / cm ² .

Then, the gate electrode was formed by the gold layer, the titanium layer, and the platinum layer, and the portion of the gate insulating film overlapping the source electrode and the portion overlapping the drain electrode in the thickness direction of the film formation target were removed. .. Next, a source wiring pad connected to the source electrode, a gate wiring pad connected to the gate electrode, and a drain wiring pad connected to the drain electrode were formed of a gold layer and a titanium layer, respectively. As a result, the MISFET of Test Example 1 was obtained.

[Test Example 2]
The MISFET of Test Example 2 was obtained by the same method as that of Test Example 1 except that the output of high frequency power ^{was set to 0.24 W / cm 2 when the silicon oxide layer was formed.}

[Test Example 3]
The MISFET of Test Example 3 was obtained by the same method as that of Test Example 1 except that the output of high frequency power ^{was set to 0.12 W / cm 2 when the silicon oxide layer was formed.}

[Test Example 4]
The MISFET of Test Example 4 was obtained by the same method as that of Test Example 1 except that the output of high frequency power ^{was set to 0.048 W / cm 2 when the silicon oxide layer was formed.}

[Measurement of threshold voltage]
In the MISFETs of Test Examples 1 to 4, when a DC voltage is applied to the gate electrode, the voltage value is changed from -20V to 8V, and the drain current (mA / mm) is changed in the range of -20V to 8V. Was measured. In the MISFET of each test example, the drain current when the voltage was first applied to the gate electrode and the drain current when the voltage was applied to the gate electrode a second time were measured. In the MISFET of each test example, ^{the gate voltage when the drain current was 10-6} mA / mm was set as the threshold voltage.

The measurement results of the drain current in the MISFET of each test example were as shown in FIGS. 6 to 9. In FIGS. 6 to 9, the drain current when the voltage is applied to the gate electrode for the second time, that is, the value finally converged in the drain current in each test example is shown by a solid line.

As shown in FIG. 6, in the MISFET of Test Example 1, the threshold voltage was found to be −9.7V. As shown in FIG. 7, in the MISFET of Test Example 2, it was confirmed that the threshold voltage was −9.1 V. As shown in FIG. 8, in the MISFET of Test Example 3, the threshold voltage was found to be −5.4V. As shown in FIG. 9, in the MISFET of Test Example 4, the threshold voltage was found to be -4.3V.

As described above, according to the MISFETs of Test Examples 1 to 4, it was confirmed that the smaller the high frequency power supplied to the diffusing portion when forming the silicon oxide layer, the closer the threshold voltage approaches to 0V.

[Transition area]
[Test Example 5]
By forming a MISFET having the structure described above with reference to FIG. 5, the MISFET of Test Example 5 was obtained. When the aluminum oxide layer of the MISFET of Test Example 5 is formed, the conditions are the same as when the aluminum oxide layer is formed in Test Example 1 described above, and when the silicon oxide layer is formed, oxidation is carried out in Test Example 1 described above. The conditions were the same as when the silicon layer was formed. Further, the aluminum oxide layer was formed with a thickness of 20 nm, and the silicon oxide layer was formed with a thickness of 20 nm. As the gate electrode, a laminated body in which a gold layer, a titanium layer, and a platinum layer were laminated was formed.

A TEM image obtained by photographing a part of the cross-sectional structure of the MISFET of Test Example 5 with a transmission electron microscope (TEM) (JEM-ARM200F, manufactured by JEOL Ltd.) was as shown in FIG. When the TEM image was taken, the acceleration voltage was set to 80 kV and the magnification was set to 2,000,000 times.

FIG. 10 is a TEM image of a portion in which the aluminum gallium nitride layer, the aluminum oxide layer, the silicon oxide layer, and the gate electrode are stacked in the cross section of the MISFET of Test Example 5 along the thickness direction. As shown in FIG. 10, in the MISET of Test Example 5, it was confirmed that the boundary between the aluminum oxide layer and the silicon oxide layer was almost flat.

Elemental analysis was performed on the laminate of Test Example 5 by energy loss spectroscopy (EELS) using a transmission electron microscope (same as above) and an elemental analyzer (Quantum ER, manufactured by Gatan) (Quantum is a registered trademark). .. In the transmission electron microscope, the acceleration voltage was set to 80 kV and the beam diameter was set to about 0.1 nm. Further, in the elemental analyzer, the number of measurement points was set to 100 points, the uptake time per point was set to about 3 seconds, and oxygen, aluminum, and silicon were set as measurement elements. In addition, elemental analysis of the laminate was performed from the silicon oxide layer to the aluminum oxide layer. The results of the elemental analysis were as shown in FIG.

As shown in FIG. 11, in the transition region, that is, the region including the boundary between the silicon oxide layer and the aluminum oxide layer, and the region containing oxygen, aluminum, and silicon, the silicon oxide layer and the aluminum oxide layer are formed. It was found to have a thickness of 3 nm in the stacking direction.

[Test Example 6]
By forming a MISFET having the structure described above with reference to FIG. 5, the MISFET of Test Example 6 was obtained. When the aluminum oxide layer of the MISFET of Test Example 6 is formed, the conditions are the same as when the aluminum oxide layer is formed in Test Example 4 described above, and when the silicon oxide layer is formed, oxidation is carried out in Test Example 4 described above. The conditions were the same as when the silicon layer was formed. Further, the aluminum oxide layer was formed with a thickness of 20 nm, and silicon oxide was formed with a thickness of 20 nm. As the gate electrode, a laminated body in which a gold layer, a titanium layer, and a platinum layer were laminated was formed.

The TEM image obtained by capturing a part of the cross-sectional structure of the MISFET of Test Example 6 with a transmission electron microscope (same as above) was as shown in FIG. The conditions when the TEM image was imaged were set to the same conditions as when the TEM image was imaged in the laminated body of Test Example 5.

FIG. 12 is a TEM image of a portion in which the aluminum gallium nitride layer, the aluminum oxide layer, the silicon oxide layer, and the gate electrode are stacked in the cross section of the MISFET of Test Example 6 along the thickness direction. As shown in FIG. 12, in the MISFET of Test Example 6, it was found that the boundary between the aluminum oxide layer and the silicon oxide layer was lower in flatness than the boundary in the laminate of Test Example 5.

Elemental analysis of the laminate of Test Example 6 was performed by energy loss spectroscopy. The elemental analysis of the laminate of Test Example 6 was performed under the same conditions as the elemental analysis of the laminate of Test Example 5. The result of elemental analysis was as shown in FIG.

As shown in FIG. 13, it was found that the transition region had a thickness of 7 nm in the direction in which the silicon oxide and the aluminum oxide layer were stacked. That is, it was found that the thickness of the transition region in the laminated body of Test Example 6 was larger than the thickness of the transition region in the laminated body of Test Example 5.

Further, the transition region contains aluminum and silicon, and the boundary between the aluminum oxide layer and the silicon oxide layer in Test Example 5 is flatter than the boundary between the aluminum oxide layer and the silicon oxide layer in Test Example 6. Is low, it can be said that the transition region includes at least one of the following. That is, the transition region includes at least one of the uneven surface which is the boundary between the aluminum oxide layer and the silicon oxide layer and the mutual diffusion region between the aluminum oxide layer and the silicon oxide layer.

[Relationship between high frequency power and characteristics of MISFET]
The MOSFET was formed while changing the magnitude of the high-frequency power supplied to the diffuser when the silicon oxide layer was formed. Then, in each MOSFET, the thickness of the transition region along the thickness direction of the aluminum oxide layer and the silicon oxide layer was measured. In addition, the threshold voltage was measured in each MOSFET. Each MISFET was obtained under the same conditions as when the MISFET of Test Example 1 described above was obtained, except that the high-frequency power supplied to the diffusing part was changed when the silicon oxide layer was formed. The result of measuring the thickness of the transition region is as shown in FIG. 14, and the result of measuring the threshold voltage is as shown in FIG.

As shown in FIG. 14, the magnitude of the high-frequency power supplied to the spreading unit, was gradually smaller toward the 0.48 W / cm ² to 0.024W / cm ^2, a high frequency power is 0.2 W / cm ² or less As a result, it was confirmed that the thickness of the transition region including the boundary between the aluminum oxide layer and the silicon oxide layer suddenly increased. The magnitude of high-frequency power is 0.48 / c.
The thickness of the diffusion region when a m ² is 3 nm, the thickness of the diffusion region when the magnitude of the high frequency power is 0.024W / cm ² was found to be 7.2 nm.

As shown in FIG. 15, the magnitude of the high-frequency power supplied to the spreading unit, was gradually smaller toward the 0.48 W / cm ² to 0.024W / cm ^2, a high frequency power is 0.2 W / cm ² or less It was confirmed that the absolute value of the threshold voltage was sharply reduced. The threshold voltage when the magnitude of the high frequency power is 0.48 W / cm ² is -9.7 V, and the threshold voltage when the magnitude of the high frequency power is 0.024 W / cm ² is -3. It was found to be 9V.

As described above, according to the method for forming the gate insulating film and one embodiment of the gate insulating film, the effects listed below can be obtained.
(1) Since the thickness of the transition region is 4 nm or more and 10 nm or less in the direction in which the aluminum oxide layer 61 and the silicon oxide layer 62 are stacked, the absolute value of the threshold voltage at the gate electrode may increase in the negative range. It can be suppressed. As described above, the laminated film in which the aluminum oxide layer 61 and the silicon oxide layer 62 are laminated can have a suitable configuration when used as a gate insulating film.

(2) When the silicon oxide layer 62 is formed, the aluminum nitride gallium layer 55 located under the gate insulating film 60 is covered with the aluminum oxide layer 61, so that the silicon oxide layer 62 is formed by the plasma CVD method. Also, damage to the aluminum nitride gallium layer 55 is suppressed.
(3) When the high-frequency power supplied to the diffusion unit 35 is 0.2 W / cm ² or less, the certainty that the thickness of the transition region becomes 4 nm or more is increased.

(4) Since the transition region is at least one of the region including the uneven surface and the mutual diffusion region, the thickness of the transition region is in the above-mentioned range in the direction in which the aluminum oxide layer 61 and the silicon oxide layer 62 are stacked. It is easy to exceed the lower limit.

The above-described embodiment can be appropriately modified and implemented as follows.
The aluminum oxide layer 61 is not limited to the ALD method described above, but may be formed by a CVD method, a vacuum vapor deposition method, a sputtering method, or the like. Further, the silicon oxide layer 62 is not limited to the plasma CVD method described above, and may be formed by a thermal CVD method, an ALD method, a vacuum vapor deposition method, a sputtering method, or the like. Even with such a configuration, as long as the gate insulating film 60 is composed of the aluminum oxide layer 61 and the silicon oxide layer 62 and has a transition region having a thickness of 4 nm or more and 10 nm or less, it is described above (1). ) Can be obtained.

10 ... ALD device, 11, 31 ... Vacuum tank, 12, 33 ... Support part, 13, 34 ... Heating part, 14, 37 ... Exhaust part, 21, 41 ... First piping, 21a ... First valve, 22 ... No. 2 pipes, 22a ... 2nd valve, 23 ... 3rd pipe, 23a ... 3rd valve, 24 ... 4th pipe, 24a ... 4th valve, 25 ... 1st storage, 26 ... 2nd storage, 27 ... 1 temperature control section, 28 ... second temperature control section, 30 ... plasma CVD device, 32 ... introduction section, 35 ... diffusion section, 36 ... high frequency power supply, 42 ... silicon source gas supply section, 43 ... oxygen-containing gas supply section, 51 ... Substrate, 52 ... Buffer layer, 53 ... Gallium nitride layer, 54 ... Aluminum nitride layer, 55 ... Aluminum gallium nitride layer, 56 ... Source electrode, 57 ... Drain electrode, 60 ... Gate insulating film, 61 ... Aluminum oxide layer, 62 ... Silicon oxide layer, 63 ... Gate electrode, 64 ... Source wiring pad, 65 ... Gate wiring pad, 66 ... Drain wiring pad, 70 ... MISFET, M1 ... First film forming material, S ... Film forming target, Sa ... Surface ..

Claims (5)

To form an aluminum oxide layer on the surface included in the film formation target, which includes a region formed of a semiconductor containing gallium and nitrogen.
Including forming a silicon oxide layer on a surface of the aluminum oxide layer opposite to the surface in contact with the surface.
The formation of the silicon oxide layer is a transition region containing oxygen, aluminum, and silicon at the boundary between the aluminum oxide layer and the silicon oxide layer, and the aluminum oxide layer and the silicon oxide layer are formed. A method for forming a gate insulating film that forms the silicon oxide layer so that the transition region having a thickness of 4 nm or more and 10 nm or less in the stacking direction is formed. To form the aluminum oxide layer, the aluminum oxide layer is formed by using the ALD method.
The method for forming a gate insulating film according to claim 1, wherein the silicon oxide layer is formed by using a plasma CVD method. The method for forming a gate insulating film according to claim 2, wherein the silicon oxide layer is formed by ^{supplying electric power of 0.2 W / cm 2 or less to the electrode.} An aluminum oxide layer located on the surface of a semiconductor layer containing gallium and nitrogen,
The aluminum oxide layer includes a silicon oxide layer located on a surface opposite to the surface in contact with the surface.
The region including the boundary between the aluminum oxide layer and the silicon oxide layer is a transition region containing oxygen, aluminum, and silicon.
A gate insulating film in which the width of the transition region in the direction in which the aluminum oxide layer and the silicon oxide layer are stacked is 4 nm or more and 10 nm or less. According to claim 4, the transition region is at least one of a region including an uneven surface as a boundary between the aluminum oxide layer and the silicon oxide layer and a mutual diffusion region between the aluminum oxide layer and the silicon oxide layer. The gate insulating film described.

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