JP6932611B2 - Semiconductor devices and manufacturing methods for semiconductor devices - Google Patents

Description

The techniques disclosed herein relate to semiconductor devices and methods of manufacturing semiconductor devices.

Semiconductor devices to which a high voltage is applied are required to provide protection against short circuits. In the technique of Patent Document 1, a semiconductor resistance region is provided in the source region and the source resistance is increased to suppress the saturation current and improve the short-circuit tolerance.

Japanese Unexamined Patent Publication No. 2015-95578

In the technique of Patent Document 1, an increase in source resistance leads to an increase in on-resistance. In addition, since the area of the source region becomes large, miniaturization becomes difficult. It is an object of the present specification to improve the protection performance against a short circuit and to provide a highly reliable semiconductor device.

One embodiment of the semiconductor device disclosed herein comprises a first conductive drain region. It is provided with a first conductive type drift region in contact with the upper surface of the drain region. It includes a second conductive body region that is in contact with the upper surface of the drift region and is arranged on a part of the upper surface of the drift region. It includes a first conductive type gate electrode region having a boundary region with a body region. It has a gate insulating film arranged in a part of the boundary region. It comprises a first conductive source region located above the body region. In the boundary region, in the region where the gate insulating film is arranged, the body region and the gate electrode region are in contact with each other via the gate insulating film. In the boundary region, the body region and the gate electrode region are in direct contact with each other in a specific region in which the gate insulating film is not arranged.

In the semiconductor device of the above embodiment, the gate electrode region and the body region form a pn junction in a specific region. Therefore, in the normal operating temperature range, the leakage current flowing from the gate electrode region to the source region via the body region can be made negligibly small. However, in the short-circuit state, the leak current increases exponentially because the temperature rises beyond the permissible range. As a result of the potential difference between the gate electrode region and the body region becoming smaller than the gate threshold voltage due to the voltage drop due to the leak current, the semiconductor device can be automatically turned off. It becomes possible to improve the protection performance against a short circuit.

The gate electrode region may include a high-concentration gate electrode region having a high impurity concentration and a low-concentration gate electrode region having a low impurity concentration. In the specific region, the low concentration gate electrode region may be in contact with the body region. Details of the effect will be described in Examples.

The gate insulating film may include a first contact surface which is a contact surface with the body region and a second contact surface which is a contact surface with the gate electrode region. The contact surface of the low-concentration gate electrode region with the body region may be located in the same plane as the first contact surface. The contact surface of the low-concentration gate electrode region with the gate electrode region may be located in the same plane as the second contact surface. Details of the effect will be described in Examples.

The gate electrode region may reach from the upper surface of the body region to the drift region. The gate insulating film may be arranged on the entire surface of the boundary between the gate electrode region and the drift region. The specific region may be arranged on the first side surface of the gate electrode region. The source region may be located in the vicinity of the second side surface opposite the first side surface of the gate electrode region. Details of the effect will be described in Examples.

An inhibitory region that inhibits the formation of the inversion layer may be provided at a position within the body region and below the specific region and at a position in contact with the gate insulating film. Details of the effect will be described in Examples.

An inhibitory region that inhibits the formation of the inversion layer may be provided at a position within the drift region, a position at the bottom of the gate electrode region, and a position in contact with the gate insulating film. Details of the effect will be described in Examples.

The inhibition region may be a second conductive type region having a higher impurity concentration than the body region. Details of the effect will be described in Examples.

The inhibition region may be an insulator. Details of the effect will be described in Examples.

The body region may include a first body region and a second body region. A drift region may be arranged in the opening region between the first body region and the second body region. The source region may be arranged on the upper surface of the first body region and may be arranged horizontally away from the opening region. The gate electrode region may be in contact with the source region, the first body region, the drift region in the opening region, and the upper surface of the second body region via the gate insulating film. The specific region may be arranged at a position horizontally separated from the opening region within the boundary region between the second body region and the gate electrode region. Details of the effect will be described in Examples.

An inhibitory region that inhibits the formation of the inversion layer may be provided at a position within the second body region, which is closer to the opening region than the specific region and is in contact with the gate insulating film. Details of the effect will be described in Examples.

The distance from the position closest to the drift region of the specific region to the drift region may be a distance at which the depletion layer extending from the pn junction formed in the specific region does not reach the drift region. Details of the effect will be described in Examples.

The crystal defect density of the body region in the vicinity region of the specific region may be higher than the crystal defect density of the other body region. Details of the effect will be described in Examples.

Further, a source electrode region that is in common contact with the upper surface of the plurality of source regions may be provided. When the source electrode region is viewed from above, a specific region may be arranged in the central portion of the source electrode region. Details of the effect will be described in Examples.

The method for manufacturing a semiconductor device disclosed in the present specification includes a step of forming a first conductive type drift region on the upper surface of the first conductive type drain region. A step of forming a second conductive type body region on the upper surface of the drift region is provided. A step of forming a trench reaching from the upper surface of the body region to the drift region is provided. A step of forming a gate insulating film on the inner wall of the trench is provided. A step of forming a first conductive type gate electrode inside the trench is provided. A step of removing the gate insulating film arranged on one side surface of the trench from the upper surface of the body region to the upper side of the lower surface of the body region is provided. A step of embedding a low-concentration gate electrode which is a first conductive type and has a lower impurity concentration than the gate electrode is provided in the region from which the gate insulating film has been removed. A step of forming a first conductive type source region is provided on the upper part of the body region. Details of the effect will be described in Examples.

By driving impurities from the upper surface of the body region, the impurity concentration is higher than that of the body region at a position within the body region and below the lower end of the low-concentration gate electrode and in contact with the gate insulating film. A step of forming a high second conductive type region may be further provided. Details of the effect will be described in Examples.

The method for manufacturing a semiconductor device disclosed in the present specification includes a step of forming a first conductive type drift region on the upper surface of the first conductive type drain region. A step of forming a second conductive type first body region and a second body region on the upper surface of the drift region is provided so that the drift region is arranged in the opening region between the first body region and the second body region. .. A step of forming a source region which is arranged on the upper surface of the first body region and is arranged horizontally apart from the opening region is provided. A step of forming a gate insulating film on the upper surface of the source region, the first body region, the drift region in the opening region, and the second body region is provided. A step of removing the gate insulating film is provided in the second body region and in a region horizontally separated from the opening region. A step of embedding a first conductive type low-concentration gate electrode in the region from which the gate insulating film has been removed is provided. A step of forming a first conductive type gate electrode having a higher impurity concentration than the low-concentration gate electrode is provided on the upper surface of the gate insulating film and the low-concentration gate electrode. Details of the effect will be described in Examples.

By driving impurities into the second body region, impurities are placed in the second body region, closer to the opening region than the low-concentration gate electrode, and in contact with the gate insulating film, than in the second body region. A step of forming a second conductive type region having a high concentration may be further provided. Details of the effect will be described in Examples.

The cross-sectional view of the main part of the semiconductor device of Example 1 is schematically shown. It is a top view of the semiconductor device of Example 1. FIG. It is a flowchart which shows the manufacturing method of the semiconductor device of Example 1. It is a figure which shows the manufacturing process of the semiconductor device of Example 1. It is a figure which shows the manufacturing process of the semiconductor device of Example 1. It is a figure which shows the manufacturing process of the semiconductor device of Example 1. It is a figure which shows the equivalent circuit of the semiconductor device of Example 1. It is a figure which shows the comparative example of the semiconductor device of Example 1. The cross-sectional view of the main part of the semiconductor device of Example 2 is schematically shown. It is a flowchart which shows the manufacturing method of the semiconductor device of Example 2. It is a figure which shows the comparative example of the semiconductor device of Example 1. The cross-sectional view of the main part of the semiconductor device of the modification of Example 1 is schematically shown. The cross-sectional view of the main part of the semiconductor device of the modification of Example 1 is schematically shown.

As shown in the cross-sectional view of the main part of FIG. 1, the semiconductor device 1 is a power semiconductor element called a MOSFET. The semiconductor device 1 is a trench gate type. The semiconductor device 1 includes a semiconductor substrate 10, a drain electrode 22 that covers the back surface of the semiconductor substrate 10, a source electrode 24 that covers the surface of the semiconductor substrate 10, and a trench-type insulated gate portion provided on the surface layer of the semiconductor substrate 10. 30 is provided.

The semiconductor substrate 10 is a substrate made of silicon carbide (SiC) as a material. It has an n ⁺ type drain region 11, an n ⁻ type drift region 12, a p type body region 13, an n ⁺ type source region 15 and a p ⁺ type inhibition region 16. The drain region 11, the drift region 12, the body region 13, and the source region 15 are arranged in this order along the thickness direction of the semiconductor substrate 10.

The drain region 11 is arranged on the back layer portion of the semiconductor substrate 10 and is exposed on the back surface of the semiconductor substrate 10. The drain region 11 is also a base substrate for epitaxially growing the drift region 12. The drain region 11 makes ohmic contact with the drain electrode 22 that coats the back surface of the semiconductor substrate 10. In one example, the drain region 11 may have a thickness of about 1 to 300 μm and an impurity concentration of about 1 × 10 ¹⁸ to 1 × 10 ²³ cm ^-3 .

The drift region 12 is provided on the drain region 11. The drift region 12 is in contact with the side surface of the insulated gate portion 30. The drift region 12 is formed by crystal growth from the surface of the drain region 11 by utilizing an epitaxial growth technique. In one example, the drift region 12 may have a thickness of about 5 to 200 μm and an impurity concentration of about 1 × 10 ¹³ to 1 × 10 ¹⁷ cm ^-3 .

The body region 13 is provided on the drift region 12 and is arranged on the surface layer portion of the semiconductor substrate 10. The body region 13 is in contact with the side surface of the insulated gate portion 30. The body region 13 is formed by crystal growth from the surface of the drift region 12 by utilizing an epitaxial growth technique. The body region 13 comes into contact with the source electrode 24 that coats the surface of the semiconductor substrate 10. In one example, the body region 13 may have a thickness of about 1-5 μm and an impurity concentration of about 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ^-3 .

The source region 15 is arranged near the left side surface of the gate electrode 34. The source region 15 is provided on the body region 13, is arranged on the surface layer portion of the semiconductor substrate 10, and is exposed on the surface of the semiconductor substrate 10. The source region 15 is separated from the drift region 12 by the body region 13. The source region 15 is in contact with the side surface of the insulated gate portion 30. The source region 15 is formed by introducing nitrogen or phosphorus into the surface layer portion of the semiconductor substrate 10 by using an ion implantation technique. The source region 15 makes ohmic contact with the source electrode 24 that coats the surface of the semiconductor substrate 10.

The insulated gate portion 30 extends from the surface of the semiconductor substrate 10 toward the deep portion. The insulated gate portion 30 has a gate insulating film 32, a gate electrode 34, and a low concentration gate electrode 35. The insulated gate portion 30 is provided in the trench 30T that penetrates the source region 15 and the body region 13 and penetrates a part of the drift region 12. The gate insulating film 32 is made of silicon oxide. The gate insulating film 32 is arranged on the entire surface of the boundary between the gate electrode 34 and the drift region 12. Further, on the left side surface of the trench 30T, the gate insulating film 32 is arranged at the boundary between the gate electrode 34 and the body region 13 and the boundary between the gate electrode 34 and the source region 15. Further, on the right side surface of the trench 30T, the gate insulating film 32 is arranged in a part of the boundary region R1 between the gate electrode 34 and the body region 13. An insulating film 36 for ensuring insulation from the source electrode 24 is arranged on the upper surfaces of the gate electrode 34 and the low-concentration gate electrode 35.

The gate electrode 34 is made of n ⁺ type polysilicon having a high impurity concentration. The low-concentration gate electrode 35 is made of n ^- type polysilicon having a low impurity concentration. In one example, the gate electrode 34 may have an impurity concentration of about 1 × 10 ¹⁸ to 1 × 10 ²³ cm ^-3 . Further, the low-concentration gate electrode 35 may have an impurity concentration of about 1 × 10 ¹³ to 1 × 10 ¹⁷ cm ^-3 . The low-concentration gate electrode 35 is arranged on the right side surface of the gate electrode 34. That is, they are arranged on the side surface opposite to the source region 15 with the gate electrode 34 interposed therebetween. The low-concentration gate electrode 35 is arranged in the boundary region R1 in a specific region in which the gate insulating film 32 is not arranged. That is, the contact surface between the low-concentration gate electrode 35 and the body region 13 is located in the same plane as the first contact surface C1, which is the contact surface between the gate insulating film 32 and the body region 13. The contact surface between the low-concentration gate electrode 35 and the gate electrode 34 is located in the same plane as the second contact surface C2, which is the contact surface between the gate insulating film 32 and the gate electrode 34. In the boundary region R1 where the gate insulating film 32 is arranged, the inhibition region 16 and the gate electrode 34 are in contact with each other via the gate insulating film 32. Further, in the specific region where the gate insulating film 32 is not arranged, the body region 13 and the low-concentration gate electrode 35 are in direct contact with each other. In other words, the specific region is a region in which the low-concentration gate electrode 35 is arranged instead of the gate insulating film 32.

An inhibition region 16 is arranged in the body region 13. The inhibition region 16 is arranged at a position below the low-concentration gate electrode 35 and in contact with the gate insulating film 32. The inhibition region 16 is composed of ^{p +} type polysilicon having a higher impurity concentration than the body region 13. The impurity concentration in the inhibition region 16 may be sufficiently high so that an inversion layer is not formed in the inhibition region 16 when a gate voltage for turning on the semiconductor device 1 is applied. In one example, the inhibition region 16 may have an impurity concentration of about 1 × 10 ¹⁹ to 1 × 10 ²³ cm ^-3 .

The distance from the position closest to the drift region 12 (that is, the lower end portion) of the low-concentration gate electrode 35 to the drift region 12 is the distance t1. This distance t1 is determined so that the depletion layer extending from the pn junction between the low-concentration gate electrode 35 and the body region 13 does not reach the drift region 12. In other words, the distance t1 is determined so that a leak path due to the depletion layer is not formed between the low concentration gate electrode 35 and the drift region 12. That is, the distance t1 may be determined so as to satisfy the following equation 1.
t1> (2εVg / qNid) −d ・ ・ ・ (Equation 1)
Here, the electric field layer width is d, the electric field layer concentration is Ni, the gate-on voltage is Vg, the elementary charge is q, and the dielectric constant of the semiconductor substrate is ε.

FIG. 2 shows a schematic top view of the semiconductor device 1. The cross-sectional view of the main part of FIG. 1 shows the cross section of the I-I portion in FIG. A source electrode 24 and a gate electrode pad 37 are arranged on the upper surface of the semiconductor substrate 10. The source electrode 24 is in common contact with the upper surfaces of the plurality of source regions 15. A plurality of the above-mentioned insulated gate portions 30 are arranged below the source electrode 24. In FIG. 2, the insulated gate portion 30 is shown by a dotted line. The gate electrode pad 37 is commonly connected to the gate electrodes 34 provided in the plurality of insulated gate portions 30 by a wiring (not shown).

In FIG. 2, a central region R10 exists in the central portion of the source electrode 24. The low-concentration gate electrode 35 described above is arranged only in the central region R10. This is because the temperature of the central portion of the source electrode 24 is highest during the operation of the semiconductor device 1. By forming the low-concentration gate electrode 35 only in the central region R10 where the maximum temperature is reached, the thermostat-like function described later can be exhibited. Further, since the region in which the low-concentration gate electrode 35 is arranged does not function as a current path, the on-resistance of the semiconductor device 1 increases as the area of the low-concentration gate electrode 35 increases. By arranging the low-concentration gate electrode 35 only in the required region, it is possible to suppress an increase in the on-resistance and improve the protection performance against a short circuit at the same time.

The operation of the semiconductor device 1 will be described. When a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and the gate electrode 34 of the insulated gate portion 30 is grounded, the semiconductor device 1 is turned off. When a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and a voltage that is more positive than the source electrode 24 is applied to the gate electrode 34 of the insulated gate portion 30, the gate electrode 34 and the body region 13 face each other. An inversion layer R11 (FIG. 1) is formed in the portion. The semiconductor device 1 is turned on.

(Manufacturing method of semiconductor device 1)
A method of manufacturing the semiconductor device 1 will be described with reference to FIGS. 3 to 6. In step S1 of the flowchart of FIG. 3, a laminated structure is formed in which the drift region 12 and the body region 13 are laminated on the drain region 11. In step S2, the trench 30T reaching from the upper surface of the body region 13 to the drift region 12 is machined using lithography and dry etching. In step S3, the gate insulating film 32 is formed on the inner wall of the trench 30T. In step S4, the gate electrode 34 is embedded in the trench 30T. As a result, the structure shown in FIG. 4 is formed.

In step S5, a specific region in which the gate insulating film 32 is not arranged is formed. Specifically, as shown in FIG. 5, a mask 40 in which a specific region and a region corresponding to the inhibition region 16 are open is formed by a lithography technique. Then, the gate insulating film 32 is dry-etched under conditions having a selective ratio with respect to the materials of the gate electrode 34 and the body region 13. As a result, the structure shown in FIG. 5 is formed.

In step S6, the inhibition region 16 is formed by ion implantation. Specifically, aluminum or boron is ion-implanted from the surface of the semiconductor substrate 10 through the mask 40. Ion implantation is performed under conditions such that impurities are implanted in a range below the lower end of the low-concentration gate electrode 35 and above the lower surface of the body region 13. This is possible by setting the acceleration energy as appropriate. As a result, the inhibition region 16 is formed as shown in FIG.

In the ion implantation in step S6, impurities are implanted into the inhibition region 16 through the vicinity region R2 located in the vicinity of the specific region in which the gate insulating film 32 is not arranged. Therefore, the crystal defect density of the body region 13 of the neighboring region R2 can be made higher than the crystal defect density of the other body regions 13.

In step S7, after removing the mask 40, the low-concentration gate electrode 35 is embedded in a specific region. In step S8, the source region 15, the insulating film 36, the source electrode 24, and the drain electrode 22 are formed. As a result, the semiconductor device 1 shown in FIG. 1 is completed.

(effect)
In the semiconductor device 1 according to the present embodiment, the low-concentration gate electrode 35 and the body region 13 form a pn junction. Therefore, as shown in the equivalent circuit diagram of FIG. 7, the diode D1 in which the anode is connected to the source and the cathode is connected to the gate is arranged. Within the normal operating temperature range, the leak current I1 flowing from the gate electrode 34 to the source region 15 can be negligibly small. However, when the short-circuit current I2 flows due to some factor, the temperature of the semiconductor device 1 rises beyond the permissible range, so that the leak current I1 increases exponentially. As a result of the potential difference between the gate and the source becoming smaller than the gate threshold voltage due to the voltage drop due to the leak current I1, the semiconductor device 1 can be automatically turned off. This makes it possible to improve the protection performance against a short circuit.

A region in which the low-concentration gate electrode 35 and the body region 13 are pn-junctioned can be formed in a part of the insulated gate portion 30 (see FIG. 1, boundary region R1). Therefore, the input capacitance can be reduced as compared with the case where the insulated gate portion 30 is completely insulated from the body region 13 by the gate insulating film 32. Switching loss can be reduced.

The semiconductor device 1 according to this embodiment includes a low-concentration gate electrode 35. As a result, a low-concentration electric field extension layer can be secured between the pn junctions. That is, the depletion layer can be further expanded when the low-concentration gate electrode 35 forms a pn junction with the body region 13 than when the high-concentration gate electrode 34 forms a pn junction with the body region 13. .. The wider the depletion layer, the less likely it is that breakdown will occur at the pn junction when the gate voltage is applied. Therefore, by appropriately setting the impurity concentration of the low-concentration gate electrode 35, it is possible to apply a voltage equal to or higher than the gate threshold voltage to the gate electrode 34. The semiconductor device 1 can be operated by switching.

The low-concentration gate electrode 35 is arranged on the side surface opposite to the source region 15 with the gate electrode 34 in between. As a result, the inversion layer R11 can be formed on the left side surface of the gate electrode 34, so that the left side surface can be used as the current path. Further, by forming a pn junction on the right side surface of the gate electrode 34, it is possible to improve the protection performance against a short circuit.

As a comparative example, FIG. 8 shows a semiconductor device 101 having no inhibition region 16. When the semiconductor device 101 is on, the inversion layer R12 is formed in the vicinity of the "region in which the gate insulating film 32 is arranged in the boundary region R1". Then, a leak path L1 is formed from the low-concentration gate electrode 35 to the source region 15 via the inversion layer R12, the drift region 12, and the inversion layer R11. On the other hand, since the semiconductor device 1 according to the present embodiment shown in FIG. 1 includes a p ⁺ type inhibition region 16 having a high impurity concentration, “a region in which the gate insulating film 32 in the boundary region R1 is arranged”. It is possible to prevent the formation of an inverted layer in the vicinity of. It is possible to prevent the formation of the leak path L1.

As described with reference to FIG. 6, the crystal defect density of the body region 13 of the neighboring region R2 can be made higher than the crystal defect density of the other body regions 13. The higher the crystal defect density, the higher the rate of increase of the leak current I1 when the temperature rises in the diode D1 shown in the equivalent circuit of FIG. In other words, the higher the crystal defect density, the smaller the potential difference between the gate and the source at lower temperatures than the gate threshold voltage. This makes it possible to freely set the temperature at which the semiconductor device 1 is automatically turned off depending on the crystal defect density.

FIG. 9 shows a cross-sectional view of a main part of the semiconductor device 1a according to the second embodiment. The semiconductor device 1a is a planar gate type. In FIG. 9, the parts different from the semiconductor device 1 of the first embodiment are designated by reference numerals a to c. Since the parts having the same reference numerals in FIGS. 1 and 9 have the same contents, the description thereof will be omitted.

The semiconductor device 1a includes a first body region 13a and a second body region 13b. A drift region 12 is arranged in the opening region 13c between the first body region 13a and the second body region 13b. The source region 15a is arranged on the upper surface of the first body region 13a and is arranged apart from the opening region 13c on the left side in the horizontal direction in FIG.

The insulated gate portion 30a has a gate insulating film 32a, a gate electrode 34a, and a low-concentration gate electrode 35a. The insulated gate portion 30a is in contact with the upper surface of the source region 15a, the first body region 13a, the drift region in the opening region 13c, the inhibition region 16a, and the second body region 13b. The gate electrode 34a is made of n ⁺ type polysilicon having a high impurity concentration. The low-concentration gate electrode 35a is made of n ^- type polysilicon having a low impurity concentration. An insulating film 36a for ensuring insulation from the source region 15a, the first body region 13a, and the second body region 13b is arranged on the upper surface and the side surface of the gate electrode 34a.

In the second body region 13b, the gate insulating film 32a is arranged in a part of the boundary region R1a between the gate electrode 34a and the second body region 13b. In the boundary region R1a where the gate insulating film 32a is arranged, the second body region 13b, the inhibition region 16a, and the gate electrode 34a are in contact with each other via the gate insulating film 32a. On the other hand, in the boundary region R1a, in the specific region where the gate insulating film 32a is not arranged, the second body region 13b and the low-concentration gate electrode 35a are in direct contact with each other. The specific region is arranged in the boundary region R1a at a position separated from the opening region 13c to the right in the horizontal direction. In other words, the specific region is a region in which the low-concentration gate electrode 35a is arranged instead of the gate insulating film 32a.

An inhibition region 16a is arranged in the second body region 13b. The inhibition region 16a is arranged at a position closer to the opening region 13c than the specific region (that is, the low-concentration gate electrode 35a) and in contact with the gate insulating film 32a. The content of the inhibition region 16a is the same as that of the inhibition region 16 described in Example 1.

The distance from the position closest to the opening region 13c of the low-concentration gate electrode 35a to the drift region 12 is the distance t1a. The content of this distance t1a is the same as the distance t1 described in the first embodiment. Further, the operation of the semiconductor device 1a is the same as the operation of the semiconductor device 1 described in the first embodiment.

(Manufacturing method of semiconductor device 1a)
A method of manufacturing the semiconductor device 1a will be described with reference to the flowchart of FIG. In step S1a, a laminated structure is formed in which the drift region 12, the first body region 13a, and the second body region 13b are laminated on the drain region 11. As a result, a structure is formed in which the drift region 12 is arranged in the opening region 13c between the first body region 13a and the second body region 13b. In step S2a, ion implantation forms a source region 15a and an inhibition region 16a. In step S3a, the gate insulating film 32a is formed. In step S4a, a specific region in which the gate insulating film 32a is not arranged is formed. Specifically, the gate insulating film 32a is dry-etched through a mask in which a specific region is open. In step S5a, after removing the mask, the low-concentration gate electrode 35a is embedded in a specific region. In step S6a, the gate electrode 34a is formed on the gate insulating film 32a. Further, an insulating film 36a is formed on the gate electrode 34a. As a result, the semiconductor device 1a shown in FIG. 9 is completed.

(effect)
The effect of the semiconductor device 1a according to the second embodiment is the same as that of the semiconductor device 1 according to the first embodiment described above. Hereinafter, the effects that need to be explained according to the semiconductor device 1a according to the second embodiment will be described.

As shown in FIG. 9, the low-concentration gate electrode 35a is arranged on the side opposite to the source region 15a with the opening region 13c interposed therebetween. As a result, the inversion layer R11a can be formed in the first body region 13a, so that the first body region 13a can be used as a current path. Further, by forming a pn junction in the second body region 13b, it is possible to improve the protection performance against a short circuit.

As a comparative example, FIG. 11 shows a semiconductor device 101a not provided with an inhibition region 16a. When the semiconductor device 101a is on, the inversion layer R12a is formed in the vicinity of the "region in which the gate insulating film 32 is arranged in the boundary region R1a". Then, a leak path L1a is formed from the low-concentration gate electrode 35a to the source region 15a via the inversion layer R12a, the drift region 12 in the opening region 13c, and the inversion layer R11a. On the other hand, since the semiconductor device 1a according to the present embodiment shown in FIG. 9 has a p ⁺ type inhibition region 16a having a high impurity concentration, it is possible to prevent the formation of the leak path L1a.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. In addition, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in the present specification or drawings can achieve a plurality of purposes at the same time, and achieving one of the purposes itself has technical usefulness.

(Modification example)
The position of the inhibition region 16 may be any position as long as it is on the path of the leak path L1. For example, as shown in the semiconductor device 1b of FIG. 12, the inhibition region 16b may be arranged at the bottom of the insulating gate portion 30 in the drift region 12 so as to be in contact with the gate insulating film 32. Since the diode in the reverse bias state can be inserted on the leak path L1, the leak current can be suppressed.

Inhibition regions 16, 16a, 16b are not limited to ^{p + type polysilicon.} Any material may be used as long as it blocks the leak path. For example, it may be an insulator. As a result, the leak path L1 can be cut off, so that the leak current can be suppressed.

The low-concentration gate electrode 35 may be arranged in a region where the gate insulating film 32 is not arranged, and the arrangement mode may be various. For example, as shown in the semiconductor device 1c of FIG. 13, an n ^- type low-concentration gate electrode 35c having a low impurity concentration may be arranged in the upper half of the insulated gate portion 30.

In the flowchart of FIG. 3, the order of step S5 for forming the specific region and step S6 for forming the inhibition region 16 may be reversed.

In the semiconductor device 1 according to the first embodiment, the inhibition region 16 and the low concentration gate electrode 35 can be omitted. From the above, generally speaking, the semiconductor device 1 may include at least a drain region 11, a drift region 12, a body region 13, a source region 15, a gate insulating film 32, and a gate electrode 34. Then, in the specific region where the gate insulating film 32 is not arranged, the body region 13 and the gate electrode 34 may be in contact with each other. The same applies to the semiconductor device 1a according to the second embodiment.

The material of the semiconductor substrate 10 is not limited to SiC. It may be a material such as Si, GaN, or GaAs.

The right side surface of the trench 30T is an example of the first side surface. The left side surface of the trench 30T is an example of the second side surface.

1 and 1a: semiconductor device, 10 and 10a: semiconductor substrate, 11: drain region, 12: drift region, 13: body region, 13a: first body region, 13b: second body region, 15 and 15a: source region, 16 and 16a: Inhibition region, 22: Drain electrode, 24: Source electrode, 30 and 30a: Insulated gate, 30T: Trench, 32 and 32a: Gate insulating film, 34 and 34a: Gate electrode, 35 and 35a: Low concentration Gate electrode

Claims (19)

The first conductive type drain area and
The first conductive type drift region in contact with the upper surface of the drain region and
A second conductive body region that is in contact with the upper surface of the drift region and is arranged on a part of the upper surface of the drift region.
A first conductive type gate electrode region having a boundary region with the body region,
A gate insulating film arranged in a part of the boundary region and
A first conductive source region located above the body region and
With
In the boundary area
In the region where the gate insulating film is arranged, the body region and the gate electrode region are in contact with each other via the gate insulating film.
A semiconductor device in which the body region and the gate electrode region are in direct contact with each other in a specific region in which the gate insulating film is not arranged. The gate electrode region includes a high-concentration gate electrode region having a high impurity concentration and a low-concentration gate electrode region having a low impurity concentration.
The semiconductor device according to claim 1, wherein in the specific region, the low-concentration gate electrode region is in contact with the body region. The gate insulating film includes a first contact surface which is a contact surface with the body region and a second contact surface which is a contact surface with the high-concentration gate electrode region.
The contact surface of the low-concentration gate electrode region with the body region is located in the same plane as the first contact surface.
The semiconductor device according to claim 2, wherein the contact surface of the low-concentration gate electrode region with the high-concentration gate electrode region is located in the same plane as the second contact surface. The high-concentration gate electrode region reaches from the upper surface of the body region to the drift region.
The gate insulating film is arranged on the entire surface of the boundary between the high-concentration gate electrode region and the drift region.
The specific region is arranged on the first side surface of the high-concentration gate electrode region.
The semiconductor device according to claim 2 or 3 , wherein the source region is arranged in the vicinity of a second side surface opposite to the first side surface of the high-concentration gate electrode region. The semiconductor device according to claim 4, further comprising an inhibitory region that inhibits the formation of an inversion layer at a position within the body region, lower than the specific region, and in contact with the gate insulating film. .. The semiconductor according to claim 4, further comprising an inhibitory region that inhibits the formation of an inversion layer at a position within the drift region, a position at the bottom of the high-concentration gate electrode region, and a position in contact with the gate insulating film. Device. The semiconductor device according to claim 5 or 6, wherein the inhibition region is a second conductive type region having a higher impurity concentration than the body region. The semiconductor device according to claim 5 or 6, wherein the inhibition region is an insulator. The body region includes a first body region and a second body region.
The drift region is arranged in the opening region between the first body region and the second body region.
The source region is arranged on the upper surface of the first body region and is arranged horizontally away from the opening region.
The high-concentration gate electrode region is in contact with the source region, the first body region, the drift region in the opening region, and the upper surface of the second body region via the gate insulating film.
The specific area, the second be in the boundary region between the body region and the high density gate electrode region, it is located at a distance in the horizontal direction from the opening region, according to claim 2 or 3 Semiconductor device. The ninth aspect of the present invention comprises a position in the second body region, which is closer to the opening region than the specific region and is in contact with the gate insulating film, and includes an inhibition region that inhibits the formation of the inversion layer. The semiconductor device described. The semiconductor device according to claim 10, wherein the inhibition region is a second conductive type region having a high impurity concentration. The semiconductor device according to claim 10, wherein the inhibition region is an insulator. The distance from the position closest to the drift region of the specific region to the drift region is a distance at which the depletion layer extending from the pn junction formed in the specific region does not reach the drift region. The semiconductor device according to any one of 12. The semiconductor device according to any one of claims 1 to 13, wherein the crystal defect density of the body region in the vicinity region of the specific region is higher than the crystal defect density of the other body region. Further provided with a source electrode region that is in common contact with the top surfaces of the plurality of source regions.
The semiconductor device according to any one of claims 1 to 14, wherein the specific region is arranged in the central portion of the source electrode region when the source electrode region is viewed from above. A step of forming a first conductive type drift region on the upper surface of the first conductive type drain region, and
A step of forming a second conductive type body region on the upper surface of the drift region, and
A step of forming a trench reaching from the upper surface of the body region to the drift region, and
The process of forming a gate insulating film on the inner wall of the trench and
A step of forming a first conductive type gate electrode inside the trench, and
A step of removing the gate insulating film arranged on one side surface of the trench in a region from the upper surface of the body region to the upper side of the lower surface of the body region.
A step of embedding a low-concentration gate electrode which is a first conductive type and has a lower impurity concentration than the gate electrode in the region from which the gate insulating film has been removed.
A step of forming a first conductive type source region on the upper part of the body region, and
A method for manufacturing a semiconductor device. By driving impurities from the upper surface of the body region, the body region is located in the body region, below the lower end of the low-concentration gate electrode, and in contact with the gate insulating film. The production method according to claim 16, further comprising a step of forming a second conductive type region having a higher impurity concentration. A step of forming a first conductive type drift region on the upper surface of the first conductive type drain region, and
The second conductive type first body region and the second body region are formed on the upper surface of the drift region so that the drift region is arranged in the opening region between the first body region and the second body region. And the process to do
A step of forming a source region arranged on the upper surface of the first body region and horizontally separated from the opening region.
A step of forming a gate insulating film on the upper surface of the source region, the first body region, the drift region in the opening region, and the second body region.
A step of removing the gate insulating film in the second body region and in a region horizontally separated from the opening region.
A step of embedding a first conductive type low-concentration gate electrode in the region from which the gate insulating film has been removed,
A step of forming a first conductive type gate electrode having a higher impurity concentration than the low-concentration gate electrode on the upper surface of the gate insulating film and the low-concentration gate electrode.
A method for manufacturing a semiconductor device. By driving impurities into the second body region, the second body region is located in the second body region, closer to the opening region than the low-concentration gate electrode, and in contact with the gate insulating film. 2. The manufacturing method according to claim 18, further comprising a step of forming a second conductive type region having a higher impurity concentration than the two body regions.

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