JP6933063B2 - Parallelization method, parallelization tool, in-vehicle device - Google Patents

Description

The present disclosure relates to a parallelization method for generating a parallel program for a multi-core microcomputer from a single program for a single-core microcomputer, a parallelization tool, and an in-vehicle device including a parallel program generated by the parallelization method.

Conventionally, there is a parallel compilation method disclosed in Patent Document 1 as an example of a parallelization method for generating a parallel program from a single program.

Japanese Unexamined Patent Publication No. 2015-1807

By the way, a single-core microcomputer may access an array variable by executing a single program. That is, a single program may contain array variables. In the above parallel compilation method, when a parallel program is generated from such a single program, all the elements of the array variable are treated as one variable, dependency analysis, processing order extraction, and placement in each core are performed. Will do.

In this case, each process indicating access to each element of the array variable may be treated as having a dependency even though there is no dependency. Therefore, the parallel program generated by the parallel compilation method has a problem that the synchronous processing and the free space become larger than necessary in order to maintain the dependency between the processes having no dependency. Further, the multi-core microcomputer has a problem that by executing such a parallel program, the processing load increases by the amount of synchronous processing, and the processing efficiency decreases by the amount of free space for maintaining the dependency.

The present disclosure has been made in view of the above problems, and provides a parallelization method and a parallelization tool capable of appropriately generating a parallel program even if it is a single program including a process indicating access to an array variable. Is one purpose. Further, the present invention has been made in view of the above problems, and another object is to provide an in-vehicle device capable of appropriately performing processing with a plurality of cores.

To achieve the above objectives, this disclosure is:
A parallelization method that generates a parallel program that parallelizes processes that can be parallelized for a multi-core microcomputer with multiple cores from a single program that includes multiple processes written for a single-core microcomputer with one core. There,
An array variable specification procedure (S12) for identifying an array variable by searching for an array variable character indicating that the array variable contains a plurality of array elements from a single program, and
When an array variable is specified, for each array element in the array variable, the character string that combines the array variable name that is the name of the array variable, the element number that is the number of the array element, and the array variable character is used as the variable name. Variable name definition procedure (S14) to be defined and
Variables containing the defined variables whose variable names are defined in the variable name definition procedure are extracted from a single program, the dependencies of multiple processes that access the variables are analyzed, and the dependencies of multiple processes are maintained in parallel. It is characterized in that it includes a generation procedure (S17) for generating a program.

As described above, in the present disclosure, when an array variable is specified from a single program, the array variable name which is the name of the array variable, the element number which is the number of the array element, and the array variable character are used for each array element in this array variable. Define a character string that combines and as a variable name. Therefore, in the present disclosure, instead of treating an array variable as one variable, each of a plurality of array elements included in the array variable can be treated as one variable.

Then, in the present disclosure, variables including the defined variables defined in this way are extracted from a single program, the dependencies of a plurality of processes for accessing the variables are analyzed, and the dependencies of the plurality of processes are maintained in parallel. Generate a program. In this case, since the present disclosure treats each of the plurality of array elements as one variable and analyzes the dependency, it is possible to suppress the fact that there is a dependency even though there is no dependency. Therefore, in the present disclosure, it is possible to suppress an unnecessarily large amount of space for synchronous processing and maintaining the dependency, and it is possible to appropriately generate a parallel program.

In addition, further features that achieve the above objectives are
Includes a computer that generates a parallel program that parallelizes processes that can be parallelized for a multi-core microcomputer with multiple cores from a single program that includes multiple processes written for a single-core microcomputer with one core. It ’s a parallelization tool,
An array variable identification unit (S12) that identifies an array variable by searching for an array variable character indicating that it is an array variable containing a plurality of array elements from a single program, and
When an array variable is specified, for each array element in the array variable, the character string that combines the array variable name that is the name of the array variable, the element number that is the number of the array element, and the array variable character is used as the variable name. Variable name definition unit (S14) to be defined and
Variables containing the defined variables whose variable names are defined in the variable name definition section are extracted from a single program, the dependencies of multiple processes that access the variables are analyzed, and the dependencies of multiple processes are maintained in parallel. The point is that it includes a generation unit (S17) for generating a program.

As described above, in the parallelization tool, similarly to the above parallelization method, it is possible to suppress an unnecessarily large amount of space for maintaining synchronization processing and dependencies, and it is possible to appropriately generate a parallel program.

In addition, further features that achieve the above objectives are
A multi-core microcomputer (21) having a plurality of cores (21c, 21d), and a parallel program (21a1) parallelized for a multi-core microcomputer from a plurality of processes in a single program for a single-core microcomputer having one core. It is an in-vehicle device equipped with
Parallel programs
An array variable is identified by searching the array variable character indicating that it is an array variable containing multiple array elements from a single program.
For each array element in the specified array variable, a character string that combines the array variable name that is the name of the array variable, the element number that is the number of the array element, and the array variable character is defined as the variable name.
A variable containing a defined variable with a variable name defined is extracted from a single program, the dependency of multiple processes that access the variable is analyzed, and multiple processes are assigned to each core while the dependency is maintained. Has been
The multi-core microcomputer is in that each core executes the assigned process.

As described above, in the present disclosure, as described in the parallelization method described above, it is possible to suppress an unnecessarily large amount of space for maintaining synchronization processing and dependencies, and to provide an appropriately generated parallel program. There is. Then, in the present disclosure, each core of the multi-core microcomputer executes such a parallel program. Therefore, in the present disclosure, it is possible to suppress an increase in the processing load by the amount of synchronous processing and a decrease in processing efficiency by the amount of free space for maintaining the dependency, and it is possible to appropriately perform processing in a plurality of cores. can.

The scope of claims and the reference numerals in parentheses described in this section indicate the correspondence with the specific means described in the embodiment described later as one embodiment, and the technical scope of the present disclosure. Is not limited to.

It is a block diagram which shows the schematic structure of the computer in 1st Embodiment. It is a block diagram which shows the schematic structure of the vehicle-mounted device in 1st Embodiment. It is a flowchart which shows the processing of the computer in 1st Embodiment. It is an image diagram which shows the relationship between each process and an array variable in 1st Embodiment. It is an image diagram which shows an example of each process and each core after parallelization in 1st Embodiment. It is an image diagram which shows another example of each process and each core after parallelization in 1st Embodiment. It is a flowchart which shows the processing of the computer in 2nd Embodiment. It is a flowchart which shows the processing of the computer in 3rd Embodiment. This is an example of a program code written in C language in the third embodiment. It is a flowchart which shows the processing of the computer in 4th Embodiment. This is an example of a program code written in C language in the fourth embodiment. It is an image diagram which shows an example of each process after parallelization and each core in a comparative example.

Hereinafter, a plurality of modes for carrying out the present disclosure will be described with reference to the drawings. In each form, the same reference numerals may be given to the parts corresponding to the matters described in the preceding forms, and duplicate explanations may be omitted. In each form, when only a part of the configuration is described, the other parts of the configuration can be applied with reference to the other forms described above.

(First Embodiment)
The first embodiment will be described with reference to FIGS. 1 to 6. In the present embodiment, a computer that generates a parallel program 21a1 in which a plurality of parallel processes in a single program for a single-core microcomputer having one core are parallelized for a multi-core microcomputer having a first core 21c and a second core 21d. 10 is adopted. That is, the computer 10 is a parallel program 21a1 that parallelizes processes that can be parallelized for a multi-core microcomputer having a plurality of cores from a single program including a plurality of processes described for a single-core microcomputer having one core. To generate.

When the parallel program 21a1 is generated, as described in Japanese Patent Application Laid-Open No. 2015-1807, the single program is analyzed and a plurality of processes are allocated to the first core 21c and the second core 21d ( Perform processing (arrangement). This point can be applied with reference to Japanese Patent Application Laid-Open No. 2015-1807.

As shown in FIG. 4, in the present embodiment, a single program having an array variable V1 including the first element V11 to the fourth element V14 as a plurality of array elements is adopted. For example, in the case of C language, the array variable V1 can be described as Array [4] or the like. The Array [4] has four elements, and includes Array [0], Array [1], Array [2], and Array [3] as array elements.

In this case, [in Array [4] corresponds to an array variable character indicating that it is an array variable. The Array in the Array [4] corresponds to the array variable name which is the name of the array variable. Each of 0 to 3 in the array element corresponds to the element number which is the number of the array element. In addition, 4 in Array [4] can be said to be the number of elements. The element number can also be paraphrased as a subscript. These are examples of array variable characters, array variable names, and element numbers. That is, the array variable character, the array variable name, and the element number are not limited to these, and can be adopted as long as they conform to the description rules of the single program.

Further, as shown in FIG. 4, in the present embodiment, the first processing MT1 to the fifth processing MT5 are adopted as the plurality of processing. The first process MT1 is a process indicating writing to the first element V11. The second process MT2 is a process indicating writing to the second element V12. The third process MT3 is a process indicating writing to the third element V13. The fourth process MT4 is a process indicating writing to the fourth element V14. The fifth process MT5 is a process indicating reading all of the first element V11 to the fourth element V14. Therefore, in the present embodiment, there is no dependency interval between the first processing MT1 to the fourth processing MT4, and there is a dependency relationship only between each of the first processing MT1 to the fourth processing MT4 and the fifth processing MT5. And. The processing can be rephrased as a processing block or a macro task.

Furthermore, the dependency can be regarded as the processing order. That is, any processing order may be used between each of the first processing MT1 to the fourth processing MT4. However, the processing order of the fifth processing MT5 is slower than that of each of the first processing MT1 to the fourth processing MT4.

Here, the configuration of the computer 10 and the in-vehicle device 20 will be described. The computer 10 corresponds to a parallelization tool that executes the parallelization method. Further, since the computer 10 generates the parallel program 21a1, it can be said to be a program generation tool. As shown in FIG. 1, the computer 10 includes a display 11, an HDD 12, a CPU 13, a ROM 14, a RAM 15, an input device 16, a reading unit 17, and the like. Further, the computer 10 is configured to be able to read the stored contents stored in the storage medium 18. The automatic parallelizing compiler 1 is stored in the storage medium 18. The configurations of the computer 10 and the storage medium 18 can be applied with reference to the personal computer 100 and the storage medium 180 described in Japanese Patent Application Laid-Open No. 2015-1807.

The automatic parallelization compiler 1 corresponds to the parallelization method. That is, the automatic parallelization compiler 1 is a program in which a parallelization procedure, in other words, a parallelization method is described. The computer 10 generates the parallel program 21a1 by executing the automatic parallelization compiler 1. Therefore, the automatic parallelizing compiler 1 can be said to be a program generation method. The automatic parallelizing compiler 1 can be applied by referring to those described in Japanese Patent Application Laid-Open No. 2015-1807. In particular, the automatic parallelizing compiler 1 includes an array variable identification procedure and a variable name definition procedure. The procedure for specifying the array variable and the procedure for defining the variable name will be described in detail later.

The automatic parallelizing compiler 1 may include a synchronization process for maintaining the dependency, a free space insertion procedure, and the like. This synchronous processing is, for example, a processing for waiting for the completion of the first processing MT1 to the fourth processing MT4 and executing the fifth processing MT5. In the present embodiment, as shown in FIG. 5, as an example of the synchronization process, an example in which the first synchronization process W1 and the second synchronization process W2 are inserted is adopted. Further, in the present embodiment, as shown in FIGS. 5 and 6, as an example of the vacancy for maintaining the dependency relationship, an example in which the second vacant E2 and the sixth vacant E6 are inserted is adopted.

By executing the automatic parallelization compiler 1, the computer 10 generates a parallel program 21a1 corresponding to the cores 21c and 21d as shown in FIGS. 5 and 6. That is, the computer 10 arranges the first processing MT1 to the fifth processing MT5 and the like in the first core 21c and the second core 21d, in other words, generates the assigned parallel program 21a1.

In the parallel program 21a1 shown in FIG. 5, the first processing MT1, the third processing MT3, and the fifth processing MT5 are arranged in the first core 21c, and the second processing MT2 and the fourth processing MT4 are arranged in the second core 21d. There is. Further, in the parallel program 21a1 shown in FIG. 5, the first synchronous processing W1 and the first empty E1 are arranged in the first core 21c, and the second synchronous processing W2, the second empty E2, and the third empty E3 are second. It is arranged in 2 cores 21d.

On the other hand, in the parallel program 21a1 shown in FIG. 6, all of the first processed MT1 to the fifth processed MT5 are arranged in the first core 21c. Further, in the parallel program 21a1 shown in FIG. 6, the fourth empty E4 is arranged in the first core 21c, and the fifth empty E5 to the seventh empty E7 are arranged in the second core 21d.

In this embodiment, the parallel program 21a1 shown in FIGS. 5 and 6 is adopted as an example. However, the present disclosure is not limited to this.

As shown in FIG. 2, the in-vehicle device 20 includes a multi-core processor 21, a ROM 21a, a RAM 21b, a first core 21c, a second core 21d, a communication unit 22, a sensor unit 23, and an input / output port 24. The in-vehicle device 20 can be applied to, for example, an engine control device or a hybrid control device mounted on an automobile. Here, as an example, an example in which the in-vehicle device 20 is applied to the engine control device is adopted. In this case, the parallel program 21a1 can be said to be an automobile control program such as engine control. The multi-core processor 21 corresponds to a multi-core microcomputer. The core can also be referred to as a processor element.

The RAM 21b, the communication unit 22, the sensor unit 23, and the input / output port 24 can be applied with reference to the RAM 420, the communication unit 430, the sensor unit 450, and the input / output port 460 described in Japanese Patent Application Laid-Open No. 2015-1807.

The ROM 21a includes a parallel program 21a1 capable of executing the first core 21c and the second core 21d. That is, it can be said that the in-vehicle device 20 includes a parallel program 21a1 parallelized for the multi-core processor 21 from a plurality of processes MT1 to MT5 in a single program.

In the multi-core processor 21, the cores 21c and 21d execute the processes assigned to the cores 21c and 21d. The first core 21c and the second core 21d perform, for example, engine control by executing the parallel program 21a1. In other words, the first core 21c and the second core 21d perform engine control and the like by executing control logic according to the parallel program 21a1.

In this embodiment, an example in which the multi-core processor 21 is mounted on the in-vehicle device 20 is adopted. However, the present disclosure is not limited to this, and the multi-core processor 21 may be mounted on a device different from the in-vehicle device 20, for example, a personal computer. Further, in the present embodiment, a multi-core processor 21 having two cores 21c and 21d is adopted. However, the present disclosure can also be adopted in a multi-core processor 21 having three or more cores.

Next, the processing operation of the computer 10 will be described with reference to FIG. The CPU 13 executes the flowchart shown in FIG. 3 when, for example, the input device 16 gives an instruction to execute the insertion process. The CPU 13 generates the parallel program 21a1 from the single program by executing the automatic parallelization compiler 1. The CPU 13 executes the following steps S10 to S17 when generating the parallel program 21a1 according to the procedure described in Japanese Patent Application Laid-Open No. 2015-1807.

In step S10, the extraction target file is selected. The CPU 13 selects an extraction target file, that is, a process from a single program. In step S11, the variable to be accessed is searched. The CPU 13 searches for variables to be accessed in the process selected in step S10.

In step S12, it is determined whether or not there is an array variable character. The CPU 13 determines whether or not the variable that is the search result in step S11 contains an array variable character (array variable specifying unit). That is, the CPU 13 determines whether or not the variable obtained by the search in step S11 is an array variable. If the CPU 13 does not determine that the variable contains the array variable character, the CPU 13 determines that the variable is not an array variable and proceeds to step S13. On the other hand, when the CPU 13 determines that the variable contains the array variable character, the CPU 13 considers the variable to be an array variable and proceeds to step S14. In this way, the CPU 13 searches the single program for the array variable character indicating that it is an array variable, and identifies the array variable.

In the present embodiment, a character indicating that the array variable conforms to the description rule of the single program is adopted as the array variable character. When determining that it is an array variable, the CPU 13 determines whether or not there is a character indicating that it is an array variable according to the description rule of the single program. In the array variable description rule in the C language program, in the case of an array variable, [] always exists after the variable name. Therefore, the CPU 13 can determine whether or not the variable is an array variable depending on the presence or absence of [.

The CPU 13 specifies an array variable by executing the automatic parallelizing compiler 1. Therefore, it can be said that the automatic parallelization compiler 1 includes an array variable identification procedure. That is, the automatic parallelizing compiler 1 includes an array variable identification procedure for identifying an array variable by searching for an array variable character indicating that the array variable includes a plurality of array elements from a single program.

In step S13, the variable name is extracted from the search result. The CPU 13 extracts the variable name from the variable searched in step S11.

In step S14, a character string in which the array variable name, the element number, and the array variable characters are combined is defined as the variable name (variable name definition unit). When an array variable is specified, the CPU 13 defines a character string obtained by combining an array variable name, an element number, and an array variable character as a variable name for each array element in the array variable. When, for example, Array [4] is specified as an array variable, the CPU 13 defines variable names such as Array [0], Array [1], Array [2], and Array [3] for each array element. This is because the parallel program 21a1 is generated by treating each of the array elements as one variable, instead of treating the array variable as one variable. The variable for which the variable name is defined here corresponds to the defined variable.

In this way, when accessing each element of the array variable, the CPU 13 always specifies the element number, and therefore the CPU 13 defines the variable name including the element number. By defining the CPU 13 as a variable name including characters according to the description rules of the single program, it becomes easy to search for each element of the array variable in the single program, and the time required for the process of step S17 described later. Can be shortened. That is, the CPU 13 can shorten the time required for the dependency analysis.

The CPU 13 defines a variable name for each array element by executing the automatic parallelization compiler 1. Therefore, it can be said that the automatic parallelization compiler 1 includes a variable name definition procedure. That is, when an array variable is specified, the automatic parallelization compiler 1 uses an array variable name, which is the name of the array variable, an element number, which is the number of the array element, and an array variable character, for each array element in the array variable. Includes a variable name definition procedure that defines a variable name that is a combination of.

In step S15, it is determined whether or not all the variable names have been searched. The CPU 13 determines whether or not all the variable names accessed by the process selected in step S10 have been searched, proceeds to step S16 if it is determined to have searched, and proceeds to step S11 if it does not determine that the search has been performed. return.

In step S16, it is determined whether or not the files have been extracted from all the files. The CPU 13 determines whether or not the process has been extracted from all the files of the single program, and if it is determined that the process has been extracted, the process proceeds to step S17, and if it is not determined that the process has been extracted, the process returns to step S10.

In step S17, a parallel program is generated (generation unit). The CPU 13 extracts variables including the defined variables whose variable names are defined in step S14 from a single program, analyzes the dependencies of a plurality of processes for accessing the variables, extracts the processing order, and performs a plurality of processes. Generate a parallel program that maintains the dependency of. That is, the CPU 13 analyzes the dependency of a plurality of processes for accessing the defined variable whose variable name is defined in step S14 and the variable whose variable name is extracted in step S13, and determines the dependency of the plurality of processes. The parallel program 21a1 in which the relationship is maintained is generated. That is, the CPU 13 arranges a plurality of processes in either the first core 21c or the second core 21d. This step S17 can be applied with reference to Japanese Patent Application Laid-Open No. 2015-1807. The variable whose variable name is extracted in step S13 can be regarded as a variable that is not an array variable included in the single program.

The CPU 13 generates the parallel program 21a1 by executing the automatic parallelization compiler 1. Therefore, it can be said that the automatic parallelization compiler 1 includes a generation procedure. That is, the automatic parallelization compiler 1 extracts variables including defined variables from a single program, analyzes the dependencies of a plurality of processes that access the variables, and performs parallel processing in which the dependencies of the plurality of processes are maintained. It includes a generation procedure for generating the program 21a1.

As described above, in the present embodiment, the computer 10 generates the parallel program 21a1 shown in FIGS. 5 and 6 by executing steps S10 to S17. However, the present disclosure is not limited to this. An operator or the like may generate the parallel program 21a1 by performing steps S10 to S17 in addition to the parallelization method described in Japanese Patent Application Laid-Open No. 2015-1807.

Here, the effect of the present disclosure will be described while comparing the computer 10 with the parallelization tool of the comparative example. The parallelization tool of the comparative example differs from the computer 10 in that it treats an array variable as one variable.

In the parallelization tool of the comparative example, the variable name is extracted and defined from the single program, the dependency is analyzed, and the variable name is arranged in the first core 21c and the second core 21d. That is, the parallelization tool of the comparative example performs steps S10, S11, S13, and S15 to S17 without performing steps S12 and S14 of FIG.

Therefore, the parallelization tool in the comparative example treats array elements that do not have a dependency as if they have a dependency. Therefore, the parallelization tool of the comparative example creates a parallel program such as the first pattern and the second pattern of FIG. 12 when the first processing MT1 to the fifth processing MT5 shown in FIG. 4 are parallelized. Become.

In the first pattern, the first processed MT1, the third processed MT3, and the fifth processed MT5 are arranged in the first core 21c, and the second processed MT2 and the fourth processed MT4 are arranged in the second core 21d. Further, in the first pattern, two free E10s and E11s for maintaining a dependency relationship with the four synchronization processes W10 to W13 are arranged in the first core 21c, and the dependency relationship is maintained with the four synchronization processes W14 to W17. Three empty E12 to E14 are arranged in the second core 21d.

Compared with the parallel program 21a1 shown in FIG. 5, the first pattern has more space for maintaining the synchronization processing and the dependency. In this way, the parallelization tool of the comparative example has a lot of synchronization processing and free space in order to maintain the dependency that does not actually exist.

On the other hand, in the second pattern, all of the first processed MT1 to the fifth processed MT5 are arranged in the first core 21c. Further, in the second pattern, one free E15 is arranged in the first core 21c, and a free E16 for maintaining a dependency relationship with the one free E17 is arranged in the second core 21d.

In the second pattern, there is more space (longer) for maintaining the dependency relationship than in the parallel program 21a1 shown in FIG. In this way, the parallelization tool of the comparative example has a lot of space in order to maintain the dependency that does not actually exist.

On the other hand, the computer 10 identifies the array variable V1 from the single program. Then, the computer 10 combines the array variable name, which is the name of the array variable V1, the element number, which is the number of the array element, and the array variable character for each of the array elements V11 to V14 in the array variable V1. Is defined as a variable name. Therefore, the computer 10 does not treat the array variable V1 as one variable, but can treat each of the plurality of array elements V11 to V14 included in the array variable V1 as one variable. That is, the computer 10 can handle each of the array elements V11 to V14 as individual variables.

Then, the computer 10 extracts the variable including the defined variable defined in this way from the single program. Further, the computer 10 analyzes the dependencies of the plurality of processes MT1 to MT5 that access this variable, and generates a parallel program 21a1 in which the dependencies of the plurality of processes MT1 to MT5 are maintained. At this time, the computer 10 treats each of the plurality of array elements V11 to V14 as one variable and analyzes the dependency, so that it is assumed that there is a dependency even though there is no dependency. Can be suppressed. Therefore, the computer 10 can suppress the synchronization processing and the free space for maintaining the dependency from becoming unnecessarily large, and can appropriately generate the parallel program 21a1. That is, the computer 10 can generate the parallel program 21a1 which has less space for maintaining the synchronization processing and the dependency than the parallelization tool of the comparative example as described above.

By executing the automatic parallelization compiler 1, the computer 10 can suppress an unnecessarily large amount of space for maintaining synchronization processing and dependencies, and can appropriately generate a parallel program 21a1. Therefore, like the computer 10, the automatic parallelizing compiler 1 can suppress an unnecessarily large amount of space for maintaining synchronization processing and dependencies, and can appropriately generate a parallel program 21a1.

Further, in the single program in the in-vehicle device 20, there are many cases where there is no dependency relationship for each array element. For example, in a single program for driving and controlling a 4-cylinder engine, four array elements are prepared and each array element is used as control data peculiar to each cylinder. In such a case, the computer 10 and the automatic parallelizing compiler 1 are effective.

Further, the in-vehicle device 20 includes a parallel program 21a1 generated by the computer 10. That is, the in-vehicle device 20 includes a parallel program 21a1 that is appropriately generated while suppressing an unnecessarily large amount of space for synchronizing processing and maintaining the dependency relationship. Then, in the in-vehicle device 20, such parallel programs 21a1 are executed by the cores 21c and 21d of the multi-core processor 21. Therefore, the in-vehicle device 20 can prevent the processing load from increasing by the amount of synchronous processing and the processing efficiency from decreasing by the amount of space for maintaining the dependency, and can be appropriately processed by the plurality of cores 21c and 21d. Can be done.

The preferred embodiments of the present disclosure have been described above. However, the present disclosure is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present disclosure. The second to fourth embodiments will be described below as other embodiments of the present disclosure. The above-described embodiment and the second to fourth embodiments can be carried out individually, or can be carried out in combination as appropriate. The present disclosure is not limited to the combinations shown in the embodiments, but can be implemented in various combinations.

(Second Embodiment)
The second embodiment will be described with reference to FIG. 7. In the second embodiment, mainly the parts different from the above-described embodiment will be described. Further, this modification is different from the above embodiment in that the automatic parallelizing compiler 1 includes a character designation procedure for designating a character indicating that it is an array variable. Similarly, this modification is different from the above embodiment in that the computer 10 includes a character designation unit for designating a character indicating that it is an array variable. In this embodiment, since the same step number is assigned to the same process as in the above embodiment, it can be applied with reference to the above embodiment.

The processing operation of the computer 10 will be described with reference to FIG. 7. The CPU 13 executes the flowchart shown in FIG. 7, for example, when the input device 16 gives an instruction to execute the insertion process. The CPU 13 generates the parallel program 21a1 from the single program by executing the automatic parallelization compiler 1. The CPU 13 executes the following steps S20 and S10 to S17 when generating the parallel program 21a1 according to the procedure described in Japanese Patent Application Laid-Open No. 2015-1807. Further, the CPU 13 executes step S20 before step S10.

In step S20, a character indicating that the variable is an array variable is specified (character designation unit). The CPU 13 specifies a character indicating that it is an array variable, for example, specified by a software designer or the like. This character is not a character that conforms to the description rules of a single program, but is a character arbitrarily specified by a software designer or the like.

The CPU 13 specifies a character indicating that it is an array variable by executing the automatic parallelizing compiler 1. Therefore, it can be said that the automatic parallelizing compiler 1 includes a character specification procedure. That is, the automatic parallelizing compiler 1 includes a character specification procedure for designating a character indicating that it is an array variable.

Therefore, in step S12, the CPU 13 determines the presence / absence of the array variable character by using the character specified in step S20. However, the CPU 13 may determine whether or not there is a character indicating that the array variable conforms to the description rule of the single program in addition to the character specified in step S20, as in the above embodiment. ..

The computer 10 and the automatic parallelizing compiler 1 can achieve the same effects as those in the above embodiment. Further, since the computer 10 and the automatic parallelizing compiler 1 can specify characters indicating that they are array variables, the programming language used is changed, and even if the characters indicating that they are array variables are changed, the parallel program 21a1 Can be generated. Therefore, the computer 10 and the automatic parallelizing compiler 1 can reduce the trouble of revising the software development process by changing the programming language, suppressing the repurchase of tools, and upgrading the version. Along with this, the computer 10 and the automatic parallelizing compiler 1 can be expected to reduce costs.

The in-vehicle device 20 includes a parallel program 21a1 generated by the computer 10 as in the above embodiment. Therefore, the in-vehicle device 20 can exert the same effect as that of the above embodiment.

(Third Embodiment)
The third embodiment will be described with reference to FIGS. 8 and 9. In the third embodiment, mainly the parts different from the above-described embodiment will be described. Further, this modification is different from the above embodiment in that the automatic parallelizing compiler 1 includes an element number specifying procedure. Similarly, this modification is different from the above embodiment in that the computer 10 includes an element number specifying unit. In this embodiment, since the same step number is assigned to the same process as in the above embodiment, it can be applied with reference to the above embodiment.

FIG. 9 shows a part (program code example) of a single program written in C language as an example. A single program may be described as Array [index] in order to improve versatility, for example, when it is desired to substitute 0 for Array [0] to Array [3]. As described above, in the single program, a different variable name different from the array variable may be used after the array variable character, for example, in the place corresponding to the array element number. In this case, the extraction result of the array variable name is Array [index].

Therefore, if the computer 10 (CPU 13) determines YES in step S12, the computer 10 (CPU 13) proceeds to step S30. In step S30, it is determined whether or not the variable name is specified after the array variable character (element number specifying unit). That is, the CPU 13 determines whether or not a different variable name different from the array variable is used after the array variable character in the array variable specified in step S12. Then, if it is determined that the CPU 13 is designated, the process proceeds to step S31, and if it is not determined that the designation is not specified, the CPU 13 proceeds to step S14.

In step S31, the CPU 13 searches all files for the variable name after the array variable character and performs code analysis to specify the element number (element number specifying unit). That is, the CPU 13 analyzes the value that can be taken by another variable name from the single program and specifies the element number. In the example of FIG. 9, 0, 1, 2, and 3 are specified as element numbers. Therefore, when the CPU 13 proceeds to step S14 through step S31, the CPU 13 defines a variable name using the element number specified in step S31 (variable name definition unit).

The CPU 13 specifies the element number as described above by executing the automatic parallelizing compiler 1. Therefore, it can be said that the automatic parallelizing compiler 1 includes an element number specifying procedure. That is, when another variable name is used after the array variable character in the array variable specified in step S12, the automatic parallelizing compiler 1 analyzes the value that the other variable name can take from a single program and obtains the element number. Includes the element number identification procedure to be identified.

Therefore, the computer 10 and the automatic parallelizing compiler 1 can treat each array element as an individual variable even when another variable name is described after the array variable character. Therefore, the computer 10 and the automatic parallelizing compiler 1 can obtain the same effect as that of the first embodiment even when another variable name is described after the array variable character.

The in-vehicle device 20 includes a parallel program 21a1 generated by the computer 10 as in the first embodiment. Therefore, the in-vehicle device 20 can achieve the same effect as that of the first embodiment.

The third embodiment can also be implemented in combination with the second embodiment. That is, the computer 10 may perform step S20 before step S10. Further, the automatic parallelizing compiler 1 may include a character specification procedure for designating a character indicating that it is an array variable.

(Fourth Embodiment)
The fourth embodiment will be described with reference to FIGS. 10 and 11. In the fourth embodiment, mainly the parts different from the above-described embodiment will be described. Further, this modification is different from the above embodiment in that the automatic parallelizing compiler 1 includes an element number specifying procedure. Similarly, this modification is different from the above embodiment in that the computer 10 includes an element number specifying unit. In this embodiment, since the same step number is assigned to the same process as in the above embodiment, it can be applied with reference to the above embodiment.

FIG. 11 shows a part (program code example) of a single program written in C language as an example. A single program is described as shown in FIG. 11 in order to improve versatility and reduce ROM capacity when it is desired to substitute 0 for Array [0] to [3] or 0 for Array [0] to [2]. May be done. As described above, in the single program, a different variable name different from the array variable may be used after the array variable character, for example, in the place corresponding to the array element number. In this case, the extraction result of the array variable name is Array [data1]. In FuncaA of this example, 0 is substituted for Array [0] to [3]. On the other hand, in FuncB, 0 is substituted for Array [0] to [2].

As described above, it can be said that the program code example shown in FIG. 11 is more complicated than the program code example shown in FIG. Therefore, in the third embodiment, it may take a lot of time to analyze the code for specifying the element number.

Therefore, the computer 10 includes an element information list including array elements accessed by the processing in the single program. In the case of FuncA, the element information list includes Array [0], Array [1], Array [2], and Array [3], and in the case of FuncB, Array [0], Array [1], and Array [3]. 2] is described.

Then, if the computer 10 (CPU 13) determines YES in step S12, the computer 10 (CPU 13) proceeds to step S40. In step S40, as in step S30, it is determined whether or not the variable name is specified after the array variable character (element number specifying unit).

In step S41, the CPU 13 searches the element information list of the array variable and specifies the element number (element number specifying unit). That is, the CPU 13 searches the element information list for the array element to be accessed with another variable name, and specifies the element number. In the example of FIG. 11, in the case of FuncaA, 0, 1, 2, and 3 are specified as element numbers, and in the case of FuncaB, 0, 1, and 2 are specified as element numbers. Therefore, when the CPU 13 proceeds to step S14 through step S41, the CPU 13 defines a variable name using the element number specified in step S41 (variable name definition unit).

The CPU 13 specifies the element number as described above by executing the automatic parallelizing compiler 1. Therefore, it can be said that the automatic parallelizing compiler 1 includes an element number specifying procedure. That is, when another variable name is used after the array variable character in the array variable specified in step S12, the automatic parallelizing compiler 1 searches the element information list for the array element to be accessed by the different variable name, and the element. Includes an element numbering procedure to identify the number.

Therefore, the computer 10 and the automatic parallelizing compiler 1 can achieve the same effects as those of the first embodiment and the third embodiment. Further, since the computer 10 and the automatic parallelizing compiler 1 search the element information list to specify the element number, the element number can be specified in a shorter time than in the third embodiment.

The in-vehicle device 20 includes a parallel program 21a1 generated by the computer 10 as in the first embodiment. Therefore, the in-vehicle device 20 can achieve the same effect as that of the first embodiment.

The fourth embodiment can also be implemented in combination with the second embodiment. That is, the computer 10 may perform step S20 before step S10. Further, the automatic parallelizing compiler 1 may include a character specification procedure for designating a character indicating that it is an array variable.

1 ... Automatic parallelizing compiler, 10 ... Computer, 11 ... Display, 12 ... HDD, 13 ... CPU, 14 ... ROM, 15 ... RAM, 16 ... Input device, 17 ... Reader, 18 ... Storage medium, 20 ... In-vehicle device , 21 ... Multi-core processor, 21a ... ROM, 21a1 ... Parallel program, 21b ... RAM, 21c ... 1st core, 21d ... 2nd core, 22 ... Communication unit, 23 ... Sensor unit, 24 ... Input / output port

Claims (15)

A parallelization method for generating a parallel program in which the above processes that can be parallelized for a multi-core microcomputer having a plurality of cores are generated from a single program including a plurality of processes described for a single-core microcomputer having one core. And
The sequence variable identification procedure (S12) for identifying the array variable by searching for an array variable character indicating that the array variable contains a plurality of array elements from the single program, and
When the array variable is specified, the array variable name which is the name of the array variable, the element number which is the number of the array element, and the array variable character are combined for each of the array elements in the array variable. The variable name definition procedure (S14) for defining a character string as a variable name, and
A variable including a defined variable whose variable name is defined in the variable name definition procedure is extracted from the single program, the dependency of a plurality of the processes that access the variable is analyzed, and the dependency of the plurality of processes is analyzed. A parallelization method comprising a generation procedure (S17) for generating the parallel program in which the relationship is maintained. The parallelization method according to claim 1, wherein the array variable character is a character indicating that the array variable conforms to the description rule of the single program. A character specification procedure (S20) for designating a character indicating that the array variable is provided is provided.
The parallelization method according to claim 1, wherein the array variable character is a character indicating that the array variable character is the array variable specified in the character designation procedure. When a different variable name different from the array variable is used after the array variable character in the array variable specified in the array variable identification procedure, the value that the other variable name can take is analyzed from the single program. The element number specifying procedure (S30, S31) for specifying the element number is provided.
The parallelization method according to claim 2 or 3, wherein the variable name definition procedure defines the variable name using the specified element number when the element number is specified by the element number identification procedure. It includes an element information list including the array elements accessed by the process in the single program.
When a different variable name different from the array variable is used after the array variable character in the array variable specified in the array variable identification procedure, the element information of the array element accessed by the different variable name is used. The element number specifying procedure (S40, S41) for searching from the list and specifying the element number is provided.
The parallelization method according to claim 2 or 3, wherein the variable name definition procedure defines the variable name using the specified element number when the element number is specified by the element number identification procedure. A computer that generates a parallel program that parallelizes the above processes that can be parallelized for a multi-core microcomputer with multiple cores from a single program that includes multiple processes described for a single-core microcomputer with one core. A parallelization tool that includes
From the single program, an array variable specifying unit (S12) that searches for an array variable character indicating that the array variable contains a plurality of array elements and specifies the array variable, and
When the array variable is specified, the array variable name which is the name of the array variable, the element number which is the number of the array element, and the array variable character are combined for each of the array elements in the array variable. The variable name definition unit (S14) that defines a character string as a variable name, and
A variable including a defined variable in which the variable name is defined by the variable name definition unit is extracted from the single program, the dependency of a plurality of the processes that access the variable is analyzed, and the dependency of the plurality of processes is analyzed. A parallelization tool including a generation unit (S17) that generates the parallel program in which the relationship is maintained. The parallelization tool according to claim 6, wherein the array variable character is a character indicating that the array variable conforms to the description rule of the single program. A character designation unit (S20) for designating a character indicating that the array variable is provided is provided.
The parallelization tool according to claim 6, wherein the array variable character is a character indicating that the array variable character is designated by the character designation unit. When another variable name different from the array variable is used after the array variable character in the array variable specified by the array variable identification unit, the value that the other variable name can take is analyzed from the single program. The element number specifying unit (S30, S31) for specifying the element number is provided.
The parallelization tool according to claim 7 or 8, wherein the variable name definition unit defines the variable name using the specified element number when the element number is specified by the element number identification unit. It includes an element information list including the array elements accessed by the process in the single program.
When a different variable name different from the array variable is used after the array variable character in the array variable specified by the array variable specifying unit, the element information of the array element accessed by the different variable name is used. It is provided with an element number specifying unit (S40, S41) that searches from a list and specifies the element number.
The parallelization tool according to claim 7 or 8, wherein the variable name definition unit defines the variable name using the specified element number when the element number is specified by the element number identification unit. A multi-core microcomputer (21) having a plurality of cores (21c, 21d) and a parallel program (21a1) parallelized for the multi-core microcomputer from a plurality of processes in a single program for the single-core microcomputer having one core. It is an in-vehicle device equipped with
The parallel program
The array variable is identified by searching the array variable character indicating that it is an array variable containing a plurality of array elements from the single program.
For each of the array elements in the specified array variable, a character string obtained by combining the array variable name which is the name of the array variable, the element number which is the number of the array element, and the array variable character is used as the variable name. Defined
A variable including a defined variable in which the variable name is defined is extracted from the single program, the dependency of a plurality of the processes that access the variable is analyzed, and the plurality of the processes are maintained in a state where the dependency is maintained. Is assigned to each core,
The multi-core microcomputer is an in-vehicle device that executes the process to which each core is assigned. The vehicle-mounted device according to claim 11, wherein the array variable character is a character indicating that the array variable conforms to the description rule of the single program. The vehicle-mounted device according to claim 11, wherein the array variable character is a character indicating that the array variable is a designated character. The parallel program analyzes the value that can be taken by the different variable name from the single program when a different variable name different from the sequence variable is used after the sequence variable character in the specified array variable. The vehicle-mounted device according to claim 12 or 13, wherein the element number is specified and the variable name is defined using the specified element number. The parallel program includes the array element accessed by the process in the single program when a different variable name different from the array variable is used after the array variable character in the identified array variable. The element information list is described in claim 12 or 13, wherein the element number is specified by searching for the array element accessed by the different variable name, and the variable name is defined using the specified element number. In-vehicle device.

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