JP6933798B2 - Switching amplifier - Google Patents

Description

The present invention relates to a switching amplifier, and more particularly to an improvement in distortion characteristics.

A switching amplifier is widely used as an audio amplifier that amplifies an acoustic signal. In the switching amplifier, a pulse width modulation signal whose pulse width changes according to the level of the input signal is generated, and the semiconductor element is switched according to the pulse width modulation signal. The signal obtained by this switching is smoothed by the low-pass filter and output to the speaker as a load. Generally, a switching amplifier has an advantage that a loss in a semiconductor element is small.

The following Patent Document 1 describes a switching amplifier. This switching amplifier is provided with a circuit that generates a pulse width modulated signal based on the output current of the DC amplifier after the DC amplifier that amplifies the signal in the frequency band from frequency 0 to the audible frequency. A switching output circuit that operates on and off based on the pulse width modulation signal is provided in the subsequent stage of the pulse width modulation signal generation circuit. A semiconductor element is used in the switching output circuit, and a signal is output from the switching output circuit according to the on / off of the semiconductor element. Further, Patent Documents 2 and 3 describe DC amplifiers.

Japanese Unexamined Patent Publication No. 2013-150257 Japanese Unexamined Patent Publication No. 2012-10993 Japanese Unexamined Patent Publication No. 2012-249206

In a switching output circuit as shown in Patent Document 1, a plurality of semiconductor elements that contribute to an operation of outputting a signal are used. If the characteristics of these plurality of semiconductor elements vary, the distortion of the output signal of the switching output circuit may increase.

An object of the present invention is to suppress distortion of a signal output from a switching amplifier.

In a switching amplifier having a DC amplifier and a switching amplification unit connected to a subsequent stage of the DC amplifier, the DC amplifier includes a variable resistor that adjusts a DC offset voltage that appears in a connection path with the switching amplification unit. The switching amplification unit is based on a pulse width modulation signal generation unit that generates a pulse width modulation signal that is a pulse width modulation signal and whose pulse width is determined according to the output signal of the DC amplifier, and a pulse width modulation signal. It is characterized by including a switching circuit that operates on and off.

Desirably, the DC offset voltage appearing in the connection path is determined according to the distortion included in the output signal of the switching circuit.

Desirably, the pulse width modulation signal generation unit is high or high depending on the difference between the output holding unit that holds the output value according to the output signal of the DC amplifier and the output value and the reference value from the output holding unit. The switching circuit includes two switching elements connected in series and alternately turned on and off, and a comparison unit that outputs a low-determined signal as the pulse width-modulated signal, depending on the level of the pulse-width-modulated signal. A drive circuit for on / off control of each of the switching elements is provided, and a signal is output from a connection point of the two switching elements.

Desirably, the DC amplifier converts the first circuit unit and the second circuit unit, the signal output from the first circuit unit, and the signal output from the second circuit unit into a single output signal. A conversion circuit that outputs to the switching amplification unit is provided, and each of the first circuit unit and the second circuit unit has a first emitter follower connected to a first input terminal of the DC amplifier and the DC amplifier. The base is connected to the output path of the first emitter follower and the second emitter follower connected to the second input terminal of the above, the emitter is connected to the output path of the second emitter follower, and a signal is output from the collector. The first resistor and the second resistor provided between the main body transistor, the output path of the first emitter follower, and the DC voltage source and connected in series, the first resistor, and the second resistor. The second circuit includes a constant voltage generator connected to the series connection point of the above, and a path to the collector of each transistor constituting the first emitter follower and the second emitter follower in the first circuit unit. The path connected to the series connection point in the unit and reaching the collectors of the first emitter follower and the transistors constituting the second emitter follower in the second circuit unit is connected to the series connection point in the first circuit unit. Bias settings for the first circuit unit and the second circuit unit are set in the output path of the first emitter follower in the first circuit unit and the output path of the first emitter follower in the second circuit unit. The circuit is characterized in that a bias setting circuit including the variable resistor is provided.

Desirably, each of the first circuit unit and the second circuit unit has an emitter connected to the path leading to the variable resistor and the emitter of the transistor constituting the first emitter follower, and is connected to the base of the main body transistor. The variable resistor includes an auxiliary transistor to which a collector is connected to the path leading to the transistor, and the variable resistor has a slider, a resistance value between one end and the slider, and the other end and the slider. The resistance value between them is variable according to the position of the slider, one end of the variable resistor is connected to the collector of the auxiliary transistor, and the slider of the variable resistor is the base of the auxiliary transistor. The other end of the variable resistor in the first circuit unit and the other end of the variable resistor in the second circuit unit are connected to each auxiliary transistor and each variable resistor. The device comprises the bias setting circuit.

Desirably, each of the first circuit unit and the second circuit unit has an emitter connected to a path leading to the emitter of the transistor included in the first emitter follower, and a collector connected to a path leading to the base of the main body transistor. The switching amplifier includes a bias voltage source provided between the base of the auxiliary transistor in the first circuit unit and the base of the auxiliary transistor in the second circuit unit, and the variable resistor. The resistance value of both ends of the device is variable, and in each of the first circuit unit and the second circuit unit, the variable resistor is provided in the path leading to the emitter of the transistor included in the first emitter follower. Each of the auxiliary transistors, the variable resistor, and the bias voltage source constitutes the bias setting circuit.

Desirably, the DC voltage source is a power supply source of the switching amplifier, and the switching amplifier is a power amplifier in which a speaker is connected to the switching amplification unit.

According to the present invention, distortion of the signal output from the switching amplifier can be suppressed.

It is a figure which shows the structure of a switching power amplifier. It is a figure which shows the structure of a DC amplifier concretely. It is a figure which shows the modification of the bias setting circuit.

(1) Configuration of Switching Power Amplifier FIG. 1 shows a configuration of a switching power amplifier according to an embodiment of the present invention. The switching power amplifier includes an amplifier input terminal 0, a DC amplifier 10, a switching amplification unit 38 connected to the subsequent stage of the DC amplifier 10, a negative feedback circuit 34 that negatively feeds the signal output by the switching amplification unit 38 to the DC amplifier 10, and The amplifier output terminal 4 is provided. A CD player, a tuner, a portable information terminal with a music playback function, or the like, which is a sound source device, is connected to the amplifier input terminal 0, and an acoustic signal output from the sound source device is input to the amplifier input terminal 0. Further, a speaker 32 is connected as a load between the amplifier output terminal 4 and the ground conductor. The speaker 32 reproduces the sound based on the acoustic signal amplified by the switching power amplifier.

The DC amplifier 10 includes a first input terminal 1, a second input terminal 2, and a DC amplifier output terminal 3. The first input terminal 1 is connected to the amplifier input terminal 0. The DC amplifier 10 amplifies the signal input to the first input terminal 1 in the same phase, and outputs the signal from the DC amplifier output terminal 3 to the switching amplification unit 38. A negative feedback circuit 34 is connected to the second input terminal 2. As will be described later, a feedback signal is input to the second input terminal 2 from the negative feedback circuit 34. The DC amplifier 10 amplifies the signal input to the second input terminal 2 in the opposite phase, and outputs the signal from the DC amplifier output terminal 3 to the switching amplification unit 38. The DC amplifier 10 amplifies a signal in a frequency band from 0 frequency to an audible frequency.

The switching amplification unit 38 includes a PWM signal generation unit 12, a switching circuit 18, and a low-pass filter 30. PWM is an abbreviation for Pulse Width Modulation, that is, pulse width modulation. The PWM signal generation unit 12 includes a capacitor 14 and a comparator 16. The comparison terminal C of the comparator 16 is connected to the DC amplifier output terminal 3. The reference terminal S of the comparator 16 is connected to the ground conductor. The capacitor 14 is connected between the comparison terminal C and the ground conductor.

The capacitor 14 accumulates an electric charge according to the output current of the DC amplifier 10. As a result, the capacitor 14 charges a voltage corresponding to the output current of the DC amplifier 10, and the charging voltage is input to the comparison terminal C of the comparator 16. As described above, the capacitor 14 has a function as an output holding unit that holds a voltage as an output value according to an output current as an output signal of the DC amplifier 10. Instead of the capacitor 14, an electric circuit element or an electronic circuit having a function as an output holding unit may be used.

The comparator 16 has a function as a comparison unit, and a PWM signal whose high or low is determined according to the difference between the charging voltage (output value of the output holding unit) of the capacitor 14 and the reference potential (reference value) is switched by the switching circuit 18 Output to. That is, the comparator 16 outputs a high voltage to the switching circuit 18 when the potential of the comparison terminal C (comparative potential) is larger than the reference potential, and outputs a low voltage to the switching circuit 18 when the comparative potential is equal to or lower than the reference potential. Output to 18.

In the circuit shown in FIG. 1, the comparison terminal C is connected to the terminal on the non-grounded side of the capacitor 14, and the comparison terminal C is connected to the ground conductor. Therefore, the comparator 16 outputs a high voltage H to the switching circuit 18 when the potential of the non-grounded terminal of the capacitor 14 is positive, and a low voltage when the non-grounded terminal of the capacitor 14 has a reference potential of 0 or negative. L is output to the switching circuit 18. The reference potential does not have to be 0. In this case, a semiconductor element such as a Zener diode that generates a reference potential and a constant voltage generator such as a DC voltage source are connected between the reference terminal S of the comparator 16 and the ground conductor.

With such a configuration, the comparator 16 outputs a PWM signal in which the voltage of the output signal of the DC amplifier 10 is reflected in the pulse width to the switching circuit 18. That is, when the voltage of the output signal of the DC amplifier 10 is larger than 0, the voltage value of the PWM signal becomes a high voltage H, and when the level of the output signal of the DC amplifier 10 is 0 or less, the voltage value of the PWM signal. Is a low voltage H.

The switching circuit 18 includes a drive circuit 20, a first field effect transistor 22 (first FET 22), and a second field effect transistor 24 (second FET 24). The gate of the first FET 22 and the gate of the second FET 24 are connected to the drive circuit 20. The drain of the first FET 22 is connected to the positive electrode of the first DC voltage source E1. The source of the second FET 24 is connected to the negative electrode of the second DC voltage source E2. The source of the first FET 22 and the drain of the second FET 24 are commonly connected, and the low-pass filter 30 and the negative feedback circuit 34 are connected to the connection points of the first FET 22 and the second FET 24. The negative electrode of the first DC voltage source E1 and the positive electrode of the second DC voltage source E2 are connected to the ground conductor. These DC voltage sources may supply DC power to the DC amplifier 10, the PWM signal generation unit 12, and the drive circuit 20 as the power supply source of the switching power amplifier.

The drive circuit 20 controls the voltage of each gate of the first FET 22 and the second FET 24, and controls the first FET 22 and the second FET 24 to be turned on or off. When the FET is on, it means that the drain sources are conducting, and when it is off, it means that the drain sources are open. The first FET 22 and the second FET 24 are switching elements connected in series and alternately turned on and off. That is, when the PWM signal shows a high voltage, the drive circuit 20 turns on the first FET 22 and turns off the second FET 24. Further, when the PWM signal shows a low voltage, the drive circuit 20 turns off the first FET 22 and turns on the second FET 24.

When the first FET 22 is turned on and the second FET 24 is turned off, a current flows from the first DC voltage source E1 to the first FET 22, and a current flows from the switching circuit 18 to the low-pass filter 30 and the negative feedback circuit 34. When the first FET 22 is turned off and the second FET 24 is turned on, a current flows from the low-pass filter 30 and the negative feedback circuit 34 into the switching circuit 18, and a current flows from the second FET 24 to the second DC voltage source E2. As a result, a PWM signal having a pulse width corresponding to the voltage of the output signal of the DC amplifier 10 is output from the switching circuit 18 to the low-pass filter 30 and the negative feedback circuit 34.

In this way, the switching circuit 18 includes a first FET 22 and a second FET 24 as two switching elements connected in series and alternately turned on and off, and a drive circuit 20 that controls each FET on and off according to the level of the pulse width modulation signal. The PWM signal is output from the connection point between the first FET 22 and the second FET 24. As the switching element, another semiconductor element such as a bipolar transistor may be used instead of the FET.

The output terminal of the low-pass filter 30 is connected to the amplifier output terminal 4. The speaker 32 is provided on the outside of the switching power amplifier, and is detachable between the amplifier output terminal 4 and the ground conductor.

The low-pass filter 30 performs low-pass filter processing on the PWM signal output from the switching circuit 18 to reproduce an acoustic signal, and outputs the acoustic signal to the speaker 32. The speaker 32 reproduces the sound corresponding to the acoustic signal.

A negative feedback circuit 34 is connected between the connection point of the switching circuit 18 and the low-pass filter 30 and the second input terminal 2. The negative feedback circuit 34 includes a first feedback resistor Ra, a second feedback resistor Rb, and a feedback circuit capacitor 36. The first feedback resistor Ra is connected between the connection point of the switching circuit 18 and the low-pass filter 30 and the second input terminal 2. The second feedback resistor Rb and the feedback circuit capacitor 36 are connected in parallel between one end of the first feedback resistor Ra on the second input terminal 2 side and the ground conductor. The first feedback resistor Ra and the second feedback resistor Rb form a voltage dividing circuit that divides the output voltage of the switching circuit 18 and outputs the voltage to the second input terminal 2, and the first feedback resistor Ra and the feedback circuit capacitor. Reference numeral 36 denotes a low-pass filter that performs low-pass filter processing on the output voltage of the switching circuit 18.

In this way, the negative feedback circuit 34 performs low-pass filter processing on the output voltage of the switching circuit 18, divides the voltage at a predetermined ratio, and outputs the feedback signal to the second input terminal 2. As a result, a part of the voltage output from the switching circuit 18 to the low-pass filter 30 is fed back to the DC amplifier 10. When such a negative feedback circuit 34 is not provided and the gain from the first input terminal 1 to the low-pass filter 30 is sufficiently large, the gain when the negative feedback circuit 34 is provided is switched. It is determined by the rate at which the output voltage of the circuit 18 is fed back to the second input terminal 2.

(2) Distortion of acoustic signal Distortion of the acoustic signal output from the switching power amplifier to the speaker 32 will be described. If there are variations in the characteristics of the first FET 22 and the second FET 24 included in the switching circuit 18, the acoustic signal will be distorted. For example, under the condition that the voltage output to the gate of the first FET 22 and the voltage output to the gate of the second FET 24 are the same value, the current flowing through the drain and the source of the first FET 22 and the current flowing through the drain and the source of the second FET 24 If there is a difference in current, the positive and negative values of the acoustic signal will be disproportionate, and the acoustic signal output from the switching power amplifier will be distorted.

Further, when no signal is input to the amplifier input terminal 0, ideally, the voltage output by the DC amplifier 10 to the switching amplification unit 38 is 0. However, depending on the state of each transistor included in the DC amplifier 10, the DC amplifier 10 may output a DC offset voltage to the switching amplification unit 38. When a DC offset voltage is output from the DC amplifier 10 to the switching amplification unit 38, an error occurs in the pulse width of the PWM signal. That is, when the DC offset voltage is positive, an error occurs in which the time width during which the PWM signal becomes a high voltage becomes long. As a result, an imbalance occurs between the current flowing through the first FET 22 and the current flowing through the second FET 24, and further, the positive and negative values of the acoustic signal output from the switching power amplifier are disproportionate, and the acoustic signal is distorted. Occurs.

The DC amplifier 10 according to the present embodiment includes a variable resistor for adjusting the DC offset voltage output to the switching amplification unit 38. Therefore, as will be described later, by adjusting the resistance value of the variable resistor so that the distortion generated in the acoustic signal due to the characteristic variation of the first FET 22 and the second FET 24 and the distortion generated in the acoustic signal due to the DC offset voltage are suppressed from each other. The DC offset voltage is adjusted. If the distortion generated in the acoustic signal due to the variation in the characteristics of the FET is sufficiently small, the DC offset voltage may be adjusted to 0 or a vicinity of 0.

As described above, in the switching power amplifier, the DC amplifier 10 includes a variable resistor that adjusts the DC offset voltage that appears in the connection path between the DC amplifier 10 and the switching amplifier 38, and the DC offset voltage that appears in this connection path is By adjusting the resistance value of the variable resistor, it is determined according to the distortion included in the output signal of the switching circuit 18.

(3) Configuration of DC amplifier (3-1) Outline of configuration of DC amplifier FIG. 2 shows the configuration of the DC amplifier 10 in detail. The components shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. The DC amplifier 10 includes a front stage circuit 101 and a rear stage circuit 102. The front-stage circuit 101 inverts the phase of the acoustic signal input from the first input terminal 1, amplifies it, and outputs it to the rear-stage input terminal 6 and the rear-stage input terminal 7 included in the rear-stage circuit 102. The front-stage circuit 101 amplifies the acoustic signal input from the second input terminal 2 in the same phase and outputs it to the rear-stage input terminal 6 and the rear-stage input terminal 7.

The latter-stage circuit 102 inverts the phase of the acoustic signal input from the latter-stage input terminal 6, amplifies it, and outputs it to the DC amplifier output terminal 3. Similarly, the post-stage circuit 102 inverts the phase of the acoustic signal input from the post-stage input terminal 7, amplifies it, and outputs it to the DC amplifier output terminal 3. A switching amplification unit 38 is connected to the DC amplifier output terminal 3, and a speaker 32 is connected to the switching amplification unit 38.

With such a configuration, an acoustic signal having the same phase as the acoustic signal input to the first input terminal 1 is output to the switching amplification unit 38, and an acoustic signal having a phase opposite to the acoustic signal input to the second input terminal 2 is output. It is output to the switching amplification unit 38. The switching amplification unit 38 amplifies the acoustic signal and outputs it to the speaker 32.

(3-2) Configuration of Pre-Stage Circuit The pre-stage circuit 101 includes a first circuit unit 40 and a second circuit unit 42 that can be complementary to each other. Complementary to each other means that the bias voltages appearing at symmetrical positions on the structure have the same value and opposite polarity, and the bias currents flowing in the symmetrical path on the structure have the same value and opposite directions. A certain relationship. Ideally, the potential at each node connecting the two complementary circuits is zero. Except for the variable resistors R11 and R13, semiconductor elements complementary to each other and resistors (resistors) having the same resistance value are used in the first circuit unit 40 and the second circuit unit 42.

The first circuit unit 40 includes transistors Q1, Q3, Q5, Q7, resistors R1, R14, R16, a variable resistor R11, and a Zener diode D3. The second circuit unit 42 includes transistors Q2, Q4, Q6, Q8, resistors R2, R15, R17, a variable resistor R13, and a Zener diode D4. Transistors Q1, Q4, Q5 and Q8 are PNP type, and transistors Q2, Q3, Q6 and Q7 are NPN type.

The variable resistors R11 and R13 include a linear resistor material and a slider that can slide while in contact with the resistor material. The resistance values at both ends of these variable resistors are constant with the resistance value R of the linear resistance material. The resistance value between one end of these variable resistors and the slider is kR, and the resistance value between the other end and the slider is (1-k) R. However, k is a number of 0 or more and 1 or less, which is determined according to the slide position of the slider. As described above, the resistance value between one end of the variable resistor and the slider and the resistance value between the other end of the variable resistor and the slider are variable depending on the position of the slider. .. Variable resistors with sliders are sometimes referred to by those skilled in the art as potentiometers.

The circuit configuration of the first circuit unit 40 will be described. The base of the transistor Q1 is connected to the first input terminal 1. The emitter of transistor Q1 is connected to the emitter of transistor Q3. The collector of transistor Q3 is connected to the base of transistor Q7. One end of the variable resistor R11 is connected to the collector of the transistor Q3, and the slider of the variable resistor R11 is connected to the base of the transistor Q3.

The base of the transistor Q5 is connected to the second input terminal 2. One end of the resistor R1 is connected to the emitter of the transistor Q5, and the other end is connected to the emitter of the transistor Q7. The cathode of the bias diode D1 of the third circuit unit 44 described later is connected to the collector of the transistor Q7, and the resistor of the third circuit unit 44 described later is connected between the anode of the bias diode D1 and the positive electrode of the DC voltage source E1. R3 is connected.

The negative electrode of the DC voltage source E1 is connected to the ground conductor. Resistors R16 and R14 connected in series are connected between the positive electrode of the DC voltage source E1 and the base of the transistor Q7. The cathode of the Zener diode D3 is connected to the series connection point of the resistors R16 and R14, and the anode of the Zener diode D3 is connected to the ground conductor.

The circuit configuration of the second circuit unit 42 will be described. The base of the transistor Q2 is connected to the first input terminal 1. The emitter of transistor Q2 is connected to the emitter of transistor Q4. The collector of transistor Q4 is connected to the base of transistor Q8. One end of the variable resistor R13 is connected to the collector of the transistor Q4, and the slider of the variable resistor R13 is connected to the base of the transistor Q4.

The base of the transistor Q6 is connected to the second input terminal 2. One end of the resistor R2 is connected to the emitter of the transistor Q6, and the other end is connected to the emitter of the transistor Q8. The anode of the bias diode D2 of the fourth circuit unit 46 described later is connected to the collector of the transistor Q8, and the resistor of the fourth circuit unit 46 described later is connected between the cathode of the bias diode D2 and the negative electrode of the DC voltage source E2. R4 is connected.

The positive electrode of the DC voltage source E2 is connected to the ground conductor. Resistors R17 and R15 connected in series are connected between the negative electrode of the DC voltage source E2 and the base of the transistor Q8. The anode of the Zener diode D4 is connected to the series connection point of the resistors R17 and R15, and the cathode of the Zener diode D4 is connected to the ground conductor.

The connection between the first circuit unit 40 and the second circuit unit 42 will be described. The lower end of the variable resistor R11 included in the first circuit unit 40 (one end on the side opposite to the collector side of the transistor Q3) is the upper end of the variable resistor R13 included in the second circuit unit 42 (opposite the collector side of the transistor Q4). It is connected to one end of the side). Each collector of the transistors Q1 and Q5 included in the first circuit unit 40 is connected to the anode of the Zener diode D4 included in the second circuit unit 42. Each collector of the transistors Q2 and Q6 included in the second circuit unit 42 is connected to the cathode of the Zener diode D3 included in the first circuit unit 40.

(3-3) Bias of each transistor included in the pre-stage circuit The bias of each transistor included in the pre-stage circuit 101 will be described. In the following description, the reference numerals attached to each resistor shall represent the resistance value of each resistor. Further, the sliders of the variable resistors are arranged so that the first circuit unit 40 and the second circuit unit 42 are complementary to each other and the DC offset voltage appearing at the first input terminal 1 and the second input terminal 2 becomes 0. It is assumed that the basic state in which the position is adjusted is established.

The bias of each transistor is the complementarity of the first circuit unit 40 and the second circuit unit 42, the base-emitter voltage of each transistor is a general value, and the terminal voltage appearing in the Zener diodes D3 and D4 is constant. It is determined under certain conditions. Here, the collector current, the emitter current, and the base current will be described as the bias of each transistor. The PNP transistor is sometimes referred to as the emitter-base voltage, but in order to simplify the expression, the expression is unified here as the base-emitter voltage.

First, pay attention to the voltage between the base and emitter of each of the transistors Q1 to Q4. The voltage Va between the base of the transistor Q3 and the base of the transistor Q4 is the sum of the base-emitter voltages of the transistors Q3, Q1, Q2 and Q4. That is, the voltage of the emitter based on the base of the transistor Q4, the voltage of the base based on the emitter of the transistor Q2, the voltage of the emitter based on the base of the transistor Q1, and the voltage of the base based on the emitter of the transistor Q3. The sum of the voltages is the voltage Va.

In FIG. 2, the portion of the variable resistor R11 above the slider is shown as the resistance portion R11a, and the portion below the slider is shown as the resistance portion R11b. Further, the portion of the variable resistor R13 below the slider is indicated as the resistance portion R13a, and the portion above the slider is indicated as the resistance portion R13b. Further, the portion where the resistance portions R11b and R13b are connected in series is shown as the resistance portion R12.

Generally, the base-emitter voltage Vbe of a transistor is 0.6V to 0.7V, and the change is small. As a result, a current of Ia = Va / R12 = 4 · Vbe / R12 flows through the resistor portion R12. That is, the current Ia flowing through the resistance portion R12 is determined according to (Equation 1).

(Equation 1) Ia = 4 · Vbe / R12

Since the current flowing through the bases of the transistors Q3 and Q4 is very small, a current having substantially the same value as the current Ia flowing through the resistance portion R12 flows through the resistance portions R11a and R13a. Therefore, the voltage drop of the series connection portion of the resistors R11a, R12 and R13a is determined, and the voltage Vb between the base of the transistor Q7 and the base of the transistor Q8 is determined. That is, the voltage Vb is determined according to (Equation 2).

(Equation 2) Vb = (R11a + R12 + R13a) · Ia
= 4 · Vbe · (R11a + R12 + R13a) / R12

As described above, the transistors Q1 to Q4 and the resistors R11a, R12 and R13a form a voltage stabilizing circuit for stabilizing the voltage Vb between the base of the transistor Q7 and the base of the transistor Q8.

Next, pay attention to the voltage between the bases and emitters of the transistors Q5 to Q8. The base-emitter voltage of each of the transistors Q7, Q5, Q6 and Q8 is also 0.6V to 0.7V, and the change is small. Further, assuming that the first circuit unit 40 and the second circuit unit 42 are complementary to each other and the potential of the second input terminal 2 (voltage with respect to the ground conductor) is 0, the resistors R1 and R2 The voltages Vr applied to each are equal, and Vr = Vb / 2-2 · Vbe. That is, the voltage Vr applied to each of the resistors R1 and R2 is determined according to (Equation 3).

(Equation 3) Vr = Vb / 2-2 ・ Vbe

Here, the voltage Vb is a value determined according to (Equation 2). Since the resistance values of the resistors R1 and R2 are equal, the currents flowing through them are equal, and Vr / R1 = Vr / R2. This current is equal to the emitter current Ie of the transistors Q5 to Q8.

Therefore, the emitter currents Ie of the transistors Q5 to Q8 are determined according to (Equation 4).

(Equation 4) Ie = (Vb / 2-2 ・ Vbe) / R1 = (Vb / 2-2 ・ Vbe) / R2

The collector currents Ic of the transistors Q5 to Q8 are substantially equal to the respective emitter currents Ie. That is, Ic = Ie may be considered.

Next, focusing on the inter-terminal voltage appearing in the Zener diodes D3 and D4, the collector current and the emitter current of the transistors Q1 to Q4 will be described. A reverse bias voltage is applied to the Zener diode D3 from the positive electrode of the DC voltage source E1 via the resistor R16. The diode D3 functions as a constant voltage generator, and a constant voltage Vz3 appears between the terminals with the cathode side as positive. A reverse bias voltage is applied to the Zener diode D4 from the negative electrode of the DC voltage source E2 via the resistor R17. The diode D4 functions as a constant voltage generator, and a constant voltage Vz4 appears between the terminals with the anode side as negative.

Since the first circuit unit 40 and the second circuit unit 42 are complementary to each other, the potential of the base of the transistor Q7, that is, the potential of the collector of the transistor Q3 is Vb / 2. Since the potential of the cathode of the Zener diode D3 is Vz3, the current I14 flowing through the resistor R14 connected between the cathode of the Zener diode D3 and the collector of the transistor Q3 is determined according to (Equation 5).

(Equation 5) I14 = (Vz3-Vb / 2) / R14

The current flowing through the resistor R14 is shunted to the collector of the transistor Q3 and the resistor R11. Therefore, the collector current Ic3 of the transistor Q3 is a value obtained by subtracting the above current Ia from the current I14 as shown in (Equation 6).

(Equation 6) Ic3 = I14-Ia

The emitter current of the transistors Q3 and Q1 and the collector current of the transistor Q1 are substantially equal to the collector current Ic3 of the transistor Q3. Therefore, it can be considered that the collector current and the emitter current of the transistors Q1 and Q3 are determined according to (Equation 6).

Since the first circuit unit 40 and the second circuit unit 42 are complementary to each other, the collector current Ic4 of the transistor Q4 is determined by the same principle as the collector current Ic3. That is, the current I15 flowing through the resistor R15 is determined according to (Equation 7), and the collector current Ic4 is determined according to (Equation 8).

(Equation 7) I15 = (Vz4-Vb / 2) / R15

(Equation 8) Ic4 = I15-Ia

Further, it can be considered that the collector current and the emitter current of the transistors Q2 and Q4 are determined according to (Equation 8).

The base current of each transistor Q1 to Q8 is a value obtained by dividing the collector current of each transistor by the current amplification factor hfe peculiar to each transistor.

As described above, the bias of the transistors Q1 to Q8 is based on the complementarity of the first circuit unit 40 and the second circuit unit 42, and the base-emitter voltage Vbe (= 0.6V to 0.7V) of each transistor and the Zener It is determined by the voltage between the terminals appearing on the diodes D3 and D4. Therefore, the bias of the transistors Q1 to Q8 is not easily affected by the fluctuation of the output voltage of the DC voltage sources E1 and E2.

The collector potentials of the transistors Q7 and Q8 fluctuate according to the fluctuations of the output voltages of the DC voltage sources E1 and E2, and the fluctuations of these collector potentials are transmitted to the first input terminal 1 and the second input terminal 2. The effect on the appearing DC offset voltage is small. The reason is that even if the collector potentials of the transistors Q7 and Q8 fluctuate, the bias of the transistors Q1 to Q8 is determined by the base-emitter voltage Vbe of each transistor and the terminal voltage appearing in the Zener diodes D3 and D4.

(3-4) Amplification operation of the pre-stage circuit The amplification operation by the first circuit unit 40 will be described. The transistor Q1 constitutes an emitter follower in which the collector is AC-grounded. As will be described later, it can be considered that the collector-emitter of the transistor Q3 is short-circuited in an alternating current manner, and it can be said that the resistor R14 and the transistor Q7 are connected to the emitter of the transistor Q1. Here, the term “AC grounded or short-circuited” means that the potential or the voltage between terminals does not fluctuate even if the current fluctuates according to the acoustic signal.

The acoustic signal input from the first input terminal 1 to the base of the transistor Q1 is output from the emitter of the transistor Q1 to the base of the resistor R14 and the transistor Q7. The connection point between the resistor R14 and the Zener diode D3 is AC grounded, and an acoustic signal is transmitted to the base of the transistor Q7 according to the voltage generated in the resistor R14.

Since the bias diode D1 connected to the collector of the transistor Q7 is in a forward bias state, it can be considered that it is short-circuited in an alternating current, and the resistor R3 and the base of the transistor Q9 are connected to the collector of the transistor Q7. It can be said that there is.

The transistor Q7 outputs the amplified acoustic signal to the base of the resistor R3 and the transistor Q9 according to the acoustic signal input from the base. That is, the connection point between the resistor R3 and the DC voltage source E1 is AC grounded, and an acoustic signal is transmitted to the base of the transistor Q9 according to the voltage generated in the resistor R3.

Like the transistor Q1, the transistor Q5 constitutes an emitter follower in which the collector is AC-grounded. The emitter of the transistor Q7 is connected to the emitter of the transistor Q5 via a resistor R1. Since the transistor Q5 constitutes an emitter follower, the impedance seen from the resistor R1 on the transistor Q5 side is small. Therefore, the transistor Q7 constitutes an emitter grounded amplifier circuit in which a resistor R1 is inserted between the emitter and the grounded conductor with respect to the emitter follower formed by the transistor Q1. Therefore, the acoustic signal input to the first input terminal 1 and transmitted by the emitter follower is amplified after the phase is inverted by the grounded-emitter amplifier circuit, and the acoustic signal is transmitted to the base of the transistor Q9.

The acoustic signal input from the second input terminal 2 to the base of the transistor Q5 is output to the emitter of the transistor Q7 via the resistor R1. The transistor Q7 outputs the amplified acoustic signal to the base of the resistor R3 and the transistor Q9 according to the acoustic signal input from the emitter. An acoustic signal is transmitted to the base of the transistor Q9 according to the voltage generated in the resistor R3.

Since the transistor Q1 constitutes an emitter follower, the impedance seen from the transistor Q7 on the transistor Q1 side is small. Therefore, the transistor Q7 forms a base grounded amplifier circuit with respect to the emitter follower formed by the transistor Q5. Therefore, the acoustic signal input to the second input terminal 2 and transmitted by the emitter follower is amplified in the same phase by the base grounded amplifier circuit, and the acoustic signal is transmitted to the base of the transistor Q9.

Next, the amplification operation by the second circuit unit 42 will be described. The second circuit unit 42 performs the same amplification operation as the first circuit unit 40 with respect to the acoustic signals input to the first input terminal 1 and the second input terminal 2, and the amplified acoustic signal is used as the base of the transistor Q10. Output to.

The acoustic signal input from the first input terminal 1 to the base of the transistor Q2 is output from the emitter of the transistor Q2 to the base of the resistor R15 and the transistor Q8, and acoustically to the base of the transistor Q8 according to the voltage generated in the resistor R15. The signal is transmitted. The acoustic signal input from the second input terminal 2 to the base of the transistor Q6 is output to the emitter of the transistor Q8 via the resistor R2.

The transistor Q8 outputs an acoustic signal to the resistor R4 and the transistor Q10 according to the acoustic signal transmitted by each emitter follower and input to the base and the emitter. An acoustic signal is transmitted to the base of the transistor Q10 according to the voltage generated in the resistor R4.

Since the transistor Q8 forms an emitter grounded amplifier circuit with respect to the emitter follower formed by the transistor Q2, the acoustic signal input to the first input terminal 1 and transmitted by the emitter follower is amplified after the phase is inverted. , The acoustic signal is transmitted to the base of the transistor Q10.

Further, since the transistor Q8 forms a base grounded amplifier circuit with respect to the emitter follower formed by the transistor Q6, the acoustic signal input to the second input terminal 2 is amplified in the same phase, and the acoustic signal is amplified to the base of the transistor Q10. The signal is transmitted.

As described above, the transistors Q1 and Q2 form an emitter follower for increasing the input impedance of the first input terminal 1, and the transistors Q5 and Q6 form an emitter follower for increasing the input impedance of the first input terminal 2. To configure. The transistors Q7 and Q8 function as a main body transistor that amplifies the acoustic signal input from the first input terminal 1 after inverting the phase and amplifies the acoustic signal input from the second input terminal 2 in the same phase. Have.

Transistors Q3 and Q4 are auxiliary transistors for bias setting, and it can be considered that these collector-emitters are short-circuited in an alternating current manner. In response to the acoustic signal input from the first input terminal 1, the transistors Q1 and Q2 output acoustic signals of the same amplitude and phase to the emitters of the transistors Q3 and Q4. The bases of the transistors Q3 and Q4 are connected by the resistance section R12, but since the acoustic signals at the emitters of the transistors Q3 and Q4 have the same amplitude and phase, a voltage based on the acoustic signal appears at both ends of the resistance section R12. No. Therefore, since a voltage that changes according to the acoustic signal does not appear between the base emitters and collector emitters of the transistors Q3 and Q4, these collector emitters are short-circuited with respect to the acoustic signal, that is, short-circuited with alternating current. May be.

As described above, the output path of the emitter follower formed by the transistor Q1 and the output path of the emitter follower formed by the transistor Q2 are provided with a bias setting circuit having a small influence on the acoustic signal. This bias setting circuit includes transistors Q3, resistor portions R11a, R12, R13a and transistors Q4, and together with transistors Q1 and Q4, constitutes the above-mentioned voltage stabilization circuit.

(3-5) Configuration of Post-Stage Circuit The post-stage circuit 102 includes a third circuit unit 44 and a fourth circuit unit 46. Here, it is assumed that the third circuit unit 44 and the fourth circuit unit 46 are complementary to each other. The third circuit unit 44 includes transistors Q9, Q11, resistors R3, R5, R7 and a bias diode D1. The fourth circuit unit 46 includes transistors Q10, Q12, resistors R4, R6, R8 and a bias diode D2. Transistors Q9 and Q11 are PNP type, and transistors Q10 and Q12 are NPN type. The specific configuration of the subsequent circuit 102 is not limited to the circuit configuration shown in the figure.

The circuit configuration of the third circuit unit 44 will be described. The base of the transistor Q9 forms the post-stage input terminal 6. The base of the transistor Q9 is connected to the collector of the transistor Q7 included in the first circuit unit 40. A resistor R5 is connected between the emitter of the transistor Q9 and the positive electrode of the DC voltage source E1. The collector of transistor Q9 is connected to the ground conductor. The base of transistor Q11 is connected to the emitter of transistor Q9. A resistor R7 is connected between the emitter of the transistor Q11 and the positive electrode of the DC voltage source E1. The collector of the transistor Q11 is connected to the DC amplifier output terminal 3.

The circuit configuration of the fourth circuit unit 46 will be described. The base of the transistor Q10 forms the post-stage input terminal 7. The base of the transistor Q10 is connected to the collector of the transistor Q8 included in the second circuit unit 42. A resistor R6 is connected between the emitter of the transistor Q10 and the negative electrode of the DC voltage source E2. The collector of transistor Q10 is connected to the ground conductor. The base of transistor Q12 is connected to the emitter of transistor Q10. A resistor R8 is connected between the emitter of the transistor Q12 and the negative electrode of the DC voltage source E2. The collector of the transistor Q12 is connected to the DC amplifier output terminal 3.

In the third circuit unit 44 and the fourth circuit unit 46, the output voltage of the DC voltage source E1, the output voltage of the DC voltage source E2, the base-emitter voltage of the transistors Q9 to Q12, and the forward voltage of the diodes D1 and D2, respectively. Has a predetermined value. Therefore, the bias of each transistor included in the first circuit unit 40 and the second circuit unit 42 and the bias of each transistor included in the third circuit unit 44 and the fourth circuit unit 46 are determined.

(3-6) Amplification operation of the rear circuit The rear circuit 102 transmits the signal output from the first circuit unit 40 and the signal output from the second circuit unit 42 between one path and the ground conductor. It operates as a conversion circuit that converts to a single output signal. First, the amplification operation of the third circuit unit 44 will be described. The transistor Q9 causes a current corresponding to the acoustic signal input to the base to flow through the resistor R5. As a result, an acoustic signal is transmitted to the base of the transistor Q11 according to the voltage appearing in the resistor R5.

The transistor Q11 passes a current corresponding to the acoustic signal transmitted to the base through the path connected to the resistor R7 and the collector of the transistor Q11. As a result, an acoustic signal is output from the DC amplifier output terminal 3 to the switching amplification unit 38.

The transistor Q9 constitutes an emitter follower, and the transistor Q11 constitutes an emitter grounded amplifier circuit in which a resistor R7 is connected between the emitter and the DC voltage source E1 (grounded conductor for an acoustic signal). Therefore, the third circuit unit 44 has an emitter follower and a grounded-emitter amplifier circuit connected in series, and the acoustic signal input to the subsequent input terminal 6 is amplified after the phase is inverted, and the switching amplifier unit 38 Is output to.

The fourth circuit unit 46 performs the same amplification operation as the third circuit unit 44, and outputs the amplified acoustic signal from the fourth circuit unit 46. That is, the transistor Q10 constitutes an emitter follower, and the transistor Q12 constitutes an emitter grounded amplifier circuit in which a resistor R8 is connected between the emitter and the grounded conductor for an acoustic signal. Therefore, the fourth circuit unit 46 has an emitter follower and a grounded-emitter amplifier circuit connected in series, and the acoustic signal input to the subsequent input terminal 7 is amplified after the phase is inverted, and the switching amplifier unit 38 Is output to.

(3-7) Switching Amplification Unit The acoustic signal output from the third circuit unit 44 and the acoustic signal output from the fourth circuit unit 46 are input to the switching amplification unit 38 from the DC amplifier output terminal 3. The switching amplification unit 38 amplifies the acoustic signal output from the DC amplifier output terminal 3 and outputs it to the speaker 32. The speaker 32 reproduces the sound corresponding to the acoustic signal.

As described above, the acoustic signal input from the first input terminal 1 is output to the speaker 32 in the same phase, and the acoustic signal input from the second input terminal 2 is output to the speaker 32 in the opposite phase. A negative feedback circuit 34 is connected between the connection point of the switching circuit 18 and the low-pass filter 30 and the second input terminal 2, and a part of the voltage output to the speaker 32 is negatively fed back to the DC amplifier 10. Will be done.

(3-8) Adjustment of Variable Resistor When the first circuit unit 40 and the second circuit unit 42 are complementary, the DC offset voltage appearing at the first input terminal 1 and the second input terminal 2 becomes 0. .. In reality, the DC offset voltage is often a non-zero value because the electrical characteristics of each circuit element vary. Since the gain of the DC amplifier 10 also exceeds 1 with respect to the DC voltage, in this case, the DC amplifier 10 outputs a non-zero DC offset voltage from the DC amplifier output terminal 3 to the switching amplification unit 38.

Further, even if there is no variation in the electrical characteristics of each circuit element, the first circuit unit 40 and the second circuit unit 40 and the second circuit unit 40 can be changed by changing the position of the slider of the variable resistor R11 or the position of the slider of the variable resistor R13. Even if the complement of the circuit unit 42 is broken, the DC amplifier 10 outputs a non-zero DC offset voltage from the DC amplifier output terminal 3. That is, the DC amplifier 10 is not 0 from the DC amplifier output terminal 3 by changing the resistance values of the resistance unit R11a and the resistance unit R12, or by changing the resistance values of the resistance unit R13a and the resistance unit R12. Output voltage.

That is, from the potential of the base of the transistor Q3, the voltage Vbe between the base and emitter of the transistor Q3, the voltage Vbe between the base and emitter of the transistor Q1 (the potential of the first input terminal 1), and the potential of the base of the transistor Q4. The operating state is determined so that the base-emitter voltage Vbe of the transistor Q4 and the potential (potential of the first input terminal 1) increased by the base-emitter voltage Vbe of the transistor Q2 are equal to each other. Then, the potential of the first input terminal 1 in such an operating state in which the basic state is broken becomes the DC offset voltage. The DC amplifier 10 amplifies the DC offset voltage of the first input terminal 1 and outputs it to the switching amplification unit 38.

As described in the item of "(2) Distortion of acoustic signal" above, the switching power amplifier according to the present embodiment uses such a DC offset voltage to reduce distortion. That is, the variable resistor R11 and the variable resistor R11 and The position of at least one slider of R13 is adjusted. As a result, the DC offset voltage is adjusted, and the distortion of the acoustic signal output to the speaker 32 is reduced. If the distortion generated in the acoustic signal due to the variation in the characteristics of the FET is sufficiently small, the DC offset voltage may be adjusted to 0 or a vicinity of 0.

(4) Effect Generally, in an audio power amplifier, a regulated power supply circuit is not used as a DC voltage source. That is, the AC voltage from the commercial power supply is stepped down by the transformer, rectified by the diode, and the voltage smoothed by the capacitor is often used as the power supply voltage without using the regulator IC.

When the regulated power supply circuit is not used in the DC voltage sources E1 and E2 shown in FIG. 2, the output voltage of the DC voltage sources E1 and E2 may decrease due to a large current flowing through the DC voltage sources E1 and E2. ..

As described above, in the DC amplifier 10 according to the present embodiment, the bias current, base potential, and emitter potential of the transistors Q1 to Q8 have small fluctuations due to fluctuations in the output voltages of the DC voltage sources E1 and E2. As a result, fluctuations in the DC offset voltage appearing at the first input terminal 1 and the second input terminal 2 are suppressed, and by extension, fluctuations in the DC offset voltage output from the subsequent circuit 102 to the switching amplification unit 38 are also suppressed. Since the DC amplifier 10 amplifies the signal in the frequency band from frequency 0 to the audible frequency, the DC offset voltage generated at each input terminal is amplified and output.

According to the present embodiment, by suppressing the fluctuation of the DC offset voltage in the pre-stage circuit 101, the fluctuation of the DC offset voltage output from the DC amplifier 10 to the switching amplification unit 38 is suppressed. As a result, the distortion contained in the acoustic signal due to the DC offset voltage is stabilized, and the distortion generated in the acoustic signal due to the variation in the characteristics of the first FET 22 and the second FET 24 is stably suppressed.

(5) Modification Example of Bias Setting Circuit FIG. 3 shows a modification of a switching power amplifier. This switching power amplifier is a modification of the bias setting circuit composed of the transistors Q3, the variable resistors R11, R13, and the transistors Q4 in FIG.

A variable bias resistor R18 is connected between the emitter of the transistor Q1 and the emitter of the transistor Q3. The collector of the transistor Q3 is connected to the base of the transistor Q7 and one end of the resistor R14. The variable bias resistor R18 has a variable resistance value at both ends.

Similarly, a variable bias resistor R19 is connected between the emitter of the transistor Q2 and the emitter of the transistor Q4. The collector of the transistor Q4 is connected to the base of the transistor Q8 and one end of the resistor R15. The variable bias resistor R19 has a variable resistance value at both ends. The positive electrode of the bias voltage source V34 is connected to the base of the transistor Q3, and the negative electrode of the bias voltage source V34 is connected to the base of the transistor Q4. Here, a reference state in which the resistance values of the variable bias resistors R18 and R19 are adjusted so that the first circuit unit 40 and the second circuit unit 42 are complementary will be described.

Assuming that the DC offset voltage at the first input terminal 1 is 0 and the potential of the first input terminal 1 is 0, the base potential V3 of the transistor Q3 is the base-emitter voltage Vbe of the transistor Q1 and the variable bias resistance. It is the sum of the voltage drops R18 and I14 in the device R18 and the base-emitter voltage Vbe of the transistor Q3. Assuming that the first circuit unit 40 and the second circuit unit 42 are operating in a complementary manner, the potential V3 at the base of the transistor Q3 is V34 / 2. Therefore, the following (Equation 9) is established, and (Equation 10) is obtained by solving this for I14.

(Number 9) V34 / 2 = 2 ・ Vbe + R18 ・ I14

(Equation 10) I14 = (V34 / 2-2 ・ Vbe) / R18

The base potential of the transistor Q7 is obtained by subtracting the inter-terminal voltages R14 and I14 of R14 from the inter-terminal voltage Vz3 of the Zener diode D3. Therefore, the potential V7 at the base of the transistor Q7 is determined according to (Equation 11).

(Number 11) V7 = Vz3-R14 / I14
= Vz3-R14 ・ (V34 / 2-2 ・ Vbe) / R18

From the complementarity of the first circuit unit 40 and the second circuit unit 42, the current I15 flowing through the resistor R15 is determined according to (Equation 12), and the potential V8 at the base of the transistor Q8 is determined according to (Equation 13).

(Equation 12) I15 = (V34 / 2-2 ・ Vbe) / R19

(Equation 13) V8 = -Vz4 + R15 / I15
= -Vz3 + R15 ・ (V34 / 2-2 ・ Vbe) / R19

The voltage V78 between the base of the transistor Q7 and the base of the transistor Q8 can be obtained by subtracting (Equation 13) from (Equation 11).

(Number 14) V78 = Vz3 + Vz4
-(R14 / R18 + R15 / R19) · (V34 / 2-2 · Vbe)

Thus, under reference conditions where the variable bias resistors R18 and R19 are adjusted to a certain resistance value and the first circuit unit 40 and the second circuit unit 42 are complementary, the base of transistor Q7 according to (Equation 14). The voltage V78 between the transistor Q8 and the base of the transistor Q8 is determined. Further, the collector current and the emitter current of the transistors Q5 to Q8 are determined according to the equation in which V78 is substituted into Vb of (Equation 4).

Next, the distortion of the acoustic signal output from the switching power amplifier to the speaker 32 will be described. In the switching power amplifier according to this modification, the complementarity of the first circuit unit 40 and the second circuit unit 42 is broken by adjusting the resistance value of the variable bias resistor R18 or R19. That is, (i) a potential (th) that is lower than the base potential of the transistor Q3 by the base-emitter voltage Vbe of the transistor Q3, the voltage drops R18 and I14 at the variable bias resistor R18, and the base-emitter voltage Vbe of the transistor Q1. From the potential of 1 input terminal 1) and the potential of the base of the transistor Q4, the voltage Vbe between the base and emitter of the transistor Q4, the voltage drop R19 and I15 in the variable bias resistor R19, and the voltage Vbe between the base and emitter of the transistor Q2 increase. The operating state is determined so that the generated potential (potential of the first input terminal 1) becomes equal to (ii) the voltage between the base of the transistor Q3 and the base of the transistor Q4 becomes V34. Then, the potential of the first input terminal 1 in such an operating state that has collapsed from the basic state becomes the DC offset voltage. The DC amplifier 10 amplifies the DC offset voltage of the first input terminal 1 and outputs it to the switching amplification unit 38.

As a result, the DC amplifier 10 outputs a non-zero DC offset voltage. In this state, the variable bias resistor suppresses the distortion generated in the acoustic signal due to the characteristic variation of the first FET 22 and the second FET 24 in the switching circuit 18 and the distortion generated in the acoustic signal due to the DC offset voltage output by the DC amplifier 10. The resistance value of at least one of the vessels R18 and R19 is adjusted.

(11) Other Modified Examples In the above, an example in which a Zener diode is used as a constant voltage generator in the pre-stage circuit 101 of the DC amplifier 10 has been described. As the constant voltage generator, a DC voltage source or a battery may be used instead of the Zener diode. This DC voltage source may be one in which the AC voltage from a commercial power source is stepped down by a transformer, rectified by a diode, and further stabilized by a regulator IC for output.

In the embodiment shown in FIG. 2, by adjusting the position of at least one of the sliders of the variable resistors R11 and R13, the complementarity of the first circuit unit 40 and the second circuit unit 42 is broken, and the DC amplifier 10 The DC offset voltage output by is adjusted, and further, the distortion of the acoustic signal output from the switching amplification unit 38 to the speaker 32 is suppressed.

Further, in the modified embodiment shown in FIG. 3, by adjusting the resistance value of at least one of the variable bias resistors R18 and R19, the complementarity of the first circuit unit 40 and the second circuit unit 42 is broken, and the DC The DC offset voltage output by the amplifier 10 is adjusted, and the distortion of the acoustic signal output from the switching amplification unit 38 to the speaker 32 is suppressed.

In each embodiment, the values of the resistors in complementary positions such as the pair of resistors R1 and R2 and the set of resistors R14 and R15 in the first circuit unit 40 and the second circuit unit 42 are made different. This may break the complementarity, adjust the DC offset voltage, and suppress the distortion contained in the acoustic signal.

0 Amplifier input terminal, 1 1st input terminal, 2 2nd input terminal, 3 DC amplifier output terminal, 4 amplifier output terminal, 6, 7 Post-stage input terminal, 10 DC amplifier, 12 PWM signal generator, 14 capacitors, 16 comparison Instrument, 18 switching circuit, 20 drive circuit, 22 1st FET, 24 2nd FET, 30 low frequency pass filter, 32 speaker, 34 negative feedback circuit, 36 feedback circuit capacitor, 38 switching amplifier, 40 1st circuit unit, 42nd 2 circuit unit, 44 3rd circuit unit, 46 4th circuit unit, 101 pre-stage circuit, 102 post-stage circuit.

Claims (7)

DC amplifier and
A switching amplifier connected to the subsequent stage of the DC amplifier,
A negative feedback circuit that negatively feeds the signal output by the switching amplification unit to the DC amplifier,
In a switching amplifier with
The DC amplifier
The signal input to the first input terminal is amplified in phase and output to the switching amplification unit.
The signal input from the negative feedback circuit to the second input terminal is amplified in opposite phase and output to the switching amplification unit.
A variable resistor for adjusting the DC offset voltage appearing at the first input terminal and the second input terminal, which is a connection path with the switching amplification unit, is provided.
The switching amplification unit
A pulse width modulation signal generation unit that generates a pulse width modulation signal that is a pulse width modulation signal and whose pulse width is determined according to the output signal of the DC amplifier.
A switching circuit that operates on and off based on the pulse width modulation signal,
A switching amplifier characterized by being equipped with. In the switching amplifier according to claim 1,
A switching amplifier characterized in that the DC offset voltage appearing in the connection path is determined according to the distortion included in the output signal of the switching circuit. In the switching amplifier according to claim 1 or 2.
The pulse width modulation signal generation unit
An output holding unit that holds an output value according to the output signal of the DC amplifier,
A comparison unit that outputs a signal whose high or low is determined according to the difference between the output value from the output holding unit and the reference value as the pulse width modulation signal is provided.
The switching circuit
Two switching elements that are connected in series and turned on and off alternately,
A switching amplifier comprising a drive circuit that controls on / off of each of the switching elements according to the level of the pulse width modulated signal, and outputting a signal from a connection point of the two switching elements. The switching amplifier according to any one of claims 1 to 3.
The DC amplifier
The first circuit unit and the second circuit unit,
A conversion circuit that converts a signal output from the first circuit unit and a signal output from the second circuit unit into a single output signal and outputs the signal to the switching amplification unit is provided.
Each of the first circuit unit and the second circuit unit
A first emitter follower connected to the first input terminal of the DC amplifier,
A second emitter follower connected to the second input terminal of the DC amplifier,
A main body transistor in which a base is connected to the output path of the first emitter follower, an emitter is connected to the output path of the second emitter follower, and a signal is output from a collector.
A first resistor and a second resistor provided between the output path of the first emitter follower and a DC voltage source and connected in series, and
A constant voltage generator connected to a series connection point of the first resistor and the second resistor is provided.
The path leading to the collector of the first emitter follower and the transistors constituting the second emitter follower in the first circuit unit is connected to the series connection point in the second circuit unit.
The path leading to the collector of the first emitter follower and the transistors constituting the second emitter follower in the second circuit unit is connected to the series connection point in the first circuit unit.
A bias setting circuit for the first circuit unit and the second circuit unit in the output path of the first emitter follower in the first circuit unit and the output path of the first emitter follower in the second circuit unit. A switching amplifier characterized in that a bias setting circuit including the variable resistor is provided. In the switching amplifier according to claim 4,
Each of the first circuit unit and the second circuit unit
With the variable resistor
An auxiliary transistor in which an emitter is connected to a path leading to the emitter of a transistor constituting the first emitter follower and a collector is connected to a path leading to the base of the main body transistor is provided.
The variable resistor has a slider, and the resistance value between one end and the slider and the resistance value between the other end and the slider are variable according to the position of the slider. And
One end of the variable resistor is connected to the collector of the auxiliary transistor, and the slider of the variable resistor is connected to the base of the auxiliary transistor.
The other end of the variable resistor in the first circuit unit and the other end of the variable resistor in the second circuit unit are connected to each other.
A switching amplifier in which each of the auxiliary transistors and the variable resistor constitutes the bias setting circuit. In the switching amplifier according to claim 4,
Each of the first circuit unit and the second circuit unit
An auxiliary transistor is provided in which the emitter is connected to the path leading to the emitter of the transistor included in the first emitter follower and the collector is connected to the path leading to the base of the main body transistor.
The switching amplifier
A bias voltage source provided between the base of the auxiliary transistor in the first circuit unit and the base of the auxiliary transistor in the second circuit unit is provided.
The variable resistor has a variable resistance value at both ends.
In each of the first circuit unit and the second circuit unit,
The variable resistor is provided in the path leading to the emitter of the transistor included in the first emitter follower.
A switching amplifier in which each of the auxiliary transistors, the variable resistor, and the bias voltage source constitutes the bias setting circuit. The switching amplifier according to any one of claims 4 to 6.
The DC voltage source is a power supply source of the switching amplifier, and the switching amplifier is a power amplifier in which a speaker is connected to the switching amplification unit.

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