JP6935539B2 - Wiring board manufacturing method - Google Patents

Description

The present invention relates to a method for manufacturing a wiring board.

A support in which a thick foil made of copper, a release layer, and a thin foil made of copper are sequentially laminated on a support substrate is known. When manufacturing a wiring board using this support, first, a resist layer having an opening is formed on a thin foil. Then, a wiring layer made of copper is formed on the thin foil exposed in the opening, and after removing the resist layer, an insulating layer covering the wiring layer is formed on the thin foil. If necessary, the wiring layer and the insulating layer are sequentially laminated on the insulating layer, the support substrate and the thick foil are mechanically removed via the release layer, and the thin foil is removed by etching (for example, Patent Document). 1).

Further, there is known a support in which a thick foil made of copper, a release layer, and a thin foil made of a metal that can be selectively etched with respect to a wiring layer are sequentially laminated on a support substrate. When a wiring board is manufactured using this support, a resist layer having an opening is formed on the thin foil. Then, a wiring layer is formed on the thin foil exposed in the opening, and after removing the resist layer, an insulating layer covering the wiring layer is formed on the thin foil. If necessary, the wiring layer and the insulating layer are sequentially laminated on the insulating layer, the support substrate and the thick foil are mechanically removed via the release layer, and the thin foil is removed by etching (for example, Patent Document). 2).

Patent No. 4273895 JP-A-2002-76578

However, in the method for manufacturing a wiring board described in Patent Document 1, since the thin foil and the wiring layer are soluble in the same etching solution, when the thin foil is removed by etching, the edge of the wiring layer is overetched. The portion is also etched, and the surface of the wiring layer is dented from the surface of the insulating layer. If the surface of the wiring layer is dented from the surface of the insulating layer, it is difficult for the solder to enter the dent when connecting the wiring layer and the semiconductor chip with solder, so that the connection reliability between the wiring board and the semiconductor chip is lowered. There is a risk of

In the method for manufacturing a wiring board described in Patent Document 2, since the thin foil can be selectively etched with respect to the wiring layer, there is a problem that the thickness of the wiring layer is reduced due to overetching in the step of removing the thin foil. Does not occur. However, for example, when the thin foil is nickel, the surface of nickel is easily oxidized to form a passivation film, so that the adhesion between nickel and the wiring layer cannot be obtained and the interface between nickel and the wiring layer may be peeled off. be. As a result, the yield of the wiring board is reduced.

The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a wiring board capable of improving connection reliability and yield.

In the method of manufacturing this wiring substrate, a first metal layer and a second metal layer whose upper surface is a roughened surface or is made of particles are sequentially laminated on a support substrate, and the second metal layer is formed by stacking the second metal layer. A step of preparing a support that can be selectively etched with respect to the first metal layer, a step of selectively forming a third metal layer on the upper surface of the second metal layer, and an etching solution. At the same time as roughening the third metal layer, the second metal layer not covered with the third metal layer was melted, and the third metal layer was laminated on the second metal layer. The step of forming the first wiring layer, the step of forming an insulating layer covering the first wiring layer on the first metal layer, the step of removing the support substrate, and further the first metal. It is required to have a step of removing the layer by etching.

According to the disclosed technique, it is possible to provide a method for manufacturing a wiring board that enables improvement in connection reliability and yield.

It is a figure which illustrates the wiring board which concerns on 1st Embodiment. It is a figure (the 1) which illustrates the manufacturing process of the wiring board which concerns on 1st Embodiment. It is a figure (the 2) which illustrates the manufacturing process of the wiring board which concerns on 1st Embodiment. It is a figure which illustrates the wiring board which concerns on 2nd Embodiment. It is a figure (the 1) which illustrates the manufacturing process of the wiring board which concerns on 2nd Embodiment. It is a figure (the 2) which illustrates the manufacturing process of the wiring board which concerns on 2nd Embodiment. It is a figure (the 3) which illustrates the manufacturing process of the wiring board which concerns on 2nd Embodiment. It is sectional drawing which shows the modification of the support.

Hereinafter, modes for carrying out the invention will be described with reference to the drawings. In each drawing, the same components may be designated by the same reference numerals, and duplicate description may be omitted.

<First Embodiment>
[Structure of Wiring Board According to First Embodiment]
First, the structure of the wiring board according to the first embodiment will be described. FIG. 1 is a cross-sectional view illustrating the wiring board according to the first embodiment.

With reference to FIG. 1, the wiring board 1 is a coreless wiring board having one layer of wiring layer 10 and one layer of insulating layer 60. The wiring layer 10 has a laminated structure in which the second layer 12 is laminated on the first layer 11.

In the wiring board 1, the wiring layer 10 is embedded in the lower surface side of the insulating layer 60. The lower surface of the wiring layer 10 is exposed from the lower surface of the insulating layer 60, and a part of the upper surface and the side surface of the wiring layer 10 are covered with the insulating layer 60. The upper surface of the wiring layer 10 is selectively exposed in the opening 60x of the insulating layer 60. The lower surface of the wiring layer 10 exposed from the lower surface of the insulating layer 60 has, for example, a circular planar shape and can be used as a pad for connecting to a semiconductor chip. The upper surface of the wiring layer 10 selectively exposed in the opening 60x of the insulating layer 60 has, for example, a circular planar shape and can be used as a pad for connecting to another wiring board or the like.

The wiring layer 10 may have a wiring pattern in which the lower surface is exposed from the lower surface of the insulating layer 60 and the upper surface and the side surfaces are covered with the insulating layer 60.

In the present embodiment, for convenience, in the wiring board 1, the side where the opening 60x of the insulating layer 60 opens is one side or the upper side, and the side where the first layer 11 of the wiring layer 10 is exposed from the insulating layer 60. The lower side or the other side. Further, the surface on the side where the opening 60x of the insulating layer 60 of each portion opens is defined as one surface or the upper surface, and the surface on the side where the first layer 11 is exposed from the insulating layer 60 is defined as the other surface or the lower surface. However, the wiring board 1 can be used upside down, or can be arranged at an arbitrary angle. Further, the plan view means that the object is viewed from the normal direction of one surface of the insulating layer 60, and the planar shape refers to the shape of the object viewed from the normal direction of one surface of the insulating layer 60. It shall point.

The first layer 11 constituting the wiring layer 10 can be formed by using, for example, copper (Cu) or the like. The thickness of the first layer 11 can be, for example, about 0.01 to 1.0 μm. The upper surface of the first layer 11 is a roughened surface. The surface roughness of the upper surface of the first layer 11 can be, for example, about Ra 0.3 to 0.6 μm. The lower surface of the first layer 11 can be flush with, for example, the lower surface of the insulating layer 60. The lower surface of the first layer 11 is not a roughened surface but a flat surface, unlike the upper surface.

The second layer 12 constituting the wiring layer 10 can be formed by using, for example, copper (Cu) or the like. The thickness of the second layer 12 can be, for example, about 30 μm. The upper surface of the second layer 12 is selectively exposed in the opening 60x of the insulating layer 60. The upper surface and the side surface of the second layer 12 are roughened surfaces. The surface roughness of the upper surface and the side surface of the second layer 12 can be, for example, about Ra0.3 to 0.6 μm.

By making the upper surface of the first layer 11 a roughened surface in this way, the adhesion to the lower surface of the second layer 12 can be improved. As a result, it is possible to prevent the first layer 11 and the second layer 12 from peeling off. Further, by making the upper surface and the side surface of the second layer 12 (the upper surface and the side surface of the wiring layer 10) rough surfaces, the adhesion to the insulating layer 60 can be improved. Further, by improving the adhesion with the resist layer 900, which will be described later, highly reliable patterning becomes possible and the wiring can be refined.

The insulating layer 60 is a layer on which the wiring layer 10 is formed, and also functions as a solder resist layer. As the material of the insulating layer 60, for example, a photosensitive epoxy-based insulating resin, an acrylic-based insulating resin, or the like can be used. However, as the material of the insulating layer 60, for example, a non-photosensitive (thermosetting resin) epoxy-based insulating resin or a polyimide-based insulating resin may be used. The thickness of the insulating layer 60 can be, for example, about 10 to 50 μm. The thickness of the insulating layer 60 is the distance from the upper surface of the second layer 12 to the upper surface of the insulating layer 60 (the same applies to other insulating layers). The insulating layer 60 has an opening 60x that opens on the upper surface side, and a part of the upper surface of the second layer 12 of the wiring layer 10 is exposed in the opening 60x.

If necessary, an external connection terminal such as a solder ball may be provided on the upper surface of the second layer 12 exposed in the opening 60x. Further, if necessary, a metal layer may be formed on the lower surface of the first layer 11 and the upper surface of the second layer 12 exposed in the opening 60x. Examples of metal layers include an Au layer, a Ni / Au layer (a metal layer in which a Ni layer and an Au layer are laminated in this order), and a Ni / Pd / Au layer (a Ni layer, a Pd layer, and an Au layer in this order). Laminated metal layers) and the like. Further, instead of forming the metal layer, an antioxidant treatment such as an OSP (Organic Solderability Preservative) treatment may be performed. The surface treatment layer formed by the OSP treatment is an organic film made of an azole compound, an imidazole compound, or the like.

[Manufacturing method of wiring board according to the first embodiment]
Next, a method of manufacturing the wiring board according to the first embodiment will be described. 2 and 3 are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment. In the present embodiment, an example of a process of producing a plurality of wiring boards on the support, removing the supports, and then disassembling them into individual wiring boards is shown. One wiring board is shown on the support. May be used as a step of producing and removing the support.

First, in the step shown in FIG. 2A, a support 100 in which a metal layer 130, a metal layer 120, and a metal layer 110 are sequentially laminated on a support substrate 140 is prepared.

As the support substrate 140, for example, a cured prepreg can be used. The prepreg is, for example, a woven fabric such as glass fiber or aramid fiber or a non-woven fabric (not shown) impregnated with an epoxy-based insulating resin or the like. The thickness of the support substrate 140 can be, for example, about 18 to 100 μm.

The metal layer 130 is, for example, a metal foil (carrier foil) made of copper and having a thickness of about 10 to 50 μm. A metal layer 120 having a thickness of about 1.5 to 5 μm made of nickel or the like is attached to the metal layer 130 in a state where it can be peeled off via a release layer (not shown). A metal layer 110 having a thickness of about 0.01 to 1.0 μm made of copper or the like is laminated on the metal layer 120. The upper surface of the metal layer 110 is a roughened surface, and the surface roughness is larger than that of the lower surface. The roughened surface of the metal layer 110 may be formed by adjusting the composition of the plating solution in the electrolytic plating method, or may be formed by etching. The surface roughness of the upper surface of the metal layer 110 can be, for example, Ra 0.3 to 0.6 μm. The combination of the metal layer 110 and the metal layer 120 is not limited to copper and nickel, and metals that can be selectively etched with each other can be used.

Next, in the step shown in FIG. 2B, a resist layer 900 is formed on the upper surface of the metal layer 110 of the support 100. Specifically, for example, a dry film resist made of a photosensitive resin is laminated as a resist layer 900 on the upper surface of the metal layer 110. Since the upper surface of the metal layer 110 is a roughened surface, the adhesion to the resist layer 900 can be improved.

Next, in the step shown in FIG. 2C, the resist layer 900 made of a dry film resist or the like is patterned by exposure and development, and the upper surface (roughened surface) of the metal layer 110 is selected for the portion forming the wiring layer 10. An opening 900x that is specifically exposed is formed.

Next, in the step shown in FIG. 2D, the upper surface (roughened surface) of the metal layer 110 exposed in the opening 900x of the resist layer 900 is subjected to an electrolytic plating method using the metal layer 110 as the plating feeding layer. The second layer 12 is selectively formed. The lower surface of the second layer 12 is in contact with the upper surface of the metal layer 110, and the upper surface is exposed in the opening 900x. By forming a metal layer soluble in the same etching solution as the metal layer 110 as the second layer 12, the surfaces of the second layer 12 and the metal layer 110 are simultaneously roughened in the step shown in FIG. 3 (b). be able to. The second layer 12 and the metal layer 110 can be, for example, a copper layer.

Next, in the step shown in FIG. 3A, the resist layer 900 shown in FIG. 2D is peeled off. The resist layer 900 can be peeled off using, for example, a stripping solution containing sodium hydroxide or the like.

Next, in the step shown in FIG. 3B, the second layer 12 is roughened with an etching solution, and at the same time, the metal layer 110 not coated on the second layer 12 is dissolved and removed. As a result, the remaining portion of the metal layer 110 becomes the first layer 11, and the wiring layer 10 in which the second layer 12 is laminated on the first layer 11 is formed. For example, when the first layer 11 and the second layer 12 are copper layers, for example, an etching solution such as a hydrogen peroxide / sulfuric acid aqueous solution, a sodium persulfate aqueous solution, or an ammonium persulfate aqueous solution can be used. At this time, when the metal layer 120 is made of nickel, the metal layer 120 becomes an etching stop layer, so that the metal layer 130 is not etched.

At the same time that the metal layer 110 not covered by the second layer 12 is removed by etching, the upper surface and the side surface of the second layer 12 are roughened (that is, the upper surface and the side surface of the wiring layer 10 are roughened). The surface roughness of the upper surface and the side surface of the wiring layer 10 is preferably about Ra 0.3 to 0.6 μm, and the etching amount in this case is about 0.3 to 1.5 μm.

That is, in the step shown in FIG. 2A, the metal layer 110 is formed to have a thickness (for example, about 0.01 to 1.0 μm) that can be removed with an etching amount of 0.35 to 1.5 μm. As a result, in the step shown in FIG. 3B, the upper surface and the side surface of the wiring layer 10 are etched aiming at Ra 0.3 to 0.6 μm, and at the same time, the metal layer 110 not covered by the second layer 12 is formed. Can be removed.

Next, in the step shown in FIG. 3C, an insulating layer 60 covering the wiring layer 10 is formed on the upper surface of the metal layer 120. The insulating layer 60 can be formed by, for example, applying a liquid or paste-like insulating resin so as to cover the wiring layer 10 by a screen printing method, a roll coating method, a spin coating method, or the like. Alternatively, a film-shaped insulating resin may be laminated so as to cover the wiring layer 10. As the insulating resin, for example, a photosensitive or non-photosensitive epoxy-based insulating resin, an acrylic-based insulating resin, a polyimide-based insulating resin, or the like can be used.

Then, by exposing and developing the coated or laminated insulating resin, an opening 60x that selectively exposes the upper surface of the wiring layer 10 is formed in the insulating layer 60 (photolithography method). When a non-photosensitive epoxy-based insulating resin, a polyimide-based insulating resin, or the like is used as the material of the insulating layer 60, the opening 60x may be formed by a laser processing method, a blast treatment, or the like. When the opening 60x is formed by a laser processing method, it is preferable to perform a desmear treatment to remove the resin residue of the insulating layer 60 adhering to the upper surface of the wiring layer 10 exposed in the opening 60x.

Next, in the step shown in FIG. 3D, a part of the support 100 is removed from the structure shown in FIG. 3C. Specifically, a mechanical force is applied to the support 100 to peel off the interface between the metal layer 120 and the metal layer 130. As described above, since the metal layer 120 is attached to the metal layer 130 in a state where it can be peeled off via a peeling layer (not shown), the interface between the metal layer 120 and the metal layer 130 can be easily formed. Can be peeled off. As a result, only the metal layer 120 remains on the insulating layer 60 side, and other members (metal layer 130 and the support substrate 140) constituting the support 100 are removed.

Next, in the step shown in FIG. 3 (e), the metal layer 120 (see FIG. 3 (d)) is removed. When the metal layer 120 is made of nickel (Ni) and the first layer 11 of the wiring layer 10 is made of copper, an etching solution that removes nickel (Ni) without removing copper is selected. For example, an etching solution such as a hydrogen peroxide / nitric acid aqueous solution can be used. As a result, only the metal layer 120 can be etched without etching the first layer 11 of the wiring layer 10. As a result, the lower surface of the first layer 11 of the wiring layer 10 is exposed on the lower surface of the insulating layer 60. The lower surface of the first layer 11 of the wiring layer 10 can be flush with, for example, the lower surface of the insulating layer 60.

If the residue of the metal layer 110 is present in a region other than the exposed lower surface of the first layer 11 on the lower surface of the insulating layer 60, it can be removed by etching. At this time, since the amount of the residue is very small, there is almost no possibility that the lower surface of the first layer 11 is dented by etching. Of course, in the step of FIG. 3B, the metal layer 110 not coated on the second layer 12 may be completely removed.

If necessary, the lower surface of the first layer 11 of the wiring layer 10 exposed on the lower surface of the insulating layer 60 and the upper surface of the second layer 12 of the wiring layer 10 exposed in the opening 60x may be subjected to, for example, electroless plating. A metal layer may be formed. Examples of the metal layer are as described above. Further, the lower surface of the first layer 11 of the wiring layer 10 exposed on the lower surface of the insulating layer 60 and the upper surface of the second layer 12 of the wiring layer 10 exposed in the opening 60x are subjected to antioxidant treatment such as OSP treatment. You may.

After the step shown in FIG. 3 (e), a plurality of wiring boards 1 (see FIG. 1) are completed by cutting the structure shown in FIG. 3 (e) at the cutting position C with a slicer or the like and separating the structures into individual pieces. do. If necessary, an external connection terminal such as a solder ball may be provided on the upper surface of the second layer 12 of the wiring layer 10 exposed in the opening 60x.

As described above, according to the method for manufacturing the wiring board according to the first embodiment, the metal layer 120 and the metal layer 110 that can be selectively etched with respect to the metal layer 120 are sequentially laminated on the support substrate 140. A support 100 is used in which the upper surface of the metal layer 110 is a roughened surface. Then, the second layer 12 is selectively formed on the roughened surface of the metal layer 110, the second layer 12 is roughened with an etching solution, and at the same time, the metal layer 110 not covered with the second layer 12 is dissolved and removed. Then, the wiring layer 10 in which the second layer 12 is laminated on the first layer 11 is formed.

This eliminates the need for the step of etching the metal layer 110 after removing the support substrate 140 and the metal layers 120 and 130 as in the conventional method, so that the lower surface of the wiring layer 10 is recessed from the lower surface of the insulating layer 60. There is no. Therefore, when the wiring layer 10 and the semiconductor chip or the like are connected by solder, there is no problem that the solder does not easily enter the dent, so that the connection reliability between the wiring board 1 and the semiconductor chip or the like can be improved.

Further, in the conventional method, it is necessary to increase the original thickness of the wiring layer in consideration of the decrease in the thickness of the wiring layer due to the lower surface of the wiring layer being recessed from the lower surface of the insulating layer. In this case, since the thickness of the resist layer used when selectively forming the wiring layer becomes thick, it becomes difficult to increase the density (fine pattern) of the wiring layer. According to the method for manufacturing a wiring board according to the first embodiment, the thickness of the resist layer can be reduced as compared with the conventional method, so that the density of the wiring layer can be increased (fine patterning).

Further, according to the method for manufacturing a wiring board according to the first embodiment, the metal layer 110 is formed on the metal layer 120 to be the etching stop layer, and separate materials are used for the metal layer 120 and the metal layer 110. You can choose. Therefore, even when nickel is selected as the material of the metal layer 120 to be the etching stop layer, the surface of nickel is covered with the metal layer 110, so that the formation of a passivation film due to the oxidation of the surface is suppressed. .. Further, by selecting copper or the like, which is difficult to form a passivation film, as the material of the metal layer 110, it is possible to avoid deterioration of the adhesion between the metal layer 110 and the second layer 12 due to the passivation film. As a result, the interface between the metal layer 110 and the second layer 12 does not peel off, and the yield of the wiring board 1 can be improved.

Further, in the method for manufacturing a wiring board according to the first embodiment, it is preferable to form a metal layer soluble in the same etching solution as the metal layer 110 as the second layer 12. Thereby, the metal layer 110 not coated on the second layer 12 can be removed, and at the same time, the side surface of the metal layer 110 coated on the second layer 12 and the upper surface and the side surface of the second layer 12 can be roughened. .. That is, since the unnecessary metal layer 110 can be removed and the roughening for improving the adhesion to the insulating layer 60 can be performed at the same time, the manufacturing process of the wiring board 1 can be simplified and the cost can be reduced. Become.

<Second Embodiment>
In the second embodiment, an example of a wiring board having a three-layer structure is shown. In the second embodiment, the description of the same components as those in the above-described embodiment may be omitted.

[Structure of Wiring Board According to Second Embodiment]
First, the structure of the wiring board according to the second embodiment will be described. FIG. 4 is a cross-sectional view illustrating the wiring board according to the second embodiment. With reference to FIG. 4, in the wiring board 2 according to the second embodiment, the wiring board 1 (the point where the insulating layer 20, the wiring layer 30, the insulating layer 40, the wiring layer 50, and the insulating layer 70 are added is the wiring board 1 ( See FIG. 1).

The insulating layer 20 is formed so as to cover the upper surface and the side surface of the wiring layer 10. As the material of the insulating layer 20, for example, a non-photosensitive (thermosetting resin) epoxy-based insulating resin, a polyimide-based insulating resin, or the like can be used. However, as the material of the insulating layer 60, for example, a photosensitive epoxy-based insulating resin, an acrylic-based insulating resin, or the like may be used. The insulating layer 20 may contain a filler such as _{silica (SiO 2).} The thickness of the insulating layer 20 can be, for example, about 10 to 50 μm. The insulating layer 20 has a via hole 20x that opens on the upper surface side, and a part of the upper surface of the second layer 12 of the wiring layer 10 is exposed in the via hole 20x.

The wiring layer 30 is formed on the insulating layer 20. The wiring layer 30 includes a via wiring filled in a via hole 20x that penetrates the insulating layer 20 and exposes the upper surface of the wiring layer 10, and a wiring pattern formed on the upper surface of the insulating layer 20. The via hole 20x is an inverted cone-shaped recess in which the diameter of the opening opened on the insulating layer 40 side is larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 10. The wiring layer 30 is electrically connected to the wiring layer 10 exposed at the bottom of the via hole 20x.

The wiring layer 30 includes a first layer 31, a second layer 32, and a third layer 33. The first layer 31 is formed around the via hole 20x on the upper surface of the insulating layer 20. The second layer 32 is formed on the first layer 31, extends from the first layer 31, is formed along the inner wall of the via hole 20x, and further covers the upper surface of the wiring layer 10 exposed in the via hole 20x. ing. The third layer 33 is formed on the second layer 32, and fills the inside of the via hole 20x in which the second layer 32 is formed on the inner wall.

As the material of the first layer 31, the second layer 32, and the third layer 33, for example, copper or the like can be used. The thickness of the first layer 31 can be, for example, about 0.5 to 5 μm. The thickness of the second layer 32 can be, for example, about 0.3 to 1.5 μm. The thickness of the third layer 33 can be, for example, about 4 to 30 μm.

The side surface of the first layer 31 is a roughened surface. The side surface of the second layer 32 is a roughened surface. Further, the upper surface and the side surface of the third layer 33 are roughened surfaces. That is, the upper surface and the side surface of the wiring layer 30 are roughened surfaces. The surface roughness of the side surface of the first layer 31, the side surface of the second layer 32, and the upper surface and the side surface of the third layer 33 can be, for example, about Ra0.3 to 0.6 μm.

The insulating layer 40 is formed so as to cover the upper surface and the side surface of the wiring layer 30. The material and thickness of the insulating layer 40 can be, for example, the same as that of the insulating layer 20. The insulating layer 40 has a via hole 40x that opens on the upper surface side, and a part of the upper surface of the third layer 33 of the wiring layer 30 is exposed in the via hole 40x.

The wiring layer 50 is formed on the insulating layer 40. The wiring layer 50 includes via wiring filled in a via hole 40x that penetrates the insulating layer 40 and exposes the upper surface of the wiring layer 30, and a wiring pattern formed on the upper surface of the insulating layer 40. The via hole 40x is an inverted cone-shaped recess in which the diameter of the opening opened on the insulating layer 60 side is larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 30. The wiring layer 50 is electrically connected to the wiring layer 30 exposed at the bottom of the via hole 40x.

The wiring layer 50 includes a first layer 51, a second layer 52, and a third layer 53. The structures and materials of the first layer 51, the second layer 52, and the third layer 53 of the wiring layer 50 shall be the same as those of the first layer 31, the second layer 32, and the third layer 33 of the wiring layer 30. Can be done.

The side surface of the first layer 51 is a roughened surface. The side surface of the second layer 52 is a roughened surface. Further, the upper surface and the side surface of the third layer 53 are roughened surfaces. That is, the upper surface and the side surface of the wiring layer 50 are roughened surfaces. The surface roughness of the side surface of the first layer 51, the side surface of the second layer 52, and the upper surface and the side surface of the third layer 53 can be, for example, about Ra0.3 to 0.6 μm.

The insulating layer 60 is formed so as to cover the upper surface and the side surface of the wiring layer 50. A part of the upper surface of the third layer 53 of the wiring layer 50 is exposed in the opening 60x of the insulating layer 60. The upper surface of the wiring layer 50 that is selectively exposed in the opening 60x of the insulating layer 60 has, for example, a circular planar shape and can be used as a pad for connecting to another wiring board or the like.

The insulating layer 70 is formed so as to cover the wiring layer 10 on the lower surface of the insulating layer 20, and functions as a solder resist layer. The insulating layer 70 has an opening 70x, and the opening 70x selectively exposes the wiring layer 10. The lower surface of the wiring layer 10 exposed in the opening 70x has, for example, a circular planar shape and can be used as a pad for connecting to a semiconductor chip. The material and thickness of the insulating layer 70 can be, for example, the same as that of the insulating layer 60.

[Manufacturing method of wiring board according to the second embodiment]
Next, a method of manufacturing the wiring board according to the second embodiment will be described. 5 to 7 are diagrams illustrating a manufacturing process of a wiring board according to a second embodiment. In the present embodiment, an example of a process of producing a plurality of wiring boards on the support, removing the supports, and then disassembling them into individual wiring boards is shown. One wiring board is shown on the support. May be used as a step of producing and removing the support.

First, the steps shown in FIGS. 2 (a) to 3 (b) of the first embodiment are executed. Then, in the step shown in FIG. 5A, a metal foil 310 such as a copper foil is laminated on the insulating layer 20. Specifically, for example, a prepreg with a metal foil having a metal foil 310 adhered to one surface of the prepreg is prepared. Then, the prepreg with metal foil is laminated on the upper surface of the metal layer 120 so that the prepreg covers the wiring layer 10, and press-molded with a mold while being heat-treated. As a result, the prepreg is cured, and the insulating layer 20 in which the metal foil 310 is laminated on the upper surface is formed. Not limited to the prepreg, a photosensitive / non-photosensitive resin containing no glass cloth may be used.

Next, in the step shown in FIG. 5B, a via hole 20x is formed which penetrates the metal foil 310 and the insulating layer 20 and exposes the upper surface of the wiring layer 10. The via hole 20x can be formed, for example, by a laser processing method in which the metal foil 310 and the insulating layer 20 are irradiated with laser light. When the via hole 20x is formed by a laser processing method, it is preferable to perform a desmear treatment to remove the resin residue of the insulating layer 20 adhering to the upper surface of the wiring layer 10 exposed in the via hole 20x.

Next, in the steps shown in FIGS. 5 (c) to 6 (b), the wiring layer 30 is formed. The wiring layer 30 can be formed by, for example, a semi-additive method. In order to form the wiring layer 30 by using the semi-additive method, first, as shown in FIG. 5C, a metal layer 320 made of copper or the like is formed as a seed layer by an electroless plating method or a sputtering method. .. The metal layer 320 is formed so as to continuously cover the entire upper surface of the metal foil 310, the inner wall surface of the via hole 20x, and the upper surface of the wiring layer 10 exposed in the via hole 20x. The thickness of the metal layer 320 can be, for example, about 0.3 to 1.5 μm.

In the process shown in FIG. 5 (a), only the prepreg to be the insulating layer 20 is laminated without laminating the metal foil 310, and the metal layer 320 is directly formed on the insulating layer 20 in the process shown in FIG. 5 (c). You may. However, when the prepreg with the metal foil is used, the adhesion between the insulating layer 20 and the metal foil 310 can be improved. Therefore, when the metal layer 320 is formed on the metal foil 310, the metal layer 320 and the insulating layer 20 are brought into close contact with each other as a result. It is preferable in that the property can be improved.

Next, as shown in FIG. 5D, a resist layer 910 (dry film resist or the like) having an opening 910x corresponding to the wiring layer 30 is formed on the metal layer 320. Then, as shown in FIG. 6A, copper or the like is deposited in the opening 910x of the resist layer 910 by the electrolytic plating method using the metal layer 320 as the feeding layer, and the third layer 33 which is the electrolytic plating layer is formed. Is selectively formed.

Next, as shown in FIG. 6B, after removing the resist layer 910, the metal foil 310 and the metal layer 320 not covered by the third layer 33 are removed by etching using the third layer 33 as a mask. do. As a result, the first layer 31 is formed from the metal foil 310, the second layer 32 is formed from the metal layer 320, and the wiring layer 30 including the first layer 31, the second layer 32, and the third layer 33 is provided. Is formed. For example, when the first layer 31 and the second layer 32 are made of copper, for example, an etching solution such as a hydrogen peroxide / sulfuric acid aqueous solution, a sodium persulfate aqueous solution, or an ammonium persulfate aqueous solution can be used.

The metal foil 310 and the metal layer 320 that are not covered by the third layer 33 are removed by etching, and at the same time, the side surfaces of the first layer 31 and the second layer 32, and the upper surface and the side surface of the third layer 33 are roughened ( That is, the upper surface and the side surface of the wiring layer 30 are roughened). By roughening the upper surface and the side surface of the wiring layer 30, the adhesion between the wiring layer 30 and the insulating layer 40 formed in the subsequent process can be improved. The surface roughness of the upper surface and the side surface of the wiring layer 30 is preferably about Ra 0.3 to 0.6 μm, and the etching amount in this case is about 0.3 to 1.5 μm.

That is, in the steps shown in FIGS. 5A and 5C, the total thickness of the metal foil 310 and the metal layer 320 can be removed with an etching amount of 0.35 to 1.5 μm (for example, thickness 0). The metal foil 310 and the metal layer 320 are formed so as to be 0.8 μm). As a result, in the step shown in FIG. 6B, the upper surface and the side surface of the wiring layer 30 are etched aiming at Ra 0.3 to 0.6 μm, and at the same time, the metal foil 310 not covered by the third layer 33. And the metal layer 320 can be removed. Further, the removal of the seed layer and the roughening may be performed in separate steps.

Next, in the step shown in FIG. 6 (c), the same steps as in FIGS. 5 (a) to 6 (b) are executed to form the insulating layer 40 and the wiring layer 50. Specifically, an insulating layer 40 that covers the wiring layer 30 is formed on the insulating layer 20, a via hole 40x that exposes the upper surface of the wiring layer 30 is formed on the insulating layer 40, and then a via hole 40x is formed on the insulating layer 40. A wiring layer 50 that is electrically connected to the wiring layer 30 is formed. The upper surface and the side surface of the wiring layer 50 are roughened in the same manner as the upper surface and the side surface of the wiring layer 30. By roughening the upper surface and the side surface of the wiring layer 50, the adhesion between the wiring layer 50 and the insulating layer 60 formed in the subsequent process can be improved.

Next, in the step shown in FIG. 7A, a part of the support 100 is removed from the structure shown in FIG. 6C in the same manner as in the step shown in FIG. 3D. Specifically, a mechanical force is applied to the support 100 to peel off the interface between the metal layer 120 and the metal layer 130. As a result, only the metal layer 120 remains on the insulating layer 20 side, and other members (metal layer 130 and support substrate 140) constituting the support 100 are removed.

Next, in the step shown in FIG. 7 (b), the metal layer 120 (see FIG. 7 (a)) is removed in the same manner as in the step shown in FIG. 3 (e). As a result, the lower surface of the first layer 11 of the wiring layer 10 is exposed on the lower surface of the insulating layer 20. The lower surface of the first layer 11 of the wiring layer 10 can be flush with, for example, the lower surface of the insulating layer 20.

If the residue of the metal layer 110 is present in a region other than the exposed lower surface of the first layer 11 on the lower surface of the insulating layer 20, it can be removed by etching. At this time, since the amount of the residue is very small, there is almost no possibility that the lower surface of the first layer 11 is dented by etching.

Next, in the step shown in FIG. 7C, an insulating layer 60 covering the wiring layer 50 is formed on the upper surface of the insulating layer 40. Further, an insulating layer 70 that covers the wiring layer 10 is formed on the lower surface of the insulating layer 20. The insulating layers 60 and 70 are layers that function as solder resist layers. Then, an opening 60x that selectively exposes the upper surface of the wiring layer 50 is formed in the insulating layer 60. Further, the insulating layer 70 is formed with an opening 70x that selectively exposes the lower surface of the wiring layer 10. The insulating layers 60 and 70 and the openings 60x and 70x can be formed, for example, by the same method as the insulating layers 60 and the openings 60x in the step shown in FIG. 3C.

If necessary, the lower surface of the first layer 11 of the wiring layer 10 exposed on the lower surface of the insulating layer 20 and the upper surface of the third layer 53 of the wiring layer 50 exposed in the opening 60x may be subjected to, for example, electroless plating. A metal layer may be formed. Examples of the metal layer are as described above. Further, the lower surface of the first layer 11 of the wiring layer 10 exposed on the lower surface of the insulating layer 20 and the upper surface of the third layer 53 of the wiring layer 50 exposed in the opening 60x are subjected to antioxidant treatment such as OSP treatment. You may.

The insulating layer 60 may be formed after the wiring layer 50 is formed in the step shown in FIG. 6C. Further, the insulating layer 70 may be formed as needed.

After the step shown in FIG. 7 (c), a plurality of wiring boards 2 (see FIG. 4) are completed by cutting the structure shown in FIG. 7 (c) at the cutting position C with a slicer or the like and separating the structures into individual pieces. do. If necessary, an external connection terminal such as a solder ball may be provided on the upper surface of the third layer 53 of the wiring layer 50 exposed in the opening 60x.

In this way, the wiring board 2 having a three-layer structure can be realized. It is also possible to alternately stack a required number of insulating layers and wiring layers on the wiring layer 50 to form a wiring board having a four-layer structure or more. The wiring board 2 has the same effect as that of the first embodiment. Further, for the second and subsequent wiring layers, unnecessary metal layers can be removed and the wiring layer can be roughened to improve the adhesion to the insulating layer at the same time. Therefore, the wiring board 2 is manufactured. The process can be simplified and the cost can be reduced.

<Modification example of support>
Here, a modified example of the support is shown. In the modified example of the support, the description of the same component as that of the embodiment already described may be omitted.

FIG. 8 is a cross-sectional view showing a modified example of the support. As shown in FIG. 8A, in the support 100A, the metal layer 150 formed by the sputtering method is laminated between the metal layer 120 and the metal layer 110. As the material of the metal layer 150, for example, copper, nickel, or the like can be used. The thickness of the metal layer 150 can be, for example, about 0.1 μm or less.

For example, when the metal layer 120 is made of nickel foil and the metal layer 110 is made of electrolytic copper plating layer, the adhesion between the two may not be ensured. In this case, by arranging the metal layer 150 formed by the sputtering method between the two, the adhesion between the two can be improved.

As shown in FIG. 8B, in the support 100B, the metal layer 130A is laminated between the support substrate 140 and the metal layer 120, and the lower surface of the metal layer 130A in contact with the support substrate 140 is a roughened surface. There is. The surface roughness of the lower surface of the metal layer 130A can be, for example, Ra 0.3 to 1.0 μm. By making the surface of the metal layer 130A in contact with the support substrate 140 a roughened surface in this way, the adhesion between the metal layer 130A and the support substrate 140 can be improved. In the support 100B, similarly to the support 100A, the metal layer 150 formed by the sputtering method may be laminated between the metal layer 120 and the metal layer 110.

As shown in FIG. 8C, in the support 100C, a metal layer 110A made of particles is provided on the metal layer 120. The metal layer 110A is composed of primary particles 111 and secondary particles 112 formed from primary particles 111.

The diameter of the primary particles 111 can be, for example, 10 to 200 nm. More preferably, it can be about 10 to 40 nm. Further, the diameter phi ₁ of the secondary particles 112, for example, may be of the order 1μm or less. More preferably, it can be about 400 nm or less. However, the cross-sectional shapes of the primary particles 111 and the secondary particles 112 are not limited to a circle, and may be various shapes such as an ellipse and a polygon.

The surface roughness of the upper surface of the metal layer 110A can be Rz ≦ 2.0 μm (10-point average roughness). It should be noted that this Rz also includes irregularities generated following the surface roughness of the underlying metal layer 120.

The metal layer 110A can be formed by, for example, performing cathode electrolysis in the vicinity of the limit current density in a copper sulfate solution to precipitate dendrite-like or fine-grained copper precipitates on the surface of the metal layer 120. The upper surface of the metal layer 110A may be coated with copper plating or the like in order to prevent the copper precipitates from falling off. The surface roughness at that time may follow the surface roughness of the upper surface of the metal layer 110A before being coated by copper plating or the like, or the surface of the copper plating or the like covering the upper surface of the metal layer 110A is newly formed. It may be roughened.

Although the preferred embodiments and the like have been described in detail above, the embodiments are not limited to the above-described embodiments and the like, and various embodiments and the like described above are used without departing from the scope of the claims. Modifications and substitutions can be added.

For example, in the method for manufacturing the wiring board 1 and the wiring board 2, a support in which the metal layer 130, the metal layer 120, and the metal layer 110 are sequentially laminated on both surfaces of the support substrate 140 may be used. In this case, it is possible to form each component portion to be a wiring board on both side surfaces of the support, and then separate or remove unnecessary portions of the support.

Further, the release layer does not necessarily have to be provided in the support. For example, the support may have a structure in which the metal layer 120 and the metal layer 130 are bonded only at the outer edge portion without providing the release layer. In this structure, the metal layer 120 and the metal layer 130 are only in contact with each other except for the outer edge portion. In this case, in the step shown in FIG. 3D, the metal layer is removed by cutting and removing the outer edge portion to which the metal layer 120 and the metal layer 130 of the structure shown in FIG. 3C are adhered. The 130 and the support substrate 140 can be easily separated from the metal layer 120.

Further, the first layer 11 may be removed by etching in the step of roughening the surface of the wiring layer 10 when forming the insulating layer 70, but even in that case, the amount of dents is very small and electronic components are mounted. There is almost no effect on sex.

1, 2 Wiring board 10 Wiring layer 11, 31, 51 First layer 12, 32, 52 Second layer 20, 40, 60, 70 Insulation layer 20x, 40x Via hole 33, 53 Third layer 60x, 70x Opening 100, 100A, 100B Support 110, 110A, 120, 130, 130A, 150, 320 Metal layer 111 Primary particle 112 Secondary particle 140 Support substrate 310 Metal leaf

Claims (9)

A first metal layer and a second metal layer whose upper surface is a roughened surface or is made of particles are sequentially laminated on the support substrate, and the second metal layer is relative to the first metal layer. And the process of preparing a support that can be selectively etched
A step of selectively forming a third metal layer on the upper surface of the second metal layer, and
At the same time as roughening the third metal layer with the etching solution, the second metal layer not covered with the third metal layer is dissolved, and the third metal layer is formed on the second metal layer. The process of forming the first laminated wiring layer and
A step of forming an insulating layer covering the first wiring layer on the first metal layer, and
A method for manufacturing a wiring board, comprising a step of removing the support substrate and further removing the first metal layer by etching. The method for manufacturing a wiring board according to claim 1, further comprising a step of forming a second wiring layer on the insulating layer. A claim for completely removing the second metal layer in the step of roughening the third metal layer with the etching solution and at the same time melting the second metal layer not covered with the third metal layer. Item 2. The method for manufacturing a wiring board according to Item 1. The step according to any one of claims 1 to 3, wherein in the step of selectively forming the third metal layer, a third metal layer that is soluble in the same etching solution as the second metal layer is formed. How to manufacture a wiring board. In the step of forming the second wiring layer, a step of forming a seed layer on the insulating layer and a step of forming the seed layer
A step of selectively forming an electrolytic plating layer on the seed layer and
The method for manufacturing a wiring board according to claim 2, wherein the seed layer that is not coated on the electrolytic plating layer is removed by etching to form a second wiring layer in which the electrolytic plating layer is laminated on the seed layer. .. The method for manufacturing a wiring board according to any one of claims 1 to 5, wherein the first metal layer is nickel, and the second metal layer and the third metal layer are copper. The invention according to any one of claims 1 to 6, wherein a fourth metal layer formed by a sputtering method is laminated between the first metal layer and the second metal layer of the support. How to manufacture a wiring board. The method for manufacturing a wiring board according to any one of claims 1 to 7, wherein a fifth metal layer is laminated between the support substrate of the support and the first metal layer. The method for manufacturing a wiring board according to claim 8, wherein the surface of the fifth metal layer in contact with the support substrate is a roughened surface.

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