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JP6936310B2 - Semiconductor devices and methods for manufacturing semiconductor devices - Google Patents
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JP6936310B2 - Semiconductor devices and methods for manufacturing semiconductor devices - Google Patents

Semiconductor devices and methods for manufacturing semiconductor devices Download PDF

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JP6936310B2
JP6936310B2 JP2019506746A JP2019506746A JP6936310B2 JP 6936310 B2 JP6936310 B2 JP 6936310B2 JP 2019506746 A JP2019506746 A JP 2019506746A JP 2019506746 A JP2019506746 A JP 2019506746A JP 6936310 B2 JP6936310 B2 JP 6936310B2
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semiconductor chip
solder material
electrode
semiconductor device
solder
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JPWO2019167102A1 (en
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政雄 中川
政雄 中川
桑野 亮司
亮司 桑野
洋平 篠竹
洋平 篠竹
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Shindengen Electric Manufacturing Co Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • H10W72/07351Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07354Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in dispositions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • H10W72/341Dispositions of die-attach connectors, e.g. layouts
    • H10W72/347Dispositions of multiple die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/853On the same surface
    • H10W72/871Bond wires and strap connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/921Structures or relative sizes of bond pads
    • H10W72/926Multiple bond pads having different sizes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/941Dispositions of bond pads
    • H10W72/944Dispositions of multiple bond pads
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/761Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors
    • H10W90/766Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

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  • Die Bonding (AREA)

Description

本発明は、半導体装置及び半導体装置の製造方法に関する。 The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

従来、半導体チップとリードとがはんだを介して接合された半導体装置を製造する半導体装置の製造方法が知られている(例えば、特許文献1参照。)。 Conventionally, a method for manufacturing a semiconductor device for manufacturing a semiconductor device in which a semiconductor chip and a lead are joined via solder is known (see, for example, Patent Document 1).

特許文献1に記載の従来の半導体装置900は、図12に示すように、半導体チップ配置面912を有する基板910と、半導体チップ配置面912上に配置され、基板910側の面(半導体チップ配置面12と対向する面)に形成されたコレクタ電極922、並びに、基板910側の面とは反対側の面(半導体チップ配置面12と対向する面とは反対側の面)に形成されたエミッタ電極924(電極)及びエミッタ電極924とは離間した位置に形成されたゲート電極926を有する半導体チップ920と、電極接続片932を有し、電極接続片932がエミッタ電極924とはんだ940を介して接合されたリード930とを備える As shown in FIG. 12, the conventional semiconductor device 900 described in Patent Document 1 is arranged on a substrate 910 having a semiconductor chip arrangement surface 912 and a semiconductor chip arrangement surface 912, and is arranged on a surface on the substrate 910 side (semiconductor chip arrangement). The collector electrode 922 formed on the surface facing the surface 12) and the emitter formed on the surface opposite to the surface on the substrate 910 side (the surface opposite to the surface facing the semiconductor chip arrangement surface 12). It has a semiconductor chip 920 having a gate electrode 926 formed at a position separated from the electrode 924 (electrode) and the emitter electrode 924, and an electrode connecting piece 923, and the electrode connecting piece 923 is interposed via the emitter electrode 924 and the solder 940. With a joined lead 930

従来の半導体装置900によれば、電極接続片932がエミッタ電極924とはんだ940を介して接合されている、すなわち、半導体チップ920とリード930とがはんだ940のみを介して(ワイヤ等の介在部材を介さずに)直接接続されているため、半導体装置900は、電流容量が大きく、大電流を使用する電子機器(例えば、電源)に適した半導体装置となる。 According to the conventional semiconductor device 900, the electrode connection piece 923 is joined to the emitter electrode 924 via the solder 940, that is, the semiconductor chip 920 and the lead 930 are joined only through the solder 940 (intervening member such as a wire). Since it is directly connected (without using), the semiconductor device 900 has a large current capacity and is suitable for an electronic device (for example, a power source) that uses a large current.

特開2010−123686号公報JP-A-2010-123686 特開2017−199809号公報Japanese Unexamined Patent Publication No. 2017-199809

ところで、一般に、半導体チップとリードとの間のはんだに作用する応力(例えば熱応力)を緩和するためには、はんだの厚みをある一定以上の厚さに保つことが有効であることが知られている(例えば、特許文献2参照。)。 By the way, it is generally known that it is effective to keep the thickness of the solder at a certain level or higher in order to alleviate the stress (for example, thermal stress) acting on the solder between the semiconductor chip and the lead. (See, for example, Patent Document 2).

しかしながら、従来の半導体装置の製造過程において、ペースト状のはんだ材941をある一定以上の厚さとすると、はんだ材941の上にリード930を配置したときにはんだ材941が潰れて余剰なはんだ材が所望しない場所にはみ出してしまうおそれがあり、半導体装置の信頼性が低下するおそれがある、という問題がある(図13参照。)。 However, in the conventional manufacturing process of a semiconductor device, if the paste-like solder material 941 has a certain thickness or more, the solder material 941 is crushed when the leads 930 are arranged on the solder material 941, and excess solder material is generated. There is a problem that the semiconductor device may protrude to an undesired place and the reliability of the semiconductor device may be lowered (see FIG. 13).

そこで、本発明は、上記した問題を解決するためになされたものであり、信頼性が低下し難い半導体装置を提供することを目的とする。また、そのような半導体装置を製造するための半導体装置の製造方法を提供することを目的とする。 Therefore, the present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device whose reliability is unlikely to decrease. Another object of the present invention is to provide a method for manufacturing a semiconductor device for manufacturing such a semiconductor device.

[1]本発明の半導体装置は、半導体チップ配置面を有する基板と、前記半導体チップ配置面上に配置され、前記半導体チップ配置面と対向する面とは反対側の面に形成された電極を有する半導体チップと、前記電極とはんだを介して接合された電極接続片を有するリードとを備え、前記電極接続片は、前記はんだと接合する領域において、前記半導体チップ側に突出した凸部と、前記凸部の頂上部に形成され、前記半導体チップ側の面から前記半導体チップ側とは反対側の面まで貫通された貫通孔とを有することを特徴とする。 [1] In the semiconductor device of the present invention, a substrate having a semiconductor chip arranging surface and electrodes arranged on the semiconductor chip arranging surface and formed on a surface opposite to the surface facing the semiconductor chip arranging surface are formed. The semiconductor chip includes a lead having an electrode connecting piece joined to the electrode via solder, and the electrode connecting piece has a convex portion protruding toward the semiconductor chip side in a region to be joined to the solder. It is characterized by having a through hole formed on the top of the convex portion and penetrating from a surface on the semiconductor chip side to a surface on the side opposite to the semiconductor chip side.

[2]本発明の半導体装置において、前記リードは、断面で見たときに、前記凸部の部分で半導体チップ側に折り曲げられた形状を有することが好ましい。 [2] In the semiconductor device of the present invention, it is preferable that the lead has a shape bent toward the semiconductor chip at the convex portion when viewed in cross section.

[3]本発明の半導体装置においては、前記凸部の側面形状は、前記半導体チップ側が狭いテーパ形状であることが好ましい。 [3] In the semiconductor device of the present invention, the side surface shape of the convex portion is preferably a tapered shape in which the semiconductor chip side is narrow.

[4]本発明の半導体装置においては、前記凸部の側面形状は、丸みを帯びた形状になっていることが好ましい。 [4] In the semiconductor device of the present invention, the side surface shape of the convex portion is preferably a rounded shape.

[5]本発明の半導体装置においては、前記はんだの厚さは、300μm以上であることが好ましい。 [5] In the semiconductor device of the present invention, the thickness of the solder is preferably 300 μm or more.

[6]本発明の第1の半導体装置の製造方法は、上記[1]〜[5]のいずれかに記載の半導体装置を製造するための半導体装置の製造方法であって、基板上に半導体チップを配置する半導体チップ配置工程と、一方の面側に突出した凸部と、前記凸部の頂上部に形成され、前記一方の面から前記一方の面とは反対側の他方の面まで貫通された貫通孔とを有する電極接続片を有するリードを、前記半導体チップの電極と前記電極接続片とがはんだ材を挟んで対向した状態、かつ、前記凸部が前記電極側に向かって突出した状態となるように配置して組立体を形成する組立体形成工程と、前記はんだ材を溶融した後で固化することにより、前記電極と前記電極接続片とをはんだを介して接合する接合工程とを含むことを特徴とする。 [6] The first method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device for manufacturing the semiconductor device according to any one of the above [1] to [5], wherein the semiconductor is mounted on a substrate. The semiconductor chip arranging step of arranging the chips, the convex portion protruding to one surface side, and the convex portion formed on the top of the convex portion, penetrating from the one surface to the other surface on the opposite side to the one surface. A lead having an electrode connecting piece having a through hole formed therein is in a state where the electrode of the semiconductor chip and the electrode connecting piece face each other with a solder material interposed therebetween, and the convex portion protrudes toward the electrode side. An assembly forming step in which the solder material is arranged so as to be in a state to form an assembly, and a joining step in which the electrode and the electrode connecting piece are joined via solder by solidifying after melting the solder material. It is characterized by including.

[7]本発明の第2の半導体装置の製造方法は、上記[1]〜[5]のいずれかに記載の半導体装置を製造するための半導体装置の製造方法であって、基板上に半導体チップを配置する半導体チップ配置工程と、一方の面側に突出した凸部と、前記凸部の頂上部に形成され、前記一方の面から前記一方の面とは反対側の他方の面まで貫通された貫通孔とを有する電極接続片を有し、前記他方の面における、前記貫通孔を含む所定の領域にはんだ材が配置されたリードを、前記半導体チップの電極と前記電極接続片とが所定の間隔で対向した状態、かつ、前記凸部が前記電極側に向かって突出した状態となるように配置して組立体を形成する組立体形成工程と、前記はんだ材を溶融して前記貫通孔を通して前記電極と前記電極接続片との間に前記はんだ材を流し込んだ後で前記はんだ材を固化することにより、前記電極と前記電極接続片とをはんだを介して接合する接合工程とを含むことを特徴とする。 [7] The second method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device according to any one of the above [1] to [5], wherein the semiconductor is mounted on a substrate. The semiconductor chip arranging step of arranging the chips, the convex portion protruding to one surface side, and the convex portion formed on the top of the convex portion, penetrating from the one surface to the other surface on the opposite side to the one surface. A lead having an electrode connection piece having a through hole and a solder material arranged in a predetermined region including the through hole on the other surface is provided by the electrode of the semiconductor chip and the electrode connection piece. An assembly forming step of forming an assembly by arranging the convex portions so as to face each other at a predetermined interval and projecting the convex portions toward the electrode side, and the penetration of the solder material by melting the solder material. A joining step of joining the electrode and the electrode connecting piece via solder by solidifying the solder material after pouring the solder material between the electrode and the electrode connecting piece through a hole is included. It is characterized by that.

[8]本発明の半導体装置の製造方法において、前記組立体形成工程においては、前記電極と前記電極接続片の間のうちの一部にもはんだ材が配置されていることが好ましい。 [8] In the method for manufacturing a semiconductor device of the present invention, it is preferable that the solder material is also arranged in a part of the space between the electrode and the electrode connecting piece in the assembly forming step.

[9]本発明の半導体装置の製造方法において、前記組立体形成工程においては、断面で見たときに、前記凸部の部分で半導体チップ側に折り曲げられた形状を有する前記リードを配置することが好ましい。 [9] In the method for manufacturing a semiconductor device of the present invention, in the assembly forming step, the lead having a shape bent toward the semiconductor chip at the convex portion when viewed in cross section is arranged. Is preferable.

[10]本発明の半導体装置の製造方法において、前記組立体形成工程においては、前記凸部の側面形状が、前記半導体チップ側が狭いテーパ形状である前記リードを配置することが好ましい。 [10] In the method for manufacturing a semiconductor device of the present invention, in the assembly forming step, it is preferable to dispose the lead having a side surface shape of the convex portion having a narrow tapered shape on the semiconductor chip side.

[11]本発明の半導体装置の製造方法において、前記組立体形成工程においては、前記凸部の側面形状が、丸みを帯びた形状になっている前記リードを配置することが好ましい。 [11] In the method for manufacturing a semiconductor device of the present invention, in the assembly forming step, it is preferable to arrange the leads having a rounded side surface shape of the convex portion.

[12]本発明の半導体装置の製造方法において、前記はんだ材は、溶剤を含有するペースト状のはんだ材からなることが好ましい。 [12] In the method for manufacturing a semiconductor device of the present invention, the solder material is preferably made of a paste-like solder material containing a solvent.

本発明の半導体装置によれば、電極接続片は、はんだと接合する領域において、半導体チップ側に突出した凸部と、凸部の頂上部に形成され、半導体チップ側の面から半導体チップ側とは反対側の面まで貫通された貫通孔とを有するため、製造過程において、はんだ材上にリードを配置したときに、余剰なはんだ材を貫通孔を通してリードにおける半導体チップとは反対側の面に流れさせることができる。従って、はんだの厚みをある一定以上の厚さに保つ場合において、(接合工程前の)はんだ材上にリードを配置したときでも、余剰なはんだ材が所望しない場所にはみ出すことを防ぐことができ、半導体装置の信頼性が低下し難くなる。 According to the semiconductor device of the present invention, the electrode connection piece is formed on the convex portion protruding toward the semiconductor chip side and the top portion of the convex portion in the region to be joined with the solder, and is formed from the surface on the semiconductor chip side to the semiconductor chip side. Has a through hole that penetrates to the opposite surface, so when the lead is placed on the solder material in the manufacturing process, excess solder material is passed through the through hole to the surface of the lead opposite to the semiconductor chip. Can be made to flow. Therefore, when the thickness of the solder is kept above a certain level, even when the leads are arranged on the solder material (before the joining process), it is possible to prevent the excess solder material from squeezing out to an undesired place. , The reliability of the semiconductor device is less likely to decrease.

また、本発明の半導体装置によれば、電極接続片は、はんだと接合する領域において、半導体チップ側に突出した凸部を有するため、従来の半導体装置と比較して、リードとはんだとの接触面積が大きくなる。
また、本発明の半導体装置によれば、電極接続片は、凸部の頂上部に形成され、半導体チップ側の面から半導体チップ側とは反対側の面まで貫通された貫通孔とを有するため、はんだ材上にリードを配置したときに、余剰なはんだ材を貫通孔を通してリードにおける半導体チップとは反対側の面に流れさせることができる。従って、貫通孔内及びリードにおける半導体チップ側とは反対側の面にもはんだが存在することになるため、リードとはんだとの接触面積がより大きくなる。
従って、リードとはんだとの接合強度が高くなり、半導体装置の信頼性が高くなる。
Further, according to the semiconductor device of the present invention, since the electrode connection piece has a convex portion protruding toward the semiconductor chip side in the region to be joined with the solder, the contact between the lead and the solder is compared with that of the conventional semiconductor device. The area becomes large.
Further, according to the semiconductor device of the present invention, the electrode connection piece is formed on the top of the convex portion and has a through hole penetrating from the surface on the semiconductor chip side to the surface on the side opposite to the semiconductor chip side. When the lead is arranged on the solder material, the excess solder material can flow through the through hole to the surface of the lead opposite to the semiconductor chip. Therefore, since the solder is also present in the through hole and on the surface of the lead opposite to the semiconductor chip side, the contact area between the lead and the solder becomes larger.
Therefore, the bonding strength between the lead and the solder is increased, and the reliability of the semiconductor device is increased.

本発明の第1の半導体装置の製造方法によれば、組立体形成工程において、一方の面側に突出した凸部と、凸部の頂上部に形成され、一方の面から一方の面とは反対側の他方の面まで貫通された貫通孔とを有する電極接続片を有するリードを、電極と電極接続片とがはんだ材を挟んで対向した状態、かつ、凸部が電極側に向かって突出した状態となるように配置して組立体を形成し、接合工程において、はんだ材を溶融した後で固化することにより、電極と電極接続片とをはんだを介して接合するため、はんだ材上にリードを配置したときに、余剰なはんだ材を貫通孔を通してリードにおける半導体チップとは反対側の面に向かって流れさせることができる。従って、はんだの厚みをある一定以上の厚さに保つ場合において、はんだ材上にリードを配置したときでも、余剰なはんだ材が所望しない場所にはみ出すことを防ぐことができ、信頼性が低下し難い半導体装置を製造することができる。 According to the first method for manufacturing a semiconductor device of the present invention, in the assembly forming step, a convex portion protruding toward one surface side and a convex portion formed on the top of the convex portion, from one surface to one surface. A lead having an electrode connecting piece having a through hole penetrated to the other surface on the opposite side is in a state where the electrode and the electrode connecting piece face each other with the solder material sandwiched between them, and the convex portion protrudes toward the electrode side. In the joining process, the electrodes and electrode connection pieces are joined via solder by solidifying after melting the solder material, so that the electrodes are joined on the solder material. When the leads are arranged, excess solder material can flow through the through holes toward the surface of the leads opposite to the semiconductor chip. Therefore, when the thickness of the solder is kept above a certain level, even when the leads are arranged on the solder material, it is possible to prevent the excess solder material from squeezing out to an undesired place, and the reliability is lowered. It is possible to manufacture difficult semiconductor devices.

本発明の第2の半導体装置の製造方法によれば、組立体形成工程において、一方の面側に突出した凸部と、凸部の頂上部に形成され、一方の面から一方の面とは反対側の他方の面まで貫通された貫通孔とを有する電極接続片を有し、他方の面における、貫通孔を含む所定の領域にはんだ材が配置されたリードを、電極と電極接続片とが所定の間隔で対向した状態、かつ、凸部が電極側に向かって突出した状態となるように配置して組立体を形成し、接合工程において、はんだ材を溶融して貫通孔を通して電極と電極接続片との間にはんだ材を流し込んだ後ではんだ材を固化することにより、電極と電極接続片とをはんだを介して接合するため、接合工程前のはんだ材を厚くしすぎることがなく、ある一定以上の厚さのはんだ材上にリードを配置する、ということもない。従って、余剰なはんだ材が所望しない場所にはみ出すことを防ぐことができる。その結果、信頼性が低下し難い半導体装置を製造することができる。 According to the method for manufacturing the second semiconductor device of the present invention, in the assembly forming step, the convex portion protruding toward one surface side and the convex portion formed on the top of the convex portion are formed from one surface to one surface. A lead having an electrode connecting piece having a through hole penetrating to the other surface on the opposite side and having a solder material arranged in a predetermined region including the through hole on the other surface is formed with the electrode and the electrode connecting piece. Are arranged so as to face each other at predetermined intervals and the convex portions are projected toward the electrode side to form an assembly. By solidifying the solder material after pouring the solder material between the electrode connection pieces, the electrodes and the electrode connection pieces are joined via solder, so the solder material before the joining process does not become too thick. There is no need to place the leads on a solder material with a certain thickness or more. Therefore, it is possible to prevent the excess solder material from squeezing out to an undesired place. As a result, it is possible to manufacture a semiconductor device whose reliability is unlikely to decrease.

実施形態1に係る半導体装置1を示す図である。図1(a)は半導体装置1の平面図であり、図1(b)は半導体装置1の断面図である。It is a figure which shows the semiconductor device 1 which concerns on Embodiment 1. FIG. FIG. 1A is a plan view of the semiconductor device 1, and FIG. 1B is a cross-sectional view of the semiconductor device 1. 実施形態1に係る半導体装置1の要部拡大図である。図2(a)は半導体装置1の要部拡大断面図であり、図2(b)は半導体装置1の要部拡大平面図である。FIG. 5 is an enlarged view of a main part of the semiconductor device 1 according to the first embodiment. FIG. 2A is an enlarged cross-sectional view of a main part of the semiconductor device 1, and FIG. 2B is an enlarged plan view of a main part of the semiconductor device 1. 実施形態1に係る半導体装置の製造方法のフローチャートである。It is a flowchart of the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. 実施形態1に係る半導体装置の製造方法の工程図である。図4(a)は基板準備工程を示す図であり、図4(b)は半導体チップ配置工程を示す図であり、図4(c)ははんだ材配置工程を示す図である。It is a process drawing of the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. FIG. 4A is a diagram showing a substrate preparation process, FIG. 4B is a diagram showing a semiconductor chip arrangement process, and FIG. 4C is a diagram showing a solder material arrangement process. 実施形態1に係る半導体装置の製造方法の工程図である。図5(a)はリードフレーム配置工程を示す図であり、図5(b)は接合工程(リフロー工程)を示す図であり、図5(c)はワイヤボンディング工程を示す図である。It is a process drawing of the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. 5 (a) is a diagram showing a lead frame arrangement process, FIG. 5 (b) is a diagram showing a joining process (reflow process), and FIG. 5 (c) is a diagram showing a wire bonding process. 実施形態1に係る半導体装置の製造方法の効果を説明するために示す図である。図6(a)ははんだ材上にリード(リードフレーム)を配置する前の組立体50の断面図であり、図6(b)ははんだ材上にリードを配置する前の組立体50の平面図であり、図6(c)ははんだ材上にリードを配置した後の組立体50の断面図であり、図6(d)ははんだ材上にリードを配置した後の組立体50の平面図であり、図6(e)は接合工程後の組立体50の断面図であり、図6(f)は接合工程後の組立体50の平面図である。It is a figure which shows for demonstrating the effect of the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. 6A is a cross-sectional view of the assembly 50 before arranging the leads (lead frame) on the solder material, and FIG. 6B is a plane view of the assembly 50 before arranging the leads on the solder material. 6 (c) is a cross-sectional view of the assembly 50 after the leads are arranged on the solder material, and FIG. 6 (d) is a plan view of the assembly 50 after the leads are arranged on the solder material. 6 (e) is a cross-sectional view of the assembly 50 after the joining step, and FIG. 6 (f) is a plan view of the assembly 50 after the joining step. 実施形態2に係る半導体装置の製造方法の効果を説明するために示す図である。図7(a)は接合工程(リフロー工程)実施前の組立体51の断面図であり、図7(b)は接合工程(リフロー工程)実施前の組立体51の平面図であり、図7(c)は接合工程(リフロー工程)実施中の組立体51の断面図であり、図7(d)は接合工程(リフロー工程)実施中の組立体51の平面図である。It is a figure which shows for demonstrating the effect of the manufacturing method of the semiconductor device which concerns on Embodiment 2. FIG. 7A is a cross-sectional view of the assembly 51 before the joining step (reflow step) is carried out, and FIG. 7B is a plan view of the assembly 51 before the joining step (reflow step) is carried out. (C) is a cross-sectional view of the assembly 51 during the joining step (reflow step), and FIG. 7 (d) is a plan view of the assembly 51 during the joining step (reflow step). 実施形態3に係る半導体装置の製造方法の効果を説明するために示す図である。図8(a)は接合工程(リフロー工程)実施前の組立体52の断面図であり、図8(b)は接合工程(リフロー工程)実施前の組立体52の平面図であり、図8(c)は接合工程(リフロー工程)実施中の組立体52の断面図であり、図8(d)は接合工程(リフロー工程)実施中の組立体52の平面図である。It is a figure which shows for demonstrating the effect of the manufacturing method of the semiconductor device which concerns on Embodiment 3. FIG. 8A is a cross-sectional view of the assembly 52 before the joining step (reflow step) is carried out, and FIG. 8B is a plan view of the assembly 52 before the joining step (reflow step) is carried out. (C) is a cross-sectional view of the assembly 52 during the joining step (reflow step), and FIG. 8 (d) is a plan view of the assembly 52 during the joining step (reflow step). 変形例1〜4に係る半導体装置におけるリードの凸部及び貫通孔を示す要部拡大断面図である。図9(a)〜図9(d)は変形例1〜4に係る半導体装置におけるリードの凸部及び貫通孔を示す要部拡大断面図である。FIG. 5 is an enlarged cross-sectional view of a main part showing a convex portion and a through hole of a lead in the semiconductor device according to the modified examples 1 to 4. 9 (a) to 9 (d) are enlarged cross-sectional views of a main part showing the convex portion and the through hole of the lead in the semiconductor device according to the modified examples 1 to 4. 変形例5に係る半導体装置における要部拡大図である。図10(a)は変形例5に係る半導体装置における要部拡大断面図であり、図10(b)は変形例5に係る半導体装置における要部拡大平面図である。It is an enlarged view of the main part in the semiconductor device which concerns on modification 5. FIG. 10A is an enlarged cross-sectional view of a main part of the semiconductor device according to the modified example 5, and FIG. 10B is an enlarged plan view of the main part of the semiconductor device according to the modified example 5. 変形例6に係る半導体装置2を示す図である。図11(a)は半導体装置2の斜視図であり、図11(b)は半導体装置2の断面図である。It is a figure which shows the semiconductor device 2 which concerns on modification 6. FIG. 11A is a perspective view of the semiconductor device 2, and FIG. 11B is a cross-sectional view of the semiconductor device 2. 従来の半導体装置900を示す断面図である。なお、図12中、符号946ははんだを示し、符号960、符号962は端子を示し、符号970はワイヤを示し、符号980は樹脂を示す。It is sectional drawing which shows the conventional semiconductor device 900. In FIG. 12, reference numeral 946 indicates solder, reference numeral 960 and reference numeral 962 indicate terminals, reference numeral 970 indicates wire, and reference numeral 980 indicates resin. 従来の半導体装置の製造方法の問題点を示す図である。図13(a)はリード配置前の組立体の様子を示す図であり、図13(b)はリード配置後の組立体の様子を示す図である。なお、符号941,945はペースト状のはんだ材を示す。It is a figure which shows the problem of the manufacturing method of the conventional semiconductor device. FIG. 13A is a diagram showing a state of the assembly before the lead arrangement, and FIG. 13B is a diagram showing the state of the assembly after the lead arrangement. Reference numerals 941 and 945 indicate a paste-like solder material.

以下、本発明の半導体装置の製造方法について、図に示す実施形態に基づいて説明する。なお、各図面は模式図であり、必ずしも実際の寸法を厳密に反映したものではない。 Hereinafter, the method for manufacturing the semiconductor device of the present invention will be described based on the embodiment shown in the figure. It should be noted that each drawing is a schematic view and does not necessarily accurately reflect the actual dimensions.

[実施形態1]
1.実施形態1における半導体装置1の構成
実施形態1に係る半導体装置1は、図1及び図2に示すように、基板10と、半導体チップ20と、リード30,62,64と、はんだ40,46と、ワイヤ70とを備え、リード30,62,64の外部接続端子及び放熱性の金属板18の一部を除いて樹脂80で樹脂封止されている。
[Embodiment 1]
1. 1. Configuration of Semiconductor Device 1 in Embodiment 1. As shown in FIGS. 1 and 2, the semiconductor device 1 according to the first embodiment includes a substrate 10, a semiconductor chip 20, leads 30, 62, 64, and solders 40, 46. And the wire 70, and the leads 30, 62, 64 are resin-sealed with the resin 80 except for a part of the external connection terminals and the heat-dissipating metal plate 18.

基板10は、半導体チップ配置面12を有する基板である。基板10としては適宜の基板(例えば、プリント基板)を用いることができるが、実施形態1においては、絶縁性基板14と、絶縁性基板14の一方の面に形成され、半導体チップ配置面12を有する回路16と、絶縁性基板14の他方の面に形成された放熱用の金属板18とを有するDCB(Direct Cоpper Bonding)基板を用いる。なお、放熱用の金属板18は樹脂80から露出している。 The substrate 10 is a substrate having a semiconductor chip arranging surface 12. An appropriate substrate (for example, a printed circuit board) can be used as the substrate 10, but in the first embodiment, the insulating substrate 14 and the insulating substrate 14 are formed on one surface, and the semiconductor chip arranging surface 12 is formed. A DCB (Direct Copper Bonding) substrate having a circuit 16 having the circuit 16 and a metal plate 18 for heat dissipation formed on the other surface of the insulating substrate 14 is used. The heat-dissipating metal plate 18 is exposed from the resin 80.

半導体チップ20は、半導体チップ配置面12上に配置されており、一方の面(半導体チップ配置面12と対向する面。あるいは、基板10側の面)に形成されたコレクタ電極22、並びに、他方の面(半導体チップ配置面12と対向する面とは反対側の面。あるいは、基板10側の面とは反対側の面)に形成されたエミッタ電極24(電極)及びエミッタ電極24とは離間した位置に形成されたゲート電極26を有するIGBT(Insulated Gate Bipolar Transistor)である。 The semiconductor chip 20 is arranged on the semiconductor chip arrangement surface 12, and has a collector electrode 22 formed on one surface (a surface facing the semiconductor chip arrangement surface 12 or a surface on the substrate 10 side), and the other. The emitter electrode 24 (electrode) and the emitter electrode 24 formed on the surface (the surface opposite to the surface facing the semiconductor chip arrangement surface 12 or the surface opposite to the surface on the substrate 10 side) are separated from each other. It is an IGBT (Integrated Gate Bipolar Semiconductor) having a gate electrode 26 formed at the above-mentioned position.

コレクタ電極22は、基板10の半導体チップ配置面12とはんだ46を介して接合されており、はんだ46、基板10(回路16)及びリード64を介して外部と接続される。
エミッタ電極24は、リード30の電極接続片32とはんだ40を介して接合されており、はんだ40及びリード30(外部接続端子34)を介して外部と接続される。
The collector electrode 22 is joined to the semiconductor chip arranging surface 12 of the substrate 10 via the solder 46, and is connected to the outside via the solder 46, the substrate 10 (circuit 16), and the lead 64.
The emitter electrode 24 is joined to the electrode connection piece 32 of the lead 30 via the solder 40, and is connected to the outside via the solder 40 and the lead 30 (external connection terminal 34).

リード30,62,64は、平板状の金属部材であり、リードフレームを切り離して形成されたものである。リード30,62,64はワイヤよりも断面積が大きく、大電流を流すことができる。 The leads 30, 62, and 64 are flat metal members, and are formed by separating the lead frame. The leads 30, 62, and 64 have a larger cross-sectional area than the wire and can carry a large current.

リード30は、一方の端部にエミッタ電極24と接続するための電極接続片32を有し、他方の端部に外部と接続するための外部接続端子34を有する。 The lead 30 has an electrode connection piece 32 for connecting to the emitter electrode 24 at one end, and an external connection terminal 34 for connecting to the outside at the other end.

電極接続片32は、はんだ40と接合する領域において、半導体チップ20側に突出した凸部36と、凸部36の頂上部37に形成され、半導体チップ20側の面から半導体チップ20側とは反対側の面まで貫通された貫通孔38とを有する。 The electrode connection piece 32 is formed on a convex portion 36 protruding toward the semiconductor chip 20 side and a top portion 37 of the convex portion 36 in a region to be joined with the solder 40, and is formed from a surface on the semiconductor chip 20 side to the semiconductor chip 20 side. It has a through hole 38 that penetrates to the opposite surface.

リード30は、断面で見たときに、凸部36の部分で半導体チップ20側に折り曲げられた形状を有する。凸部36は、半導体チップ20側に向かって打ち出し加工されたような形状を有する。凸部36の側面形状は、半導体チップ20側が狭いテーパ形状であり、凸部の側面形状(側面の断面形状)は、丸みを帯びた形状をしている。言い換えると、凸部36の側面形状は、半導体チップ20側が頂上部となり、かつ、裾野が広い富士山型の形状、あるいは、半導体チップ20とは反対側が広いラッパ型の形状をしている。 The lead 30 has a shape that is bent toward the semiconductor chip 20 at the portion of the convex portion 36 when viewed in cross section. The convex portion 36 has a shape as if it was punched toward the semiconductor chip 20 side. The side surface shape of the convex portion 36 is a tapered shape narrow on the semiconductor chip 20 side, and the side surface shape (cross-sectional shape of the side surface) of the convex portion is a rounded shape. In other words, the side surface shape of the convex portion 36 has a Mt. Fuji shape in which the semiconductor chip 20 side is the top and a wide base, or a trumpet shape in which the side opposite to the semiconductor chip 20 is wide.

電極接続片32を半導体チップ20側とは反対側の面からみると、凸部36の形状に対応した形状の凹部があるように見える。言い換えると、半導体チップ20側とは反対側の面から半導体チップ20側に向かうに従って狭くなっている凹部があるように見える。凹部の最底部には貫通孔38がある。凹部内にはエミッタ電極24と電極接続片32との間のはんだ40から流れ出たはんだが入り込んでおり、当該はんだは、貫通孔38近傍のリード30における半導体チップ20側とは反対側からリード30に接している。 When the electrode connection piece 32 is viewed from the surface opposite to the semiconductor chip 20 side, it seems that there is a concave portion having a shape corresponding to the shape of the convex portion 36. In other words, it seems that there is a recess that becomes narrower toward the semiconductor chip 20 side from the surface opposite to the semiconductor chip 20 side. There is a through hole 38 at the bottom of the recess. The solder that has flowed out from the solder 40 between the emitter electrode 24 and the electrode connection piece 32 has entered the recess, and the solder is the lead 30 from the side of the lead 30 near the through hole 38 opposite to the semiconductor chip 20 side. Is in contact with.

貫通孔38は、凸部36の頂上部37に形成され、半導体チップ20側の面から半導体チップ20側とは反対側の面まで貫通されている。貫通孔38は、接合工程前にリード30をはんだ材の上に配置したときに、はんだ材が貫通孔38を介して行き来できる程度の大きさである(すなわち、はんだ材が貫通孔38を介して十分行き来できず、意図しない領域にはんだ材が飛び出してしまうことを防ぐことができる程度の大きさである)。 The through hole 38 is formed in the top portion 37 of the convex portion 36, and penetrates from the surface on the semiconductor chip 20 side to the surface on the side opposite to the semiconductor chip 20 side. The through hole 38 is large enough so that the solder material can move back and forth through the through hole 38 when the lead 30 is placed on the solder material before the joining process (that is, the solder material passes through the through hole 38). It is large enough to prevent the solder material from jumping out to an unintended area because it cannot come and go sufficiently).

リード62は、一方の端部がワイヤ70を介してゲート電極26と接続されており、他方の端部が外部接続用の端子となっている。リード64は、一方の端部がコレクタ電極22と接続された回路16と接続されており、他方の端部が外部接続用の端子となっている。 One end of the lead 62 is connected to the gate electrode 26 via a wire 70, and the other end is a terminal for external connection. One end of the lead 64 is connected to the circuit 16 connected to the collector electrode 22, and the other end is a terminal for external connection.

はんだ40,46は、導電性及び接着性を有する合金又は金属である。はんだ40、46ははんだ材を加熱することにより溶融して固化したものである。
はんだ40は、エミッタ電極24と電極接続片32とを接合している。はんだ40の厚さ(はんだ厚)は、はんだ46(基板10と半導体チップ20との間のはんだ)の厚さよりも厚く、例えば300μm以上である。
はんだ46は、コレクタ電極22と半導体チップ配置面12を接合している。はんだ46は、溶剤(具体的にはフラックス)を含有するペースト状のはんだ材(いわゆるクリームはんだ)から形成されたものであり、印刷により基板10の半導体チップ配置面12上に配置され、リフローして加熱することにより基板10と半導体チップ20とを接合する。なお、はんだ46は、はんだ40の場合と異なり、はんだに作用する応力(例えば熱応力)を緩和するという事情がなく、厚くなると導通損失が大きくなるため、比較的薄い方が好ましい。
Solders 40 and 46 are alloys or metals having conductivity and adhesiveness. The solders 40 and 46 are melted and solidified by heating the solder material.
The solder 40 joins the emitter electrode 24 and the electrode connection piece 32. The thickness of the solder 40 (solder thickness) is thicker than the thickness of the solder 46 (solder between the substrate 10 and the semiconductor chip 20), for example, 300 μm or more.
The solder 46 joins the collector electrode 22 and the semiconductor chip arranging surface 12. The solder 46 is formed of a paste-like solder material (so-called cream solder) containing a solvent (specifically, flux), is arranged on the semiconductor chip arrangement surface 12 of the substrate 10 by printing, and reflows. The substrate 10 and the semiconductor chip 20 are joined by heating. Unlike the case of the solder 40, the solder 46 does not have a situation of relaxing the stress acting on the solder (for example, thermal stress), and the thicker the solder 46, the larger the conduction loss. Therefore, it is preferable that the solder 46 is relatively thin.

樹脂80は、適宜の樹脂を用いることができる。 As the resin 80, an appropriate resin can be used.

2.実施形態1に係る半導体装置の製造方法
実施形態1に係る半導体装置の製造方法は、図3に示すように、基板準備工程S100と、半導体チップ配置工程S200と、組立体形成工程S300と、接合工程S400と、ワイヤボンディング工程S500と、樹脂封止工程S600と、リード加工工程S700とを含む。
2. Manufacturing method of semiconductor device according to the first embodiment As shown in FIG. 3, the manufacturing method of the semiconductor device according to the first embodiment is a bonding of a substrate preparation step S100, a semiconductor chip arranging step S200, and an assembly forming step S300. It includes a step S400, a wire bonding step S500, a resin sealing step S600, and a lead processing step S700.

(1)基板準備工程S100
基板準備工程S100においては、基板10を準備する(図4(a)参照。)。具体的には、所定の治具上に基板10を位置決めして配置する。
(1) Substrate preparation step S100
In the substrate preparation step S100, the substrate 10 is prepared (see FIG. 4A). Specifically, the substrate 10 is positioned and arranged on a predetermined jig.

(2)半導体チップ配置工程S200
半導体チップ配置工程S200においては、基板10の半導体チップ配置面12上にはんだ材45を介して半導体チップ20を配置する(図4(b)参照。)。具体的には、まず、基板10の半導体チップ配置面12上にペースト状のはんだ材45(例えば、いわゆるクリームはんだ)を印刷する。次に、半導体チップ配置面12と半導体チップ20のコレクタ電極22とがはんだ材45を挟んで対向した状態となるように半導体チップ配置面12上に半導体チップ20を配置する。
なお、実施形態1においては、はんだ材45を印刷することによりはんだ材を供給しているが、ディスペンサによってはんだ材を供給する、はんだフィーダ等で送り出した糸はんだによってはんだ材を供給する、溶融したはんだ材を流し込むことによってはんだ材を供給する等、適宜の方法ではんだ材を供給してもよい。
(2) Semiconductor chip placement process S200
In the semiconductor chip arranging step S200, the semiconductor chip 20 is arranged on the semiconductor chip arranging surface 12 of the substrate 10 via the solder material 45 (see FIG. 4B). Specifically, first, a paste-like solder material 45 (for example, so-called cream solder) is printed on the semiconductor chip arrangement surface 12 of the substrate 10. Next, the semiconductor chip 20 is arranged on the semiconductor chip arrangement surface 12 so that the semiconductor chip arrangement surface 12 and the collector electrode 22 of the semiconductor chip 20 face each other with the solder material 45 interposed therebetween.
In the first embodiment, the solder material is supplied by printing the solder material 45, but the solder material is supplied by the dispenser, the solder material is supplied by the thread solder sent out by the solder feeder or the like, and the solder material is melted. The solder material may be supplied by an appropriate method such as supplying the solder material by pouring the solder material.

なお、クリームはんだは、はんだ粉末にフラックスを添加して、適当な粘度のペースト状にしたものである。フラックスは、高温(例えば、はんだの溶融温度)で揮発する成分である。フラックスとしては、ロジン、変性ロジン、合成樹脂などを主成分として用いた樹脂系フラックスが用いられ、さらに、チクソトロピック剤や、活性剤および活性剤用の溶剤、分散安定剤などが添加される場合もある。 The cream solder is obtained by adding a flux to the solder powder to form a paste having an appropriate viscosity. Flux is a component that volatilizes at high temperatures (eg, the melting temperature of solder). As the flux, a resin-based flux containing rosin, modified rosin, synthetic resin, etc. as the main component is used, and when a thixotropic agent, a solvent for an activator and an activator, a dispersion stabilizer, etc. are added. There is also.

(3)組立体形成工程S300
組立体形成工程S300は、はんだ材配置工程S310とリードフレーム配置工程S320を含む。
(3) Assembly forming step S300
The assembly forming step S300 includes a solder material arranging step S310 and a lead frame arranging step S320.

(3−1)はんだ材配置工程S310
はんだ材配置工程S310においては、半導体チップ20のエミッタ電極24上にはんだ材41を配置する(図4(c)参照。)。はんだ材41としては、溶剤を含有するペースト状のはんだ材を用いる。実施形態1においては、溶剤として、高温(例えば、はんだの溶融温度)で揮発する成分を含有する溶剤(例えば、フラックス)を含有するペースト状のはんだ材(具体的には、いわゆるクリームはんだ)を用いる。なお、溶剤として、高温で揮発する成分を含有する溶剤以外の溶剤を含有するペースト状のはんだ材を用いてもよいし、後のリードフレーム配置工程において、貫通孔38を通してはんだ材41が移動できる程度の粘度があるはんだ材であれば、他の適宜のはんだ材を用いてもよい。
(3-1) Solder material placement process S310
In the solder material arranging step S310, the solder material 41 is arranged on the emitter electrode 24 of the semiconductor chip 20 (see FIG. 4C). As the solder material 41, a paste-like solder material containing a solvent is used. In the first embodiment, as the solvent, a paste-like solder material (specifically, so-called cream solder) containing a solvent (for example, flux) containing a component that volatilizes at a high temperature (for example, the melting temperature of the solder) is used. Use. As the solvent, a paste-like solder material containing a solvent other than the solvent containing a component that volatilizes at a high temperature may be used, or the solder material 41 can move through the through hole 38 in the subsequent lead frame arrangement step. Any other suitable solder material may be used as long as it is a solder material having a certain degree of viscosity.

(3−2)リードフレーム配置工程S320
リードフレーム配置工程においては、一方の面側に突出した凸部36と、凸部36の頂上部37に形成され、一方の面から一方の面とは反対側の他方の面まで貫通された貫通孔38とを有する電極接続片32を有するリード30(リード30が連結されているリードフレーム)を、エミッタ電極24と電極接続片32とがはんだ材41を挟んで対向した状態、かつ、凸部36がエミッタ電極24側に向かって突出した状態となるように配置する(図5(a)参照。)。このとき、リードフレーム200内のリード62,64も所定の位置に配置される。
(3-2) Lead frame arrangement step S320
In the lead frame arranging step, the convex portion 36 projecting to one surface side and the top 37 of the convex portion 36 are formed and penetrated from one surface to the other surface on the opposite side to the other surface. A lead 30 having an electrode connecting piece 32 having a hole 38 (a lead frame to which the lead 30 is connected) is in a state where the emitter electrode 24 and the electrode connecting piece 32 face each other with the solder material 41 in between, and a convex portion. 36 is arranged so as to protrude toward the emitter electrode 24 side (see FIG. 5A). At this time, the leads 62 and 64 in the lead frame 200 are also arranged at predetermined positions.

具体的には、はんだ材41上に、凸部36がエミッタ電極24側に向くように配置する(図6(a)及び(b)参照。)。このとき、余剰なはんだ材41が貫通孔を通って、リード30の半導体チップ20側とは反対側に向かって移動する(図6(c)及び(d)参照。)。従って、はんだ材41が意図しない領域(例えば、平面的に見てエミッタ電極が形成されていない領域)にはんだ材41が流れ出てしまうことがない。なお、リード30の半導体チップ20側とは反対側の面にはんだ材が流れ出ても周囲に異なる電位の電極がなく、不具合が起こり難い。 Specifically, the convex portion 36 is arranged on the solder material 41 so as to face the emitter electrode 24 side (see FIGS. 6A and 6B). At this time, the surplus solder material 41 moves through the through hole toward the side of the lead 30 opposite to the semiconductor chip 20 side (see FIGS. 6 (c) and 6 (d)). Therefore, the solder material 41 does not flow out to an unintended region (for example, a region where the emitter electrode is not formed when viewed in a plane). Even if the solder material flows out on the surface of the lead 30 opposite to the semiconductor chip 20 side, there are no electrodes having different potentials around it, so that a problem is unlikely to occur.

これにより、一方の面側に突出した凸部36と、凸部36の頂上部37に形成され、一方の面から一方の面とは反対側の他方の面まで貫通された貫通孔38とを有する電極接続片32を有するリード30を、エミッタ電極24と電極接続片32とがはんだ材41を挟んで対向した状態、かつ、凸部36がエミッタ電極24側に向かって突出した状態となるように配置して組立体50を形成することができる(図5(a)参照。)。 As a result, the convex portion 36 protruding toward one surface side and the through hole 38 formed at the top 37 of the convex portion 36 and penetrating from one surface to the other surface on the opposite side to the other surface are formed. The lead 30 having the electrode connecting piece 32 is in a state where the emitter electrode 24 and the electrode connecting piece 32 face each other with the solder material 41 interposed therebetween, and the convex portion 36 projects toward the emitter electrode 24 side. The assembly 50 can be formed by arranging in (see FIG. 5 (a)).

(4)接合工程(リフロー工程)S400
接合工程(リフロー工程)S400においては、組立体50をリフロー炉(図示せず。)に入れて加熱し、はんだ材41、45を溶融した後で、はんだ材41、45を固化してはんだ40、46とする(図5(b)参照。)。このとき、余剰なはんだ材が貫通孔38を介してリード30の半導体チップ20側とは反対側の面に移動する(図6(e)及び(f)参照。)。また、このとき、フラックス等のガスが貫通孔38を通って外部に放出される。これにより、基板10の半導体チップ配置面12と半導体チップ20のエミッタ電極24とをはんだ46を介して接合するとともに、半導体チップ20のコレクタ電極22とリード30の電極接続片32とをはんだ40を介して接合する。
(4) Joining process (reflow process) S400
In the joining step (reflow step) S400, the assembly 50 is placed in a reflow furnace (not shown) and heated to melt the solder materials 41 and 45, and then the solder materials 41 and 45 are solidified to solidify the solder 40. , 46 (see FIG. 5 (b)). At this time, the excess solder material moves to the surface of the lead 30 opposite to the semiconductor chip 20 side through the through hole 38 (see FIGS. 6 (e) and 6 (f)). At this time, a gas such as flux is discharged to the outside through the through hole 38. As a result, the semiconductor chip arranging surface 12 of the substrate 10 and the emitter electrode 24 of the semiconductor chip 20 are joined via the solder 46, and the collector electrode 22 of the semiconductor chip 20 and the electrode connection piece 32 of the lead 30 are soldered 40. Join through.

(5)ワイヤボンディング工程S500
次に、ゲート電極26とリード62(図1参照。)とをワイヤ70を用いて接続する(図5(c)参照。)。ワイヤ70は適宜のものを用いることができる。
(5) Wire bonding step S500
Next, the gate electrode 26 and the lead 62 (see FIG. 1) are connected by using a wire 70 (see FIG. 5 (c)). Any wire 70 can be used as appropriate.

(6)樹脂封止工程S600及びリード加工工程S700
次に、リード30,62,64の外部端子及び放熱用の金属板18を除いて樹脂80で樹脂封止する(樹脂封止工程S600、図示せず。)、次に、リード30,62,64をリードフレームから切り離すとともに、所定の箇所の折り曲げ等の加工を行う(リード加工工程S700、図示せず。)。
このようにして実施形態1における半導体装置1を製造することができる。
(6) Resin sealing step S600 and lead processing step S700
Next, the external terminals of the leads 30, 62, 64 and the metal plate 18 for heat dissipation are removed, and the resin is sealed with the resin 80 (resin sealing step S600, not shown). Next, the leads 30, 62, The 64 is separated from the lead frame, and processing such as bending of a predetermined portion is performed (lead processing step S700, not shown).
In this way, the semiconductor device 1 according to the first embodiment can be manufactured.

3.実施形態1に係る半導体装置の製造方法の効果
実施形態1に係る半導体装置1によれば、電極接続片32は、はんだ40と接合する領域において、半導体チップ20側に突出した凸部36と、凸部36の頂上部37に形成され、半導体チップ20側の面から半導体チップ20側とは反対側の面まで貫通された貫通孔38とを有するため、製造過程において、はんだ材41上にリード30を配置したときに、余剰なはんだ材を貫通孔38を通してリード30における半導体チップ20とは反対側の面に流れさせることができる。従って、はんだ40の厚みをある一定以上の厚さに保つ場合において、(接合工程前の)はんだ材41上にリードを30配置したときでも、余剰なはんだ材41が所望しない場所にはみ出すことを防ぐことができ、半導体装置の信頼性が低下し難くなる。
3. 3. Effect of the method for manufacturing a semiconductor device according to the first embodiment According to the semiconductor device 1 according to the first embodiment, the electrode connection piece 32 has a convex portion 36 protruding toward the semiconductor chip 20 in a region to be joined with the solder 40. Since it has a through hole 38 formed on the top 37 of the convex portion 36 and penetrating from the surface on the semiconductor chip 20 side to the surface on the side opposite to the semiconductor chip 20 side, it leads on the solder material 41 in the manufacturing process. When the 30 is arranged, the excess solder material can flow through the through hole 38 to the surface of the lead 30 opposite to the semiconductor chip 20. Therefore, when the thickness of the solder 40 is kept to a certain thickness or more, even when 30 leads are arranged on the solder material 41 (before the joining process), the excess solder material 41 does not protrude to an undesired place. This can be prevented, and the reliability of the semiconductor device is less likely to decrease.

また、実施形態1に係る半導体装置1によれば、電極接続片32は、はんだ40と接合する領域において、半導体チップ20側に突出した凸部36を有するため、従来の半導体装置と比較して、リード30とはんだ40との接触面積が大きくなる。
また、実施形態1に係る半導体装置1によれば、電極接続片32は、凸部36の頂上部37に形成され、半導体チップ20側の面から半導体チップ20側とは反対側の面まで貫通された貫通孔38とを有するため、はんだ材41上にリード30を配置したときに、余剰なはんだ材41を貫通孔38を通してリード30における半導体チップ20とは反対側の面に流れさせることができる。従って、貫通孔38内及びリード30における半導体チップ20側とは反対側の面にもはんだ40が存在することになるため、リード30とはんだ40との接触面積がより大きくなる。
従って、リード30とはんだ40との接合強度が高くなり、半導体装置の信頼性が高くなる。
Further, according to the semiconductor device 1 according to the first embodiment, since the electrode connection piece 32 has a convex portion 36 protruding toward the semiconductor chip 20 in the region where the solder 40 is joined, the electrode connection piece 32 is compared with the conventional semiconductor device. , The contact area between the lead 30 and the solder 40 becomes large.
Further, according to the semiconductor device 1 according to the first embodiment, the electrode connection piece 32 is formed on the top 37 of the convex portion 36 and penetrates from the surface on the semiconductor chip 20 side to the surface on the side opposite to the semiconductor chip 20 side. Since the lead 30 is provided with the through hole 38, when the lead 30 is arranged on the solder material 41, the surplus solder material 41 can flow through the through hole 38 to the surface of the lead 30 opposite to the semiconductor chip 20. can. Therefore, since the solder 40 is also present in the through hole 38 and on the surface of the lead 30 opposite to the semiconductor chip 20 side, the contact area between the lead 30 and the solder 40 becomes larger.
Therefore, the bonding strength between the lead 30 and the solder 40 is increased, and the reliability of the semiconductor device is increased.

実施形態1に係る半導体装置1及び半導体装置の製造方法によれば、リード30は、断面で見たときに、凸部36の部分で半導体チップ20側に折り曲げられた形状を有するため、接合工程において、貫通孔38を通った余剰なはんだ材41をリード30の半導体チップ側の面の裏側に回りこませることができる。従って、リード30における貫通孔38の開口近傍の部分は、半導体チップ20側及び半導体チップ20とは反対側の両側ではんだ40と接触することになる。従って、リード30とはんだ40との接合強度がより一層高くなり、半導体装置の信頼性がより低下し難くなる。 According to the semiconductor device 1 and the method for manufacturing the semiconductor device according to the first embodiment, the lead 30 has a shape that is bent toward the semiconductor chip 20 at the convex portion 36 when viewed in cross section, and thus is a joining step. In the above, the surplus solder material 41 that has passed through the through hole 38 can be wrapped around the back side of the surface of the lead 30 on the semiconductor chip side. Therefore, the portion of the lead 30 near the opening of the through hole 38 comes into contact with the solder 40 on both the semiconductor chip 20 side and the side opposite to the semiconductor chip 20. Therefore, the joint strength between the lead 30 and the solder 40 is further increased, and the reliability of the semiconductor device is less likely to be lowered.

また、実施形態1に係る半導体装置1及び半導体装置の製造方法によれば、凸部36の側面形状は、半導体チップ20側が狭いテーパ形状であるため、凸部36の側面が半導体チップに対して垂直である場合と比較して、リード30とはんだ40との接触面積が大きくなる。従って、リード30とはんだ40との接合強度がより一層高くなり、半導体装置の信頼性が高くなる。 Further, according to the semiconductor device 1 and the method for manufacturing the semiconductor device according to the first embodiment, the side surface shape of the convex portion 36 is a tapered shape in which the semiconductor chip 20 side is narrow, so that the side surface of the convex portion 36 is relative to the semiconductor chip. The contact area between the lead 30 and the solder 40 is larger than that in the case of being vertical. Therefore, the bonding strength between the lead 30 and the solder 40 is further increased, and the reliability of the semiconductor device is increased.

なお、凸部36が、断面で見たときに、リード30が半導体チップ20側に折り曲げられた形状を有し、かつ、凸部36の側面形状が、半導体チップ20側が狭いテーパ形状である場合には、リード30を半導体チップ20側とは反対側から見たときに側面がテーパ形状の凹部が形成されていることとなるため、接合工程において、貫通孔38を通って半導体チップ20とは反対側に流れたはんだ材41が貫通孔38近傍に滞りやすく、そのようなはんだ材41が固化するとねじの頭のような形状(半導体チップ側が頂点の円錐形のような形状)のはんだとなる。従って、リード30とはんだ40とがより一層剥がれ難くなり、リード30とはんだ40との接合強度をより一層高くすることができる、という効果もある。 When the convex portion 36 has a shape in which the lead 30 is bent toward the semiconductor chip 20 when viewed in cross section, and the side surface shape of the convex portion 36 is a tapered shape in which the semiconductor chip 20 side is narrow. When the lead 30 is viewed from the side opposite to the semiconductor chip 20 side, the side surface is formed with a concave portion having a tapered shape. The solder material 41 that has flowed to the opposite side tends to stay in the vicinity of the through hole 38, and when such a solder material 41 solidifies, it becomes solder having a shape like a screw head (a shape like a conical shape with the semiconductor chip side at the apex). .. Therefore, there is also an effect that the lead 30 and the solder 40 are more difficult to peel off, and the bonding strength between the lead 30 and the solder 40 can be further increased.

また、実施形態1に係る半導体装置1及び半導体装置の製造方法によれば、凸部36の側面形状は、丸みを帯びた形状になっているため、はんだ材41上にリード30(リードフレーム)を配置したときに、余剰なはんだ材が移動し易く、かつ、はんだ材内に空気溜まりができ難い。従って、より信頼性が低下し難い半導体装置を製造することができる。 Further, according to the semiconductor device 1 and the method for manufacturing the semiconductor device according to the first embodiment, since the side surface shape of the convex portion 36 is a rounded shape, the lead 30 (lead frame) is placed on the solder material 41. When the above is placed, the excess solder material is easy to move, and it is difficult for air to accumulate in the solder material. Therefore, it is possible to manufacture a semiconductor device whose reliability is less likely to decrease.

また、実施形態1に係る半導体装置1によれば、実施形態1に係る半導体装置の製造方法によれば、はんだ40の厚さは、300μm以上であるため、半導体チップ20とリード30との間のはんだ40に作用する応力(例えば熱応力)を緩和することができ、はんだ40にクラックが入る等の不具合が生じ難くなる。その結果、信頼性が低下し難い半導体装置を製造することができる。この観点で言えば、上記した不具合をより生じ難くするためには、はんだ40の厚さが400μm以上であることが好ましく、はんだ40の厚さが500μm以上であることがより一層好ましい。 Further, according to the semiconductor device 1 according to the first embodiment, according to the method for manufacturing the semiconductor device according to the first embodiment, the thickness of the solder 40 is 300 μm or more, and therefore, between the semiconductor chip 20 and the lead 30. The stress acting on the solder 40 (for example, thermal stress) can be relaxed, and problems such as cracks in the solder 40 are less likely to occur. As a result, it is possible to manufacture a semiconductor device whose reliability is unlikely to decrease. From this point of view, in order to make the above-mentioned defects less likely to occur, the thickness of the solder 40 is preferably 400 μm or more, and the thickness of the solder 40 is even more preferably 500 μm or more.

実施形態1に係る半導体装置の製造方法によれば、組立体形成工程において、一方の面側に突出した凸部36と、凸部36の頂上部37に形成され、一方の面から一方の面とは反対側の他方の面まで貫通された貫通孔38とを有する電極接続片32を有するリード30を、エミッタ電極24と電極接続片32とがはんだ材41を挟んで対向した状態、かつ、凸部36がエミッタ電極24側に向かって突出した状態となるように配置して組立体50を形成し、接合工程において、はんだ材41を溶融した後で固化することにより、エミッタ電極24と電極接続片32とをはんだ40を介して接合するため、はんだ材41上にリード30を配置したときに、余剰なはんだ材41を貫通孔38を通してリード30における半導体チップ20とは反対側の面に向かって流れさせることができる。従って、はんだ40の厚みをある一定以上の厚さに保つ場合において、接合工程前にはんだ材41上にリード30を配置したときでも、余剰なはんだ材41が所望しない場所にはみ出すことを防ぐことができ、信頼性が低下し難い半導体装置を製造することができる。 According to the method for manufacturing a semiconductor device according to the first embodiment, in the assembly forming step, a convex portion 36 protruding toward one surface side and a top 37 of the convex portion 36 are formed, and one surface is formed from one surface. A lead 30 having an electrode connecting piece 32 having a through hole 38 penetrating to the other surface on the opposite side of the lead 30 is in a state where the emitter electrode 24 and the electrode connecting piece 32 face each other with the solder material 41 in between. The convex portion 36 is arranged so as to protrude toward the emitter electrode 24 side to form the assembly 50, and in the joining step, the solder material 41 is melted and then solidified to form the emitter electrode 24 and the electrode. Since the connection piece 32 is joined via the solder 40, when the lead 30 is arranged on the solder material 41, the surplus solder material 41 is passed through the through hole 38 to the surface of the lead 30 opposite to the semiconductor chip 20. It can flow toward. Therefore, when the thickness of the solder 40 is kept to a certain thickness or more, even when the leads 30 are arranged on the solder material 41 before the joining process, it is possible to prevent the excess solder material 41 from protruding to an undesired place. It is possible to manufacture a semiconductor device whose reliability is unlikely to decrease.

実施形態1に係る半導体装置の製造方法によれば、はんだ材41は、溶剤を含有するペースト状のはんだ材からなり、このようなはんだ材は流動性があるため、はんだ材41上にリード30を配置したときに、余剰なはんだ材41を貫通孔38を通してリード30における半導体チップ20とは反対側の面に向かって流れさせることができる。 According to the method for manufacturing a semiconductor device according to the first embodiment, the solder material 41 is made of a paste-like solder material containing a solvent, and since such a solder material has fluidity, the lead 30 is placed on the solder material 41. When the above is arranged, the surplus solder material 41 can flow through the through hole 38 toward the surface of the lead 30 opposite to the semiconductor chip 20.

[実施形態2]
実施形態2に係る半導体装置の製造方法は、基本的には実施形態1に係る半導体装置の製造方法と同様の工程を有するが、はんだ材を配置する位置が実施形態1に係る半導体装置の製造方法の場合とは異なる。実施形態2に係る半導体装置の製造方法においては、組立体形成工程(リードフレーム配置工程)において、エミッタ電極24と電極接続片32との間にはんだ材41を配置せず、電極接続片32のエミッタ電極24側の面とは反対側の面(凸部が形成されている面とは反対側の面)における、貫通孔38を含む所定の領域にはんだ材42を配置する(図7(a)参照。)。すなわち、電極接続片32のエミッタ電極24側の面とは反対側の面における、貫通孔38を含む所定の領域にはんだ材42を配置されたリード30を、エミッタ電極24と電極接続片32とが所定の間隔で対向した状態、かつ、凸部36がエミッタ電極24側に向かって突出した状態となるように配置して組立体51を形成する。
[Embodiment 2]
The semiconductor device manufacturing method according to the second embodiment basically has the same steps as the semiconductor device manufacturing method according to the first embodiment, but the position where the solder material is arranged is the manufacturing of the semiconductor device according to the first embodiment. Different from the method. In the method for manufacturing a semiconductor device according to the second embodiment, in the assembly forming step (lead frame arranging step), the solder material 41 is not arranged between the emitter electrode 24 and the electrode connecting piece 32, and the electrode connecting piece 32 is used. The solder material 42 is arranged in a predetermined region including the through hole 38 on the surface opposite to the surface on the emitter electrode 24 side (the surface opposite to the surface on which the convex portion is formed) (FIG. 7 (a). )reference.). That is, the lead 30 in which the solder material 42 is arranged in a predetermined region including the through hole 38 on the surface of the electrode connection piece 32 opposite to the surface on the emitter electrode 24 side is connected to the emitter electrode 24 and the electrode connection piece 32. The assembly 51 is formed by arranging the solders so as to face each other at predetermined intervals and the convex portions 36 to protrude toward the emitter electrode 24 side.

組立体形成工程(リードフレーム配置工程)においては、リード30(リードフレーム)のうちの所定の部分(複数の部分が好ましい)を上下から所定の治具で挟持して固定することにより、エミッタ電極24と電極接続片32とが所定の間隔で離間した状態とする。 In the assembly forming step (lead frame arranging step), a predetermined portion (preferably a plurality of portions) of the leads 30 (lead frame) is sandwiched and fixed by a predetermined jig from above and below to fix the emitter electrode. The 24 and the electrode connecting piece 32 are separated from each other at a predetermined interval.

接合工程においては、電極接続片32のエミッタ電極24側の面とは反対側の面における、貫通孔38を含む所定の領域に配置したはんだ材42を溶融して貫通孔38を通してエミッタ電極24と電極接続片32との間に流し込む(図7(b)参照。)。そして、エミッタ電極24と電極接続片32との間にはんだ材41が満たされた段階ではんだ材42を固化する。これにより、エミッタ電極24と電極接続片32とをはんだ40を介して接合することができる。 In the joining step, the solder material 42 arranged in a predetermined region including the through hole 38 on the surface of the electrode connection piece 32 opposite to the surface on the emitter electrode 24 side is melted and passed through the through hole 38 to the emitter electrode 24. It is poured between the electrode connection piece 32 and the electrode connection piece 32 (see FIG. 7B). Then, the solder material 42 is solidified when the solder material 41 is filled between the emitter electrode 24 and the electrode connection piece 32. As a result, the emitter electrode 24 and the electrode connection piece 32 can be joined via the solder 40.

このように、実施形態2に係る半導体装置の製造方法は、はんだ材を配置する位置が実施形態1に係る半導体装置の製造方法の場合とは異なるが、組立体形成工程において、一方の面側に突出した凸部36と、凸部36の頂上部37に形成され、一方の面から一方の面とは反対側の他方の面まで貫通された貫通孔38とを有する電極接続片32を有し、他方の面における、貫通孔38を含む所定の領域にはんだ材42が配置されたリード30を、エミッタ電極24と電極接続片32とが所定の間隔で対向した状態、かつ、凸部36がエミッタ電極24側に向かって突出した状態となるように配置して組立体51を形成し、接合工程において、はんだ材42を溶融して貫通孔38を通してエミッタ電極24と電極接続片32との間にはんだ材42を流し込んだ後ではんだ材42を固化することにより、エミッタ電極24と電極接続片32とをはんだ40を介して接合するため、ある一定以上の厚さの(接合工程前の)はんだ材上にリード30を配置する、ということがなく、余剰なはんだ材が所望しない場所にはみ出すことを防ぐことができる。その結果、信頼性が低下し難い半導体装置を製造することができる。 As described above, in the method for manufacturing the semiconductor device according to the second embodiment, the position where the solder material is arranged is different from the case of the method for manufacturing the semiconductor device according to the first embodiment, but in the assembly forming step, one surface side. It has an electrode connection piece 32 having a convex portion 36 protruding from the surface and a through hole 38 formed in the top portion 37 of the convex portion 36 and penetrating from one surface to the other surface on the opposite side to the other surface. Then, on the other surface, the lead 30 in which the solder material 42 is arranged in a predetermined region including the through hole 38 is in a state where the emitter electrode 24 and the electrode connecting piece 32 face each other at a predetermined interval, and the convex portion 36. Is arranged so as to protrude toward the emitter electrode 24 side to form the assembly 51, and in the joining step, the solder material 42 is melted and passed through the through hole 38 to form the emitter electrode 24 and the electrode connecting piece 32. By solidifying the solder material 42 after pouring the solder material 42 between them, the emitter electrode 24 and the electrode connection piece 32 are joined via the solder 40, so that the thickness is a certain thickness or more (before the joining process). ) The leads 30 are not arranged on the solder material, and it is possible to prevent the excess solder material from protruding to an undesired place. As a result, it is possible to manufacture a semiconductor device whose reliability is unlikely to decrease.

また、実施形態2に係る半導体装置の製造方法によれば、はんだ材42は、ペースト状のはんだ材からなるため、接合工程において、はんだ材が溶融し易く、はんだ材41を溶融したときに、はんだ材42を貫通孔38を通してエミッタ電極24と電極接続片32との間にはんだ材41を流し込ませ易くなる。 Further, according to the method for manufacturing a semiconductor device according to the second embodiment, since the solder material 42 is made of a paste-like solder material, the solder material is easily melted in the joining step, and when the solder material 41 is melted, the solder material 41 is melted. It becomes easy to flow the solder material 41 between the emitter electrode 24 and the electrode connection piece 32 through the through hole 38 through the solder material 42.

また、実施形態2に係る半導体装置の製造方法によれば、組立体形成工程においては、凸部36の側面形状が、半導体チップ20側が狭いテーパ形状であるリード30を配置するため、エミッタ電極24と電極接続片32との間に供給したはんだ材41が貫通孔38から逆流し難く、エミッタ電極24と電極接続片32との間にはんだ材41を効率よく供給することができる。 Further, according to the method for manufacturing a semiconductor device according to the second embodiment, in the assembly forming step, the emitter electrode 24 is arranged because the lead 30 whose side surface shape of the convex portion 36 has a narrow tapered shape on the semiconductor chip 20 side is arranged. The solder material 41 supplied between the and the electrode connection piece 32 is unlikely to flow back from the through hole 38, and the solder material 41 can be efficiently supplied between the emitter electrode 24 and the electrode connection piece 32.

また、実施形態2に係る半導体装置の製造方法によれば、凸部36の側面形状は、丸みを帯びた形状になっているため、はんだ材42が移動し易く、エミッタ電極24と電極接続片32との間にはんだ材41を効率よく供給することができる。 Further, according to the method for manufacturing a semiconductor device according to the second embodiment, since the side surface shape of the convex portion 36 has a rounded shape, the solder material 42 can easily move, and the emitter electrode 24 and the electrode connection piece can be easily moved. The solder material 41 can be efficiently supplied between the 32 and the 32.

なお、実施形態2に係る半導体装置の製造方法は、はんだ材を配置する位置以外の点においては実施形態1に係る半導体装置の製造方法と同様の構成を有するため、実施形態1に係る半導体装置の製造方法が有する効果のうち該当する効果を有する。 Since the semiconductor device manufacturing method according to the second embodiment has the same configuration as the semiconductor device manufacturing method according to the first embodiment except for the position where the solder material is arranged, the semiconductor device according to the first embodiment has the same configuration. It has the corresponding effect among the effects of the manufacturing method of.

[実施形態3]
実施形態3に係る半導体装置の製造方法は、基本的には実施形態2に係る半導体装置の製造方法と同様の工程を有するが、エミッタ電極24と電極接続片32との間にもはんだ材が配置されている点が実施形態2に係る半導体装置の製造方法の場合とは異なる。すなわち、実施形態3に係る半導体装置の製造方法においては、組立体形成工程において、電極接続片32のエミッタ電極24側の面とは反対側の面における、貫通孔38を含む所定の領域だけでなく、エミッタ電極24と電極接続片32の間のうちの一部にもはんだ材43が配置されている(図8(a)及び(b)参照。)。接合工程においては、貫通孔38を通ってエミッタ電極24と電極接続片32の間に供給されたはんだ材と、エミッタ電極24と電極接続片32との間にあらかじめ配置されているはんだ材とが混ざり合ってエミッタ電極24と電極接続片32の間をはんだ材で満たし固化する(図8(c)及び(d)参照。)。
[Embodiment 3]
The method for manufacturing a semiconductor device according to the third embodiment basically has the same steps as the method for manufacturing a semiconductor device according to the second embodiment, but a solder material is also provided between the emitter electrode 24 and the electrode connecting piece 32. The point of arrangement is different from the case of the method for manufacturing the semiconductor device according to the second embodiment. That is, in the method for manufacturing a semiconductor device according to the third embodiment, in the assembly forming step, only a predetermined region including the through hole 38 is formed on the surface of the electrode connection piece 32 opposite to the surface on the emitter electrode 24 side. The solder material 43 is also arranged in a part of the space between the emitter electrode 24 and the electrode connection piece 32 (see FIGS. 8A and 8B). In the joining step, the solder material supplied between the emitter electrode 24 and the electrode connecting piece 32 through the through hole 38 and the solder material previously arranged between the emitter electrode 24 and the electrode connecting piece 32 are formed. The mixture is mixed and the space between the emitter electrode 24 and the electrode connecting piece 32 is filled with a solder material and solidified (see FIGS. 8 (c) and 8 (d)).

このように、実施形態3に係る半導体装置の製造方法は、エミッタ電極24と電極接続片32との間にもはんだ材が配置されている点が実施形態2に係る半導体装置の製造方法の場合とは異なるが、実施形態2に係る半導体装置の製造方法の場合と同様に、組立体形成工程において、一方の面側に突出した凸部36と、凸部36の頂上部37に形成され、一方の面から一方の面とは反対側の他方の面まで貫通された貫通孔38とを有する電極接続片32を有し、他方の面における、貫通孔38を含む所定の領域にはんだ材42が配置されたリード30を、エミッタ電極24と電極接続片32とが所定の間隔で対向した状態、かつ、凸部36がエミッタ電極24側に向かって突出した状態となるように配置して組立体51を形成し、接合工程において、はんだ材42を溶融して貫通孔38を通してエミッタ電極24と電極接続片32との間にはんだ材42を流し込んだ後ではんだ材42を固化することにより、エミッタ電極24と電極接続片32とをはんだ40を介して接合するため、ある一定以上の厚さの(接合工程前の)はんだ材上にリード30を配置する、ということがなく、余剰なはんだ材が所望しない場所にはみ出すことを防ぐことができる。その結果、信頼性が低下し難い半導体装置を製造することができる。 As described above, in the method of manufacturing the semiconductor device according to the third embodiment, the point that the solder material is also arranged between the emitter electrode 24 and the electrode connecting piece 32 is the case of the method of manufacturing the semiconductor device according to the second embodiment. However, as in the case of the method for manufacturing the semiconductor device according to the second embodiment, in the assembly forming step, the convex portion 36 projecting to one surface side and the convex portion 36 are formed on the top 37 of the convex portion 36. The electrode connection piece 32 has an electrode connection piece 32 having a through hole 38 penetrating from one surface to the other surface on the opposite side to the other surface, and the solder material 42 is formed in a predetermined region including the through hole 38 on the other surface. Are arranged so that the emitter electrode 24 and the electrode connection piece 32 face each other at a predetermined interval, and the convex portion 36 projects toward the emitter electrode 24 side. By forming the solid 51, and in the joining process, the solder material 42 is melted, the solder material 42 is poured between the emitter electrode 24 and the electrode connection piece 32 through the through hole 38, and then the solder material 42 is solidified. Since the emitter electrode 24 and the electrode connection piece 32 are joined via the solder 40, the leads 30 are not arranged on the solder material (before the joining process) having a certain thickness or more, and excess solder is used. It is possible to prevent the material from sticking out to an undesired place. As a result, it is possible to manufacture a semiconductor device whose reliability is unlikely to decrease.

また、実施形態3に係る半導体装置の製造方法によれば、組立体形成工程においては、エミッタ電極24と電極接続片32の間のうちの一部にもはんだ材43が配置されているため、エミッタ電極24と電極接続片32の間の空間を短時間ではんだ材で満たすことができ、効率よく半導体装置を製造することができる。 Further, according to the method for manufacturing a semiconductor device according to the third embodiment, in the assembly forming step, the solder material 43 is also arranged in a part of the space between the emitter electrode 24 and the electrode connection piece 32. The space between the emitter electrode 24 and the electrode connecting piece 32 can be filled with the solder material in a short time, and the semiconductor device can be efficiently manufactured.

なお、実施形態3に係る半導体装置の製造方法は、エミッタ電極24と電極接続片32との間にもはんだ材が配置されている点以外の点においては実施形態2に係る半導体装置の製造方法と同様の構成を有するため、実施形態2に係る半導体装置の製造方法が有する効果のうち該当する効果を有する。 The method for manufacturing the semiconductor device according to the third embodiment is the method for manufacturing the semiconductor device according to the second embodiment, except that the solder material is also arranged between the emitter electrode 24 and the electrode connecting piece 32. Since it has the same configuration as that of the above, it has the corresponding effect among the effects of the method for manufacturing the semiconductor device according to the second embodiment.

以上、本発明を上記の実施形態に基づいて説明したが、本発明は上記の実施形態に限定されるものではない。その趣旨を逸脱しない範囲において種々の態様において実施することが可能であり、例えば、次のような変形も可能である。 Although the present invention has been described above based on the above-described embodiment, the present invention is not limited to the above-described embodiment. It can be carried out in various aspects within a range that does not deviate from the purpose, and for example, the following modifications are also possible.

(1)上記実施形態において記載した材質、形状、位置、大きさ等は例示であり、本発明の効果を損なわない範囲において変更することが可能である。 (1) The materials, shapes, positions, sizes, etc. described in the above embodiments are examples, and can be changed as long as the effects of the present invention are not impaired.

(2)上記各実施形態においては、凸部36を、側面が曲線的なテーパ形状を有することとしたが、本発明はこれに限定されるものではない。例えば、凸部を、側面が直線的なテーパ形状を有することとしてもよいし(図9(a)参照。)、凸部を、頂上部に平面部分があり、その一部に貫通孔が形成することとしてもよい(図9(b)参照。)。また、凸部を、リード30をより緩やかに半導体チップ側に曲げた形状としてもよい(図9(c)参照。)。 (2) In each of the above embodiments, the convex portion 36 has a tapered shape whose side surface is curved, but the present invention is not limited to this. For example, the convex portion may have a tapered shape on the side surface (see FIG. 9A), or the convex portion has a flat portion at the top and a through hole is formed in a part thereof. This may be done (see FIG. 9B). Further, the convex portion may have a shape in which the lead 30 is bent more gently toward the semiconductor chip side (see FIG. 9C).

(3)上記各実施形態においては、凸部を、断面で見たときに、リード30が半導体チップ20側に折り曲げられた形状を有する凸部としたが、本発明はこれに限定されるものではない。例えば、貫通孔近傍のリードの厚さを厚くして凸部を形成してもよい(図9(d)参照。)。 (3) In each of the above embodiments, the convex portion is a convex portion having a shape in which the lead 30 is bent toward the semiconductor chip 20 when viewed in cross section, but the present invention is limited thereto. is not it. For example, the thickness of the lead in the vicinity of the through hole may be increased to form a convex portion (see FIG. 9D).

(4)上記各実施形態においては、半導体チップとして、エミッタ電極が複数の電極に分割されている半導体チップを用いてもよい。この場合には、分割された各電極に対応した位置(はんだ材が配置される位置に対応した位置)に凸部及び貫通孔を形成したリードを用いてもよい(変形例5。図10参照。)。 (4) In each of the above embodiments, as the semiconductor chip, a semiconductor chip in which the emitter electrode is divided into a plurality of electrodes may be used. In this case, a lead having a convex portion and a through hole formed at a position corresponding to each of the divided electrodes (a position corresponding to a position where the solder material is arranged) may be used (Modification Example 5, see FIG. 10). .).

(5)上記各実施形態においては、半導体装置として、半導体チップを1つ備える半導体装置としたが、本発明はこれに限定されるものではない。例えば、半導体装置として、半導体チップを2つ備える半導体装置(図11参照。)としてもよいし、半導体チップを3以上備える半導体装置としてもよい。 (5) In each of the above embodiments, the semiconductor device is a semiconductor device including one semiconductor chip, but the present invention is not limited thereto. For example, the semiconductor device may be a semiconductor device having two semiconductor chips (see FIG. 11) or a semiconductor device having three or more semiconductor chips.

半導体チップを2つ備える半導体装置としては、例えば、以下のような、2つの半導体チップをカスコード接続した半導体装置(変形例6における半導体装置2、図11参照。)が考えられる。変形例6における半導体装置2においては、半導体チップ20fのエミッタ電極24fはリード30fと電気的に接続され、半導体チップ20fのコレクタ電極22fは、基板10fの回路16fを介してリード30gと接続されるとともに、半導体チップ20gのエミッタ電極24gとリード30gを介して電気的に接続され、図示されていないが半導体チップ20gのコレクタ電極22gは回路16gを介してリード66と接続されている。このような構成の半導体装置においても、リード30f,30gに凸部及び貫通孔を形成してもよい。 As a semiconductor device including two semiconductor chips, for example, the following semiconductor device in which two semiconductor chips are cascode-connected (semiconductor device 2 in Modification 6, see FIG. 11) can be considered. In the semiconductor device 2 of the sixth modification, the emitter electrode 24f of the semiconductor chip 20f is electrically connected to the lead 30f, and the collector electrode 22f of the semiconductor chip 20f is connected to the lead 30g via the circuit 16f of the substrate 10f. At the same time, the emitter electrode 24g of the semiconductor chip 20g is electrically connected via the lead 30g, and the collector electrode 22g of the semiconductor chip 20g is connected to the lead 66 via the circuit 16g, although not shown. Even in a semiconductor device having such a configuration, convex portions and through holes may be formed in the leads 30f and 30g.

(6)上記各実施形態においては、凸部及び貫通孔が1つのリードを用いたが、本発明はこれに限定されるものではない。凸部及び貫通孔が2つ以上のリードを用いてもよい。 (6) In each of the above embodiments, a lead having one convex portion and one through hole is used, but the present invention is not limited thereto. Leads having two or more protrusions and through holes may be used.

(7)上記各実施形態においては、半導体チップ20を3端子のIGBTとしたが、本発明はこれに限定されるものではない。半導体チップ20を他の3端子の半導体素子(例えば、MOSFET)としてよいし、半導体チップ20を2端子の半導体素子(例えば、ダイオード)としてよいし、半導体チップ20を4端子以上の半導体素子(4端子としては、例えばサイリスタ)としてもよい。 (7) In each of the above embodiments, the semiconductor chip 20 is a 3-terminal IGBT, but the present invention is not limited thereto. The semiconductor chip 20 may be another three-terminal semiconductor element (for example, MOSFET), the semiconductor chip 20 may be a two-terminal semiconductor element (for example, a diode), and the semiconductor chip 20 may be a semiconductor element with four or more terminals (4). The terminal may be, for example, a thyristor).

(8)上記各実施形態において、半導体装置を、半導体チップの一方の面にコレクタ電極を有し、他方の面にエミッタ電極及びゲート電極を有する、いわゆる縦型の半導体装置としたが、本発明はこれに限定されるものではない。例えば、半導体装置を、基板側とは反対側の面に全ての電極を有する、いわゆる横型半導体装置としてもよい。 (8) In each of the above embodiments, the semiconductor device is a so-called vertical semiconductor device having a collector electrode on one surface of the semiconductor chip and an emitter electrode and a gate electrode on the other surface. Is not limited to this. For example, the semiconductor device may be a so-called horizontal semiconductor device having all electrodes on the surface opposite to the substrate side.

1…半導体装置、10,10a,10b…基板、12,12a,12b…チップ配置面、14,14a,14b…絶縁性基板、16,16a,16b…回路、18、18a,18b…放熱用の金属板、20,20a,20b…チップ、22,22a,22b…コレクタ電極、24,24a,24b…エミッタ電極(電極)、26…ゲート電極、30,30a,30b,30c,30d,30e,30f,30g,62,64,66…リード、32,32a,32b,32c,32d,32e,32f,32g,…電極接続片、34…外部接続端子、36,36a,36b,36c,36d,36f,36g…凸部、37,37a,37b,37c,37d,36f,36g…凸部の頂上部、38,38a,38b,38c,38d,38f,38g…貫通孔、40,46…はんだ、41,42,43,45…はんだ材、50,51,52…組立体、70…ワイヤ、80…樹脂 1 ... Semiconductor device, 10, 10a, 10b ... Substrate, 12, 12a, 12b ... Chip arrangement surface, 14, 14a, 14b ... Insulating substrate, 16, 16a, 16b ... Circuit, 18, 18a, 18b ... For heat dissipation Metal plate, 20, 20a, 20b ... Chip, 22, 22a, 22b ... Collector electrode, 24, 24a, 24b ... Emitter electrode (electrode), 26 ... Gate electrode, 30, 30a, 30b, 30c, 30d, 30e, 30f , 30g, 62, 64, 66 ... Leads, 32, 32a, 32b, 32c, 32d, 32e, 32f, 32g, ... Electrode connection pieces, 34 ... External connection terminals, 36, 36a, 36b, 36c, 36d, 36f, 36g ... Convex, 37, 37a, 37b, 37c, 37d, 36f, 36g ... Top of convex, 38, 38a, 38b, 38c, 38d, 38f, 38g ... Through hole, 40, 46 ... Solder, 41, 42, 43, 45 ... Solder material, 50, 51, 52 ... Assembly, 70 ... Wire, 80 ... Resin

Claims (1)

基板の半導体チップ配置面上に、前記半導体チップ配置面と対向する面とは反対側の面に形成された電極を有する半導体チップを配置する半導体チップ配置工程と、
前記半導体チップ側の面から前記半導体チップ側とは反対側の面まで貫通された貫通孔と、前記貫通孔の周囲の部分を前記半導体チップ側に曲線状に折り曲げた形状の凸部と、前記凸部に対応して前記半導体チップ側とは反対側の面に形成された凹部とを有する電極接合部を有し、前記電極接合部の前記半導体チップとは反対側の面にはんだ材が配置されたリード端子を、前記半導体チップの前記電極と前記電極接合部とが所定の間隔を置いて対向した状態、かつ、前記凸部が前記電極側に向かって突出した状態となるように配置して組立体を形成する組立体形成工程と、
前記はんだ材を溶融して前記貫通孔を通して前記電極と前記電極接合部との間に前記はんだ材を流し込んだ後で前記はんだ材を固化することにより、前記電極と前記電極接合部とを前記はんだ材を介して接合し、前記はんだ材を前記凸部に接合するとともに前記凸部の周囲の前記電極接合部及び前記凸部から離れた前記電極接合部に接合する接合工程とを含み、
前記組立体形成工程においては、前記電極と前記電極接合部の間のうちの一部にもはんだ材が配置されていることを特徴とする半導体装置の製造方法。
A semiconductor chip arranging step of arranging a semiconductor chip having electrodes formed on a surface opposite to the surface facing the semiconductor chip arranging surface on the semiconductor chip arranging surface of the substrate.
A through hole penetrating from a surface on the semiconductor chip side to a surface on the side opposite to the semiconductor chip side, a convex portion having a shape in which a portion around the through hole is bent toward the semiconductor chip side in a curved shape, and the above. It has an electrode joint having a concave portion formed on the surface opposite to the semiconductor chip side corresponding to the convex portion, and the solder material is arranged on the surface of the electrode joint portion opposite to the semiconductor chip. The lead terminals are arranged so that the electrodes of the semiconductor chip and the electrode joints face each other at a predetermined distance, and the convex portions project toward the electrodes. Assembly forming process to form the assembly
By melting the solder material, pouring the solder material between the electrode and the electrode joint portion through the through hole, and then solidifying the solder material, the electrode and the electrode joint portion are soldered. joined through the wood, saw including a bonding step of bonding the solder material to the electrode junction remote from the electrode bonded part and the convex portions of the periphery of the convex portion as well as joined to the convex portion,
A method for manufacturing a semiconductor device, characterized in that, in the assembly forming step, a solder material is also arranged in a part of the space between the electrode and the electrode joint.
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