JP6940762B2 - Semiconductor devices and their manufacturing methods - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the same.

Nitride semiconductors have features such as high saturated electron velocities and wide band gaps. Therefore, various studies have been conducted on applying a nitride semiconductor to a semiconductor device having a high withstand voltage and a high output by utilizing these characteristics. As a semiconductor device using a nitride semiconductor, many reports have been made on field effect transistors, particularly high electron mobility transistors (HEMTs). As a HEMT using a nitride semiconductor, a HEMT using GaN as a channel layer and AlGaN as a barrier layer is known. In this HEMT, strain due to the difference in lattice constant between AlGaN and GaN is generated in AlGaN, and the piezo polarization generated by this strain obtains a high-concentration two-dimensional electron gas.

In recent years, a transistor having a quantum confinement structure in which an AlN barrier layer having a thickness of a critical film thickness or less is provided on a GaN layer and a GaN channel layer and an AlN cap layer are provided on the AlN barrier layer is also known. Metal-organic vapor phase epitaxy (MOVPE method) is suitable for mass production of transistors with a quantum confined structure.

However, when the barrier layer and the channel layer are formed by the MOVPE method, sufficient electron mobility cannot be obtained.

Japanese Unexamined Patent Publication No. 2013-118383 Japanese Unexamined Patent Publication No. 2006-310644

An object of the present invention is to provide a semiconductor device capable of improving electron mobility in a quantum confinement structure and a method for manufacturing the same.

In one aspect of the semiconductor device, an AlN underlayer, an AlN barrier layer on the N polar surface of the underlayer, a GaN channel layer on the barrier layer, and an AlGaN cap layer on the channel layer. , _{A back barrier layer of In a} Al _b Ga _1-ab N (0 ≦ a ≦ 0.05, 0.60 ≦ b <1.00) between the base layer and the barrier layer is included. ..

In one aspect of the method for manufacturing a semiconductor device , In _a Al _b Ga _1-ab N (0 ≦ a ≦ 0.05, 0.60 ≦ b <1.00) is formed on the N polar surface of the base layer of AlN. A back barrier layer is formed, an AlN barrier layer is formed on the back barrier layer, a GaN channel layer is formed on the barrier layer, and an AlGaN cap layer is formed on the channel layer.

According to the above-mentioned semiconductor device or the like, since an appropriate base layer and barrier layer are included, the mobility of electrons can be improved in the quantum confinement structure.

It is a figure which shows the reference example. It is a figure which shows the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment in process order. Following FIG. 4A, it is a cross-sectional view showing a manufacturing method of a semiconductor device in the order of processes. Following FIG. 4B, it is a cross-sectional view which shows the manufacturing method of a semiconductor device in process order. It is a figure which shows the semiconductor device which concerns on 3rd Embodiment. It is a figure which shows the semiconductor device which concerns on 4th Embodiment. It is a figure which shows the semiconductor device which concerns on 5th Embodiment. It is a figure which shows the semiconductor device which concerns on 6th Embodiment. It is a figure which shows the semiconductor device which concerns on 7th Embodiment. It is a figure which shows the semiconductor device which concerns on 8th Embodiment. It is a figure which shows the semiconductor device which concerns on 9th Embodiment. It is a figure which shows the discrete package which concerns on 10th Embodiment. It is a wiring diagram which shows the PFC circuit which concerns on 11th Embodiment. It is a wiring diagram which shows the power supply device which concerns on 12th Embodiment. It is a wiring diagram which shows the amplifier which concerns on 12th Embodiment.

The inventors of the present application examined the reference example shown in FIG. 1 in order to clarify the characteristics of a transistor having a conventional quantum confinement structure. FIG. 1A is a cross-sectional view of a reference example, and FIG. 1B is a band diagram of the reference example.

As shown in FIG. 1A, the semiconductor device 10 of the reference example includes a GaN buffer layer 1, an AlN barrier layer 2 on the N-polar plane of the buffer layer 1, and a GaN channel on the barrier layer 2. A layer 3 and an AlN cap layer 4 on the channel layer 3 are included. In the semiconductor device 10, since the barrier layer 2 is on the N-polar plane of the buffer layer 1, two-dimensional electron gas (2DEG) 5 is generated in the vicinity of the interface of the channel layer 3 with the barrier layer 2.

When the barrier layer 2, the channel layer 3 and the cap layer 4 are formed by the MOVPE method in the manufacture of the semiconductor device 10, the barrier layer 2 of AlN takes in Ga atoms from the buffer layer 1 of GaN, and the cap layer 4 of AlN is made of GaN. Ga atoms are taken in from the channel layer 3. As a result, as shown in FIG. 1 (b), the valence band Ec of the barrier layer 2 is lowered, and the band offset with the channel layer 3 is lowered. Therefore, a sufficient quantum confinement effect cannot be obtained, and a sufficient mobility cannot be obtained.

Further, since the difference in lattice constant between AlN and GaN is large, the critical film thickness of the barrier layer 2 is very small, and if the barrier layer 2 is formed thick, defects are likely to occur in the barrier layer 2. In this respect as well, a sufficient quantum confinement effect cannot be obtained, and sufficient mobility cannot be obtained.

As a result of diligent studies based on these findings, the present inventors have come up with the following embodiments.

Hereinafter, embodiments will be specifically described with reference to the accompanying drawings.

(First Embodiment)
First, the first embodiment will be described. FIG. 2 is a diagram showing a semiconductor device according to the first embodiment.

As shown in FIG. 2A, the semiconductor device 100 according to the first embodiment includes an AlN base layer 101, an AlN barrier layer 102 on the N polar surface of the base layer 101, and a barrier layer 102. The GaN channel layer 103 and the AlGaN cap layer 104 on the channel layer 103 are included. The composition of the cap layer 104 may be AlN.

In the semiconductor device 100, since the barrier layer 102 is on the N-polar plane of the base layer 101, compression strain occurs in the channel layer 103, and the two-dimensional electron gas (2DEG) 105 near the interface of the channel layer 103 with the barrier layer 102. Occurs. Even if the barrier layer 102 is formed by the MOVPE method, the barrier layer 102 does not take in Ga atoms from the base layer 101 of AlN. Therefore, the valence band Ec and the band offset do not decrease due to the uptake of Ga atoms, and as shown in FIG. 2B, the band offset between the channel layer 103 and the barrier layer 102 is large, and the electrons Is tightly confined in the channel layer 103. When the cap layer 104 is formed by the MOVPE method, the cap layer 104 may take in Ga atoms from the channel layer 103, and the band offset with the channel layer 103 may decrease. However, the barrier to 2DEG 105 is high because the spontaneous polarization difference between the cap layer 104 and the channel layer 103 is large and the band is pushed up by the piezo polarization of the channel layer 103. Further, since the barrier layer 102 of AlN is formed on the base layer 101 of AlN, the barrier layer 102 can be formed thicker than the barrier layer 2 of the reference example. Due to these factors, in the first embodiment, excellent electron mobility can be obtained.

(Second Embodiment)
Next, the second embodiment will be described. The second embodiment relates to an example of a HEMT including a compound semiconductor epitaxial substrate. FIG. 3 is a diagram showing a semiconductor device according to the second embodiment.

As shown in FIG. 3, the semiconductor device 200 according to the second embodiment includes an AlN substrate 201, an AlN barrier layer 202 on the N polar surface of the substrate 201, and a GaN channel layer 203 on the barrier layer 202. And the AlN cap layer 204 on the channel layer 203 is included.

The thickness of the barrier layer 202 is 5 nm to 15 nm, for example, about 10 nm, the thickness of the channel layer 203 is about 2 nm to 20 nm, for example, about 10 nm, and the thickness of the cap layer 204 is about 2 nm to 10 nm, for example, about 5 nm. .. The cap layer 204 may take in Ga atoms from the channel layer 203 and contain Ga. In this case, the composition of the cap layer 204 changes in the thickness direction, that is, the closer to the channel layer 203, the lower the Al composition. The overall Al composition of the cap layer 204 is generally in the range of 0.30 or more and less than 1.00. In order to obtain a particularly excellent quantum confinement effect, the thickness of the channel layer 203 is preferably 20 nm or less.

The element separation region 211 that defines the element region is formed on the laminated body of the substrate 201, the barrier layer 202, the channel layer 203, and the cap layer 204. In the element region, the opening 212 for the source and the opening 213 for the drain are formed in the cap layer 204, the source electrode 221 is formed in the opening 212, and the drain electrode 222 is formed in the opening 213. Has been done. A passivation film 224 covering the source electrode 221 and the drain electrode 222 is formed on the cap layer 204. The thickness of the passivation film 224 is 2 nm to 500 nm, for example, about 100 nm. The material of the passivation film 224 is, for example, an oxide, nitride or oxynitride of Si, Al, Hf, Zr, Ti, Ta or W, preferably silicon nitride. An opening 214 for a gate is formed in the passivation film 224 between the source electrode 221 and the drain electrode 222. The semiconductor device 200 includes a gate electrode 223 that contacts the cap layer 204 through the opening 214. The source electrode 221 and the drain electrode 222 include, for example, a Ta film and an Al film on the Ta film, and are in ohmic contact with the channel layer 203. The gate electrode 223 includes, for example, a Ni film and an Au film on the Ni film, and is in Schottky contact with the cap layer 204. As described above, the semiconductor device 200 includes a source electrode 221 above the channel layer 203, a drain electrode 222, and a gate electrode 223.

In the second embodiment, the substrate 201, the barrier layer 202, the channel layer 203, and the cap layer 204 are included in the compound semiconductor epitaxial substrate. The substrate 201 is an example of the base layer of AlN.

Next, a method of manufacturing the semiconductor device according to the second embodiment will be described. 4A to 4C are cross-sectional views showing the manufacturing method of the semiconductor device according to the second embodiment in the order of processes.

First, as shown in FIG. 4A (a), the barrier layer 202, the channel layer 203, and the cap layer 204 are formed on the substrate 201. The barrier layer 202, the channel layer 203, and the cap layer 204 can be formed by a crystal growth method such as the MOVPE method or the molecular beam epitaxy (MBE) method. When formed by the MOVPE method, for example, a mixed gas of trimethylaluminum (TMAl) gas, trimethylgallium (TMGa) gas, trimethylindium (TMIn) gas and ammonia (NH ₃ ) gas is used as a raw material gas, and nitrogen (TH3) is used as a carrier gas. N ₂ ) gas or hydrogen (H ₂ ) gas is used. Depending on the compound semiconductor layer to be formed, the presence or absence of supply of TMAl gas, TMGa gas and TMIn gas and the flow rate are appropriately set. For example, the growth pressure is about 1 kPa to 100 kPa, and the growth temperature is about 700 ° C. to 1500 ° C.

Next, as shown in FIG. 4A (b), an element separation region 211 that defines the element region is formed in a partial laminate of the cap layer 204, the channel layer 203, the barrier layer 202, and the substrate 201. In the formation of the element separation region 211, for example, a photoresist pattern that exposes the region where the element separation region 211 is to be formed is formed on the cap layer 204, and ion implantation of Ar or the like is performed using this pattern as a mask. Dry etching using a chlorine-based gas may be performed using this pattern as an etching mask.

Then, in the element region, openings 212 and 213 are formed in the cap layer 204 as shown in FIG. 4A (c). In the formation of the openings 212 and 213, for example, dry etching using a chlorine-based gas is performed.

Subsequently, as shown in FIG. 4B (d), the source electrode 221 is formed in the opening 212, and the drain electrode 222 is formed in the opening 213. The source electrode 221 and the drain electrode 222 can be formed by, for example, a lift-off method. That is, the region where the source electrode 221 is to be formed and the region where the drain electrode 222 is to be formed are exposed to form a photoresist pattern covering the other regions, and a metal film is formed by a vapor deposition method using this pattern as a growth mask. It forms and removes this pattern along with the metal film on it. In the formation of the metal film, for example, a Ta film having a thickness of 10 nm to 30 nm, for example, about 20 nm is formed, and an Al film having a thickness of 180 nm to 220 nm, for example, about 200 nm is formed on the Ta film. Then, for example, heat treatment such as rapid thermal annealing (RTA) is performed at 400 ° C. to 1000 ° C. (for example, 550 ° C.) in _{an N 2 gas atmosphere to obtain ohmic contact.}

Then, as shown in FIG. 4B (e), a passivation film 224 covering the source electrodes 221 and 222 electrodes 107 is formed on the cap layer 104. The passivation film 224 can be formed by, for example, a plasma enhanced chemical vapor deposition (PECVD) method, an atomic layer deposition (ALD) method, or a sputtering method. When forming a silicon nitride film as the passivation film 224, the plasma CVD method is preferable.

Subsequently, as shown in FIG. 4C (f), an opening 214 is formed in the passivation film 224. When forming the opening 214, a resist pattern that exposes the region where the opening 214 is to be formed is formed on the passivation film 224, and the passivation film 224 is etched. As the etching, for example, dry etching using a fluorine-based gas or a chlorine-based gas or wet etching using a fluoroacid or a buffered fluoroacid is performed.

Next, as shown in FIG. 4C (g), a gate electrode 223 in contact with the cap layer 204 through the opening 214 is formed on the passivation film 224. The gate electrode 223 can be formed by, for example, a lift-off method. That is, a pattern of a photoresist that exposes a region where the gate electrode 223 is to be formed is formed, a metal film is formed by a vapor deposition method using this pattern as a growth mask, and this pattern is removed together with the metal film on the pattern. In the formation of the metal film, for example, a Ni film having a thickness of 20 nm to 40 nm, for example, about 30 nm is formed, and then an Au film having a thickness of 350 nm to 450 nm, for example, about 400 nm is formed.

Then, if necessary, a protective film, wiring, and the like are formed to complete the semiconductor device.

In the second embodiment, since the barrier layer 202 is on the N-polar plane of the substrate 201, compression strain is generated in the channel layer 203, and 2DEG is generated in the vicinity of the interface of the channel layer 203 with the barrier layer 202. Even if the barrier layer 202 is formed by the MOVPE method, the barrier layer 202 does not take in Ga atoms from the AlN substrate 201. Therefore, the band offset does not decrease due to the uptake of Ga atoms, the band offset between the channel layer 203 and the barrier layer 202 is large, and electrons are strongly confined in the channel layer 203. When the cap layer 204 is formed by the MOVPE method, the cap layer 204 may take in Ga atoms from the channel layer 203, and the band offset with the channel layer 203 may decrease. However, since the spontaneous polarization difference between the cap layer 204 and the channel layer 203 is large and the band is pushed up by the piezo polarization of the channel layer 203, the barrier to 2DEG is high. Further, since the barrier layer 202 of AlN is formed on the substrate 201 of AlN, even if the barrier layer 202 is formed thicker than the barrier layer 2 of the reference example, defects are less likely to occur in the barrier layer 2 and the channel layer 203 is formed. Can cause compression distortion. Due to these factors, excellent electron mobility can be obtained even in the second embodiment.

(Third Embodiment)
Next, a third embodiment will be described. The third embodiment relates to an example of a HEMT including a compound semiconductor epitaxial substrate. FIG. 5 is a diagram showing a semiconductor device according to the third embodiment.

As shown in FIG. 5, the semiconductor device 300 according to the third embodiment includes an AlGaN cap layer 304 instead of the AlN cap layer 204. The composition of the cap layer 304 is represented by, for example, Al _y Ga _1-y N (0.30 ≦ y <1.00), and the thickness of the cap layer 304 is 2 nm to 10 nm, for example, about 5 nm. The cap layer 304 is, for example, an Al _0.5 Ga _0.5 N layer. Other configurations are the same as in the second embodiment.

When manufacturing the semiconductor device 300 according to the third embodiment, the AlGaN cap layer 304 is formed in place of the AlN cap layer 204. That is, the cap layer 304 is formed while supplying the raw material gas (TMGa gas) of Ga. By forming the cap layer 304 while supplying the raw material gas of Ga, the uptake of Ga atoms from the channel layer 203 is controlled, and the composition of the cap layer 304 is unlikely to change in the thickness direction. Therefore, it is easy to obtain stable characteristics as compared with the second embodiment.

(Fourth Embodiment)
Next, a fourth embodiment will be described. A fourth embodiment relates to an example of a HEMT including a compound semiconductor epitaxial substrate. FIG. 6 is a diagram showing a semiconductor device according to the fourth embodiment.

As shown in FIG. 6A, the semiconductor device 400 according to the fourth embodiment includes a cap layer 404 instead of the AlN cap layer 204. The cap layer 404 includes a first AlGaN layer 404a on the channel layer 203 and a second AlGaN layer 404b on the first layer 404a, and the Al composition of the layer 404a is lower than the Al composition of the layer 404b. .. For example, the composition of layer 404a is Al _0.2 Ga _0.8 N, and the composition of layer 404b is Al _0.8 Ga _0.2 N. The thickness of the layers 404a and 404b is 1 nm to 5 nm, for example, about 2 nm. The overall composition of the cap layer 404 is represented by, for example, Al _y Ga _1-y N (0.30 ≦ y <1.00). Other configurations are the same as in the second embodiment.

In a fourth embodiment, layer 404a can function as a subchannel, as shown in FIG. 6 (b). That is, when the drain voltage becomes high, the electrons move from the channel layer 203 to the layer 404a, so that the operation can be performed up to a higher voltage. Therefore, an excellent pressure resistance can be obtained as compared with the second embodiment.

As long as the Al composition is higher as it is closer to the upper surface, the number of layers contained in the cap layer 404 may be 3 or more. The Al composition may change continuously rather than stepwise.

(Fifth Embodiment)
Next, a fifth embodiment will be described. A fifth embodiment relates to an example of a HEMT including a compound semiconductor epitaxial substrate. FIG. 7 is a diagram showing a semiconductor device according to the fifth embodiment.

As shown in FIG. 7, the semiconductor device 500 according to the fifth embodiment includes a back barrier layer 506 between the substrate 201 and the barrier layer 202 in the thickness direction. The composition of the back barrier layer 506 is represented by In _a Al _b Ga _1-ab N (0 ≦ a ≦ 0.05, 0.60 ≦ b <1.00), and the thickness of the back barrier layer 506 is from 1 nm to 1 nm. It is about 5 nm, for example, about 2 nm. Further, the semiconductor device 500 includes an AlN barrier layer 502 containing an n-type impurity instead of the barrier layer 202. The thickness of the barrier layer 502 is 5 nm to 15 nm, for example, about 10 nm. The barrier layer 502 contains, for example, Si as an n-type impurity of about 3 × 10 ¹⁸ cm ^{-3 to} 7 × 10 ¹⁸ cm ^-3 , for example, about ^{5 × 10 18} cm ^-3. The back barrier layer 506 is, for example, an Al _0.8 Ga _0.2 N layer. Other configurations are the same as in the second embodiment.

In the fifth embodiment, there is a spontaneous polarization difference between the back barrier layer 506 and the barrier layer 502, compression strain is generated in the back barrier layer 506, and these spontaneous polarization differences and the piezo polarization cause FIG. 7 ( As shown in b), the band of the barrier layer 202 is pushed up. Therefore, the electrons are more strongly confined in the channel layer 203, and better electron mobility can be obtained. Further, since the back barrier layer 506 is provided between the barrier layer 502 and the substrate 201, the carrier concentration is improved by the n-type impurities contained in the barrier layer 502.

Although the back barrier layer 506 contains Ga, the Ga composition is low, so even if the barrier layer 502 takes in Ga, the effect on the band offset is negligible.

The n-type impurity contained in the barrier layer 502 may be Ge or Sn. Instead of the barrier layer 502, a barrier layer 202 in which impurities are not intentionally introduced may be used. However, it is preferable to use the barrier layer 502 containing n-type impurities because 2DEG can be generated at a high density by the interaction with the back barrier layer 506. In the first to fourth embodiments, a barrier layer 502 containing an n-type impurity may be used instead of the barrier layer 202.

(6th to 9th embodiments)
Next, the sixth to ninth embodiments will be described. Sixth to ninth embodiments relate to an example of a HEMT including a compound semiconductor epitaxial substrate. 8 to 11 are diagrams showing semiconductor devices according to the sixth to ninth embodiments, respectively.

As shown in FIG. 8, the passivation film 224 included in the semiconductor device 600 according to the sixth embodiment does not have an opening 214, and the gate electrode 223 is formed on the passivation film 224. Other configurations are the same as in the second embodiment. That is, while the second embodiment has a Schottky type gate structure, the sixth embodiment has a MIS type gate structure. The same effect as that of the second embodiment can be obtained by the sixth embodiment.

As shown in FIG. 9, the passivation film 224 included in the semiconductor device 700 according to the seventh embodiment does not have an opening 214, and the gate electrode 223 is formed on the passivation film 224. Other configurations are the same as in the third embodiment. That is, while the third embodiment has a Schottky type gate structure, the seventh embodiment has a MIS type gate structure. The same effect as that of the third embodiment can be obtained by the seventh embodiment.

As shown in FIG. 10, the passivation film 224 included in the semiconductor device 800 according to the eighth embodiment does not have an opening 214, and the gate electrode 223 is formed on the passivation film 224. Other configurations are the same as in the fourth embodiment. That is, while the fourth embodiment has a Schottky type gate structure, the eighth embodiment has a MIS type gate structure. The same effect as that of the fourth embodiment can be obtained by the eighth embodiment.

As shown in FIG. 11, the passivation film 224 included in the semiconductor device 900 according to the ninth embodiment does not have an opening 214, and the gate electrode 223 is formed on the passivation film 224. Other configurations are the same as in the fifth embodiment. That is, the fifth embodiment has a Schottky type gate structure, whereas the ninth embodiment has a MIS type gate structure. The same effect as that of the fifth embodiment can be obtained by the ninth embodiment.

(10th Embodiment)
Next, a tenth embodiment will be described. A tenth embodiment relates to a discrete package of HEMTs. FIG. 12 is a diagram showing a discrete package according to the tenth embodiment.

In the tenth embodiment, as shown in FIG. 12, the back surface of the HEMT HEMT chip 1210 according to any one of the second to ninth embodiments is attached to a land (die pad) 1233 using a die-attaching agent 1234 such as solder. It is fixed. Further, a wire 1235d such as an Al wire is connected to the drain pad 1226d connected to the drain electrode 222, and the other end of the wire 1235d is connected to the drain lead 1232d integrated with the land 1233. A wire 1235s such as an Al wire is connected to a source pad 1226s connected to the source electrode 221 and the other end of the wire 1235s is connected to a source lead 1232s independent of the land 1233. A wire 1235 g such as an Al wire is connected to a gate pad 1226 g connected to the gate electrode 223, and the other end of the wire 1235 g is connected to a gate lead 1232 g independent of the land 1233. Then, the land 1233, the HEMT chip 1210, and the like are packaged with the mold resin 1231 so that a part of the gate lead 1232g, a part of the drain lead 1232d, and a part of the source lead 1232s protrude.

Such a discrete package can be manufactured, for example, as follows. First, the HEMT chip 1210 is fixed to the land 1233 of the lead frame using a die-attaching agent 1234 such as solder. Next, the gate pad 1226g is connected to the gate lead 1232g of the lead frame, the drain pad 1226d is connected to the drain lead 1232d of the lead frame, and the source pad 1226s is connected to the source of the lead frame by bonding using the wires 1235g, 1235d and 1235s. Connect to lead 1232s. Then, sealing is performed using the mold resin 1231 by the transfer molding method. Then, the lead frame is separated.

(11th Embodiment)
Next, the eleventh embodiment will be described. The eleventh embodiment relates to a PFC (Power Factor Correction) circuit including HEMT. FIG. 13 is a wiring diagram showing the PFC circuit according to the eleventh embodiment.

The PFC circuit 1250 is provided with a switch element (transistor) 1251, a diode 1252, a choke coil 1253, capacitors 1254 and 1255, a diode bridge 1256, and an alternating current power supply (AC) 1257. Then, the drain electrode of the switch element 1251 and the anode terminal of the diode 1252 and one terminal of the choke coil 1253 are connected. The source electrode of the switch element 1251 is connected to one terminal of the capacitor 1254 and one terminal of the capacitor 1255. The other terminal of the capacitor 1254 and the other terminal of the choke coil 1253 are connected. The other terminal of the capacitor 1255 and the cathode terminal of the diode 1252 are connected. A gate driver is connected to the gate electrode of the switch element 1251. AC1257 is connected between both terminals of the capacitor 1254 via a diode bridge 1256. A direct current (DC) is connected between both terminals of the capacitor 1255. Then, in this embodiment, the HEMT of any of the second to ninth embodiments is used for the switch element 1251.

In manufacturing the PFC circuit 1250, for example, the switch element 1251 is connected to the diode 1252, the choke coil 1253, etc. by using solder or the like.

(12th Embodiment)
Next, a twelfth embodiment will be described. A twelfth embodiment relates to a power supply device including a HEMT. FIG. 14 is a wiring diagram showing a power supply device according to the twelfth embodiment.

The power supply device is provided with a high-voltage primary circuit 1261 and a low-voltage secondary circuit 1262, and a transformer 1263 disposed between the primary circuit 1261 and the secondary circuit 1262.

The primary side circuit 1261 is provided with an inverter circuit connected between both terminals of the PFC circuit 1250 and the capacitor 1255 of the PFC circuit 1250 according to the eleventh embodiment, for example, a full bridge inverter circuit 1260. The full bridge inverter circuit 1260 is provided with a plurality of (four in this case) switch elements 1264a, 1264b, 1264c, and 1264d.

The secondary circuit 1262 is provided with a plurality of (three in this case) switch elements 1265a, 1265b, and 1265c.

In the present embodiment, the switch element 1251 of the PFC circuit 1250 constituting the primary side circuit 1261 and the switch elements 1264a, 1264b, 1264c and 1264d of the full bridge inverter circuit 1260 are subjected to any one of the second to ninth embodiments. HEMT is used. On the other hand, ordinary MIS type FETs (field effect transistors) using silicon are used for the switch elements 1265a, 1265b and 1265c of the secondary side circuit 1262.

(13th Embodiment)
Next, the thirteenth embodiment will be described. A thirteenth embodiment relates to an amplifier with a HEMT. FIG. 15 is a wiring diagram showing the amplifier according to the thirteenth embodiment.

The amplifier is provided with a digital predistortion circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273.

The digital predistortion circuit 1271 compensates for the non-linear distortion of the input signal. The mixer 1272a mixes the input signal and the AC signal in which the non-linear distortion is compensated. The power amplifier 1273 includes a HEMT according to any of the second to ninth embodiments, and amplifies an AC signal and a mixed input signal. In the present embodiment, for example, the output side signal can be mixed with the AC signal by the mixer 1272b and sent to the digital predistortion circuit 1271 by switching the switch. This amplifier can be used as a high frequency amplifier and a high output amplifier.

The type of the substrate is not particularly limited as long as an AlN base layer having an N-polar surface on the upper surface can be obtained. When a SiC substrate is used, by forming an AlN layer on the C-polar surface of the SiC substrate, a base layer having an N-polar surface on the upper surface can be obtained. When a sapphire substrate is used, the surface of the sapphire substrate is nitrided with ammonia and an AlN layer is formed on the nitrided surface to obtain a base layer having an N-polar surface on the upper surface.

The structures of the gate electrode, the source electrode and the drain electrode are not limited to those of the above-described embodiment. For example, these may be composed of a single layer. Further, these forming methods are not limited to the lift-off method. The gate electrode may contain Pd and / or Pt in addition to Ni and Au.

Hereinafter, various aspects of the present invention will be collectively described as appendices.

(Appendix 1)
The base layer of AlN and
The AlN barrier layer on the N-polar surface of the base layer and
The GaN channel layer on the barrier layer and
The AlGaN cap layer on the channel layer and
A semiconductor device characterized by having.

(Appendix 2)
The semiconductor device according to Appendix 1, further comprising a source electrode, a drain electrode, and a gate electrode above the channel layer.

(Appendix 3)
The semiconductor device according to Appendix 1 or 2, wherein the base layer is an AlN substrate.

(Appendix 4)
The semiconductor device according to any one of Supplementary note 1 to 3, wherein the thickness of the channel layer is 20 nm or less.

(Appendix 5)
The semiconductor device according to any one of Supplementary note 1 to 4, wherein the Al composition of the cap layer becomes higher as the distance from the channel layer increases.

(Appendix 6)
The semiconductor device according to any one of Supplementary note 1 to 5, wherein the channel layer is compressed and strained.

(Appendix 7)
_{It is characterized by having a back barrier layer of In a} Al _b Ga _1-ab N (0 ≦ a ≦ 0.05, 0.60 ≦ b <1.00) between the base layer and the barrier layer. The semiconductor device according to any one of Supplementary note 1 to 6.

(Appendix 8)
The semiconductor device according to Appendix 7, wherein the back barrier layer is compressed and strained.

(Appendix 9)
The semiconductor device according to any one of Supplementary note 1 to 8, wherein the barrier layer contains n-type impurities.

(Appendix 10)
A power supply device comprising the semiconductor device according to any one of Supplementary notes 1 to 9.

(Appendix 11)
An amplifier comprising the semiconductor device according to any one of Supplementary notes 1 to 9.

(Appendix 12)
The process of forming the barrier layer of AlN on the N-polar surface of the base layer of AlN, and
A step of forming a GaN channel layer on the barrier layer and
A step of forming an AlGaN cap layer on the channel layer and
A method for manufacturing a semiconductor device.

(Appendix 13)
The method for manufacturing a semiconductor device according to Appendix 12, further comprising a step of forming a source electrode, a drain electrode, and a gate electrode above the channel layer.

(Appendix 14)
The method for manufacturing a semiconductor device according to Appendix 12 or 13, wherein the base layer is an AlN substrate.

(Appendix 15)
The method for manufacturing a semiconductor device according to any one of Supplementary note 12 to 14, wherein the thickness of the channel layer is 20 nm or less.

(Appendix 16)
The method for manufacturing a semiconductor device according to any one of Supplementary note 12 to 15, wherein the Al composition of the cap layer is increased so as to be separated from the channel layer.

(Appendix 17)
_{It has a step of forming a back barrier layer of In a} Al _b Ga _1-ab N (0 ≦ a ≦ 0.05, 0.60 ≦ b <1.00) between the base layer and the barrier layer. The method for manufacturing a semiconductor device according to any one of Appendix 12 to 16, wherein the semiconductor device is manufactured.

(Appendix 18)
The method for manufacturing a semiconductor device according to any one of Supplementary note 12 to 17, wherein the barrier layer contains n-type impurities.

100, 200, 300, 400, 500, 600, 700, 800, 900: Semiconductor device 101: Underlayer layer 102, 202: Barrier layer 103, 203: Channel layer 104, 204: Cap layer 105: Two-dimensional electron gas 201: Substrate 221: Source electrode 222: Drain electrode 223: Gate electrode 506: Back barrier layer

Claims (12)

The base layer of AlN and
The AlN barrier layer on the N-polar surface of the base layer and
The GaN channel layer on the barrier layer and
The AlGaN cap layer on the channel layer and
A back barrier layer of In _a Al _b Ga _1-ab N (0 ≦ a ≦ 0.05, 0.60 ≦ b <1.00) between the base layer and the barrier layer.
A semiconductor device characterized by having. The semiconductor device according to claim 1, further comprising a source electrode, a drain electrode, and a gate electrode above the channel layer. The semiconductor device according to claim 1 or 2, wherein the base layer is an AlN substrate. The semiconductor device according to any one of claims 1 to 3, wherein the thickness of the channel layer is 20 nm or less. The semiconductor device according to any one of claims 1 to 4, wherein the Al composition of the cap layer becomes higher as the distance from the channel layer increases. The semiconductor device according to any one of claims 1 to 5 , wherein the barrier layer contains n-type impurities. A step of forming a back barrier layer of In _a Al _b Ga _1-ab N (0 ≦ a ≦ 0.05, 0.60 ≦ b <1.00) on the N-polar surface of the base layer of AlN, and
A step of forming an AlN barrier layer on the back barrier layer and
A step of forming a GaN channel layer on the barrier layer and
A step of forming an AlGaN cap layer on the channel layer and
A method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to claim 7 , further comprising a step of forming a source electrode, a drain electrode, and a gate electrode above the channel layer. The method for manufacturing a semiconductor device according to claim 7 or 8 , wherein the base layer is an AlN substrate. The method for manufacturing a semiconductor device according to any one of claims 7 to 9 , wherein the thickness of the channel layer is 20 nm or less. The method for manufacturing a semiconductor device according to any one of claims 7 to 10 , wherein the Al composition of the cap layer is increased so as to be separated from the channel layer. The method for manufacturing a semiconductor device according to any one of claims 7 to 11 , wherein the barrier layer contains n-type impurities.

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