JP6941346B2 - MIS type semiconductor device and its manufacturing method - Google Patents

Description

The present invention relates to a MIS type semiconductor device and a method for manufacturing the same, and particularly relates to a MIS type semiconductor device having a high dielectric constant of an insulating film and a low hydrogen transmittance.

With the increase in speed of MISFET (Metal Insulator Semiconductor Field Effect Transistor), which is a MIS (Metal-Insulator-Semiconductor) type semiconductor device, the transistor is being miniaturized for constant electric field scaling.
One of the performance indexes of the MISFET is the current drive capability Gm, which is the capacitance (gate capacitance) of the capacitor composed of the mobility μ, the gate width W, the gate electrode, the gate insulating film, and the semiconductor substrate. It is proportional to Cox and inversely proportional to the gate length L. Therefore, the speed of the MISFET has been increased by thinning the gate insulating film and miniaturizing the gate length L.

When the physical thickness of the gate insulating film is thinned to 2 nm or less, the tunnel leakage current increases, the dielectric strength when the gate voltage is applied is remarkably lowered, and the power consumption of the MISFET is increased.
The gate capacitance Cox is proportional to the relative permittivity and inversely proportional to the thickness of the gate insulating film. Focusing on this relationship, a high dielectric constant insulating film (High-k film) that uses an insulating film with a higher dielectric constant than _{the silicon oxide film (SiO 2} film) that has been conventionally used as the mainstream gate insulating film is used. The development of the existing transistor is being vigorously promoted (see Patent Document 1). When a high-k film is used, the physical film thickness required to obtain the same gate capacitance Cox can be increased, and the tunnel leakage current can be suppressed. The relative permittivity ε of the SiO _{2 film is about 3.9.} For these reasons, the high-k film (High-k gate insulating film) under development includes hafnium oxide film (HfO ₂ ), zirconium oxide film (ZrO ₂ ), and alumina (Al ₂ O ₃ ). , Their silicates and aluminates, and oxide films such as rare earth oxide films.

However, the high-k gate insulating film of the oxide film system tends to form an undesired oxide layer at the semiconductor interface, and the oxide layer has a problem that the gate capacitance Cox is reduced and the current driving capacity Gm or the like is lowered. there were. That is, the gate insulating film becomes a laminated film of the High-k film and its oxide layer, the dielectric constant of the effective gate insulating film is lowered, and the film thickness of the effective gate insulating film is increased. There is a problem that the current driving capacity Gm or the like is lowered.

Further, in many semiconductors such as silicon, when hydrogen is introduced at the interface between the semiconductor and the gate insulating film, an interface state is formed, which often causes a problem of deteriorating the characteristics of the MIS type semiconductor device. _{In particular, SiO 2} , which is widely used as a gate insulating film, easily permeates hydrogen, and the generation of an interface state due to hydrogen permeation has become a problem.

Japanese Unexamined Patent Publication No. 2011-54872 Japanese Patent No. 5118276

An object of the present invention is to solve the problems of undesired oxide layer formation and hydrogen permeation that occur at the semiconductor interface found in the conventional High-k gate insulating film, and a MIS type semiconductor having a large gate capacitance Cox. It is an object of the present invention to provide an apparatus and a method for manufacturing the MIS type semiconductor apparatus thereof.

The configuration of the present invention is shown below.
(Structure 1)
A MIS type semiconductor device having a semiconductor layer, an insulator layer, and a conductor layer, wherein the insulator layer is sandwiched between the semiconductor layer and the conductor layer.
The insulator layer is a MIS type semiconductor device containing cerium fluoride.
(Structure 2)
The Seriumufu' product is CeF _3, structure 1 MIS type semiconductor device according.
(Structure 3)
The MIS type semiconductor device according to the configuration 2, wherein the CeF _{3 is amorphous.}
(Structure 4)
The MIS type semiconductor device according to any one of configurations 1 to 3, _{wherein a film having MgF 2} is formed between the semiconductor layer and the insulator layer.
(Structure 5)
The MIS type semiconductor device according to any one of configurations 1 to 4, wherein the semiconductor layer includes a group 4 semiconductor.
(Structure 6)
The MIS type semiconductor device according to any one of configurations 1 to 4, wherein the semiconductor layer contains silicon.
(Structure 7)
The MIS-type semiconductor device according to configuration 6, wherein a silicon oxide film is formed between the silicon-containing semiconductor layer and the insulator layer.
(Structure 8)
The MIS type semiconductor device according to any one of configurations 1 to 4, wherein the semiconductor layer contains germanium.
(Structure 9)
In a method for manufacturing a MIS type semiconductor device, which includes an insulator layer forming step of forming an insulator layer on a semiconductor substrate and a conductor layer forming step of forming a conductor layer on the insulator layer.
A method for manufacturing a MIS type semiconductor device, wherein the insulator layer contains cerium fluoride.
(Structure 10)
The method for manufacturing a MIS type semiconductor device according to the configuration 9, wherein the cerium fluoride is CeF _3.
(Structure 11)
The method for manufacturing a MIS type semiconductor device according to the configuration 9 or 10, wherein the insulator layer is formed by a vacuum vapor deposition method, and the temperature at the time of performing the vacuum vapor deposition is 20 ° C. or higher and 500 ° C. or lower.
(Structure 12)
After the insulator layer forming step and before the conductor layer forming step, a heat treatment using nitrogen gas is performed.
The method for manufacturing a MIS type semiconductor device according to any one of configurations 9 to 11, wherein the heat treatment has a nitrogen gas pressure of 1 Pa or more and 2000 hPa or less and a heat treatment temperature of 200 ° C. or more and 500 ° C. or less.
(Structure 13)
After the conductor layer forming step, heat treatment is performed after forming the conductor layer using a mixed gas of nitrogen gas and hydrogen gas.
In the heat treatment after forming the conductor layer, the mixing ratio of nitrogen gas and hydrogen gas is 1% or more and 5% or less by volume of hydrogen gas with respect to 1 nitrogen gas, the pressure of the mixed gas is 1 Pa or more and 2000 hPa or less, and the heat treatment temperature. The method for manufacturing a MIS type semiconductor device according to any one of configurations 9 to 12, wherein the temperature is 200 ° C. or higher and 500 ° C. or lower.

According to the present invention, the formation of an undesired oxide layer generated at the semiconductor interface seen in the conventional High-k gate insulating film is prevented, and the hydrogen permeability of the gate insulating film which is the basis of the interface state generation is prevented. A MIS-type semiconductor device having a high-k gate insulating film having a low dielectric constant and a high dielectric constant and a method for manufacturing the MIS-type semiconductor device are provided. As a result, the provided MIS-type semiconductor device becomes a MIS-type semiconductor device having stable electrical characteristics and a large gate capacitance Cox.

The cross-sectional view which shows the MIS structure of this invention. The characteristic figure which shows the relative permittivity characteristic of the insulating film of this invention. The characteristic figure which shows the hydrogen permeation characteristic of the insulating film of this invention. X-ray photoelectron spectroscopy characteristic diagram for obtaining binding energy. Explanatory drawing explaining the state of a band gap. The cross-sectional view which shows the structure of the MISFET according to this invention. The cross-sectional view which shows the structure of the 2nd MISFET according to this invention. FIG. 5 is a cross-sectional view of a main part showing a manufacturing process of the second MISFET. The characteristic diagram which shows the capacitance characteristic. The characteristic diagram which shows the capacitance characteristic. The characteristic diagram which shows the capacitance characteristic. The characteristic diagram which shows the capacitance characteristic. The characteristic diagram which shows the capacitance characteristic. The characteristic diagram which shows the capacitance characteristic.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.
When an oxide film is used as the high-k gate insulating film, the semiconductor interface is also oxidized and an undesired oxide film easily grows between the semiconductor and the high-k gate insulating film. _{For example, when HfO 2} is used as the High-k film and Si is used as the semiconductor, SiO ₂ grows on the surface of Si. In this case, the gate insulating film is a two-layer film composed _{of SiO 2} and HfO _2. Since _{the relative permittivity of SiO 2} is not as high as 3.9, the dielectric constant of the gate insulating film cannot be increased as expected even if a Hikg-k film made of _{HfO 2 is used.} Further, a _{level may be formed between SiO 2} and HfO _2, and the electrical characteristics of the manufactured MIS semiconductor device may become unstable or the reliability may decrease.
Therefore, various studies were conducted after trial and error on a gate insulating film that replaces the oxide film. As a result, it was found that cerium fluoride is a suitable film as a High-k gate insulating film. An example of an attempt to use fluoride as a High-k gate insulating film is LaF _3, which is described in Patent Document 2.

As shown in FIG. 1, the MIS structure 101 of the present invention has a structure in which a buffer layer 2, a cerium fluoride layer 3, and a conductor layer 4 are sequentially formed on a semiconductor layer 1.

Here, as the material of the semiconductor layer 1, for example, silicon (Si) which is a group 4 semiconductor (general IV semiconductor), germanium (Ge), and gallium which is a group 3-5 compound semiconductor (group III-V compound semiconductor). Arsenic compound (GaAs), indium phosphorus compound (InP), zinc selenium compound (ZnSe) which is a group 2-6 compound semiconductor (II-VI group compound semiconductor), cadmium sulfur compound (CdS), group 4 compound semiconductor (group IV) Examples thereof include silicon carbide (SiC), which is a compound semiconductor), and a silicon germane compound (SiGe).
A dopant is added to the semiconductor layer 1. The dopant may be one that is usually used. For example, when an n-type semiconductor layer is formed with respect to a group IV semiconductor such as Si or Ge, arsenic (As), phosphorus (P), antimony (Sb), and nitrogen ( When N) or the like is used as the p-type semiconductor layer, boron (B), gallium (Ga), indium (In), aluminum (Al), or the like can be used.

The cerium fluoride layer 3 is composed of a CeF ₃ film. The CeF ₃ film is preferably formed by a vacuum vapor deposition method, but may be formed by a sputtering method or an ALD (Atomic Layer Deposition) method. As the sputtering method, the RF sputtering method is preferable from the viewpoint of throughput. Here, as the sputtering gas, a noble gas such as argon (Ar) gas or krypton (Kr) gas can be preferably used.
In the case of film formation by a vacuum deposition CeF ₃ film, it is preferable that a substrate temperature of 20 ° C. or higher 500 ° C. or less.

CeF ₃ film is less affected by amorphous and crystalline lattice matching with the semiconductor layer 1 is preferably rich in versatility, semiconductors GaN, if such Ga ₂ O ₃ is also preferably a single crystal .. In that case, the crystal plane is preferably (001) because it has a high relative permittivity and a small dielectric loss. The single crystal of CeF ₃ has a Fermi level shifted from amorphous to about 1 eV amorphous film toward the valence band side, and is characterized in that band alignment can be easily obtained depending on the combination with the semiconductor layer 1 and the conductor layer 4.
The C-V characteristics of CeF ₃ single crystal film (001) crystal plane and a (110) a result of comparison by the crystal plane shown in FIG. CeF ₃ single crystal film produced by the CZ method (Czochralski method) and has a thickness of 1 mm. CeF ₃ were measured and the specific dielectric constant and dielectric loss applying an AC of 1MHz between the front and back of platinum (Pt) across the electrode both electrodes of the single crystal film. Here, the dielectric loss is defined by the ratio of the real part and the imaginary part of the complex permittivity. The relative permittivity (dielectric constant) is as high as about 50 for the (110) crystal and about 52 for the (001) crystal. The dielectric loss is about 29 for the (110) crystal and about 18 for the (001) crystal, which is about 40% lower than the (110) crystal.

CeF ₃ The thickness of a film, preferably 1nm or more 100nm or less, and more preferably 5nm or 10nm or less. When the film thickness is less than 5 nm, a tunnel leak current begins to appear, and when the film thickness is less than 1 nm, the tunnel current becomes remarkable. If the film thickness exceeds 100 nm, it becomes difficult to obtain a sufficient capacitance.

The CeF ₃ film has a lower hydrogen permeability than _{the SiO 2 film.} FIG. 3 shows an example in which the hydrogen transmittance of the CeF ₃ single crystal film and the SiO _{2 glass substrate was measured by a reduced pressure differential pressure.} The crystal plane of the CeF ₃ single crystal film is (001), the film thickness is 980 μm, and the thickness of the SiO ₂ glass substrate is 524 μm. The base back pressure was set to less than 2 Pa, and the pressure of hydrogen was 300 kPa, and the measurement was performed at room temperature (23 ° C.).
As a result, the transmission coefficient of hydrogen, CeF ₃ film ^{7.8 × 10 -12 cc · cm /} (cm 2 · s · cmHg), SiO 2 film is ^{9.4 × 10 -12 cc · cm /} (cm ^{At 2} · s · cmHg), the CeF ₃ film was about 18% lower than the _{SiO 2 film.} Since the CeF ₃ film has a high relative permittivity, the physical film thickness when the film is used as the gate insulating film is _{significantly thicker than when the SiO 2} film is used as it. Therefore, CeF ₃ film is a good hydrogen permeation suppression film.

CeF ₃ the valence band of XPS: was examined using (X-ray Photoelectron Spectroscopy X-ray photoelectron spectroscopy), as shown in FIG. 4, was about 2.8 eV. Since the bandwidth of CeF ₃ film is known to be 4.2 eV, band state of CeF ₃ becomes the relationship shown in the band state and 5 of Ge, CeF ₃ functions as an MIS respect Ge semiconductor Has good band alignment.

The conductor layer 4 is made of a conductive film such as polysilicon to which a metal or a dopant is added. Metals include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), titanium (Ti), aluminum (Al), chromium (Cr), and tantalum. (Ta) and the like can be mentioned. Further, alloys such as AlCu, CuNiFe and NiCr, silicides such as WSi and TiSi, and metal compounds such as WN, TiN, CrN and TaN can also be used. For the conductor layer 4, an appropriate material may be selected from among such materials in consideration of conductivity, work function, workability, and the like. When the MIS semiconductor device of the present invention is used as an integrated circuit, various heat treatments as integration are added. Therefore, the material is selected in consideration of the diffusion of the material in consideration of those heat treatments.

The buffer layer 2 is a layer having functions such as diffusion suppression of substances constituting the semiconductor layer 1 such as Ge to the cerium fluoride layer 3, interface state generation suppression (interface control), and stress relaxation, and is a fluoride film or silicon. It consists of at least one or more of oxide films.

When the semiconductor layer 1 is Si, the buffer layer 2 is preferably a silicon oxide film or a laminated film of a _{silicon oxide film and an MgF 2 film.} In the case of this laminated film, it is preferable that a silicon oxide film is formed in contact with Si because a level is unlikely to be generated at the interface with Si. _{Here, SiO 2} is preferable as the silicon oxide film. _{This is because SiO 2} , which is a stoichiometric state of the silicon oxide film, is unlikely to generate a level in the film.

When the semiconductor layer 1 is Ge, the buffer layer 2 is preferably an MgF ₂ film or a laminated film of an _{MgF 2} film and a SiO _{2 film.} Here, it is preferable that the SiO ₂ film is formed on the semiconductor layer 1 side made of Ge.
Ge is difficult to diffuse into Ce in an oxygen atmosphere, but has a property of being easily diffused into Ce in a vacuum. In fact, it performed Ge substrate sample, Ge sample thickness on the substrate to form a CeF ₃ film of 10 nm, and Ge film thickness on the substrate was prepared a sample to form a CeF ₃ film of 20nm to assay by XPS As a result, a diffusion layer in which Ge _{diffuses into the CeF 3} film was observed with a thickness of about 5 nm between the Ge and the substrate CeF _{3 film.}
Ge in a vacuum is less likely to diffuse in the order of Ce> Ba (barium)> Mg. The MgF ₂ film also has a relatively large dielectric constant (relative permittivity). Fluoride is less likely to form a layer different from the fluoride or oxide at the interface with the semiconductor layer 1 as compared with oxide. Therefore, the MgF ₂ film is suitable as the buffer layer 2.

The film thickness of the buffer layer 2 is preferably 0.1 nm or more and 2 nm or less, and particularly preferably 0.5 nm or more and 1 nm or less. When the film thickness of the buffer layer 2 is less than 0.5 nm, the functions such as diffusion suppression, interface level generation suppression (interface control) and stress relaxation are deteriorated, and when it is less than 0.1 nm, it becomes insufficient. If it exceeds 2 nm, it becomes difficult to increase the dielectric constant of the gate insulating film as a whole, and the performance of the gate capacitance Cox and the like deteriorates.
_{Further, the film thickness of the MgF 2} film as the buffer layer 2 is preferably 1 nm or more. When the _{film thickness of the MgF 2} film is 1 nm or more, it is possible to sufficiently suppress the diffusion of substances such as Ge constituting the semiconductor layer 1 into the cerium fluoride layer 3.

Next, the MISFET of the present invention will be described.

The first MISFET (102) of the present invention has a semiconductor layer 1, a buffer layer pattern 2a in which patterns for drains and sources are formed in a buffer layer, and a cerium fluoride layer, as shown in FIG. 6, which is a cross-sectional view of a main part. It is composed of a cerium fluoride layer pattern 3a, a gate 4a, a source 5a and a drain 6a in which a pattern for a drain and a source is formed.
Here, the gate 4a, the source 5a and the drain 6a are made of a conductive film such as a metal, an alloy, a metal compound, silicide, and polysilicon to which a polyside or a dopant is added.

The temperature when the cerium fluoride layer is formed by the vacuum vapor deposition method is preferably 20 ° C. or higher and 500 ° C. or lower in order to obtain good electrical characteristics.
_{Further, it is preferable that the heat treatment using nitrogen gas (N 2} gas) is performed after the cerium fluoride layer is formed and before the conductive film forming the gate 4a is formed in order to improve the electrical characteristics of the MISFET. As the conditions for the heat treatment, the pressure of nitrogen gas is preferably 1 Pa or more and 2000 hPa or less, and the temperature is preferably 200 ° C. or more and 500 ° C. or less.
Further, it is preferable to perform heat treatment using a mixed gas of _{nitrogen gas and hydrogen gas (H 2} gas) after forming the conductive film constituting the gate 4a in order to improve the electrical characteristics of the MISFET. The conditions for the heat treatment are that the mixing ratio of nitrogen gas and hydrogen gas is 1% or more and 5% or less by volume of hydrogen gas with respect to 1 nitrogen gas, the pressure of the mixed gas is 1 Pa or more and 2000 hPa or less, and the temperature is 200 ° C. It is preferably 500 ° C. or higher and 500 ° C. or lower.

In producing a MISFET having this structure, it is necessary to open a pattern having openings for the source 5a and the drain 6a in the cerium fluoride layer. Pattern formation for this purpose is performed by lithography and dry etching, but _{cerium fluoride such as CeF 3} is difficult to perform reactive dry etching, and dry etching using ionic milling-like physical impact is performed.
Dry etching using physical impact tends to damage the base of the work piece. However, in the case of the present invention, since the buffer layer serves as an etching stopper when the cerium fluoride layer is dry-etched, there is a feature that the semiconductor layer 1 which is the base is not easily damaged by the dry etching.

The second MISFET (103) of the present invention has a semiconductor layer 1, a buffer film (buffer layer) 12b, a CeF ₃ film 13b, a gate 14b, a source 15b, and a drain 16b, as shown in FIG. 7, which is a cross-sectional view of a main part. And a patterned interlayer film 21b. In this structure, the gate 14b has an embedded structure. Here, the gate 14a, the source 15a, and the drain 16a are made of a conductive film such as a metal, an alloy, a metal compound, silicide, polysilicon added with a polyside or a dopant, similarly to the first MISFET (102).

The second MISFET (103) can be manufactured by the steps shown below. The manufacturing method will be described with reference to FIG. 8 in which the manufacturing process is described using the cross-sectional view of the main part.
First, the interlayer film 21 is formed on the semiconductor layer 1 (see FIG. 8A). As the interlayer film 21, for example, an insulating film such as _{SiO x by a plasma CVD method can be mentioned.}
Next, an opening for forming a gate in the interlayer film 21 is formed by lithography and dry etching to form an interlayer film pattern 21a (FIG. 8 (b)).
Then, the buffer film 12a and the CeF ₃ film 13a are sequentially formed (FIG. 8 (c)). These films are preferably conformally adhered.
_{Next, the buffer film 12a and the CeF 3} film 13a formed on the upper surface of the interlayer film pattern 21a are removed by a method such as CMP (Chemical Mechanical Polishing) or etch back to form an opening of the interlayer film pattern 21a. Only the buffer film 12b and the CeF ₃ film 13b formed are obtained (FIG. 8 (d)).
After that, the conductor film 14a is adhered (FIG. 8 (e)), and subsequently, the conductor film 14a formed on the upper surface of the interlayer film pattern 21a is removed by a method such as CMP or etchback. A conductor film pattern in which a conductor film is embedded is formed in a groove where the CeF _{3 film 13b is exposed, and the conductor film pattern is designated as a gate 14b (FIG. 8 (f)).}
Then, by using lithography and dry etching, an interlayer film pattern 21b having openings 22 and 23 is formed in the interlayer film pattern 21a (FIG. 8 (g)).
Then, a conductor film is embedded in the openings 22 and 23, and the conductor film pattern is set as a second MISFET (103) as a source 15b and a drain 16b, respectively.

According to the second MISFET manufacturing method, since the CeF ₃ film 13b is processed by CMP or etch back, it is not easy to perform dry etching with less damage to the semiconductor layer, and electricity is also _{applied to the CeF 3 film.} It is possible to obtain a MISFET with less target damage.

Hereinafter, examples in which the characteristics of the MIS semiconductor device of the present invention have been investigated based on the capacitor characteristics will be described. As a matter of course, the present invention is not limited to such a specific form, and the technical scope of the present invention is defined by the claims.

(Example 1)
In Example 1, when Si was used as the semiconductor layer 1, a semiconductor device having the MIS structure 101 shown in FIG. 1 was manufactured, and its capacitance and dielectric loss were measured.
The semiconductor layer 1 is a Si substrate having a resistivity of 1 to 5 Ω · cm doped with boron (B), the buffer layer 2 is a thermally oxidized SiO ₂ film having a thickness of 4 nm, and the cerium fluoride layer 3 has a film thickness of 10 nm. As the amorphous CeF ₃ film and the conductor layer 4 of the above, Pt having a thickness of 150 nm was used, and the capacitance and the dielectric loss between the conductor layer 4 and the semiconductor layer 1 were measured. Here, the size of the conductor pattern composed of the conductor layer 4 is 100 μmφ.

The method for preparing the evaluation sample is as follows.
First, the Si substrate with a 4 nm thermal oxide SiO ₂ film was washed with acetone, ethanol, and pure water, and then UV ozone washing was performed.
It was then formed to a thickness of 10nm to CeF ₃ film by vacuum deposition. At this time, the degree of vacuum is 5 × ^10-6 Pa, and the substrate temperature is room temperature (23 ° C.). By forming a film on the SiO _{2 film, CeF 3} becomes an amorphous film.
After that, Pt was formed by DC sputtering to a thickness of 150 nm. At this time, the degree of vacuum is 1 Pa, and the substrate temperature is room temperature (23 ° C.). Here, in forming this Pt, a patterned Pt was formed using a mask, and this was used as a Pt electrode.
A semiconductor parameter analyzer (B1500A, manufactured by Keysight) was used to measure the capacitance and the dielectric loss.

The measurement results of capacitance and dielectric loss are shown in FIGS. 9 to 11.
FIG. 9 shows a case where no special heat treatment is applied. FIG. 10 shows a case where heat treatment is performed at 300 ° C. for 30 minutes under nitrogen gas (N _{2 gas) to which 4% of hydrogen gas (H 2} gas) is added after forming a Pt electrode as forming gas annealing for the purpose of interfacial termination. FIG. 11 shows a case where heat treatment is performed at 400 ° C. for 30 minutes under _{N 2} gas before forming the Pt electrode for the purpose of defect compensation. Here, the heat treatment was performed using a quartz lamp heating furnace, and the gas pressure was set to atmospheric pressure in both the cases of FIG. 10 and FIG.
The measurement frequency is 1 MHz, and in order to express the hysteresis characteristic, the case where the bias voltage is swept applied in the positive direction and the case where the bias voltage is swept applied in the negative direction are shown together.

When the CeF ₃ film and the SiO ₂ film of the film thickness and the Pt electrode area and 9 from the magnitude of the capacitance shown in FIG. 11 determine the dielectric constant of CeF ₃ film, its size is 20 or more 30 It can be seen from the following that the insulating film of the present invention composed of the SiO ₂ buffer layer 2 and the cerium fluoride layer (CeF ₃ film) 3 is a film having a sufficiently large dielectric constant (relative permittivity).
Further, when the heat treatment is performed before or after the formation of the Pt electrode, the effects of reducing the hysteresis, reducing the flat band shift and reducing the dielectric loss are recognized. In the heat treatment at a high temperature (400 ° C.) before the formation of the Pt electrode for the purpose of defect compensation, the capacitance is not significantly different from that before the heat treatment, but the heat treatment after the formation of the Pt electrode is significant. The capacitance is decreasing.

(Example 2)
In Example 2, the buffer layer 2 is _{a two-layer film composed of a SiO 2 film having a thickness of 4 nm and thermal oxidation and an MgF 2} film having a film thickness of 1 nm from the semiconductor layer 1 side, and CeF constituting the cerium fluoride layer 3. _When the film thickness of the three films was changed from 10 nm in Example 1 to 9 nm, the film had the same structure as in Example 1 except for the case, and was produced by the same method. Here, the MgF ₂ film is an amorphous film formed by a vacuum vapor deposition method, and the degree of vacuum at the time of film formation is 5 × ^10-6 Pa, and the substrate temperature is room temperature (23 ° C.). As the heat treatment, it is subjected to a heat treatment of 400 ° C. 30 minutes under _{N 2} gas before Pt electrode formation. The heat treatment under the mixed gas _{of H 2} and N ₂ after the formation of the Pt electrode was not performed.

As shows the measurement results of the capacitance and dielectric loss of MIS semiconductor device of Embodiment 2 in FIG. 12, shown within dashed box in the figure, the insertion of MgF ₂ film, the depletion layer side shoulder It was confirmed that the amount of electricity was reduced and the electrical characteristics were good.

(Example 3)
In Example 3, when Ge was used as the semiconductor layer 1, a semiconductor device having a MIS structure 101 was manufactured, and its capacitance and electrostatic characteristics were measured.
The semiconductor layer 1 is a Ga-doped Ge substrate having a resistivity of 0.01 to _{0.05 Ω · cm, the buffer layer 2 is an MgF 2} film having a film thickness of 1 nm, and the cerium fluoride layer 3 has a film thickness of 13 nm. As the amorphous CeF ₃ film and the conductor layer 4, Pt having a film thickness of 150 nm was used. Further, a Pt conductor layer is also arranged on the semiconductor layer 1 side, and the semiconductor layer 1, the buffer layer 2, and the cerium fluoride layer 3 are sandwiched between the Pt conductor layers arranged on both the front and back surfaces to form a capacitance and a dielectric. The loss was measured. Here, the Pt conductor layer is patterned like an electrode to form a Pt electrode. The size of the Pt electrode is 100 μmφ.

The method for preparing the evaluation sample is as follows.
First, the Ge layer was washed with acetone, ethanol, and pure water, and then heat-treated at 420 ° C. for 20 minutes under ^{a high vacuum (1 × 10-6} Pa) to remove the _{natural oxide film (Ga 2} O _{3).
Then, an MgF 2} amorphous film having a film thickness of 1 nm was formed by a vacuum vapor deposition method. At this time, the degree of vacuum is 5 × ^10-6 Pa, and the substrate temperature is room temperature (23 ° C.).
It was then formed to a thickness of 13nm to CeF ₃ film by vacuum deposition. At this time, the degree of vacuum is 5 × ^10-6 Pa, and the substrate temperature is room temperature (23 ° C.). By forming a film on the amorphous MgF _{2 film, the crystallinity of CeF 3} is lowered, and _{the film thickness of MgF 2} is 1 nm or more, and CeF ₃ becomes an amorphous film.
After that, Pt was formed by DC sputtering to a thickness of 150 nm. At this time, the degree of vacuum is 1 Pa, and the substrate temperature is room temperature (23 ° C.). Here, in forming this Pt, a patterned Pt was formed using a mask, and this was used as a Pt electrode.
A semiconductor parameter analyzer (B1500A, manufactured by Keysight) was used for measuring the capacitance and the dielectric loss as in Example 1.

The measurement results of capacitance and dielectric loss are shown in FIG.
The measurement frequency is set to 1 MHz as in the first embodiment, and the case where the bias voltage is swept applied in the positive direction and the case where the bias voltage is swept applied in the negative direction are described together in order to express the hysteresis characteristic.
_{The total physical film thickness of the CeF 3} film and the MgF ₂ film is 14 nm, but the EOT (Effective Dielectric Pickness) obtained by using the capacitance measurement shown in FIG. 13, that is, the SiO ₂ equivalent film thickness is 3.5 nm. This film is a High-k film having a sufficiently large dielectric constant (relative permittivity).
From this _{, it was confirmed that the fluoride insulating film composed of the CeF 3} film and the MgF ₂ film is an insulating film having a high relative permittivity capable of suppressing interfacial oxidation and diffusion of Ge.

(Reference example 1)
Reference Example 1 in place of the Seriumufu' oxide layer 3 made of CeF ₃ film of the buffer layer 2 and the thickness of 13nm formed of MgF ₂ film having a thickness of 1nm in Example 3, MgF ₂ of the CeF ₃ 3 wt% is mixed This is the same as in Example 3 except that the single-layer cerium fluoride layer obtained is used. The film thickness of the cerium fluoride layer in Reference Example 1 is 14 nm.
The measurement results of capacitance and dielectric loss are shown in FIG.
In the case of this structure, the diffusion of Ge into the cerium fluoride could not be sufficiently suppressed, the hysteresis was large, and the electrostatic loss was also large.

As described above, according to the present invention, the formation of an undesired oxide layer generated at the semiconductor interface seen in the conventional High-k gate insulating film is prevented, and the gate insulating film which is the basis of the interface state generation is prevented. A MIS-type semiconductor device having a High-k gate insulating film having a low hydrogen permeability and a high dielectric constant and a method for manufacturing the MIS-type semiconductor device are provided. As a result, the provided MIS-type semiconductor device becomes a high-performance MIS-type semiconductor device that is stable and has a large gate capacity Cox, and may be used in many industrial fields.

1: Semiconductor layer 2: Buffer layer 2a: Buffer layer pattern 3: Cerium fluoride layer (CeF ₃ film)
3a: Cerium fluoride layer pattern (CeF ₃ film pattern)
4: Conductor layer 4a: Gate 5a: Source 6a: Drain 12a: Buffer film 12b: Buffer film 13a: CeF ₃ film 13b: CeF ₃ film 14a: Conductor film 14b: Gate 15b: Source 16b: Drain 21: interlayer film 21a: interlayer film pattern 21b: patterned interlayer film 22: opening 23: opening 101: MIS structure 102: MISFET
103: MISFET

Claims (11)

A MIS type semiconductor device having a semiconductor layer, an insulator layer, and a conductor layer, wherein the insulator layer is sandwiched between the semiconductor layer and the conductor layer.
The insulator layer is a MIS type semiconductor device including CeF _3. The CeF ₃ is amorphous, MIS-type semiconductor device according to claim 1, wherein. The MIS type semiconductor device according to claim 1 or 2 , wherein a film having _{MgF 2} is formed between the semiconductor layer and the insulator layer. The MIS type semiconductor device according to any one of claims 1 to 3 , wherein the semiconductor layer includes a group 4 semiconductor. The MIS type semiconductor device according to any one of claims 1 to 3 , wherein the semiconductor layer contains silicon. The MIS-type semiconductor device according to claim 5 , wherein a silicon oxide film is formed between the semiconductor layer containing silicon and the insulator layer. The MIS type semiconductor device according to any one of claims 1 to 3 , wherein the semiconductor layer contains germanium. In a method for manufacturing a MIS type semiconductor device, which includes an insulator layer forming step of forming an insulator layer on a semiconductor substrate and a conductor layer forming step of forming a conductor layer on the insulator layer.
A method for manufacturing a MIS type semiconductor device, wherein the insulator layer contains CeF _3. The method for manufacturing a MIS type semiconductor device according to claim 8 , wherein the insulator layer is formed by a vacuum vapor deposition method, and the temperature at the time of performing the vacuum vapor deposition is 20 ° C. or higher and 500 ° C. or lower. After the insulator layer forming step and before the conductor layer forming step, a heat treatment using nitrogen gas is performed.
The method for manufacturing a MIS type semiconductor device according to claim 8 or 9 , wherein the heat treatment is a nitrogen gas pressure of 1 Pa or more and 2000 hPa or less, and a heat treatment temperature of 200 ° C. or more and 500 ° C. or less. After the conductor layer forming step, heat treatment is performed after forming the conductor layer using a mixed gas of nitrogen gas and hydrogen gas.
In the heat treatment after forming the conductor layer, the mixing ratio of nitrogen gas and hydrogen gas is 1% or more and 5% or less by volume of hydrogen gas with respect to 1 nitrogen gas, the pressure of the mixed gas is 1 Pa or more and 2000 hPa or less, and the heat treatment temperature. The method for manufacturing a MIS type semiconductor device according to any one of claims 8 to 10 , wherein the temperature is 200 ° C. or higher and 500 ° C. or lower.

Images