JP6942824B2 - 構成可能論理プラットフォーム - Google Patents
構成可能論理プラットフォーム Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
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Description
1.構成可能論理プラットフォームであって、
構成可能論理プラットフォームをプロセッサに接続するための物理的相互接続と、
構成データに基づいて構成された論理ブロックを備える再構成可能論理領域と、
再構成可能論理領域が構成データに基づいて構成されるように、再構成可能論理領域に構成データを適用するための構成ポートと、
物理的相互接続のトランザクションを介してアクセス可能な制御プレーン機能であって、制御プレーン機能は構成ポートと通信しており、制御プレーン機能は物理的相互接続から構成ポートへの制限付きアクセスのみを提供する、制御プレーン機能と、
物理的相互接続のトランザクションを介してアクセス可能なデータプレーン機能であって、データプレーン機能は、物理的相互接続を介して情報を送信させて再構成可能論理領域が物理的相互接続に直接アクセスするのを防止する、再構成可能論理領域とのインターフェースを提供する、データプレーン機能と、
を備える構成可能論理プラットフォーム。
2.構成ポートに制限付きアクセスのみを提供することは、第1のアドレス範囲内のアドレスを備えるトランザクションが構成ポートにアクセスできるようにすることのみを備える、条項1に記載の構成可能論理プラットフォーム。
3.物理的相互接続はペリフェラルコンポーネント相互接続エクスプレス(Peripheral Component Interconnect Express)であり、制御プレーン機能およびデータプレーン機能は物理機能である、上記条項のいずれかに記載の構成可能論理プラットフォーム。
4.データプレーン機能は、再構成可能論理領域が1つ以上のアドレス範囲外のアドレスを有するトランザクションを生成することができず、再構成可能論理領域が物理的相互接続上で不正な形式のトランザクションを生成できないように、再構成可能論理領域から生じる全てのトランザクションをフォーマットするようになっている、上記条項のいずれかに記載の構成可能論理プラットフォーム。
5.データプレーン機能と制御プレーン機能との間でメッセージを渡すようになっているメールボックス論理をさらに備える、上記条項のいずれかに記載の構成可能論理プラットフォーム。
6.アプリケーション論理を実装するように構成可能なハードウェアを備える再構成可能論理領域と、
再構成可能論理領域をカプセル化するためのホスト論理であって、ホスト論理は、
プロセッサと通信するためのホストインターフェースと、
ホストインターフェースを介してアクセス可能な管理機能であって、管理機能は再構成可能論理領域を、ホストインターフェースで受信された認証済みトランザクションに応答してアプリケーション論理で構成させるようになっている、管理機能と、
ホストインターフェースを介してアクセス可能なデータパス機能であって、データパス機能は、ホストインターフェースとアプリケーション論理との間のデータ転送をフォーマットするための層を備える、データパス機能と、
を備えるホスト論理と、を備える装置。
7.再構成可能論理領域をアプリケーション論理で構成させることは、装置の構成ポートにアクセスすることを備える、条項6に記載の装置。
8.ホストインターフェースで受信した認証済みトランザクションは、管理機能に割り当てられたアドレス範囲内のアドレスを備える、条項6または7に記載の装置。
9.ホスト論理の少なくとも一部は、デアサートされている装置のリセットに応答して装置上にロードされる静的論理である、条項6から8のいずれかに記載の装置。
10.ホスト論理の少なくとも一部は、ホストインターフェースで受信された認証済みトランザクションに応答して装置上にロードされる再構成可能論理である、条項6から9のいずれかに記載の装置。
11.ホスト論理は、アプリケーション論理とパブリックペリフェラルとの間に変換層をさらに備え、変換層は、アプリケーション論理と、パブリックペリフェラルとの通信に使用される装置の論理との間のデータ転送をフォーマットするようになっている、条項6から10のいずれかに記載の装置。
12.パブリックペリフェラルはフィールドプログラマブルゲートアレイであり、論理はシリアライザ・デシリアライザトランシーバを含む、条項11に記載の装置。
13.ホスト論理はプライベートペリフェラルとのインターフェースをさらに備え、プライベートペリフェラルはアプリケーション論理およびデータパス機能にアクセス不可能である、条項6から12のいずれかに記載の装置。
14.ホスト論理は、管理機能とデータパス機能との間でメッセージを渡すためのメールボックス論理をさらに備える、条項6から13のいずれかに記載の装置。
15.再構成可能論理およびホストインターフェースを備える構成可能論理プラットフォームを動作させる方法であって、方法は、
構成可能ハードウェアプラットフォームがホスト論理の動作を実行するように再構成可能論理の第1領域上にホスト論理をロードするステップであって、ホスト論理は、ホストインターフェースからトランザクションへの制限付きアクセスを強制する制御プレーン機能を含む、ステップと、
ホストインターフェースにおいて、アプリケーション論理を再構成可能論理の第2領域上にロードさせるための第1トランザクションを受信するステップと、
第1トランザクションが制御プレーン機能のアクセス基準を満たすときにのみアプリケーション論理の動作を実行するように再構成可能論理の第2領域を構成するステップと、
アプリケーション論理がホストインターフェースの使用において制限されるように、ホスト論理の変換層を使用してホストインターフェースを介してアプリケーション論理から情報を送信するステップと、
を備える方法。
16.再構成可能論理の第1領域上にホスト論理をロードするステップは、
再構成可能論理の第1領域の少なくとも一部に再構成可能ホスト論理をロードさせるための第2トランザクションを、ホストインターフェース上で受信するステップと、
第2トランザクションが制御プレーン機能のアクセス基準を満たすときにのみ再構成可能ホスト論理の動作を実行するように構成可能ハードウェアプラットフォームを構成するステップと、
を備える、条項15に記載の方法。
17.構成可能ハードウェアプラットフォーム上にホスト論理をロードするステップは、電力事象に応答して構成可能ハードウェアプラットフォームのメモリから静的ホスト論理をロードするステップを備える、条項15または16に記載の方法。
18.ホストインターフェースの使用においてアプリケーション論理を制限するステップは、アプリケーション論理で生じてホストインターフェースに向かう全てのトランザクションをフォーマットするために変換層を使用するステップを備える、条項15から17のいずれかに記載の方法。
19.アプリケーション論理で生じて構成可能ハードウェアプラットフォームと通信するペリフェラルに向かうトランザクションをフォーマットするためにホスト論理を使用するステップ
をさらに備える、条項15から18のいずれかに記載の方法。
20.アプリケーション論理で生じたトランザクションを監視および分析し、拒否されたトランザクションがホストインターフェース上で送信される前に、所定の基準と一致するトランザクションを拒否するために、ホスト論理を使用するステップ
をさらに備える、条項15から19のいずれかに記載の方法。
Claims (10)
- アプリケーション論理と前記アプリケーション論理をカプセル化するためのホスト論理とを実装するように構成可能なハードウェアを備える再構成可能論理領域を備える装置であって、前記ホスト論理は、
プロセッサと通信するためのホストインターフェース論理と、
前記ホストインターフェース論理を介してアクセス可能な管理機能であって、前記管理機能は前記再構成可能論理領域の一部を、前記ホストインターフェース論理で受信される認証済みトランザクションに応答して前記アプリケーション論理で構成させるようになっている、管理機能と、
前記ホストインターフェース論理を介してアクセス可能なデータパス機能であって、前記データパス機能は、前記ホストインターフェース論理と前記アプリケーション論理との間のデータ転送をフォーマットするための層を備える、データパス機能と、
を備える、装置。 - 前記再構成可能論理領域を前記アプリケーション論理で構成させることは、前記装置の構成ポートにアクセスすることを含む、請求項1に記載の装置。
- 前記ホストインターフェース論理で受信される認証済みトランザクションは、前記管理機能に割り当てられたアドレス範囲内のアドレスを含む、請求項1に記載の装置。
- 前記ホスト論理の少なくとも一部は、デアサートされている前記装置のリセットに応答して前記装置上にロードされる静的論理である、請求項1に記載の装置。
- 前記ホスト論理の少なくとも一部は、前記ホストインターフェース論理で受信される認証済みトランザクションに応答して前記装置上にロードされる再構成可能論理である、請求項1に記載の装置。
- 前記ホスト論理は、前記アプリケーション論理とパブリックペリフェラルとの間に変換層をさらに備え、前記変換層は、前記アプリケーション論理と、前記パブリックペリフェラルとの通信に使用される前記装置の論理との間のデータ転送をフォーマットするようになっている、請求項1に記載の装置。
- 前記パブリックペリフェラルはフィールドプログラマブルゲートアレイであり、前記論理はシリアライザ・デシリアライザトランシーバを含む、請求項6に記載の装置。
- 前記ホスト論理はプライベートペリフェラルとのインターフェースをさらに備え、前記プライベートペリフェラルは前記アプリケーション論理および前記データパス機能にアクセス不可能である、請求項1に記載の装置。
- 前記ホスト論理は、前記管理機能と前記データパス機能との間でメッセージを渡すためのメールボックス論理をさらに備える、請求項1に記載の装置。
- 前記ホスト論理は、前記アプリケーション論理のアクセスを、前記ホストインターフェース論理、または前記プロセッサとの物理インターフェースのうちの少なくとも1つに制限するように構成されている、請求項1に記載の装置。
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| US15/279,232 US10223317B2 (en) | 2016-09-28 | 2016-09-28 | Configurable logic platform |
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| JP2019516662A JP6739633B2 (ja) | 2016-09-28 | 2017-09-27 | 構成可能論理プラットフォーム |
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