JP6943709B2 - Power supply device - Google Patents

Description

The present invention relates to a power supply device.

Conventionally, a vehicle such as an automobile is a junction in which a power supply device for supplying or shutting off battery power to an electric component (load) such as a headlight in response to an operation of a switch such as a headlight switch or an audio switch is housed. A box (electrical junction box) is installed. This junction box is connected to a battery, various switches, and various loads via electric wires (harnesses).

Further, the power supply circuit in the junction box is provided with a plurality of semiconductor switches for supplying or shutting off the power supplied from the battery to the load according to the operation of the switch. Conventionally, an overcurrent protection element such as a fuse is provided in order to protect a load, a semiconductor switch, and an electric wire from an overcurrent. In recent years, computerization of overcurrent protection elements has been promoted, and various power supply devices that protect electric wires by using overcurrent protection and overheat protection functions of semiconductor switches instead of conventional fuses have been proposed (for example). See Patent Documents 1 to 3).

In Patent Document 1, the temperature in the vicinity of the load driving power element that supplies electric power to the load is detected, and when the detected temperature is equal to or higher than a predetermined temperature, the control means blocks the input of the control signal to the power element. A technique for protecting the power element itself by maintaining the cutoff state is disclosed.

Further, in Patent Document 2, the load current flowing from the semiconductor element to the load via the wire is detected, and when the load current exceeds the overcurrent limit threshold, the drive current of the semiconductor element is reduced by the current limit circuit to load. A technique for limiting the current below the overcurrent limit threshold has been disclosed. This overcurrent limit threshold is set to a value equal to or less than the current value at which the wire burns out due to the load current. Further, this overcurrent limit threshold value is set to a first threshold value so as not to be erroneously moved by an inrush current during a predetermined time from the start-up, and after a predetermined time elapses, a second threshold value smaller than the first threshold value is set. Is set to. This protects the electric wire.

Further, in Patent Document 3, the current value flowing from the power supply to the load via the semiconductor switch is detected, the squared current value is obtained from the detected current value, and the temperature equivalent value of the semiconductor switch is obtained by calculation by the heat equivalent circuit. , A technique is disclosed in which an abnormality is determined when the abnormality determination value set based on the limit temperature of the semiconductor switch is exceeded, and the semiconductor switch is turned off when the abnormality is determined.

Japanese Unexamined Patent Publication No. 10-145205 Japanese Unexamined Patent Publication No. 2003-11164 Japanese Unexamined Patent Publication No. 2009-142146

By the way, in the technique disclosed in Patent Document 1, since the temperature in the vicinity of the power element is detected and the semiconductor switch is shut off based on the detected temperature, the semiconductor switch cannot be sufficiently protected. That is, since the detected temperature varies greatly depending on the detection accuracy of the sensor itself and the temperature distribution in the chip, there is a problem that the actual breaking temperature also varies based on this. Further, since the accuracy of the temperature sensor is generally not good (about ± 25 ° C.), there is a problem that the breaking current value is not stable and the variation becomes large when the semiconductor switch breaking method by temperature detection is used. Therefore, the protection function by temperature detection cannot sufficiently protect the power element and the like. Furthermore, in the method of detecting the heat generation of the element with respect to the inrush current at the time of short circuit, it takes time for the heat to be conducted, so there is a problem that the rated current of the power element is exceeded and the power element is damaged. be.

Further, in the technique disclosed in Patent Document 2, an overcurrent detection method in which different threshold values are set between a predetermined time from the start-up and after a predetermined time has elapsed is used. In the protection function using such an overcurrent detection method, unless the number of cutoff thresholds is set to a large number and finely controlled, the allowable current range becomes considerably narrower than the transient allowable current value of the electric wire. That is, in order to use the overcurrent detection method in which different threshold values are set depending on the time, a complicated process such as setting a plurality of threshold values for the time and switching the threshold values with a predetermined timing as a trigger is required.

Further, in the technique disclosed in Patent Document 3, since a circuit for squared the current value is required, there is a problem that the manufacturing cost increases and the substrate area increases.

Further, in the techniques disclosed in Patent Documents 1 to 3, even though the load is operating normally, a malfunction occurs such that the supply of current to the load is stopped or momentarily interrupted due to erroneous detection or the like. There is a problem.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a power supply device capable of protecting a semiconductor switch and a load by a simple circuit configuration without causing a malfunction. It is said.

In order to solve the above problems, the present invention is a semiconductor that is connected between a power supply and a load and turns on / off the power supply power supplied to the load in a power supply device that supplies power supply power from the power supply to the load. A switch, a current detecting means for detecting a current flowing through the load via the semiconductor switch, and a current value detected by applying the current detected by the current detecting means to a predetermined time-constant circuit or detecting the current. Is converted into a voltage by applying to a time constant equation, a determination means for determining whether or not the voltage obtained by the voltage conversion means exceeds a predetermined reference voltage, and the determination means for determining the voltage. When it is determined that the voltage obtained by the conversion means exceeds the predetermined reference voltage, the control means for controlling the semiconductor switch to the off state and the power supply device after the power supply is started. Alternatively, it is determined that the voltage obtained by the voltage conversion means exceeds the predetermined reference voltage from the start of supplying current to the load via the semiconductor switch until the predetermined condition is satisfied. Even in such a case, the control means has a holding means for holding the semiconductor switch off.
In addition, a simple circuit configuration makes it possible to protect the semiconductor switch and the load without causing a malfunction.

Further, in the present invention, the time constant circuit is an RC ladder type time constant circuit, the time constant equation is an equation having the characteristics of the RC ladder type time constant circuit, and the limit value of the current flowing with respect to the load. It is a threshold value indicating the above, and is characterized by exhibiting a current cutoff characteristic in which the value decreases with the passage of time.
According to such a configuration, it is possible to protect the semiconductor switch and the load by a simple circuit configuration.

Further, in the present invention, the holding means has a predetermined time after the power supply to the power supply device is started or the current is started to be supplied to the load via the semiconductor switch. It is characterized in that the semiconductor switch is suspended from being turned off even when it is determined that the voltage obtained by the voltage conversion means exceeds the predetermined reference voltage until the lapse of time.
According to such a configuration, it is possible to surely prevent the occurrence of a malfunction based on the time.

Further, in the present invention, the holding means generates a mask signal based on a control signal for controlling the semiconductor switch and a signal delayed from the control signal, and the semiconductor switch is based on the mask signal. It is characterized by withholding turning off.
According to such a configuration, a mask signal can be generated by a simple configuration, and the occurrence of a malfunction can be reliably prevented based on the mask signal.

Further, in the present invention, the holding means has a microcomputer, and when the state of the control signal for controlling the semiconductor switch changes, the holding means holds the semiconductor switch off for a predetermined period of time. It is characterized by that.
According to such a configuration, the microcomputer can surely prevent the malfunction.

Further, in the present invention, the holding means is the current detecting means after the power supply to the power supply device is started or after the current supply to the load is started via the semiconductor switch. When the difference value of the voltage applied to the non-inverting input terminal and the inverting input terminal of the differential amplifier has a predetermined threshold value or more, the voltage obtained by the voltage conversion means exceeds the predetermined reference voltage. Even if it is determined that the semiconductor switch is turned off, the semiconductor switch is suspended from being turned off.
According to such a configuration, the malfunction can be surely prevented based on the difference value of the voltage applied to the non-inverting input terminal and the inverting input terminal of the differential amplifier which causes the malfunction.

Further, the present invention is characterized in that the power supply device is detachably connected to a relay box, a junction box, or a connection connector.
With such a configuration, it is possible to reliably control the load connected via the relay box, the junction box, or the connector.

According to the present invention, it is possible to provide a semiconductor switch and a power supply device capable of protecting a load without causing a malfunction by a simple circuit configuration.

It is a perspective view which shows the structural example of the power supply device which concerns on embodiment of this invention. It is a block diagram which shows the structural example of 1st Embodiment of this invention. It is a circuit diagram which shows the structural example of 1st Embodiment shown in FIG. It is a figure which shows the configuration example which excluded the state change holding part from the 1st Embodiment shown in FIG. It is a figure for demonstrating the operation of the embodiment shown in FIG. It is a figure for demonstrating the operation of the embodiment shown in FIG. It is a figure for demonstrating the operation of the embodiment shown in FIG. It is a figure for demonstrating the operation of the embodiment shown in FIG. It is a figure for demonstrating the operation of the embodiment shown in FIG. It is a figure for demonstrating the operation of the embodiment shown in FIG. It is a figure for demonstrating the operation of 1st Embodiment shown in FIG. It is a block diagram which shows the structural example of the 2nd Embodiment of this invention. It is a block diagram which shows the structural example of the 3rd Embodiment of this invention. It is a block diagram which shows the structural example of the 4th Embodiment of this invention. It is a block diagram which shows the structural example of the 5th Embodiment of this invention.

Next, an embodiment of the present invention will be described.

(A) Explanation of Configuration of First Embodiment of the Present Invention FIG. 1 is a perspective view showing a configuration example of a power supply device 1 according to the first embodiment of the present invention. As shown in this figure, the power supply device 1 according to the first embodiment of the present invention has a main body portion 100 and a lid portion 120. Here, the main body 100 is made of, for example, resin or the like, and an element group 105 including a semiconductor switch 12 described later is arranged on the surface 100a. Further, the surface 100b is formed with claws 101 and 102 that engage with the holes 121 and 122 provided on the side surface of the lid 120. Further, terminals 111 to 115 are provided on the surface 100c. In the example of FIG. 1, the terminal 111 is a ground terminal, the terminal 112 is a terminal to which a drive signal is input, and the terminal 113 outputs a DIAG signal indicating that the semiconductor switch 12 is turned off. Terminal 114 is a terminal to which a battery is connected, and terminal 115 is a terminal to which a load is connected. Of course, other arrangements may be used. The lid portion 120 is made of resin or the like, the main body portion 100 is inserted into the lid portion 120, and the claw portions 101 and 102 engage with the holes 121 and 122 to fix the main body portion 100 at a predetermined position.

The power supply device 1 shown in FIG. 1 is detachably connected to, for example, a relay box, a junction box, or a connection connector of a vehicle, and supplies power to a load connected to these.

FIG. 2 is a block diagram showing an example of an electrical configuration of the power supply device 1. In the example shown in FIG. 2, the power supply device 1 includes a semiconductor switch 12, a current detection unit 13, a time constant circuit 14, an abnormality determination unit 15, a semiconductor switch drive unit 16, and a state change holding unit 17. ..

Here, the semiconductor switch 12 is configured by, for example, a power MOS-FET (Metal-Oxide-Semiconductor Field-Effect Transistor), and is turned on / off by controlling the voltage of the gate terminal by the semiconductor switch drive unit 16. Is controlled. When it is turned on, the electric power stored in the battery 2 is used as the power source and is supplied to the load 10 via the electric wire 11. As the semiconductor switch 12, a semiconductor element other than the power MOS-FET, for example, an IGBT (Insulated Gate Bipolar Transistor) or a bipolar transistor can be used.

The current detection unit 13 detects the current flowing from the battery 2 to the load 10 via the semiconductor switch 12 and the electric wire 11, and supplies the current to the time constant circuit 14. More specifically, when the load current flowing through the electric wire 11 is an Iload, a current Is that is proportional to the value of the Iload and is smaller than the Iload (for example, a value of 1/1000) is supplied to the time constant circuit 14. do.

The time constant circuit 14 is a threshold value indicating a limit value of the current flowing with respect to the load 10 when the semiconductor switch 12 is turned on, as will be described later with reference to FIG. It has a time constant to generate a current cutoff characteristic whose value decreases.

As will be described later with reference to FIG. 3, the abnormality determination unit 15 compares the output voltage Vo output from the time constant circuit 14 with a predetermined reference voltage Vref, and when the output voltage Vo exceeds the reference voltage Vref, , The semiconductor switch drive unit 16 is controlled via the state change holding unit 17, the semiconductor switch 12 is turned off, and the power supply to the load 10 is cut off.

The state change holding unit 17 temporarily holds the state change of the semiconductor switch 12 at the start / stop of power supply to the power supply device 1 and at the start / stop of power supply to the load 10, and the semiconductor switch 12 Suppress the occurrence of malfunctions.

As will be described later with reference to FIG. 3, the semiconductor switch drive unit 16 is composed of a logic element and a transistor, and gates the semiconductor switch 12 based on an external input signal input from the outside to the power supply device 1. Drive.

FIG. 3 is a diagram showing a detailed configuration example of FIG. In the following, the configuration and operation will be described with reference to the basic configuration example shown in FIG. 4 excluding the state change holding unit 17, and then with reference to FIG. 3, the operation including the state change holding unit 17 will be described. explain.

As shown in FIG. 4, the current detection unit 13 that detects the load current (Iload) flowing through the electric wire 11 connected to the load 10 includes a differential amplifier 23, a resistor Rs, and a P-channel type MOS-FET 24. Be prepared. An electric wire 11 is connected to the non-inverting input terminal of the differential amplifier 23, a battery 2 is connected to the inverting input terminal via a resistor Rs, and a gate terminal of the MOS-FET 24 is connected to the output terminal. The drain terminal of the MOS-FET 24 is the connection point between the inverting input terminal of the differential amplifier 23 and the resistor Rs, and the source terminal is the connection point of the capacitor element C1, the resistor element R1 of the time constant circuit 14 and the input terminal of the comparator 27. It is connected to the. Reference numeral 24a indicates a parasitic diode of the MOS-FET 24. Reference numeral 12a indicates a parasitic diode of the semiconductor switch 12.

The current detection unit 13 controls the gate potential of the MOS-FET 24 by the output of the differential amplifier 23 so that the drain-source voltage Vds of the semiconductor switch 12 and the terminal voltage Vs of the resistor Rs are equal to each other. The current (detection current) Is proportional to the load current (Iload) flowing through the electric wire 11 is configured to flow through the resistor Rs. The detected current Is is a current having a value of (load current Iload) × K. Here, K is a coefficient, and K = (on resistance Ron / Rs of the semiconductor switch 12). This detected current Is is output from the current detection unit 13 to the time constant circuit 14 as a current corresponding to the load current Iload flowing through the electric wire 11. It should be noted that it has a relationship of Is << Iload, and as an example, Is is set to about 1/1000 of Iload.

When the semiconductor switch 12 is turned on, a current flows with respect to the load 10, but when the current exceeds the limit value, the semiconductor switch 12 and the electric wire 11 are damaged by the overcurrent (for example, ASO (Area of Safe Operation)). Destruction occurs). By the way, such a limit value changes with the passage of time. FIG. 5 shows the limit characteristics of the semiconductor switch 12 and the electric wire 11. The horizontal axis of FIG. 5 shows the elapsed time since the semiconductor switch 12 was turned on, and the vertical axis shows the load current Iload. In FIG. 5, the semiconductor limit characteristic 30 indicates a change over time in the limit current that can be passed through the semiconductor switch 12 after the semiconductor switch 12 is turned on, and the wire limit characteristic 31 is similarly passed through the wire 11. It shows the change over time of the limit current that can be generated. As shown in FIG. 5, when the semiconductor switch 12 is turned on, a certain amount of large current can be passed through the electric wire 11 and the semiconductor switch 12, but the electric wire (over time) with the passage of time. The value of the current that can be passed through the 11 and the semiconductor switch 12 decreases. Further, the semiconductor limit characteristic 30 and the electric wire limit characteristic 31 are different in characteristics. The cutoff prohibition region shown in FIG. 5 indicates the range of the current flowing when the load 10 is operating normally, and when the current flowing through the semiconductor switch 12 falls within this region, the semiconductor switch 12 is cut off. This is an area where it is prohibited to do so.

Therefore, in the present embodiment, the current cutoff characteristic 32 is set in consideration of both the semiconductor limit characteristic 30 and the electric wire limit characteristic 31. Then, the electric wire 11 and the semiconductor switch 12 are overcurrent by controlling the load current Iload so as not to exceed the curve showing the time-varying current cutoff characteristic 32 (hereinafter referred to as “current cutoff curve”). Prevent damage by. More specifically, in the present embodiment, the detection current Is is input to the time constant circuit 14 having the time constant corresponding to the current cutoff characteristic 32 shown in FIG. 5, and the output voltage Vo exceeds the reference voltage Vref. In this case, the semiconductor switch 12 is turned off so that the load current Iload does not exceed the current cutoff curve.

The abnormality determination unit 15 has a comparator 27, compares the output voltage Vo from the time constant circuit 14 with the reference voltage Vref, and when Vo> Vref, the current flowing through the semiconductor switch 12 is the current at that time. It is determined that the cutoff curve is exceeded, an H level signal is output, and when Vo ≦ Vref, an L level signal is output.

The output signal from the comparator 27 is input to the latch circuit 28. The latch circuit 28 outputs an L level signal while the comparator 27 outputs an L level signal, and when an H level signal is output from the comparator 27, latches the output to the H level. ..

The semiconductor switch drive unit 16 includes a NAND circuit 20, a PNP-type transistor 21, an NPN-type transistor 22, and an inverter 29. A control signal for turning on / off the semiconductor switch 12 is input from the terminal 112 to one input terminal of the NAND circuit 20. For example, when a switch (not shown) for operating the load 10 is turned on, an H level (for example, 5V) control signal is turned on, and when the switch is turned off, an L level control signal is sent to the NAND circuit 20. It is input to one of the input terminals. The output signal of the latch circuit 28 is input to the other input terminal of the NAND circuit 20 via the inverter 29.

In the transistor 21 and the transistor 22, collectors are connected to each other and bases are connected to each other. A voltage (driving voltage) obtained by boosting the power supply voltage is supplied to the emitter of the transistor 21 from the charge pump 6, and the emitter of the transistor 22 is grounded.

The semiconductor switch drive unit 16 having the above configuration operates as follows.

(1) With the switch (not shown) for operating the load 10 turned off, the L level control signal is input from the terminal 112 to one input terminal of the NAND circuit 20, and the output signal of the latch circuit 28 is input. At the L level, when the signal is inverted by the inverter 29 and the H level signal is input to the other input terminal of the NAND circuit 20, the NAND circuit 20 outputs the H level signal. As a result, the transistor 21 is turned off and the transistor 22 is turned on, so that the drive voltage from the charge pump 6 is not applied to the gate terminal of the semiconductor switch 12, and the semiconductor switch 12 is maintained in the off state.

(2) When a switch (not shown) for operating the load 10 is turned on, one input of the NAND circuit 20 is input while an H level signal is input to the other input terminal of the NAND circuit 20. Since the H level control signal is input to the terminal, the NAND circuit 20 outputs the L level signal. As a result, the transistor 22 is turned off and the transistor 21 is turned on, so that the drive voltage from the charge pump 6 is applied to the gate terminal of the semiconductor switch 12, and the semiconductor switch 12 is turned on. As a result, battery power is supplied to the load 10 via the electric wire 11, and the load 10 is driven.

(3) When the output signal of the latch circuit 28 changes from the L level to the H level when the semiconductor switch 12 is in the ON state, the H level signal is input to one of the input terminals of the NAND circuit 20. Since the L level signal is input to the other input terminal, the NAND circuit 20 outputs the H level signal. As a result, the drive voltage from the charge pump 6 is no longer applied to the gate terminal of the semiconductor switch 12, and the semiconductor switch 12 changes from the on state to the off state. As a result, the supply of the battery power to the load 10 is cut off, and the drive of the load 10 is stopped.

Further, in the power supply device 1 shown in FIG. 4, the input side of the inverter 29 and the output side of the latch circuit 28 are connected to the DIAG terminal 113. The DIAG terminal 113 is used as a terminal for inputting a reset signal for resetting the latch circuit 28 from a state in which an H level signal is output to a state in which an L level signal is output, and is also used as an output of the latch circuit 28. It is used as a terminal for outputting the output signal of the latch circuit 28 to the external circuit in order to externally monitor the on / off state of the semiconductor switch 12 from the signal.

(B) Description of Operation of First Embodiment of the Present Invention Next, the operation of the first embodiment of the present invention will be described. Hereinafter, the operation will be described with reference to the basic configuration example shown in FIG. 4 excluding the state change holding unit 17, and then the operation including the state change holding unit 17 will be described with reference to FIG.

As shown in FIG. 4, when the switch (for example, the headlight switch) is turned on to drive the load (for example, the headlight) 10, the output of the NAND circuit 20 becomes the L level and the transistor 21 is turned on. Then the transistor 22 is turned off. As a result, the drive voltage is applied from the charge pump 6 to the gate terminal of the semiconductor switch 12 via the transistor 21, and the semiconductor switch 12 is turned on. As a result, the power supply power of the battery 2 is supplied to the load 10 via the electric wire 11, and the load 10 is activated.

When the load 10 is activated in this way, the current detection unit 13 detects a current (detection current Is) proportional to the load current (Iload) flowing through the electric wire 11. The detected current Is is supplied from the current detection unit 13 to the time constant circuit 14.

In the time constant circuit 14, the detection current Is is input from the current detection unit 13 and supplied to the RC ladder type time constant circuit composed of the resistance elements R1 to R3 and the capacitor elements C1 to C3.

The time constant circuit 14 has a time constant corresponding to the above-mentioned current cutoff characteristic 32. Further, the abnormality determination unit 15 compares the output voltage Vo from the time constant circuit 14 with the reference voltage Vref, outputs an H level signal when Vo> Vref, and outputs an H level signal in other cases, and L level in other cases. Output the signal of.

In the present embodiment, the following functions are realized by the cooperation of the time constant circuit 14 and the abnormality determination unit 15. That is, as shown in FIG. 6A, it is assumed that a current I1 slightly smaller than the current breaking characteristic 32 shown by the alternate long and short dash line flows through the semiconductor switch 12. In this case, the output voltage Vo from the time constant circuit 14 is always a voltage Vo1 lower than the reference voltage Vref, as schematically shown in FIG. 6B, so that the output of the abnormality determination unit 15 is always at the L level. It becomes. On the other hand, it is assumed that a current I2 slightly larger than the current cutoff characteristic 32 flows through the semiconductor switch 12 as shown by the alternate long and short dash line. In this case, the output voltage Vo from the time constant circuit 14 is always higher than the reference voltage Vref as shown in FIG. 6B, so that the output of the abnormality determination unit 15 is always H level. Become. The above has been described with an extreme example for the sake of simplification of the explanation. For example, in actual operation, when the current value becomes larger than the current cutoff characteristic 32 even temporarily, the output voltage Vo of the time constant circuit 14 becomes higher. Since the voltage is higher than the reference voltage Vref, the output of the abnormality determination unit 15 becomes the H level.

As a result of the determination by the comparator 27, (1) while the output voltage Vo is lower than the reference voltage Vref, the comparator 27 outputs an L level signal. As a result, the output signal of the NAND circuit 20 is maintained at the L level, the semiconductor switch 12 is maintained in the ON state, and the drive of the load 10 is continued.

On the other hand, (2) in the transient state after the load 10 is started or in the steady state thereafter, the overcurrent flows through the semiconductor switch 12, so that the current flowing through the semiconductor switch 12 has the current cutoff characteristic 32 shown in FIG. When it exceeds, the comparator 27 outputs an H level signal, and the latch circuit 28 latches the output of the comparator 27 to the H level. As a result, the output signal of the NAND circuit 20 changes from the L level to the H level, the transistor 21 is turned off, and the transistor 22 is turned on. Therefore, the drive voltage from the charge pump 6 is applied to the gate terminal of the semiconductor switch 12. The semiconductor switch 12 is forcibly turned off, the supply of the battery power to the load 10 is cut off, and the drive of the load 10 is stopped.

When the overcurrent flows through the semiconductor switch 12, for example, the overcurrent occurs in a very short time (for example, several hundred μs or less) due to a dead short, or a pulse width-modulated control signal is applied. In some cases, intermittent overcurrent may occur due to intermittent shorts (rare shorts). In the present embodiment, the semiconductor switch 12 can be turned off by detecting such an overcurrent.

In this embodiment, the following effects are exhibited.

In the present embodiment, the output voltage Vo of the time constant circuit 14 changes according to the current Ids flowing through the semiconductor switch 12 after the semiconductor switch 12 is turned on (after the load 10 is started). For example, when the current flowing through the semiconductor switch 12 increases, the output voltage Vo increases in the time constant circuit 14 in response to the increase in the current. The output value of the time constant circuit 14 that changes in this way is compared with the reference voltage Vref, and when the output voltage Vo exceeds the reference voltage Vref, the semiconductor switch 12 is turned off to turn off the current shown in FIG. The semiconductor switch 12 can be controlled based on the breaking characteristic 32. In this way, by controlling based on the current cutoff characteristic 32 in consideration of both the semiconductor limit characteristic 30 and the electric wire limit characteristic 31, the semiconductor switch 12 can be efficiently used while being protected from overcurrent and overheating. It cannot be used in such an area by the above-mentioned conventional technique.

In addition, it is possible to easily deal with a case where an instantaneous cutoff such as a dead short is required.

In the method of detecting the temperature in the vicinity of the power element for load driving and blocking the input of the control signal to the power element when the detected temperature is equal to or higher than the predetermined temperature as in the prior art described in Patent Document 1. There may be a difference between the detected temperature and the true temperature of the power element, or there may be a time delay in detecting the temperature. On the other hand, according to the present embodiment, the detected value of the current flowing through the electric wire 11 is input to the time constant circuit 14, and based on the current cutoff characteristic 32 in consideration of both the semiconductor limit characteristic 30 and the electric wire limit characteristic 31. Since the overcurrent is detected, the current flowing through the semiconductor switch 12 can be detected without causing a time delay. Therefore, deterioration and failure of the semiconductor switch 12 can be suppressed, and the electric wire can be protected against an overcurrent that occurs in a very short time (for example, several hundred μs or less) such as a dead short. can.

Further, since the time constant circuit 14 is composed of an RC ladder type time constant circuit, the current cutoff characteristic 32 corresponding to both the semiconductor switch 12 and the electric wire 11 can be arbitrarily set. Further, by using the RC ladder type time constant circuit, for example, as compared with the technique disclosed in Japanese Patent Application Laid-Open No. 2013-128343, it is possible to reduce the variation in the current cutoff characteristic in the transient region, and it is possible to reduce the variation in the current cutoff characteristic with respect to the temperature and the detected current. The design can be simplified. That is, since the technology disclosed in Japanese Patent Application Laid-Open No. 2013-128343 uses a diode or a Zener diode, there is a large variation in the transient region (depending on the design and component selection, for example, a current of plus or minus 10% or more). Variations in blocking characteristics are expected). Specifically, when the voltage between the anode and the cathode changes significantly due to the forward current flowing through the diode, and when the Zener diode has a Zener voltage of 5 to 6 V as a boundary and the voltage is higher than this, Since it has a positive temperature characteristic and has a negative temperature characteristic when the voltage is lower than this, the design when considering the temperature and the detected current becomes complicated. However, in the RC ladder type time constant circuit, the resistance element and the capacitor element are different from the diode in that the characteristics do not change due to the current. Further, in the time constant circuit, the element corresponding to the diode is a resistance element, and the resistance element has a small temperature characteristic, so that the design can be simplified. Further, since the time constant circuit 14 uses only a passive element having a linear characteristic, noise is compared with the technique disclosed in Japanese Patent Application Laid-Open No. 2013-128343 using a Zener diode having a non-linear characteristic as a switching characteristic. Can be reduced.

Further, since the output from the current detection unit 13 to the time constant circuit 14 is a current output, it is possible to cope with the transient fluctuation of the semiconductor switch 12 with almost no influence of the power supply fluctuation.

Further, the time constant circuit 14 adjusts the constant of the RC ladder type time constant circuit (the capacitance of the capacitor in each stage of the RC ladder type circuit and the resistance value of the resistance) and the reference voltage Vref to adjust the transient current region and The current cutoff characteristic in the steady operation region (steady state) can be set arbitrarily.

As an example, FIG. 7 shows a characteristic (characteristic shown by a broken line) in which the current cutoff characteristic 32 in the steady operation region is changed. In the example of FIG. 7, the transient current region is hardly changed, and only the breaking characteristic of the steady current region is changed. Further, FIG. 8 shows a characteristic (characteristic shown by a broken line) in which the current cutoff characteristic 32 in the transient current region is changed. In the example of FIG. 8, the steady-state current region is hardly changed, and only the breaking characteristic of the transient current region is changed. Further, FIG. 9 shows the characteristics when the types of the loads 10 are different from those of FIGS. 7 and 8. In the example of FIG. 9, the beginning portion of the blocking prohibition region has a rectangular shape, which is different from the triangular shape shown in FIGS. 7 and 8. In the case of the load 10 having such characteristics, by adjusting the time constant and the reference voltage Vref of the time constant circuit 14, for example, a curved shape different from that of FIGS. 7 and 8 as shown in FIG. 9 can be obtained. The current cutoff characteristic 32 can be set.

Further, in the prior art described in Patent Document 2, the electric wire is protected by the first threshold value corresponding to the transient state and the second threshold value corresponding to the steady state. On the other hand, in the present embodiment, since the control is performed based on the continuous current cutoff characteristic (current cutoff curve) based on the time constant circuit 14, finer control can be performed as compared with Patent Document 2. .. Further, in paragraph 0052 of Patent Document 2, a resistance corresponding to the first threshold value is set as a variable resistance, and a continuously changing first threshold value is set by changing the resistance value of the variable resistance with the passage of time. Although it is disclosed, it is not easy to control the variable resistance in time. On the other hand, in the present embodiment, the continuously changing current cutoff curve can be easily set by using the time constant circuit 14.

Further, in the prior art disclosed in Patent Document 3, the overcurrent is cut off based on the heat equivalent circuit of the semiconductor switch 12. However, in order to make it a heat equivalent circuit, it is necessary to calculate the square value of the current, so it is necessary to provide a current conversion circuit. Since the circuit for calculating the square value is complicated and the occupied area of the circuit is large, there is a problem that the manufacturing cost is high and it is difficult to miniaturize the circuit. However, in the present embodiment, the semiconductor switch 12 is controlled based on the current cutoff characteristic (current cutoff characteristic) instead of the thermal equivalent circuit, so that the square value is obtained. It is possible to eliminate the circuit that calculates.

Next, the operation of the state change holding unit 17 will be described. FIG. 10 is a diagram illustrating an operation when the state change holding unit 17 is not provided (configuration of FIG. 4). More specifically, FIG. 10 shows a control signal input from the terminal 112 after starting the supply of power to the power supply device 1 and turning on the switch (not shown) of the load 10. It shows the temporal change of the signal after being put into the H level state. At time 0, when the control signal input from the terminal 112 is set to the H level state, the voltage rises sharply as shown by the broken line. As a result, the output of the semiconductor switch drive unit 16 is in the H level state, and the semiconductor switch 12 is in the ON state, so that current flows from the battery 2 to the load 10. At this time, the virtual short circuit of the differential input terminal of the differential amplifier 23 is not stable, or the semiconductor switch 12 and the semiconductor switch (not shown) constituting the current mirror circuit are arranged on the upstream side of the MOS-FET 24. If this is the case, the current mirror circuit may not be stable, and an unexpected voltage may be output from the differential amplifier 23.

In such a case, a current larger than expected flows through the time constant circuit 14, and the output of the comparator 27 is in the H level state. Therefore, the output of the latch circuit 28 is in the H level state, and the semiconductor switch 12 Is forcibly turned off, the supply of power to the load 10 is cut off, and the drive of the load 10 is stopped. In the example of FIG. 10, the detection current Is sharply increases 0.0035 s after the control signal input from the terminal 112 is brought into the H level state, and the output voltage Vo exceeds the cutoff threshold value. As a result, the semiconductor switch 12 is forcibly turned off, the supply of power to the load 10 is cut off, and the drive of the load 10 is momentarily interrupted.

Therefore, in the first embodiment shown in FIG. 2, the state change holding unit 17 prevents the above-mentioned malfunction from occurring. In the following, the details of the state change holding unit 17 will be described with reference to FIG. 3, and then the operation will be described with reference to FIG.

The state change holding unit 17 shown in FIG. 3 has a delay unit 41, an EX-OR circuit 42, a NOT circuit 43, and an AND circuit 44. The delay unit 41 outputs the control signal input from the terminal 112 with a predetermined time τ delay. The EX-OR circuit 42 calculates and outputs the exclusive OR of the output signal from the delay unit 41 and the control signal input from the terminal 112. The NOT circuit 43 inverts the logic of the signal output from the EX-OR circuit 42 and outputs the signal. The AND circuit 44 calculates the logical product of the output signal from the comparator 27 and the output signal from the NOT circuit 43 and outputs it to the latch circuit 28.

Next, it will be described in more detail with reference to FIGS. 3 and 11. As shown in FIG. 11A, when the control signal input from the terminal 112 is set to the H level state at the time T1, this signal is output with a time τ delay by the delay unit 41 (FIG. 11). (B)). The EX-OR circuit 42 calculates and outputs the exclusive OR of the control signal and the output signal from the delay unit 41. As a result, the output signal from the EX-OR circuit 42 is as shown in FIG. 11 (C). More specifically, the output signal from the EX-OR circuit 42 is in the H level state from the time when the control signal becomes H level until the output signal from the delay unit 41 becomes H level, and other than that, it is in the H level state. It will be in the L level state. The NOT circuit 43 inverts the logic of the output signal from the EX-OR circuit 42 and outputs it. As a result, the signal as shown in FIG. 11D is output from the NOT circuit 43 and supplied to the AND circuit 44. The AND circuit 44 calculates and outputs the logical product of the output signal from the comparator 27 and the output signal from the NOT circuit 43. Therefore, for example, as shown in FIG. 10, even when the detection current Is suddenly increases after the control signal changes to the H level and the output of the comparator 27 changes to the H level, the output is concerned. Since the signal is masked by the output signal from the NOT circuit 43, it is possible to prevent the semiconductor switch 12 from being turned off and causing a momentary interruption.

By adjusting the delay time τ of the delay unit 41, the time for masking the output signal from the comparator 27 can be changed. In the example of FIG. 10, for example, τ ≧ 0.004 [s] can be set so that the pulse voltage appearing at 0.0035 [s] can be masked. Since the time for masking the output signal from the comparator 27 differs depending on, for example, the characteristics of the differential amplifier 23, the load 10, and the MOS-FET 24, a sufficient value including a margin is set as τ, or It is desirable to set for each individual device. Further, if the value of τ is too large, the normal shutoff operation may be hindered. Therefore, as the load 10, a load having a large inrush current (for example, a capacitive load or a resistive load having a positive temperature characteristic (for example, a defogger in which a large current flows when the temperature is low)) is connected. If the load current flowing through the load 10 exceeds the current cutoff characteristic 32, it is desirable to set the value so that the cutoff operation is normally performed.

In the example shown in FIG. 11, the mask is also performed when the control signal changes to the L level (see time T3). However, when the control signal changes to the L level, one input signal of the NAND circuit 20 becomes the L level, so that the output signal from the NAND circuit 20 is H regardless of the state of the output signal from the latch circuit 28. Become a level. Therefore, even if the current detection unit 13 or the like malfunctions, the malfunction does not affect the state change of the semiconductor switch 12, so that masking is not possible when the control signal changes to the L level. Not required.

(C) Description of the Second Embodiment of the Present Invention Next, the second embodiment of the present invention will be described. FIG. 12 is a diagram showing a configuration example of a second embodiment of the present invention. In FIG. 12, the same reference numerals are given to the portions corresponding to those in FIG. 3, and the description thereof will be omitted. In the configuration example of FIG. 12, as compared with FIG. 3, the current detection unit 13, the time constant circuit 14, the abnormality determination unit 15, and the latch circuit 28 are excluded, and the current detection unit 70, A / D (Analog to Digital). A conversion unit 71 and a digital signal processing unit 72 have been added. The configuration other than these is the same as in FIG.

Here, the current detection unit 70 is composed of, for example, a resistance element having a small resistance value (a resistance element having an element value that causes a voltage drop that does not affect the operation of the load 10), and a current flowing through the load 10. The value of Iload is detected and supplied to the A / D conversion unit 71. The A / D conversion unit 71 converts the value of the current Iload detected by the current detection unit 70 into a digital signal and supplies it to the digital signal processing unit 72. The digital signal processing unit 72 is composed of, for example, a DSP (Digital Signal Processor) or a CPU (Central Processing Unit), processes a digital signal supplied from the A / D conversion unit 71, and is a semiconductor based on the processing result. The switch drive unit 16 is controlled. The delay unit 41, the EX-OR circuit 42, the NOT circuit 43, and the AND circuit 44 constituting the state change holding unit 17 have the same functions as those described above with reference to FIG.

Next, the operation of the second embodiment will be described. Hereinafter, the operation when the state change holding unit 17 is excluded will be described, and then the operation when the state change holding unit 17 is added will be described.

In the second embodiment, the current detection unit 70 detects the value of the current Iload flowing through the load 10 and supplies it to the A / D conversion unit 71. The A / D conversion unit 71 converts the value of the current Iload supplied from the current detection unit 70 into the corresponding digital data and supplies it to the digital signal processing unit 72.

The digital signal processing unit 72 is composed of the resistance elements R1 to R3 and the capacitor elements C1 to C3 shown in FIG. 3 with respect to the digital data corresponding to the value of the current Iload supplied from the A / D conversion unit 71. The time constant equation in the discrete time region having the same characteristics as the RC ladder type time constant circuit is applied. More specifically, the transfer function H (s) in the continuous time domain of the RC ladder-type time constant circuit shown in FIG. 3 is the transfer function in the discrete time domain using, for example, an ZZ transform such as a bilinear transform. By transforming to H (z), the time constant equation in the discrete time domain can be obtained.

The digital signal processing unit 72 convolves and integrates the time constant equation (H (z)) with respect to the digital data corresponding to the value of the current Iload supplied from the A / D conversion unit 71, and the result obtained. By comparing with the value corresponding to the reference voltage Vref shown in FIG. 3, it is determined whether or not the obtained result exceeds the reference voltage Vref, and if it exceeds, it is determined that it is abnormal, and the semiconductor switch is driven. The unit 16 is controlled to turn off the semiconductor switch 12.

According to the above configuration, since it can be configured by a digital circuit, the configuration can be simplified as compared with the embodiment of FIG. 4, and the noise immunity can be improved by configuring it with a digital circuit. , It is possible to prevent the characteristic change due to aging deterioration.

Next, the operation when the state change holding unit 17 is added will be described. As shown in FIG. 11A, when the control signal input from the terminal 112 is in the H level state at time T1, this signal is output with a time τ delay by the delay unit 41 (FIG. 11B). )reference). The EX-OR circuit 42 calculates and outputs the exclusive OR of the control signal and the output signal from the delay unit 41. As a result, the output of the EX-OR circuit 42 is as shown in FIG. 11 (C). More specifically, the output signal from the EX-OR circuit 42 is in the H level state from the time when the control signal becomes H level until the output signal from the delay unit 41 becomes H level, and other than that, it is in the H level state. It will be in the L level state. The NOT circuit 43 inverts the logic of the output signal from the EX-OR circuit 42 and outputs it. As a result, the signal as shown in FIG. 11D is output from the NOT circuit 43 and supplied to the AND circuit 44. The AND circuit 44 calculates and outputs the logical product of the output signal from the digital signal processing unit 72 and the output signal from the NOT circuit 43. Therefore, for example, as shown in FIG. 10, after the control signal changes to the H level, the detection current Is detected by the current detection unit 70 rapidly increases, and the output signal from the digital signal processing unit 72 becomes Even when the level changes to H level, the output is masked by the output signal from the NOT circuit 43, so that it is possible to prevent the semiconductor switch 12 from being turned off and causing a momentary interruption.

In the embodiment shown in FIG. 12, the current detection unit 70 is arranged between the semiconductor switch 12 and the load 10, but may be arranged in parallel with the semiconductor switch 12, for example. In this case, the current can be obtained from the voltage drop of the semiconductor switch 12 and the on-resistance.

Further, in the embodiment shown in FIG. 12, the functions of the time constant circuit 14, the abnormality determination unit 15, and the latch circuit 28 are realized by the digital signal processing unit 72. Among these, for example, the time constant circuit Only the function of 14 may be realized by the digital signal processing unit 72, or the two functions of the time constant circuit 14 and the abnormality determination unit 15 may be realized by the digital signal processing unit 72.

Further, in the embodiment shown in FIG. 12, the output signal from the digital signal processing unit 72 is masked for a predetermined time τ, but for example, the output signal from the current detection unit 70 is masked or A / D conversion is performed. The output signal from unit 71 may be masked.

(D) Description of Third Embodiment of the Present Invention Next, a third embodiment of the present invention will be described. FIG. 13 is a diagram showing a configuration example of a third embodiment of the present invention. In FIG. 13, the same reference numerals are given to the portions corresponding to those in FIG. 3, and the description thereof will be omitted. In the configuration example of FIG. 13, as compared with FIG. 3, the delay unit 41 is replaced with the EX-OR circuit 45, and the difference detection unit 46 is added. The configuration other than these is the same as in FIG.

Here, the difference detection unit 46 calculates the difference value between the input signals of the non-inverting input terminal and the inverting input terminal of the differential amplifier 23, and when the difference value is equal to or higher than a predetermined threshold value, the EX-OR circuit 45 Is supplied with an H-level signal, and is otherwise supplied with an L-level signal. The EX-OR circuit 45 calculates the exclusive OR of the control signal and the output signal from the difference detection unit 46, and outputs the calculation result to the EX-OR circuit 42.

Next, the operation of the third embodiment will be described. Since the operations other than the state change holding unit 17 of the third embodiment are the same as in the case of FIG. 4, the description thereof will be omitted, and the operation of the state change holding unit 17 will be described.

When the differential amplifier 23 is operating normally, the difference value (potential difference) of the input signal becomes approximately 0 V due to the virtual short circuit, so that the output of the difference detection unit 46 is in the L level state. When the output signal from the difference detection unit 46 is L level and the control signal is L level, the L level is input to the two input terminals of the EX-OR circuit 45, respectively, so that the EX-OR circuit The output signal from 45 becomes L level. Further, when the output signal from the difference detection unit 46 is L level and the control signal is H level, H level and L level signals are input to the two input terminals of the EX-OR circuit 45, respectively. Therefore, the output signal from the EX-OR circuit 45 becomes H level.

When the output signal from the difference detection unit 46 is L level and the control signal is L level, the L level signal is input to the two input terminals of the EX-OR circuit 42, respectively, so that EX- The output signal from the OR circuit 42 is at the L level. Further, when the output signal from the difference detection unit 46 is L level and the control signal is H level, the H level signal is input to the two input terminals of the EX-OR circuit 42, respectively. The output signal from the EX-OR circuit 42 is at the L level. That is, when the output signal from the difference detection unit 46 is L level (when the differential amplifier 23 is operating normally), the output signal from the EX-OR circuit 42 does not depend on the state of the control signal. Is the L level.

When the output of the EX-OR circuit 42 is L level, the output of the NOT circuit 43 is H level. As a result, the output signal from the AND circuit 44 becomes H level or L level depending on the output signal from the comparator 27. To summarize the above, when the output of the difference detection unit 46 is at the L level (when the differential amplifier 23 is operating normally), the output signal from the AND circuit 44 is regardless of the state of the control signal. , H level or L level depending on the output signal from the comparator 27.

Next, the operation when the operation abnormality of the differential amplifier 23 occurs will be described. For example, when the output signal from the latch circuit 28 is L level, the control signal is set to H level and the power supply to the load 10 is started. At this time, consider a case where the difference value between the input voltages of the non-inverting input terminal and the inverting input terminal of the differential amplifier 23 becomes equal to or greater than a predetermined threshold value due to, for example, a sudden increase in the current flowing through the load 10. ..

In such a case, the difference detection unit 46 determines that the difference value between the input voltages of the non-inverting input terminal and the inverting input terminal of the differential amplifier 23 is equal to or higher than a predetermined threshold value, and changes the output signal from the L level to the H level. change.

In that case, since the H level signal is supplied to each of the two input terminals of the EX-OR circuit 45, the output signal from the EX-OR circuit 45 becomes the L level. As a result, H level and L level signals are supplied to the two input terminals of the EX-OR circuit 42, respectively, so that the output of the EX-OR circuit 42 becomes the H level.

When the output signal from the EX-OR circuit 42 is H level, the output signal from the NOT circuit 43 is L level. As a result, the output signal from the AND circuit 44 becomes L level regardless of the state of the output signal from the comparator 27. That is, the output signal from the comparator 27 is masked. To summarize the above, when the output of the difference detection unit 46 is H level (when the differential amplifier 23 is not operating normally), the output signal from the AND circuit 44 is the output signal from the comparator 27. Regardless of the state, the level becomes L, and the output signal from the comparator 27 is masked. Thereby, for example, even if the differential amplifier 23 malfunctions, the malfunction can be masked, so that it is possible to prevent the power to the load 10 from being interrupted momentarily.

As described above, according to the third embodiment of the present invention, for example, when the differential amplifier 23 is not operating normally, the difference detection unit 46 detects it, and the EX-OR circuit 45 , 42, NOT circuit 43, and AND circuit 44 mask the output signal from the comparator 27, so that it is possible to prevent the current flowing through the load 10 from being interrupted due to a malfunction.

Further, in the third embodiment, the condition for starting the mask can be optimally set by appropriately setting the threshold value of the difference detection unit 46. For example, if a semi-fixed resistor is used and the threshold value can be adjusted, the optimum threshold value can be selected according to the type of the load 10 and the individual difference of the power supply device 1.

(E) Description of the Fourth Embodiment of the Present Invention Next, the fourth embodiment of the present invention will be described. FIG. 14 is a diagram showing a configuration example of a fourth embodiment of the present invention. In FIG. 14, the parts corresponding to those in FIG. 3 are designated by the same reference numerals, and the description thereof will be omitted. In the configuration example of FIG. 14, as compared with FIG. 3, the delay unit 41, the EX-OR circuit 42, and the NOT circuit 43 are excluded, and a microcomputer (hereinafter, simply referred to as “microcomputer”) 47 is newly added. .. The configuration other than these is the same as in FIG.

Here, the microcomputer 47 is a microcomputer having low specifications, and is, for example, a microcomputer having lower performance (calculation speed, storage capacity, etc.) than the digital signal processing unit 72 shown in FIG. As the microcomputer 47, for example, a higher-level device and a microcomputer for communication processing for exchanging information can be diverted. Of course, a microcomputer for purposes other than communication may be diverted. When the control signal changes, the microcomputer 47 has a function of using the change as a trigger to set the output signal to the L level for a certain period of time and then to the H level.

Next, the operation of the fourth embodiment of the present invention will be described. When the control signal changes from the L level to the H level while the power is supplied to the power supply device 1, the microcomputer 47 detects this. When the control signal changes from L level to H level or from H level to L level, the microcomputer 47 sets the output to the L level state for a certain period (for example, the period corresponding to the time τ in FIG. 11) by using the change as a trigger. ..

When the output signal from the microcomputer 47 becomes L level, one input signal of the AND circuit 44 becomes L level, so that the output signal from the comparator 27 is masked. Therefore, for example, as shown in FIG. 10, when the control signal is in the H state and the semiconductor switch 12 is in the ON state, even if the output signal from the comparator 27 becomes the H level due to a malfunction. , The pulse voltage shown by the solid line in FIG. 10 is masked by the microcomputer 47. Therefore, it is possible to prevent the current flowing through the load 10 from being interrupted momentarily.

As described above, according to the fourth embodiment of the present invention, for example, the microcomputer 47 used for communication or the like is diverted, and the output is set to the L level for a certain period at the timing when the control signal changes. , The output of the comparator 27 can be masked. Further, by diverting the microcomputer 47 used for other purposes, the manufacturing cost of the apparatus can be reduced.

(F) Description of Fifth Embodiment of the Present Invention Next, a fifth embodiment of the present invention will be described. FIG. 15 is a diagram showing a configuration example of a fifth embodiment of the present invention. In FIG. 15, the same reference numerals are given to the portions corresponding to those in FIG. 12, and the description thereof will be omitted. In the configuration example of FIG. 15, the delay unit 41, the EX-OR circuit 42, the NOT circuit 43, and the AND circuit 44 are excluded as compared with FIG. The configuration other than these is the same as in FIG.

In the configuration of FIG. 15, the output port of the digital signal processing unit 72 is directly connected to the terminal 113. Similarly, the input port of the digital signal processing unit 72 is newly connected to the terminal 112. Further, the digital signal processing unit 72, as in the embodiment of FIG. 12, with respect to the digital data corresponding to the value of the current Iload supplied from the A / D conversion unit 71, the resistance elements R1 to 2 shown in FIG. The time constant equation in the discrete time region having the same characteristics as the RC ladder type time constant circuit composed of R3 and the capacitor elements C1 to C3 is applied. Then, when the value (digital data) corresponding to the current output from the A / D converter 71 exceeds the current cutoff curve, the signal supplied from the output port to the terminal 113 is set to H level to make the NAND circuit. By setting the output of 20 to the H level and turning off the semiconductor switch 12, the current flowing through the load 10 is cut off.

Further, when the state of the control signal changes, the digital signal processing unit 72 masks the output signal supplied to the terminal 113 for a certain period of time. That is, when the value (digital data) corresponding to the current output from the A / D converter 71 exceeds the current cutoff curve, the signal supplied from the output port to the terminal 113 is set to H level, but the control signal After the state changes, the signal supplied from the output port to the terminal 113 is masked for a certain period of time (for example, the period corresponding to τ shown in FIG. 11). No signal is output). With such a configuration, it is possible to prevent the current flowing through the load 10 from being interrupted momentarily due to a malfunction.

As described above, according to the fifth embodiment of the present invention, the circuit configuration can be simplified as compared with FIG.

In the above, the digital signal processing unit 72 executes a process of determining whether or not the value (digital data) corresponding to the current output from the A / D conversion unit 71 exceeds the current cutoff curve. However, communication processing with other devices may also be executed at the same time. The same applies to the case of FIG.

(G) Description of Modified Embodiments It goes without saying that each of the above embodiments is an example, and the present invention is not limited to the cases described above. For example, in each of the above embodiments, the RC ladder type time constant circuit is used as the time constant circuit, but for example, a ladder type RL circuit can also be used. Further, a switched capacitor circuit that can be easily miniaturized may be used.

Further, as the time constant circuit, the RC ladder type time constant circuit shown in FIG. 3 is shown, but FIG. 3 is only an example, and a circuit having a shape other than this may be used.

Further, in the embodiment shown in FIG. 3, the current Is detected by the current detection unit 13 is input to the time constant circuit 14, but the voltage corresponding to the detected current is supplied to the time constant circuit 14. You may. Further, although the output of the time constant circuit 14 is a voltage, a current may be output.

Further, in each of the above embodiments, the current is detected and controlled by the analog circuit shown in FIG. 3, but these functions may be realized by the digital circuit.

Further, in each of the above embodiments, the state change holding unit 17 holds the state change of the semiconductor switch 12 by masking the output of the abnormality determination unit 15, but holds it by any other method. You may. For example, a switch may be provided between the MOS-FET 24 and the time constant circuit 14 and the switch may be turned off for a certain period of time (the period corresponding to τ shown in FIG. 11) to suspend the state change. Further, the state change may be suspended by changing the reference voltage Vref of the comparator 27 to a higher voltage for a certain period of time as described above. Further, a switch may be provided between the comparator 27 and the latch circuit 28, and the switch may be turned off for a certain period of time to suspend the state change. That is, in the present specification, holding the state change of the semiconductor switch 12 is not limited to the configuration of each of the above-described embodiments, and if the state change can be held, other configurations are also included.

Further, in each of the above embodiments, a method of preventing a malfunction when the H level of the control signal is changed has been described as an example. However, for example, when the power supply device 1 itself is started to be supplied with power. However, the malfunction may be prevented.

1 Power supply device 2 Battery 10 Load 11 Electric wire 12 Semiconductor switch 13 Current detector (current detection means)
14 Time constant circuit (voltage conversion means)
15 Abnormality judgment unit (judgment means)
16 Semiconductor switch drive unit (control means)
17 State change holding unit (holding means)
20 NAND circuit 21 and 22 transistors 23 differential amplifier 24 MOS-FET
27 Comparator 28 Latch circuit 29 Inverter 41 Delay part 42 EX-OR circuit 43 NOT circuit 44 AND circuit 45 EX-OR circuit 46 Difference detection unit 47 Microcomputer 70 Current detection unit (current detection means)
71 A / D converter (current detection means)
72 Digital signal processing unit (determination means, control means)

Claims (3)

In a power supply device connected between a power source and a load and supplying power from the power source to the load.
A semiconductor switch that turns on / off the power supply to the load,
A current detecting means for detecting a current flowing through the load via the semiconductor switch, and
A voltage conversion means that converts the current detected by the current detecting means into a voltage by applying the current detected by the current detecting means to a predetermined time constant circuit or applying the value of the detected current to the time constant equation.
A determination means for determining whether or not the voltage obtained by the voltage conversion means exceeds a predetermined reference voltage, and
When the determination means determines that the voltage obtained by the voltage conversion means exceeds the predetermined reference voltage, the control means for controlling the semiconductor switch to an off state and the control means.
By the voltage conversion means from the start of supplying the power to the power supply device or the start of supplying current to the load via the semiconductor switch until a predetermined condition is satisfied. A holding means that suspends the control means from turning off the semiconductor switch even when the obtained voltage is determined to exceed the predetermined reference voltage.
Have a,
The holding means is a differential amplifier included in the current detecting means after the power supply to the power supply device is started or after the current is started to be supplied to the load via the semiconductor switch. When the difference value of the voltage applied to the non-inverting input terminal and the inverting input terminal is equal to or greater than a predetermined threshold value, it is determined that the voltage obtained by the voltage conversion means exceeds the predetermined reference voltage. A power supply device, characterized in that it suspends turning off the semiconductor switch even if it exists. The time constant circuit is an RC ladder type time constant circuit, and the time constant equation is an equation having characteristics of the RC ladder type time constant circuit, and is a threshold value indicating a limit value of a current flowing with respect to the load. The power supply device according to claim 1, wherein the power supply device exhibits a current cutoff characteristic whose value decreases with the passage of time. The power supply device according to claim 1 or 2 , wherein the power supply device is detachably connected to a relay box, a junction box, or a connector.

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