JP6945036B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device.

SiC (silicon carbide: silicon carbide) is superior to Si (silicon) in dielectric breakdown resistance and thermal conductivity. Therefore, SiC is attracting attention as a semiconductor suitable for applications such as an inverter of a hybrid vehicle, for example. MISFETs (Metal Insulator Semiconductor Field Effect Transistors) using SiC are expected as high withstand voltage devices suitable for inverters of hybrid vehicles and the like.

As an example of a MISFET using SiC, Patent Document 1 describes an n-type SiC substrate, an n-type drift layer formed on the SiC substrate, a p-type well region formed on the drift layer, and a p-type well. A SiC semiconductor device including an n-type source region formed in a region, a gate insulating film formed on the surface of a drift layer, and a gate electrode formed on the gate insulating film is disclosed.

JP-A-2009-16530 Special Table 2002-524860

One embodiment of the present invention has a laminated structure including a plurality of insulating layers, and a portion covering the opening end side edge portion of the gate trench and a portion covering the bottom surface side edge portion of the gate trench are formed in a convex curved shape. Provided is a semiconductor device provided with a gate insulating layer having the above-mentioned structure.

One embodiment of the present invention is composed of a semiconductor layer made of SiC and having a gate trench having side surfaces and a bottom surface, a first insulating layer laminated in this order from the semiconductor layer side, and the first insulating layer. It has a laminated structure including a different second insulating layer, and has a gate insulating layer formed along the side surface and the bottom surface of the gate trench and the surface of the semiconductor layer, and the inside of the gate trench via the gate insulating layer. With respect to the source region, body region, and drain region that are embedded in the gate trench and do not bulge above the opening edge of the gate trench and form the inner surface of the gate trench, the side surfaces and the bottom surface thereof sandwich the gate insulating layer. Covers the upper surface of the gate electrode and the upper surface of the gate insulating layer covering the surface of the semiconductor layer at the opening edge of the gate trench, and the end faces of the first insulating layer and the second insulating layer. An open end of the gate trench that includes an interlayer insulating film having an end face formed so as to be flush with the gate trench and connects the side surface of the gate trench and the surface of the semiconductor layer in the second insulating layer of the gate insulating layer. The portion covering the side edge portion is formed in a convex curved shape toward the inside of the gate trench, and the gate trench connecting the side surface and the bottom surface of the gate trench in the second insulating layer of the gate insulating layer. Provided is a semiconductor device in which a portion covering the bottom surface side edge portion of the semiconductor device is formed in a convex curved shape toward the outside of the gate trench.

In one embodiment of the present invention, a semiconductor layer made of GaN and having side and bottom gate trenches formed from the surface, a first insulating layer laminated in this order from the semiconductor layer side, and the first insulating layer. It has a laminated structure including a second insulating layer having a different composition, a gate insulating layer formed along the side surface and the bottom surface of the gate trench and the surface of the semiconductor layer, and a gate trench via the gate insulating layer. With respect to the source region, body region, and drain region that are embedded in the gate trench and do not bulge above the opening edge of the gate trench and form the inner surface of the gate trench, the side surfaces and the bottom surface thereof sandwich the gate insulating layer. Covers the upper surface of the gate electrode and the upper surface of the gate insulating layer covering the surface of the semiconductor layer at the opening edge of the gate trench, and the end faces of the first insulating layer and the second insulating layer. An open end of the gate trench that includes an interlayer insulating film having an end face formed so as to be flush with the gate trench and connects the side surface of the gate trench and the surface of the semiconductor layer in the second insulating layer of the gate insulating layer. The portion covering the side edge portion is formed in a convex curved shape toward the inside of the gate trench, and the gate trench connecting the side surface and the bottom surface of the gate trench in the second insulating layer of the gate insulating layer. Provided is a semiconductor device in which a portion covering the bottom surface side edge portion of the semiconductor device is formed in a convex curved shape toward the outside of the gate trench.

FIG. 1 is a cross-sectional view of a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view of the semiconductor device according to the second embodiment of the present invention. FIG. 3 is simulation data for demonstrating the dependence of the gate leak current on the _{thickness of the underlying SiO 2 film.} FIG. 4 is a perspective view of a semiconductor device used in an experimental example for demonstrating the dependence of the gate leak current. FIG. 5 is a JE curve for demonstrating the dependence of the gate leak current in the semiconductor device of FIG. FIG. 6 is a CV curve of the semiconductor device of FIG. 4 for demonstrating the dependence of _{the shift of the flat band voltage VFB} on the thickness of the underlying SiO _{2 film.} FIG. 7 is a graph for demonstrating the dependence of the shift amount of the _{flat band voltage VFB on the thickness of the underlying SiO 2 film.} FIG. 8 is a graph showing the composition of the AlON film (CVD1 film) produced according to the CVD1 method in the depth direction. FIG. 9 is a graph showing the composition of the AlON film (CVD2 film) produced according to the CVD2 method in the depth direction. FIG. 10 is a graph showing the composition of the AlON film (PVD film) produced according to the PVD method in the depth direction. FIG. 11 is a graph for demonstrating the dependence of the shift of _{the flat band voltage VFB on the N composition.} FIG. 12 is a graph for demonstrating the effect of suppressing the _{flat band voltage VFB by the AlON film.} FIG. 13 is a graph showing the relationship between the _{flat band voltage VFB and the nitrogen composition.}

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view of a semiconductor device according to the first embodiment of the present invention.
The semiconductor device 1 includes an n ⁺ type (for example, a concentration of 1 × 10 ^{19 to} 5 × 10 ¹⁹ cm ^{-3 ) SiC substrate 2 and an n −} type (for example, a concentration of 1 ×) formed on the SiC substrate 2. Includes 10 ¹⁵ to 1 × 10 ¹⁶ cm ^-3 ) SiC epitaxial layer 3. The SiC substrate 2 and the SiC epitaxial layer 3 are examples of the "semiconductor layer" of the present invention. The SiC substrate 2 and the SiC epitaxial layer 3 function as drains of the semiconductor device 1. Phosphorus (P), arsenic (As) and the like are included as n-type impurities. Hereinafter, the n-type SiC contains similar n-type impurities.

The SiC epitaxial layer 3 is formed with a gate trench 4 dug down from the surface thereof toward the SiC substrate 2. The gate trench 4 is formed in a grid pattern or a stripe pattern, for example. As a result, a plurality of unit cells 5 partitioned by the gate trench 4 are formed in the SiC epitaxial layer 3.
In the SiC epitaxial layer 3, around the gate trench 4, an n ⁺ type source region 6 and a p-type body region 7 (for example, a concentration of 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ^-3 ) are formed in the SiC epitaxial layer. It is formed in this order from the side closer to the surface of No. 3. The body region 7 contains, for example, boron (B), aluminum (Al), and the like as p-type impurities. Hereinafter, the p-type SiC contains similar p-type impurities.

The source region 6 is formed on the surface portion of each unit cell 5 so as to be exposed on the surface of the SiC epitaxial layer 3 and form an upper portion (part) of the side surface of the gate trench 4. On the other hand, the body region 7 forms a lower portion (part) of the side surface of the gate trench 4 so as to be in contact with the source region 6 on the side of the SiC substrate 2 (the back surface side of the SiC epitaxial layer 3) with respect to the source region 6. It is formed to do.

In the SiC epitaxial layer 3, region of the SiC substrate 2 side with respect to the body region 7, in the state after the epitaxial growth is maintained, n ^- has a -type drain region 8. The drain region 8 is in contact with the body region 7 on the SiC substrate 2 side with respect to the body region 7, and forms the bottom surface of the gate trench 4.
A gate insulating film 9 is formed on the inner surface of the gate trench 4 so as to cover the entire area thereof. _{The gate insulating film 9 includes a base SiO 2} film 10, an AlON film 11 and an upper SiO ₂ film 12 laminated in order from the inner surface side of the gate trench 4. _{In this embodiment, the base SiO 2} film 10 is formed so as to be in contact with the entire inner surface of the gate trench 4, and the AlON film 11 and the upper SiO ₂ film 12 having the _{same shape as the base SiO 2 film 10 are directly below the base SiO 2 film 10.} They are laminated in order so as to cover the entire area of the film. The three-layer structure of these films may be formed over the entire inner surface of the gate trench 4 as in this embodiment, or the channel portion on the inner surface of the gate trench 4 (the body on the side surface of the gate trench 4). It may be selectively formed in the portion where the region 7 is exposed). In this case, the other portion of the gate insulating film 9 may be a single-layer film made of _{SiO 2.} Further, the gate insulating film 9 may be a single-layer film of the AlON film 11 or a film having a two-layer structure in which the _{upper SiO 2 film 12 is omitted (underlayer SiO 2} film 10 / AlON film 11). May be good. Further, in this embodiment, the gate insulating film 9 may be formed so as to cover the edge portion on the open end side of the gate trench 4. The edge portion on the open end side of the gate trench 4 forms a sandwiching angle between the surface of the SiC epitaxial layer 3 and the side surface of the gate trench 4. Therefore, each vicinity of the surface of the SiC epitaxial layer 3 and the side surface of the gate trench 4 in the source region 6 is covered with the gate insulating film 9.

The thickness of the gate insulating film 9 is, for example, 55 nm to 150 nm. The preferable range of the thickness of each film is that the base SiO ₂ film 10 is 5 nm or more (more preferably 5 nm to 20 nm), the AlON film 11 is 50 nm or more (more preferably 50 nm to 100 nm), and the upper SiO is _{The two} films 12 are 0 nm or more (more preferably 0 nm to 30 nm).
In this embodiment, the base SiO ₂ film 10 is formed by, for example, thermal oxidation of the SiC epitaxial layer 3. By using a film in contact with the SiC epitaxial layer 3 (particularly, the channel portion) as a thermal oxide film, it is possible to exhibit excellent transistor characteristics as compared with a deposited film such as a CVD film.

The AlON film 11 is a film in which nitrogen (N) atoms are dispersed in the film, and is, for example, a film having a nitrogen composition of 5% to 40% (preferably 15% to 35%). The nitrogen composition is within the above range at any position in the depth direction of the AlON film 11. That is, the nitrogen composition of the AlON film 11 is substantially constant in the depth direction, and is preferably within ± 5% to ± 20% with respect to the average value in the depth direction. The composition of other atoms (Al, O) of the AlON film 11 is preferably substantially constant in the depth direction. When the nitrogen composition is within the above range, the flat band voltage _VFB of the semiconductor device 1 can be suppressed more satisfactorily, and the gate leakage current can be reduced. Further, the AlON film 11 is preferably amorphous or microcrystal. If the AlON film 11 has such a structure, the crystal grain boundaries in the gate insulating film 9 can be reduced, so that the gate leakage current can be reduced.

The upper SiO ₂ film 12 is mainly made of silicon oxide, but Al and / or N may be contained in the interface portion (near the interface) with the AlON film 11. With this configuration, electron injection into the gate insulating film 9 can be suppressed.
Such a gate insulating film 9 can be formed, for example, by forming a gate trench 4 in the SiC epitaxial layer 3 and then laminating the base SiO ₂ film 10, the AlON film 11 and the upper SiO ₂ film 12 in this order. .. The base SiO ₂ film 10 can be formed by, for example, a thermal oxidation method (for example, 1100 ° C. to 1300 ° C.). Further, the AlON film 11 can be formed by depositing each atom by, for example, an ALD (Atomic Layer Deposition) method, a CVD method, a PVD (Physical Vapor Deposition) method, or the like. Further, the upper SiO ₂ film 12 can be formed by, for example, a CVD method.

After the formation of the AlON film 11, PDA (Post Deposition Annealing) may be performed at, for example, 700 ° C. to 1000 ° C. As a result, the shift of the flat band voltage V _FB can be suppressed more satisfactorily.
In the gate trench 4, the gate electrode 13 is embedded inside the gate insulating film 9. In this way, a trench gate type MIS structure is configured in which the gate electrode 13 faces the source region 6, the body region 7, and the drain region 8 forming the inner surface of the gate trench 4 with the gate insulating film 9 interposed therebetween.

The gate electrode 13 is preferably made of a metal containing at least one selected from the group consisting of Mo, W, Cu, Ni, Al, Ti, Ag, Au and Pt, but is made of polysilicon (eg, impurities are doped. It may consist of polysilicon).
A source trench 14 is formed in the central portion of each unit cell 5 so as to be dug from the surface of the SiC epitaxial layer 3 toward the SiC substrate 2. The source trench 14 penetrates the source region 6 and the body region 7 from the surface of the SiC epitaxial layer 3 and reaches the drain region 8. In this embodiment, the source trench 14 is formed at the same depth as the gate trench 4.

In the SiC epitaxial layer 3, a p-type region 15 is formed around the source trench 14. The p-type region 15 is exposed on the inner surface of the source trench 14 so as to be continuous with (connect to) the body region 7 in the lower region of the body region 7. That is, the p-type region 15 is interposed between the drain region 8 and the inner surface of the source trench 14 in the lower region. As a result, the p-shaped region 15 is exposed on the bottom surface and the bottom edge portion of the source trench 14.

Further, in the p-type region 15, a p ⁺ -type body contact region 16 is formed on the bottom surface of the source trench 14. In this embodiment, the body contact region 16 is located in the central portion spaced inward from the side surface of the source trench 14.
An interlayer insulating film 17 is formed on the SiC epitaxial layer 3 so as to cover the gate electrode 13. A contact hole 18 having a diameter larger than that of the source trench 14 is formed in the interlayer insulating film 17. As a result, the entire source trench 14 of each unit cell 5 (that is, the entire inner surface of the source trench 14) and a part of the source region 6 are exposed in the contact hole 18.

A source electrode 19 is formed on the interlayer insulating film 17. The source electrode 19 collectively enters the source trench 14 of all the unit cells 5 through each contact hole 18. The source electrode 19 is in contact with the body contact region 16, the p-type region 15, the body region 7, and the source region 6 in this order from the bottom side of the source trench 14. That is, the source electrode 19 has a common wiring for all the unit cells 5. In this embodiment, the source electrode 19 has a structure in which a Ti / TiN layer and an Al layer are laminated in order from the contact side with the SiC epitaxial layer 3.

A drain electrode 20 is formed on the back surface of the SiC substrate 2 so as to cover the entire area thereof. The drain electrode 20 is a common electrode for all unit cells 5. As the drain electrode 20, for example, a laminated structure (Ti / Ni / Au / Ag) in which Ti, Ni, Au and Ag are laminated in order from the SiC substrate 2 side can be applied.
According to the semiconductor device 1, since the gate insulating film 9 contains the AlON film 11 having a nitrogen composition of 5% to 40%, electron traps in the gate insulating film 9 can be reduced. As a result, the shift of the flat band voltage V _FB can be suppressed, so that the shift of the threshold voltage V _th can be suppressed.

Further, by appropriately thickening the AlON film 11, the gate insulating film 9 can be thickened as a whole while maintaining the same gate capacitance as compared with the case where the single layer film of _{SiO 2 is used as the gate insulating film.} Therefore, even if the gate is driven with a high voltage, deterioration of the gate insulating film 9 can be suppressed. As a result, it is possible to suppress a decrease in the reliability of the device.
_{Further, by interposing the underlying SiO 2} film 10 below the AlON film 11 and further setting the film thickness to 5 nm or more, the rising electric field of the gate leak current can be increased. As a result, it is possible to suppress the generation of leakage current during normal drive of the gate.

Further, _{by laminating the upper SiO 2} film 12 on the AlON film 11 and covering the AlON film 11 from above, the AlON film 11 can be protected from chemicals used for etching or cleaning, for example, when the gate electrode 13 is formed. .. As a result, it is possible to prevent the AlON film 11 from being damaged.
Further, if the gate electrode 13 is a metal gate, the film can be formed at a lower temperature than the polysilicon gate. Therefore, the temperature environment at the time of the film formation can be suppressed to a low level. For example, the film formation of metal is performed at about 200 ° C., whereas the temperature environment reaches 1000 ° C. in the film formation of polysilicon. As a result, it becomes difficult for the previously formed AlON film 11 to reach the crystallization temperature, so that the crystallization of the AlON film 11 can be suppressed. As a result, it is possible to suppress an increase in the gate leak current due to an increase in grain boundaries. Further, since the gate resistance can be reduced as compared with the polysilicon gate, a faster switching operation can be realized and the switching loss can be reduced.

FIG. 2 is a cross-sectional view of the semiconductor device according to the second embodiment of the present invention. In FIG. 2, the same reference numerals are given to the parts corresponding to the parts shown in FIG. 1 described above.
In the first embodiment described above, the MIS structure is a trench in which the gate electrode 13 faces the source region 6, the body region 7, and the drain region 8 forming the inner surface of the gate trench 4 with the gate insulating film 9 interposed therebetween. It is composed of a gate type.

On the other hand, the MIS structure of the semiconductor device 41 according to the second embodiment is configured as a planar gate type.
The planar gate type MIS structure includes a p-type body region 42 selectively formed on the surface portion of the SiC epitaxial layer 3 and an n ⁺ -type source region 43 selectively formed in the body region 42. A gate insulating film 44 formed on the surface of the SiC epitaxial layer 3, a gate electrode 45 facing the body region 42 exposed on the surface of the SiC epitaxial layer 3 with the gate insulating film 44 interposed therebetween, and the surface of the SiC epitaxial layer 3. ^{Includes a p +} -shaped body contact region 46 that penetrates the source region 43 and reaches the body region 42 at the deepest portion.

Similar to the gate insulating film 9 of the first embodiment, the gate insulating film 44 of the semiconductor device 41 also has the underlying SiO ₂ film 47, the AlON film 48, and the upper SiO ₂ film laminated in order from the surface side of the SiC epitaxial layer 3. 49 is included, and the same effects as those of the semiconductor device 1 of the first embodiment can be exhibited.
Although the embodiments of the present invention have been described above, the present invention can also be implemented in other embodiments.

For example, in the semiconductor devices 1 and 41, a configuration in which the conductive type of each semiconductor portion is inverted may be adopted. For example, in the semiconductor device 1, the p-type portion may be n-type and the n-type portion may be p-type.
Further, in the above-described embodiment, the semiconductor device 1 having a SiC layer is taken up as an example of the semiconductor device of the present invention, but the structure described in the above-described embodiment is applied to a semiconductor device having a layer made of GaN and diamond. You can also do it.

Further, in the above-described embodiment, the trench gate type and planar gate type MISFETs are taken up as an example of the present invention, but the present invention is also applied to a MIS transistor structure such as a CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor). be able to.
In addition, various design changes can be made within the scope of the matters described in the claims.
<Verification example>
The effects of (1) to (6) below were confirmed by performing the following verification examples.
(1) Dependence of gate leak current on _{the thickness of the underlying SiO 2} film (simulation)
First, it was verified using a simulation device how the gate leak current changes with the change in the thickness _{of the base SiO 2} film 10 in the above-described embodiment. The simulation conditions were such that _{the thickness of the base SiO 2} film 10 was 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, and 6 nm. The results are shown in FIG.

According to FIG. 3, _{it was found that the thicker the base SiO 2} film 10 is, the more the gate leak current can be reduced. In particular, it can be seen that the gate leak current can be effectively reduced when the thickness of _{the underlying SiO 2 film 10 is 5 nm or more.}
(2) Dependence of gate leak current on the _{thickness of the underlying SiO 2} film (experimental example)
Next, a specific experiment was conducted to demonstrate the dependence of the gate leak current on the _{thickness of the underlying SiO 2 film. First, the base SiO 2} film was formed by thermally oxidizing (dry oxidizing) the (0001) surface of the n-type 4H-SiC substrate. Next, the AlON film was deposited at 90 nm by the CVD method. Then, without performing heat treatment, an aluminum film was deposited by a sputtering method, and the aluminum film was patterned by photolithography to form an aluminum pad. As a result, the MIS structure shown in FIG. 4 was produced. The experimental conditions were that _{the thickness of the underlying SiO 2} film was none (0 nm), less than 6 nm, 6 nm and 13 nm. The EOT (Equivalent Oxide Thickness) of each experimental example was 143.8 nm, 57.6 nm, 58.6 nm and 66.9 nm, respectively, in the order of description of the above experimental conditions.

Next, the JE characteristics of the MIS structure shown in FIG. 4 were determined. The results are shown in FIG. In FIG. 5, the curve indicated by “Ref.” Is a JE curve having a MIS structure in _{which a NOx—SiO 2} film (48 nm) is used instead of the gate insulating film composed _{of the underlying SiO 2 film and the AlON film.}
According to FIG. 5, the rising electric fields of the gate leak current in each experimental example are “none” = about 2 MV / cm, “<6 nm” = about 4 MV / cm, “6 nm” = about 6 MV / cm, and “13 nm” = It was about 6 MV / cm. From these experimental examples, the rising electric field of the gate leak current is higher _{when the underlying SiO 2} film is interposed between the substrate and the 4H-SiC substrate than when the AlON film is directly formed on the substrate (“none”). I found that I could do it. In particular, _{it was found that the base SiO 2} film is preferably 6 nm or more. From this experimental example and the result of the simulation, _{it was found that if the thickness of the underlying SiO 2} film 10 is 5 nm or more, the gate leakage current during normal drive of the gate can be effectively reduced.
(3) Dependence of shift of flat band voltage V _FB on the thickness of the underlying SiO ₂ film Next, for the MIS structure of FIG. 4, the starting voltage is set to 10 V, and the MIS structure is swept from + 10 V to -10 V to + 10 V. The CV characteristics at that time were obtained. The results are shown in FIG.

_{According to FIG. 6, in the MIS structure (<6 nm, 6 nm and 13 nm) having a structure in which the underlying SiO 2} film is interposed between the AlON film and the substrate, the case where the AlON film is directly formed on the 4H-SiC substrate (““ 6 nm, 6 nm and 13 nm) It was found that the shift amount of _{the flat band voltage VFB} can be reduced as compared with "none").
(4) Dependence of shift amount of flat band voltage V _{FB on} the thickness of the underlying SiO ₂ film Next, according to (3) above, the CV characteristics were obtained even under the condition that the starting voltage was changed. The conditions for changing the starting voltage were from + 5V to + 60V in 5V increments. The relationship between the accumulated voltage (Accumulation Voltage) and the flatband voltage (Flatband Voltage) at this time is shown in FIG.

According to FIG. 7, it was found that the _{thicker the base SiO 2} film 10 is, the more _{the shift amount of the flat band voltage VFB} can be reduced if the accumulated voltage is the same. For example, when the accumulated voltage is 45 V, the shift amount of each MIS structure is found to be "<6 nm" = about 9 V, "6 nm" = about 5 V, and "13 nm" = about 1 V.
(5) Dependence of the shift of the flat band voltage V _FB on the N composition Next, a concrete experiment was conducted to demonstrate the dependence of the shift of the _{flat band voltage V FB on the N composition.} As an experimental sample, the MIS structure shown in FIG. 4 was prepared according to the method described in (2) above. However, three patterns of experimental samples having different methods for forming the AlON film were prepared. There are three film forming methods adopted: the CVD1 method, the CVD2 method, and the PVD method. The compositions of the obtained CVD1 film, CVD2 film, and PVD film are shown in FIGS. 8 to 10, respectively. Further, for the CVD1 film and the CVD2 film, samples (CVD1 + PDA, CVD2 + PDA) in which PDA was performed after film formation were also prepared.

Next, the CV characteristics of each sample were determined according to the measurement methods described in (3) and (4) above. Then, based on the obtained CV characteristics, the relationship between the accumulated voltage (Accumulation Voltage) and the flatband voltage (Flatband Voltage) was investigated. The results are shown in FIG.
According to FIG. 11, it was found that the CVD1 film having a higher N composition (concentration) than the CVD2 film can reduce the shift amount of the _{flat band voltage VFB.} For example, when the storage voltage is 55V, the shift amount of the CVD2 film sample is about 15V, while the shift amount of the CVD1 film sample is about 10V. Further, regarding the presence or absence of PDA after film formation, it was found that the shift amount can be reduced by performing PDA as compared with the case where PDA is not performed.
(6) Effect of suppressing flat band voltage V _FB by AlON film Next, the shift amount _{of flat band voltage V FB} when the PDA film obtained in (5) above was used _{was the Al 2} O ₃ film. We investigated how much it was suppressed compared to the case. The results are shown in FIG.

According to FIG. 12, it was found that the shift amount of the flat band voltage _{VFB becomes very large when the Al 2} O _{3 film having an N composition of 0% is used.} As a result, it was found that the shift of the _{flat band voltage VFB} can be suppressed by including the AlON film in the gate insulating film. Therefore, in the MIS structure having the gate insulating film including the AlON film, the shift of the _{threshold voltage Vth can be suppressed.}
(7) Relationship between flat band voltage V _FB and nitrogen composition Next, _{in order to demonstrate the dependence of the shift of flat band voltage V FB} on the N composition (fixed accumulated voltage), the above (2) is used as an experimental sample. The MIS structure shown in FIG. 4 was produced on a Si substrate according to the method described. Eight kinds of experimental samples having different N compositions were prepared. Then, it was verified how the shift of the flat band voltage V _FB of each sample changed when the accumulated voltage Vacc was 25 V and 30 V. The results are shown in FIG. The obtained verification result is the data on the Si substrate, and is the reference data when the same verification is performed on the MIS structure on the SiC substrate. From FIG. 13, when the N composition is 15% or more, _{the shift of the flat band voltage VFB} is small, which is preferable. Further, if the N composition is large, the dielectric constant is lowered, so that the N composition is preferably 35% or less.

Examples of features extracted from this specification and drawings are shown below.
Item 1: The gate insulating film has a MIS structure including a semiconductor layer, a gate insulating film in contact with the semiconductor layer, and a gate electrode formed on the gate insulating film, and the gate insulating film has a nitrogen composition of 5% to 40%. A semiconductor device containing a% AlON layer.
One of the problems of SiC-MISFET is low channel mobility. The low channel mobility is due to defects (many interface states) present at high density at the MIS interface of SiC. That is, this defect traps holes or electrons, making it difficult to form channels at the MIS interface.

Conventionally, a relatively thin SiO ₂ film is used as a gate insulating film, and by driving the gate with a higher electric field than that of a Si-MISFET, the captured holes or electrons are easily released from defects. However, this method accelerates the deterioration of the gate insulating film and may lead to a decrease in the reliability of the device.
On the other hand, if a high dielectric constant film (Highk film) such _{as Al 2} O ₃ film or HfO ₂ is used as the gate insulating film, the film thickness can be increased as compared with the _{SiO 2 film while maintaining the same gate capacitance.} Maybe. However, in this case, there arises a problem that electrons are captured in the gate insulating film, the flat band voltage V _FB shifts, and the threshold voltage V _{th shifts.}

Due to such problems, there is an actual situation that a semiconductor device capable of reducing electron traps in the gate insulating film _{and suppressing the shift of the threshold voltage Vth is required.}
According to the configuration of Item 1, since the gate insulating film contains an AlON layer having a nitrogen composition of 5% to 40%, electron trapping into the gate insulating film can be reduced. As a result, the shift of the flat band voltage V _FB can be suppressed, so that the shift of the threshold voltage V _th can be suppressed. Moreover, the gate leak current can be reduced. Further _{, as compared with the case of using a single layer film of SiO 2,} the thickness can be increased while maintaining the same gate capacitance, so that deterioration of the gate insulating film can be suppressed even if the gate is driven with a high voltage. As a result, it is possible to suppress a decrease in the reliability of the device.

Item 2: The semiconductor device according to Item 1, wherein the AlON layer has a thickness of 50 nm or more.
Item 3: The semiconductor device according to Item 1 or 2, wherein the AlON layer is amorphous or microcrystal.
With this configuration, the grain boundaries in the gate insulating film can be reduced, so that the gate leak current can be reduced.

_{Item 4: The gate insulating film has a laminated structure including two} layers of base SiO in contact with the semiconductor layer and the _{AlON layer laminated on the two} layers of base SiO, according to any one of Items 1 to 3. The semiconductor device described.
If the portion of the gate insulating film in contact with the semiconductor layer is SiO ₂ , the shift amount of the flat band voltage _{VFB can be reduced.} Further, since the characteristics of the transistor having the MIS structure can be controlled in the same manner as in the conventional case, the design of the transistor characteristics can be simplified. The base SiO ₂ layer is preferably a thermal oxide film.

Item 5: The semiconductor device according to Item 4, wherein the base SiO ₂ layer has a thickness of 5 nm or more.
With this configuration, the rising electric field of the gate leak current can be increased, so that the generation of the leak current during normal drive of the gate can be suppressed.
Item 6: The semiconductor device according to Item 4 or 5, _{wherein the laminated structure further includes two} upper SiO layers laminated on the AlON layer.

With this configuration, the AlON layer is covered from above, so that the AlON layer can be protected from chemicals used for etching and cleaning, for example, when forming a gate electrode. As a result, it is possible to prevent the AlON layer from being damaged.
Item 7: The semiconductor device according to Item 6, wherein the upper SiO ₂ layer contains Al and / or N at an interface with the AlON layer.

With this configuration, electron injection into the gate insulating film can be suppressed.
Item 8. The semiconductor device according to any one of Items 1 to 7, wherein the semiconductor layer is made of SiC, GaN or diamond.
Item 9: The gate electrode is made of polysilicon or a metal containing at least one selected from the group consisting of Mo, W, Cu, Ni, Al, Ti, Ag, Au and Pt, Items 1 to 8. The semiconductor device according to any one of the above.

In the case of a metal electrode (metal gate), for example, the film can be formed at a lower temperature than that of a polysilicon electrode (polysilicon gate), so that the temperature environment at the time of the film formation can be suppressed to a low level. This makes it difficult for the AlON layer to reach the crystallization temperature, so that crystallization of the AlON layer can be suppressed. As a result, it is possible to suppress an increase in the gate leak current due to an increase in grain boundaries. Further, since the gate resistance can be reduced as compared with the polysilicon gate, a faster switching operation can be realized and the switching loss can be reduced.

Item 10. The semiconductor device according to any one of Items 1 to 9, wherein the MIS structure includes a trench gate type structure.
Item 11. The semiconductor device according to any one of Items 1 to 10, wherein the MIS structure includes a planar gate structure.
Item 12: An amorphous or microcrystal _{having a semiconductor layer made of SiC, two} underlying SiO layers laminated on the semiconductor layer, and a nitrogen composition of 5% or more and 40% or less, _{and laminated on the underlying SiO 2 layers.} A gate insulating film having a laminated structure including an _{AlON layer and an upper SiO 2} layer laminated on the AlON layer, containing Al and / or N at an interface with the AlON layer, and suppressing electron injection from the outside. A semiconductor device including a gate electrode formed on the gate insulating film.

According to the configuration of Item 12, since the gate insulating film contains an AlON layer having a nitrogen composition of 5% or more and 40% or less, electron traps in the gate insulating film can be reduced. As a result, the shift of the flat band voltage V _FB can be suppressed, so that the shift of the threshold voltage V _th can be suppressed. Moreover, the gate leak current can be reduced. Further _{, as compared with the case of using a single layer film of SiO 2,} the thickness can be increased while maintaining the same gate capacitance, so that deterioration of the gate insulating film can be suppressed even if the gate is driven with a high voltage. As a result, it is possible to suppress a decrease in the reliability of the device.

The AlON layer is amorphous or microcrystal. With this configuration, the grain boundaries in the gate insulating film can be reduced, so that the gate leak current can be reduced.
Further, the gate insulating film has a laminated structure including a _{base SiO 2} layer in contact with the semiconductor layer, an AlON layer laminated on the base SiO _{2 layer, and an upper SiO 2 layer laminated on the AlON layer.} There is. If the portion of the gate insulating film in contact with the semiconductor layer is SiO ₂ , the shift amount of the flat band voltage _{VFB can be reduced.} Moreover, since the characteristics of the transistor can be controlled in the same manner as in the conventional case, the design of the transistor characteristics can be simplified.

Further, since the AlON layer is covered from the upper side by the upper SiO ₂ layer, the AlON layer can be protected from chemicals used for etching or cleaning, for example, when forming a gate electrode. As a result, it is possible to prevent the AlON layer from being damaged. The base SiO ₂ layer is preferably a thermal oxide film.
Further, the upper SiO ₂ layer contains Al and / or N at the interface with the AlON layer. As a result, electron injection into the gate insulating film can be suppressed. As a result, the effect of reducing the electron trap and the effect of reducing the gate leak current can be enhanced.

Item 13: The semiconductor device according to Item 12, wherein the AlON layer has a thickness of 50 nm or more.
Item 14: The semiconductor device according to Item 12 or 13, wherein the base SiO _{2 layer has a thickness of 5 nm or more.} With this configuration, the rising electric field of the gate leak current can be increased, so that the generation of the leak current during normal drive of the gate can be suppressed.
Item 15. The semiconductor device according to any one of Items 12 to 14, wherein the gate insulating film has a thickness of more than 55 nm and 150 nm or less.

Item 16: The semiconductor device according to any one of Items 12 to 15, wherein the gate electrode is made of metal.
In this case, in addition to the AlON layer being amorphous or microcrystal, the gate electrode is made of metal. Therefore, since the film can be formed at a lower temperature than, for example, a polysilicon electrode (polysilicon gate), the temperature environment at the time of the film formation can be suppressed to a low level. This makes it difficult for the AlON layer to reach the crystallization temperature, so that crystallization of the AlON layer can be suppressed. As a result, it is possible to suppress an increase in the gate leak current due to an increase in grain boundaries. Further, since the gate resistance can be reduced as compared with the polysilicon gate, a faster switching operation can be realized and the switching loss can be reduced.

Item 17: The semiconductor device according to any one of Items 12 to 16, wherein the gate electrode contains at least one of Mo, W, Cu, Ni, Al, Ti, Ag, Au and Pt.
Item 2. The semiconductor device according to any one of Items 12 to 15, wherein the gate electrode is made of polysilicon.
In the case of a metal electrode (metal gate), for example, the film can be formed at a lower temperature than the polysilicon electrode (polysilicon gate), so that the temperature environment at the time of the film formation can be suppressed to a low level. This makes it difficult for the AlON layer to reach the crystallization temperature, so that crystallization of the AlON layer can be suppressed. As a result, it is possible to suppress an increase in the gate leak current due to an increase in grain boundaries. Further, since the gate resistance can be reduced as compared with the polysilicon gate, a faster switching operation can be realized and the switching loss can be reduced.

Item 18: The semiconductor device according to any one of Items 12 to 17, wherein a gate trench is formed in the semiconductor layer.
Item 19: The gate insulating film of the semiconductor layer is added to the inner surface of the gate trench so as to cover the surface of the semiconductor layer and the edge portion on the open end side of the gate trench connecting the side surfaces of the gate trench. Item 2. The semiconductor device according to Item 18, which is formed along the surface.

Item 20: The semiconductor device according to Item 18 or 19, wherein the gate electrode is embedded in the gate trench via the gate insulating film.
Item 21: In the semiconductor layer, a first conductive type source region, a second conductive type body region, and a second conductive type body region formed in this order from the surface of the semiconductor layer along the side surface of the gate trench in this order. Item 6. The semiconductor device according to any one of Items 18 to 20, further comprising a first conductive type drain region.

Item 22: The semiconductor device according to Item 21, wherein the gate electrode faces the source region, the body region, and the drain region with the gate insulating film interposed therebetween.
Item 23: The item according to any one of Items 12 to 17, wherein the gate insulating film is laminated on the surface of the semiconductor layer, and the gate electrode is laminated on the gate insulating film. Semiconductor device.

1 Semiconductor device 2 SiC substrate 3 SiC epitaxial layer 4 gate trench 9 gate insulating film 10 base SiO ₂ film 11 AlON film 12 upper SiO ₂ film 13 gate electrode 41 semiconductor device 44 gate insulating film 45 gate electrode 47 base SiO ₂ film 48 AlON Film 49 Upper SiO ₂ film

Claims (23)

A semiconductor layer made of SiC and having side and bottom gate trenches formed from the surface,
It has a laminated structure including a first insulating layer laminated in this order from the semiconductor layer side and a second insulating layer having a composition different from that of the first insulating layer, and has a side surface and a bottom surface of the gate trench and the semiconductor layer. A gate insulating layer formed along the surface and
Without bulging upward of the opening edge portion of the gate trench be embedded through the gate insulating layer in the gate trench, a source region forming the outer surface of the gate trench, with respect to the body region and the drain region , The gate electrodes whose side surfaces and bottom surfaces face each other across the gate insulating layer,
It covers the upper surface of the gate electrode and the upper surface of the gate insulating layer covering the surface of the semiconductor layer at the opening edge of the gate trench so as to be flush with the end faces of the first insulating layer and the second insulating layer. Including an interlayer insulating film on which an end face is formed,
The portion of the second insulating layer of the gate insulating layer that covers the side surface of the gate trench and the edge portion on the open end side of the gate trench connecting the surface of the semiconductor layer is a convex curve toward the inside of the gate trench. It is formed in a shape
The portion of the second insulating layer of the gate insulating layer that covers the side surface and the bottom surface of the gate trench and covers the bottom surface side edge portion of the gate trench is formed in a convex curved shape toward the outside of the gate trench .
A semiconductor device in which the gate electrode includes a portion made of Mo, Cu, Au, Ni, Pt or TiN at least in a portion in contact with the second insulating layer . A semiconductor layer made of GaN with side and bottom gate trenches formed from the surface,
It has a laminated structure including a first insulating layer laminated in this order from the semiconductor layer side and a second insulating layer having a composition different from that of the first insulating layer, and has a side surface and a bottom surface of the gate trench and the semiconductor layer. A gate insulating layer formed along the surface and
Without bulging upward of the opening edge portion of the gate trench be embedded through the gate insulating layer in the gate trench, a source region forming the outer surface of the gate trench, with respect to the body region and the drain region , The gate electrodes whose side surfaces and bottom surfaces face each other across the gate insulating layer,
It covers the upper surface of the gate electrode and the upper surface of the gate insulating layer covering the surface of the semiconductor layer at the opening edge of the gate trench so as to be flush with the end faces of the first insulating layer and the second insulating layer. Including an interlayer insulating film on which an end face is formed,
The portion of the second insulating layer of the gate insulating layer that covers the side surface of the gate trench and the edge portion on the open end side of the gate trench connecting the surface of the semiconductor layer is a convex curve toward the inside of the gate trench. It is formed in a shape
The portion of the second insulating layer of the gate insulating layer that covers the side surface and the bottom surface of the gate trench and covers the bottom surface side edge portion of the gate trench is formed in a convex curved shape toward the outside of the gate trench .
A semiconductor device in which the gate electrode includes a portion made of Mo, Cu, Au, Ni, Pt or TiN at least in a portion in contact with the second insulating layer . The gate insulating layer includes the first insulating layer laminated in this order from the semiconductor layer side, the second insulating layer having a composition different from that of the first insulating layer, and a second insulating layer having the same composition as the first insulating layer. It has a laminated structure including three insulating layers, and has a laminated structure.
The semiconductor device according to claim 1 or 2, wherein the interlayer insulating film has an end face formed so as to be flush with the end faces of the first insulating layer, the second insulating layer, and the third insulating layer. The semiconductor device according to any one of claims 1 to 3, wherein the second insulating layer has a thickness of 50 nm or more. The semiconductor device according to any one of claims 1 to 4, wherein the first insulating layer has a thickness of 5 nm or more. The semiconductor device according to any one of claims 1 to 5, wherein the gate insulating layer has a thickness of more than 55 nm and 150 nm or less. Said body region, said the surface layer portion of the semiconductor layer is a first conductivity type realm of which is formed in a region along the sidewall of the gate trench, the semiconductor device according to claim 1 or 2. The source region is a second conductivity type realm of which is formed in a region along the sidewall of the gate trench is formed on the surface side of the body region, the semiconductor device according to claim 7. The semiconductor device according to claim 8, wherein in the semiconductor layer, a source trench penetrating the source region at a distance from the gate trench is formed from the surface side. The body region is formed in a region between the gate trench and the source trench in the surface layer portion of the semiconductor layer.
The semiconductor device according to claim 9, wherein the source region is formed in a region between the gate trench and the source trench on the surface side. The semiconductor device according to claim 9 or 10, wherein the width of the source trench is larger than the width of the gate trench. 9. Semiconductor device. The semiconductor device according to claim 12, wherein the impurity region is continuous below the body region in a region along the side wall of the source trench in the semiconductor layer. A claim that further includes a first conductive contact region formed in the impurity region along the inner wall of the source trench and having a first conductive impurity concentration higher than the first conductive impurity concentration of the impurity region. Item 12. The semiconductor device according to Item 12. The semiconductor device according to claim 7 or 8, further comprising a first conductive type impurity region formed in a region below the body region at a distance from the side wall of the gate trench in the surface layer portion of the semiconductor layer. The semiconductor device according to any one of claims 12 to 15, wherein the impurity region includes a portion of the semiconductor layer formed in a region below the bottom surface of the gate trench. The semiconductor device according to any one of claims 1 to 16, wherein the first insulating layer contains an oxide. The semiconductor device according to any one of claims 1 to 17, wherein the second insulating layer contains amorphous or microcrystals. The semiconductor device according to any one of claims 1 to 18, wherein the second insulating layer contains an oxide, a nitride, or an oxynitride. The semiconductor device according to any one of claims 1 to 19, wherein the gate trench is formed in a grid pattern or a striped pattern. The semiconductor device according to any one of claims 1 to 20, wherein the gate electrode contains a metal. The semiconductor device according to claim 1, wherein the second insulating layer includes a High-k layer containing Hf. The semiconductor device according to claim 22, wherein the gate electrode includes at least a portion in contact with the High-k layer.

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