JP6946463B2 - ワードライン抵抗を低下させる方法 - Google Patents
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Description
Claims (13)
- 基板表面に、間にギャップを有する複数の離間された酸化物層と、前記離間された酸化物層の間の前記ギャップ内に付与されたポリシリコン層とを、提供することと、
前記離間された酸化物層の表面下のある深さまで前記ポリシリコン層に凹部形成することと、
前記離間された酸化物層の上にライナーを形成し、凹部形成された前記ポリシリコン層の上にはライナーを形成しないことと、
ワードラインを形成するため、前記ライナー上の前記ギャップ内に金属層を堆積することと、
を含む処理方法。 - 前記金属層がタングステンを含む、請求項1に記載の方法。
- 前記金属層は、原子ベースで95%以上タングステンである組成を有する、請求項2に記載の方法。
- 前記金属層を堆積させることが、前記基板をタングステン前駆体と反応物質に曝露することを含む、請求項2または3に記載の方法。
- 前記タングステン前駆体は、WF6、WCl6又はWCl5のうちの一又は複数を含み、前記反応物質はH2を含む、請求項4に記載の方法。
- 前記ライナーは、TiN、TiSiN、TiAlN、Al2O3又はTaNのうちの一又は複数を含む、請求項1から5のいずれか一項に記載の方法。
- 前記ライナーは、約20Åから約50Åの範囲の厚みを有する、請求項6に記載の方法。
- 前記ライナーを形成することは、チタン前駆体と窒素反応物質への順次曝露を含む、請求項6または7に記載の方法。
- 前記チタン前駆体はTiCl4を含み、前記窒素反応物質はNH3を含む、請求項8に記載の方法。
- 50より多くのワードラインがある、請求項1から9のいずれか一項に記載の方法。
- 前記ポリシリコン層に凹部形成することは、HF、CFx、HCl、Cl2、HBr、Br2又はH2のうちの一又は複数を含むエッチャントに前記基板を曝露することを含む、請求項1から10のいずれか一項に記載の方法。
- 前記ポリシリコン層に凹部形成することは、プラズマへの曝露を含む、請求項11に記載の方法。
- 前記金属層は、前記離間された酸化物層と同一面をなす、請求項1から12のいずれか一項に記載の方法。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201762515533P | 2017-06-05 | 2017-06-05 | |
| US62/515,533 | 2017-06-05 | ||
| PCT/US2018/036060 WO2018226696A1 (en) | 2017-06-05 | 2018-06-05 | Methods of lowering wordline resistance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2020522877A JP2020522877A (ja) | 2020-07-30 |
| JP6946463B2 true JP6946463B2 (ja) | 2021-10-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2019557809A Active JP6946463B2 (ja) | 2017-06-05 | 2018-06-05 | ワードライン抵抗を低下させる方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US10854511B2 (ja) |
| JP (1) | JP6946463B2 (ja) |
| KR (1) | KR102270458B1 (ja) |
| CN (1) | CN110678972B (ja) |
| WO (1) | WO2018226696A1 (ja) |
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| KR20210144776A (ko) * | 2019-03-28 | 2021-11-30 | 도쿄엘렉트론가부시키가이샤 | 반도체 장치의 제조 방법 |
| US11808715B2 (en) * | 2020-04-17 | 2023-11-07 | Onto Innovation Inc. | Target for optical measurement of trenches |
| US11515200B2 (en) * | 2020-12-03 | 2022-11-29 | Applied Materials, Inc. | Selective tungsten deposition within trench structures |
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| JP6110911B2 (ja) * | 2015-08-31 | 2017-04-05 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| KR102451170B1 (ko) * | 2015-09-22 | 2022-10-06 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 |
| US10290680B2 (en) * | 2015-10-30 | 2019-05-14 | Sandisk Technologies Llc | ReRAM MIM structure formation |
| US9947578B2 (en) * | 2015-11-25 | 2018-04-17 | Applied Materials, Inc. | Methods for forming low-resistance contacts through integrated process flow systems |
| US9960045B1 (en) * | 2017-02-02 | 2018-05-01 | Applied Materials, Inc. | Charge-trap layer separation and word-line isolation for enhanced 3-D NAND structure |
| US10020314B1 (en) * | 2017-03-02 | 2018-07-10 | Sandisk Technologies Llc | Forming memory cell film in stack opening |
-
2018
- 2018-06-05 WO PCT/US2018/036060 patent/WO2018226696A1/en not_active Ceased
- 2018-06-05 KR KR1020197031405A patent/KR102270458B1/ko active Active
- 2018-06-05 JP JP2019557809A patent/JP6946463B2/ja active Active
- 2018-06-05 US US16/000,431 patent/US10854511B2/en active Active
- 2018-06-05 CN CN201880029923.6A patent/CN110678972B/zh active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US10854511B2 (en) | 2020-12-01 |
| CN110678972A (zh) | 2020-01-10 |
| WO2018226696A1 (en) | 2018-12-13 |
| US20180350606A1 (en) | 2018-12-06 |
| JP2020522877A (ja) | 2020-07-30 |
| KR102270458B1 (ko) | 2021-06-29 |
| CN110678972B (zh) | 2023-06-20 |
| KR20190123804A (ko) | 2019-11-01 |
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