JP6948668B2 - Neutron semiconductor detector - Google Patents

Description

The present invention relates to a neutron semiconductor detector.

As a conventional neutron detector, for example, the detector described in Patent Document 1 is formed on a silicon substrate which is a P-type semiconductor or an N-type semiconductor, a silicon oxide film formed on the silicon substrate, and a silicon oxide film. A PN junction is formed between a converter layer that generates α rays in response to the incident of neutrons by containing boron (B) and a silicon substrate by having an N-type semiconductor or a P-type semiconductor, and a converter. It includes a plurality of detectors that generate electrons and holes in response to the incident of α-rays generated by the layer, and wiring that is electrically connected to the detectors.

In this neutron detector, a plurality of detectors are arranged on a silicon substrate, and each shield metal is provided so that α rays generated by the converter layer can reach only the detector immediately below the detector. It is located above the detection unit. As a result, each detection unit functions as a plurality of pixels, and by detecting α rays for each detection unit, the position where the neutron is incident on the converter layer can be specified.

Japanese Unexamined Patent Publication No. 2012-181065

In the neutron detector as described above, neutrons are incident on the converter layer, which is the outermost layer on the side where the neutrons are incident, and the neutrons react with B contained in the converter layer to generate α rays in all directions. Will be done. Of the generated α rays, only the α rays traveling toward the detection unit immediately below the generated α rays are incident on the detection unit. Therefore, such a neutron detector does not have good neutron detection efficiency because it detects only a small part of the α rays generated in response to the incident of neutrons on the converter layer.

Therefore, an object of the present invention is to provide a neutron semiconductor detector capable of improving the neutron detection efficiency while making it possible to specify the incident position of the neutron.

The neutron semiconductor detector according to the present invention is a mixture of a substrate, a P layer containing gallium nitride (GaN) of a P-type semiconductor formed on the substrate, and GaN and boron (B) formed on the P layer. The I layer containing BGaN of the crystallized intrinsic semiconductor, the N layer containing GaN of the N-type semiconductor formed on the I layer, the first electrode electrically connected to the P layer, and the N layer electrically It comprises a plurality of second electrodes connected to and arranged on the N layer.

In this neutron semiconductor detector, a P layer containing GaN of a P-type semiconductor, an I layer containing BGaN of an intrinsic semiconductor formed on the P layer and a mixed crystal of GaN and B, and an I layer formed on the I layer. An N layer containing GaN of the N-type semiconductor is provided. Therefore, when neutrons are incident on the I layer, α rays are generated in all directions by the neutron capture (n, α) reaction by B contained in the I layer. The generated α rays excite the GaN contained in the same I layer to generate electrons and holes. That is, the α rays generated in response to the incident of neutrons on the I layer can be detected as electrons and holes regardless of the traveling direction. Further, in this neutron semiconductor detector, the first electrode is provided on the P layer, and a plurality of second electrodes are arranged on the N layer formed on the I layer. Therefore, when a bias voltage for the P layer, the I layer, and the N layer is applied between the first electrode and the second electrode, the holes among the electrons and holes generated by the GaN contained in the I layer. Passes through the P layer and reaches the first electrode, and electrons pass through the N layer and reach the second electrode. Here, in general, the resistance of electrons passing through the N layer is smaller than the resistance of holes passing through the P layer. Therefore, the electrons generated in the I layer travel linearly along the stacking direction of the P layer, the I layer, and the N layer from the I layer through the N layer until they reach the second electrode. As a result, among the electrons generated in the I layer, the electrons generated immediately below each of the plurality of second electrodes arranged on the N layer reach the second electrode located immediately above the second electrode. Therefore, even if a separate configuration is not provided, each second electrode functions as a plurality of pixels, and by detecting an electron for each second electrode, the position where the neutron is incident on the I layer can be specified. .. As described above, according to this neutron semiconductor detector, it is possible to improve the neutron detection efficiency while making it possible to specify the incident position of the neutron.

In the neutron semiconductor detector according to the present invention, one P layer, one I layer, and one N layer may be provided. According to this, since a plurality of P layer, I layer, and N layer are not provided, a simple configuration can be realized.

In the neutron semiconductor detector according to the present invention, a signal reading circuit that is electrically connected to each of the first electrode and the plurality of second electrodes and reads an electric signal between each of the first electrode and the plurality of second electrodes. May be provided. According to this, signals corresponding to the number of detected neutrons can be automatically detected, and information on the incident positions of these neutrons can be automatically acquired.

According to the present invention, it is possible to improve the neutron detection efficiency while making it possible to specify the incident position of the neutron.

It is sectional drawing which shows the neutron semiconductor detector which concerns on this embodiment. It is a perspective view which shows the laminated body of the neutron semiconductor detector of FIG. It is a partial micrograph of the laminated body of FIG. 2 in a plan view. It is a schematic diagram for demonstrating the principle of neutron detection in the I layer of the neutron semiconductor detector of FIG. It is a graph which shows the result of having measured the current-voltage characteristic between the P layer and the N layer of the neutron semiconductor detector which concerns on Example. It is a graph which shows the result of having measured the electric signal corresponding to the incident of α ray to the I layer in the neutron semiconductor detector which concerns on Example. It is a graph which compares and shows the result of having measured each electric signal corresponding to the incident of α ray to each I layer in each of the neutron semiconductor detector according to an Example and the neutron semiconductor detector according to a comparative example. It is sectional drawing which shows the neutron semiconductor detector which concerns on a comparative example. It is a graph which shows the result of having measured the electric signal corresponding to the incident of the neutron to the I layer formed by GaN by the neutron semiconductor detector which concerns on a comparative example.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In each figure, the same or corresponding parts are designated by the same reference numerals, and duplicate description will be omitted.
[Structure of neutron semiconductor detector]

FIG. 1 is a cross-sectional view showing a neutron semiconductor detector according to the present embodiment. FIG. 2 is a perspective view showing a laminated body of the neutron semiconductor detector of FIG. FIG. 3 is a partial micrograph of the laminate of FIG. 2 in a plan view. As shown in FIGS. 1 to 3, the neutron semiconductor detector 1 includes a laminate 10 and a signal reading unit 30. The neutron semiconductor detector 1 is a neutron detector capable of identifying the incident position of the neutron n. The neutron semiconductor detector 1 generates α-ray a by the neutron capture (n, α) reaction (R1 in FIG. 1) between the detected neutron n and boron (B), and gallium nitride (GaN) by this α-ray a. ) (R2 in FIG. 1) to generate electrons e and holes h to detect neutrons n. Here, the neutron capture (n, α) reaction is a reaction in which the atomic nucleus of B captures neutron n and emits γ-rays (see FIG. 4).

The laminate 10 has a sapphire substrate (substrate) 11, a GaN buffer layer (substrate) 12, a P layer 13, an I layer 14, an N layer 15, a first electrode 21, and a second electrode 22. In the laminated body 10, each of the sapphire substrate (board) 11, the GaN buffer layer (board) 12, the P layer 13, the I layer 14, and the N layer 15 is provided one by one.

The sapphire substrate 11 contains alumina (Al ₂ O ₃ ). The sapphire substrate 11 has, for example, a rectangular shape in a plan view. The sapphire substrate 11 is the lowest layer of the laminated body 10.

The GaN buffer layer 12 contains GaN. The GaN buffer layer 12 is a layer formed on the sapphire substrate 11. The GaN buffer layer 12 is formed so that the outer edge 12a of the GaN buffer layer 12 coincides with the outer edge 11a of the sapphire substrate 11 (that is, for example, in a rectangular shape) in a plan view. The GaN buffer layer 12 is formed by growing it on the sapphire substrate 11 at a low temperature.

The P layer 13 contains GaN of a P-type semiconductor. In the P layer 13, the carrier (hole) concentration is set in the range ^{of, for example, 1 × 10 17} cm ^-3 or more and 1 × 10 ²⁰ cm ^{-3 or less by, for example, magnesium (Mg) doping.} The P layer 13 is a layer formed on the GaN buffer layer 12. The P layer 13 is formed so that the outer edge 13a of the P layer 13 coincides with the outer edge 11a of the sapphire substrate 11 and the outer edge 12a of the GaN buffer layer 12 in a plan view (that is, for example, in a rectangular shape). Since the P layer 13 is formed on the GaN buffer layer 12 instead of on the sapphire substrate 11 in which the lattice and the coefficient of thermal expansion are significantly different from each other, deterioration of crystal quality is suppressed.

The I layer 14 contains BGaN, which is an intrinsic semiconductor obtained by mixing GaN and B. Here, "mixing crystals" means that GaN, which is a group III nitride, incorporates the BN of the group III nitride. Further, the “intrinsic semiconductor” here means a semiconductor having a lower carrier concentration than the P layer 13 and the N layer 15. More specifically, in the I layer 14, the carrier concentration is, for example, in the range of ^{0 cm -3} or more and 1 × 10 ¹⁷ cm ^{-3 or less.} In the I layer 14, the carrier concentration may be in the range where the I layer 14 can be depleted.

The I layer 14 is a layer formed on the P layer 13. The I layer 14 is formed so that a part of the outer edge 14a of the I layer 14 is located inside the outer edge 13a of the P layer 13 in a plan view. That is, the I layer 14 covers only the covering surface 13b which is a part of the upper surface of the P layer 13 (the surface opposite to the GaN buffer layer 12) in a plan view. In other words, in plan view, the I layer 14 does not cover the exposed surface 13c, which is the rest of the upper surface of the P layer 13 except for the covering surface 13b (that is, the exposed surface 13c of the P layer 13 is the I layer. It is not covered with 14 and is exposed.) As a specific shape, the I layer 14 is formed, for example, in a square shape in a plan view.

The N layer 15 contains GaN of an N-type semiconductor. In the N layer 15, the carrier (electron) concentration is, for example, in the range of 1 × 10 ¹⁶ cm ^-3 or more and 1 × 10 ²⁰ cm ^-3 or less. The N layer 15 is a layer formed on the I layer 14. The N layer 15 is formed so that the outer edge 15a of the N layer coincides with the outer edge 14a of the I layer 14 (that is, for example, in a square shape) in a plan view.

The first electrode 21 is formed on the P layer 13 so as to be electrically connected to the P layer 13. More specifically, the first electrode 21 is formed in a long shape on the exposed surface 13c of the P layer 13 at a position along the outer edge 13a of the P layer 13. As shown in the figure, a plurality of (two in this case) first electrodes 21 may not be provided, and only one may be provided. As the first electrode 21, as an example, an Au / Ni electrode (that is, an electrode having a configuration in which Au for preventing oxidation of the Ni is provided on the Ni provided as a contact layer on the P layer 13) is used. However, the present invention is not limited to this, and any electrode may be used as long as it can form ohmic contact on the P layer 13.

The second electrode 22 is formed on the N layer 15 so as to be electrically connected to the N layer 15. A plurality of (49 in this case) second electrodes 22 are arranged on the N layer 15. More specifically, each of the second electrodes 22 exhibits, for example, a square shape in a plan view, and is arranged in a 7-by-7 matrix (that is, at the position of a grid point) on the N layer 15 so as to be separated from each other. Has been done. FIG. 3 shows four second electrodes 22 out of the 49 second electrodes 22. The second electrode 22 may not be arranged in a matrix of 7 rows and 7 columns, and may be arranged in a matrix in which at least one of the number of rows and the number of columns is different from this. Further, the second electrodes 22 may not be arranged in a matrix, and may be arranged in a honeycomb shape, for example. An example of the second electrode 22 is an Al electrode, but the second electrode 22 is not limited to this, and any electrode that can form ohmic contact on the N layer 15 may be used.

As shown in FIG. 1, the signal reading unit 30 includes a power supply 31 and a signal reading circuit 32. Further, the signal reading unit 30 electrically connects the laminate 10, the power supply 31, and the signal reading circuit 32 in series with the electric wire 33, and electrically connects the laminate 10 and the power supply 31 in the electric wire 33. It has a ground (ground) 34.

The power supply 31 is a DC variable power supply. The power supply 31 applies a voltage to the laminate 10 so that the first electrode 21 is the positive electrode and the second electrode 22 is the negative electrode. That is, the power supply 31 applies a bias voltage to the diode structure composed of the P layer 13, the I layer 14, and the N layer 15 between the first electrode 21 and the second electrode 22.

The signal reading circuit 32 is a circuit that reads an electric signal between the first electrode 21 and each of the second electrodes 22. The signal reading circuit 32 is electrically connected to the first electrode 21 and each second electrode 22 via the electric wire 33. The specific circuit configuration of the signal reading circuit 32 is not limited to a specific circuit configuration. For example, the signal reading circuit 32 may be configured to read the electric charges flowing into the second electrodes 22 in order, or the signal reading circuit 32 may be provided with a plurality of circuits corresponding to the second electrodes 22 in parallel. The circuit may be configured to read out the electric charge that has flowed into the second electrode 22 corresponding to each circuit.
[Operation of neutron semiconductor detector]

FIG. 4 is a schematic diagram for explaining the principle of neutron detection in the I layer of the neutron semiconductor detector of FIG. As shown in FIGS. 1 and 4, when the neutron n enters the sensitive layer (depletion layer) of the I layer 14 of the neutron semiconductor detector 1, it is contained in a part of the neutron n and the I layer 14. A neutron capture (n, α) reaction (R1 in FIGS. 1 and 4) occurs between B, which has a larger mass attenuation coefficient of neutron n than other elements. As a result, α-rays a are generated in all directions (directions not particularly limited), and γ-rays g are emitted.

The generated α-ray a excites GaN contained in the same I layer 14 (R2 in FIGS. 1 and 4) to generate electrons e and holes h. That is, the generated α-ray a excites GaN to generate electrons e and holes h regardless of the traveling direction. On the other hand, since the transparency of γ-rays to GaN is high, the generated γ-rays g pass through the I layer 14 and proceed to the outside.

Here, as shown in FIG. 1, when a bias voltage for the P layer 13, the I layer 14, and the N layer 15 is applied between the first electrode 21 and the second electrode 22 by the power supply 31, the hole h Passes through the P layer 13 and reaches the first electrode 21, and the electron e passes through the N layer 15 and reaches the second electrode 22. In general, the resistance of electrons to pass through the N layer is smaller than the resistance of holes to pass through the P layer. Therefore, the electrons e travel linearly along the stacking direction D of the P layer 13, the I layer 14, and the N layer 15 until they pass from the I layer 14 to the N layer 15 and reach the second electrode 22. .. As a result, among the electrons e, the electrons e generated immediately below each of the plurality of second electrodes 22 arranged on the N layer 15 reach the second electrode 22 located immediately above the second electrodes 22. In FIG. 1, the electron e generated immediately below the second electrode 22a of the plurality of second electrodes 22 reaches the second electrode 22a, and the electron e generated immediately below the second electrode 22b is the electron e. It has been shown to reach the second electrode 22b.

Further, the signal reading circuit 32 automatically detects a signal corresponding to the number of electrons e reaching each second electrode 22 for each second electrode 22. Of the plurality of second electrodes 22, which second electrode 22 the electron e reaches depends on the incident position of the neutron n in the I layer 14. Therefore, by detecting a signal corresponding to the number of electrons e reaching each second electrode 22 for each second electrode 22, information on the incident position of the neutron n in the I layer 14 can also be acquired. can.
[Action and effect]

As described above, in the neutron semiconductor detector 1, the P layer 13 containing the GaN of the P-type semiconductor and the I layer containing the BGaN of the intrinsic semiconductor formed on the P layer 13 and in which GaN and B are mixed. 14 and an N layer 15 containing GaN of an N-type semiconductor formed on the I layer 14 are provided. Therefore, when the neutron n is incident on the I layer 14, α rays a are generated in all directions by the neutron capture (n, α) reaction by B contained in the I layer 14. The generated α-ray a excites the GaN contained in the same I layer 14 to generate electrons e and holes h. That is, the α-ray a generated in response to the incident of the neutron n on the I layer 14 can be detected as an electron e and a hole h regardless of the traveling direction. Further, in the neutron semiconductor detector 1, the first electrode 21 is provided on the P layer 13, and a plurality of second electrodes 22 are arranged on the N layer 15 formed on the I layer 14. Therefore, when a bias voltage for the P layer 13, the I layer 14, and the N layer 15 is applied between the first electrode 21 and the second electrode 22 by the power supply 31, it is generated by the GaN contained in the I layer 14. Of the electrons e and holes h, the hole h passes through the P layer 13 and reaches the first electrode 21, and the electron e passes through the N layer 15 and reaches the second electrode 22. Here, in general, the resistance of electrons passing through the N layer is smaller than the resistance of holes passing through the P layer. Therefore, the electrons e generated in the I layer 14 pass through the N layer 15 from the I layer 14 and reach the second electrode 22 in the stacking direction D of the P layer 13, the I layer 14, and the N layer 15. Proceed linearly along. As a result, among the electrons e generated in the I layer 14, the electrons e generated directly under each of the plurality of second electrodes 22 arranged on the N layer 15 are located directly above the second electrode. Reach 22. Therefore, even if a separate configuration is not provided, each second electrode 22 functions as a plurality of pixels, and by detecting an electron e for each second electrode 22, the position where the neutron n is incident on the I layer 14 can be determined. Can be identified. As described above, according to the neutron semiconductor detector 1, it is possible to improve the detection efficiency of the neutron n while making it possible to specify the incident position of the neutron n.

In the neutron semiconductor detector 1, one P layer 13, one I layer 14, and one N layer 15 are provided. According to this, since a plurality of P layer 13, I layer 14, and N layer 15 are not provided, a simple configuration can be realized.

In the neutron semiconductor detector 1, a signal reading that is electrically connected to each of the first electrode 21 and the plurality of second electrodes 22 and reads an electric signal between each of the first electrode 21 and the plurality of second electrodes 22. The circuit 32 is provided. According to this, signals corresponding to the number of detected neutrons n can be automatically detected, and information on the incident positions of these neutrons n can be automatically acquired.
[Example]

Subsequently, an embodiment of the neutron semiconductor detector 1 according to the present embodiment will be described. Here, the neutron semiconductor detector according to one embodiment was manufactured, and the following characteristics and electrical signals were acquired.

FIG. 5 is a graph showing the results of measuring the current-voltage characteristics between the P layer and the N layer of the neutron semiconductor detector according to the embodiment. In FIG. 5, in this embodiment, a voltage is applied between the P layer and the N layer stacked via the I layer, and the voltage value (horizontal axis) is changed from -10 [V] to 10 [V]. ], The current value (vertical axis) output when the value is changed is shown. As shown in FIG. 5, this measurement confirmed that the laminated structure of the P layer, the I layer, and the N layer had the same current-voltage characteristics as the diode.

Next, when α rays were generated in the I layer, the following measurements were performed to confirm that the α rays were properly detected. FIG. 6 is a graph showing the results of measuring an electric signal corresponding to the incident of α rays on the I layer in the neutron semiconductor detector according to the embodiment. In FIG. 6, in this embodiment, the voltage value (vertical axis) output to the signal reading unit when α rays are incident on the I layer is shown with the horizontal axis as time. Here, as α rays, α rays emitted from americium (Am) are used. As shown in FIG. 6, since the voltage value increased in response to the incident of α rays on the I layer, it was confirmed that the neutron semiconductor detector according to this embodiment can appropriately detect α rays. rice field. It was also confirmed that the response time at the rising edge of the voltage value was 1.6 [μs].
[Comparison example]

FIG. 7 is a graph showing a comparison of the results of measuring each electric signal according to the incident of α rays into each I layer by each of the neutron semiconductor detector according to the example and the neutron semiconductor detector according to the comparative example. Is. FIG. 8 is a cross-sectional view showing a neutron semiconductor detector according to a comparative example. First, a comparative example of the neutron semiconductor detector 1 according to the present embodiment will be described with reference to FIG.

As shown in FIG. 8, the structural difference between the neutron semiconductor detector 100 according to the comparative example and the neutron semiconductor detector 1 according to the present embodiment is that the GaN of the N-type semiconductor is placed on the GaN buffer layer 12. The N layer 115 including the N layer 115 is formed, a plurality of I layers 114 containing the intrinsic semiconductor BGaN are formed on the N layer 115, and the P layer 113 containing the GaN of the P type semiconductor is formed on each I layer 114, respectively. The point is that the third electrode 123 is electrically connected to the layer 115, and the fourth electrode 124 is formed on each P layer 113. In FIG. 8, two I layer 114, P layer 113, and the fourth electrode 124 are shown, respectively, and the number of each of the I layer 114, the P layer 113, and the fourth electrode 124 is shown. Is not limited to two, and may be any number depending on the number of pixels of the neutron semiconductor detector 100. The plurality of I layer 114, P layer 113, and the fourth electrode 124 are arranged two-dimensionally (for example, in a matrix) on the N layer 115.

In such a neutron semiconductor detector 100, a plurality of I layer 114 and P layer 113 are provided and a fourth electrode 124 is provided on each P layer 113, although the apparatus configuration is complicated for the following reasons. There is a need. That is, the laminated body 110 is laminated in the order of P layer 113, I layer 114, and N layer 115 from the outermost surface side. Therefore, when a bias voltage for the N layer 115, the I layer 114, and the P layer 113 is applied between the third electrode 123 and the fourth electrode 124 by the power supply 31, it is generated by the GaN contained in the I layer 114. The electrons e and the electrons e of the holes h pass through the N layer 115 and reach the third electrode 123, and the holes h pass through the P layer 113 and reach the fourth electrode 124. Here, in general, the resistance of holes passing through the P layer is larger than the resistance of electrons passing through the N layer. Therefore, when the hole h generated in the I layer 114 tries to reach the fourth electrode 124 from the I layer 114 through the P layer 113, the holes h of the N layer 115, the I layer 114, and the P layer 113 It proceeds in an irregular direction without following the stacking direction D. Therefore, if the I layer 114 and the P layer 113 have a single configuration and a plurality of fourth electrodes 124 are arranged on the P layer 113, a plurality of electrons e generated in the I layer 114 will be generated. The electrons e generated immediately below each of the fourth electrode 124 do not necessarily reach the fourth electrode 124 located directly above the fourth electrode 124. Therefore, each of the fourth electrodes 124 does not function as a plurality of pixels, and the position where the neutron n is incident on the I layer 114 cannot be specified. For the above reasons, in the neutron semiconductor detector 100 according to the comparative example, it is necessary to adopt a configuration in which a plurality of I layer 114 and P layer 113 are provided and a fourth electrode 124 is provided on each P layer 113.

On the other hand, in the neutron semiconductor detector 1 according to the present embodiment, as described above, the I layer 14 and the N layer 15 have a single configuration, and a plurality of second electrodes 22 are arranged on the N layer 15. Even in this configuration, each second electrode 22 functions as a plurality of pixels, and by detecting an electron e for each second electrode 22, the position where the neutron n is incident on the I layer 14 can be specified. can.

In FIG. 7, in each of the examples and the comparative examples, each voltage value (vertical axis) output to each signal reading unit when α rays are incident on each I layer is shown with the horizontal axis as time. There is. The graph according to the embodiment of FIG. 7 is the same as the graph of FIG. As shown in FIG. 7, in the graphs related to each of the examples and the comparative examples, it was confirmed that the response times of the rise of each voltage value according to the incident of α rays on each I layer are about the same. ..

FIG. 9 is a graph showing the results of measuring an electric signal according to the incident of neutrons on the I layer formed of GaN by the neutron semiconductor detector according to the comparative example. In FIG. 9, the voltage value (vertical axis) output to the signal reading unit 30 when the I layer is formed of GaN in this comparative example and neutrons are incident on the I layer is shown with the horizontal axis as time. ing. Here, as the neutron, the neutron emitted from californium (Cf) is used. As shown in FIG. 9, the rise time of the voltage value rise according to the incident of neutrons on the I layer and the time from the rise to the fall of the voltage value are about the same as in the cases of FIGS. 6 and 7. ing. Therefore, it was confirmed that the neutron semiconductor detector according to the comparative example can suitably detect neutrons incident on the I layer and functions suitably as a neutron detector.

1 ... Neutron semiconductor detector, 11 ... Sapphire substrate (substrate), 12 ... GaN buffer layer (substrate), 13 ... P layer, 14 ... I layer, 15 ... N layer, 21 ... 1st electrode, 22 ... 2nd electrode , 32 ... Signal reading circuit.

Claims (3)

With the board
Look-containing gallium nitride (GaN) of P-type semiconductor formed on the substrate, and the P layer carrier concentration of 1 × ¹⁰ 20 ^{cm -3} or less than 1 × ¹⁰ 17 ^{cm -3,}
Formed on the P layer, viewed including the GaN and boron (B) and BGaN intrinsic semiconductor formed by a mixed crystal of a carrier concentration of not more than ^{0 cm -3} or more 1 × ¹⁰ 17 ^{cm -3,} said P layer The I layer that covers the covering surface, which is the central surface, and
The viewing including the GaN on the N-type semiconductor formed I layer, and the N layer carrier concentration of 1 × ¹⁰ 20 ^{cm -3} or less than 1 × ¹⁰ 16 ^{cm -3,}
A pair of first electrodes electrically connected to the P layer and exhibiting a long shape,
A plurality of second electrodes electrically connected to the N layer and arranged in a two-dimensional manner are provided.
The I layer and the N layer are each formed as a single structure.
The plurality of second electrodes are arranged apart from each other on the N layer having a single configuration.
The pair of first electrodes extend along the outer edge of the P layer on exposed surfaces, which are surfaces on both ends of the P layer that are not covered by the I layer, and are arranged so as to sandwich the coated surface. Be done,
Neutron semiconductor detector. The neutron semiconductor detector according to claim 1, wherein each of the P layer, the I layer, and the N layer is provided one by one. 1. A signal reading circuit that is electrically connected to each of the first electrode and the plurality of second electrodes and reads an electric signal between the first electrode and each of the plurality of second electrodes is provided. Or the neutron semiconductor detector according to 2.

Images