JP6955883B2 - Semiconductor device and power-on reset device - Google Patents

Description

The present invention relates to a semiconductor device, particularly a semiconductor device including a power-on reset circuit that resets an internal circuit in response to a power-on, and a power-on reset device.

The semiconductor device is provided with a power-on reset circuit that initializes the state of the internal circuit when the power is turned on. As such a power-on reset circuit, it has a voltage value that prompts a reset immediately after the power is turned on based on the comparison result between the comparison voltage obtained by dividing the power supply voltage and the monitored voltage generated by the regulator, and continuously resets. It has been proposed to generate a voltage that transitions to a voltage value that prompts the release (see, for example, Patent Document 1).

This power-on reset circuit is an output circuit that outputs a differential pair that receives the above-mentioned comparison voltage and the monitored voltage and a voltage that prompts the above-mentioned reset or reset release based on the current flowing through the differential pair due to the monitored voltage. And a generation circuit that generates a bias current to flow through these differential pairs and output circuits.

Japanese Unexamined Patent Publication No. 2016-127480

By the way, in the above configuration, the threshold voltage Vt of the transistors constituting the differential pair may fluctuate due to the variation in manufacturing. At this time, it may be difficult to set the voltage value for prompting the reset (or the voltage value for prompting the reset release) to a desired voltage value, and the power-on reset (or reset release) may not be performed on the internal circuit. there were.

Therefore, the present invention provides a semiconductor device including a power-on reset circuit capable of reliably performing a power-on reset to an internal circuit even if there is a manufacturing variation, and a power-on reset device. The purpose.

The semiconductor device according to the present invention receives a reference voltage and generates a constant power supply voltage having a voltage value corresponding to the reference voltage according to the power supply on, and the power supply is turned on based on the reference voltage and the constant power supply voltage. A power-on reset that has a first voltage value that prompts a reset for a predetermined period from a time point and generates a power-on reset signal that transitions to a second voltage value that prompts a reset release after a lapse of a predetermined period from the power-on time. The power-on reset circuit has a circuit, and supplies the drive node and a first current corresponding to the voltage value of the reference voltage to the drive node, and also supplies a second current corresponding to the constant power supply voltage. comprising a current difference acquisition section to pull current from the drive node, and a comparator for obtaining the power-on reset signal based on the comparison result of the magnitude of the voltage with a predetermined threshold voltage of the driving node, the.

The power-on reset device according to the present invention has a first voltage value that prompts a reset for a predetermined period from the time when the power is turned on, and a second voltage value that prompts the reset release after a lapse of a predetermined period from the time when the power is turned on. A power-on reset device that generates a transitional power-on reset signal, a regulator that receives a reference voltage and generates a constant power supply voltage having a voltage value corresponding to the reference voltage in response to a power-on, a drive node, and the like. A current difference acquisition unit that supplies a first current corresponding to the voltage value of the reference voltage to the drive node and draws a second current corresponding to the constant power supply voltage from the drive node, and electricity of the drive node. It includes a comparator that obtains the power-on reset signal based on the result of comparing the magnitudes of the pressure and the predetermined threshold voltage.

In the present invention, the first current corresponding to the reference voltage received by the regulator that generates the constant power supply voltage having the voltage value corresponding to the reference voltage according to the power-on, and the second current corresponding to the constant power supply voltage , Is generated. Then, a power-on reset signal is generated based on the difference in current obtained by subtracting the second current corresponding to the constant power supply voltage from the first current corresponding to the reference voltage. According to such a difference in current, the fluctuation due to the manufacturing variation occurring in the first current and the second current is canceled out, so that even if the variation occurs, the voltage value that prompts the reset is promoted. It is possible to reliably obtain a power-on reset signal that transitions from the state of the above to the state of the voltage value prompting the reset release.

It is a block diagram which shows the structure of the semiconductor device 100 which concerns on this invention. It is a circuit diagram which shows an example of the internal structure of a regulator 12 and a power-on reset circuit 13. It is a time chart which shows an example of the waveform of the constant power supply voltage VDC and the power-on reset signal POR at the time of power-on. It is a circuit diagram which shows another example of the internal structure of a regulator 12 and a power-on reset circuit 13.

Hereinafter, examples of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a semiconductor device 100 according to the present invention. As shown in FIG. 1, the semiconductor device 100 includes an internal circuit 10 that has a main function as the semiconductor device, a reference voltage generation unit 11, a regulator 12, and a power-on reset circuit 13.

The reference voltage generation unit 11 generates a reference voltage VR having a predetermined constant voltage value based on the power supply potential VDD and supplies the reference voltage VR to the regulator 12.

The regulator 12 uses a constant power supply voltage VDC having a voltage value corresponding to the voltage value of the reference voltage VR as the power supply voltage for operating the circuit element (not shown) formed in the internal circuit 10 based on the power supply potential VDD. Generate. The regulator 12 supplies a constant power supply voltage VDC to the internal circuit 10 and the power-on reset circuit 13.

Further, the regulator 12 generates a reference voltage signal S1 representing the voltage value of the reference voltage VR and a constant power supply voltage signal S2 representing the voltage value of the constant power supply voltage VDC, and supplies the regulator 12 to the power-on reset circuit 13.

The power-on reset circuit 13 generates the following power-on reset signal POR based on the above-mentioned reference voltage signal S1, constant power supply voltage signal S2, constant power supply voltage VDC, and power supply potential VDD. That is, the power-on reset circuit 13 has a low voltage value (for example, zero volt) that prompts resetting from the time when the power supply potential VDD is turned on until a predetermined period elapses, and a predetermined high voltage that prompts reset release after the elapse of a predetermined period. Generates a power-on reset signal POR with a voltage value.

The power-on reset circuit 13 supplies the power-on reset signal POR to the internal circuit 10. The circuit elements such as flip-flops and the functional module included in the internal circuit 10 are set to the reset state while the power-on reset signal POR is in the low voltage value state. After that, when the power-on reset signal POR transitions from a low voltage value to a predetermined high voltage value, the reset state of the circuit element and the functional module is released.

FIG. 2 is a circuit diagram showing an example of the internal configuration of the regulator 12 and the power-on reset circuit 13.

As shown in FIG. 2, the regulator 12 includes p-channel MOS (metal oxide semiconductor) type transistors M3, M5 to M7, n-channel MOS type transistors M4, M9 to M13, Mna, resistors R1 and R2, and the like. It comprises a so-called error amplifier including a current source G1.

The current source G1 generates a predetermined constant current based on the power supply potential VDD, and supplies this to the gate end and drain end of the transistor M9 and the gate end of the transistor M11. A ground potential VSS is applied to the source ends of the transistors M9 and M11.

The source end of each of the transistors M12 and M13 as a differential pair is connected to the drain end of the transistor M11.

The reference voltage VR generated by the reference voltage generation unit 11 is applied to the gate end of the transistor M13 as one of the transistors in the above-mentioned differential pair. The drain end of the transistor M13 is connected to the drain end and the gate end of the transistor M6 on the primary side of the first current mirror circuit CM1 and the gate end of the transistor M5 on the secondary side via the node L1. A power supply potential VDD is applied to the source ends of each of the transistors M5 and M6. The drain end of the transistor M5 is connected to the gate end of the transistor Mna and the drain end of the transistor M4 via the node La.

Here, the power supply potential VDD is applied to the drain end of the transistor Mna in which the voltage generated in the node L1 described above is supplied to the power-on reset circuit 13 as the reference voltage signal S1, and the source end thereof is the output node L0. It is connected to one end of the resistor R1 via. One end of the resistor R2 and the gate end of the transistor M12 are connected to the other end of the resistor R1. A ground potential VSS is applied to the other end of the resistor R2.

Here, due to the current sent from the transistor Mna to the output node L0 and the resistor R1, the voltage generated at one end of the resistor R1 and the output node L0 is supplied to the internal circuit 10 and the power-on reset circuit 13 as a constant power supply voltage VDC. Will be done. Further, a voltage obtained by dividing the constant power supply voltage VDC by a voltage dividing circuit including resistors R1 and R2 is supplied to the gate end of the transistor M12 as a voltage divided voltage INN.

The resistors R1 and R2 are resistors such that the voltage value of the voltage dividing voltage INN obtained when the voltage value of the constant power supply voltage VDC is in the steady state is equal to the voltage value of the reference voltage VR in the steady state. Has a value.

The drain end of the transistor M12 as the other transistor in the differential pair is the drain end and the gate end of the transistor M3 on the primary side of the second current mirror circuit CM2 via the node L2, and the gate of the transistor M7 on the secondary side. It is connected to the end. A power supply potential VDD is applied to the source ends of each of the transistors M3 and M7. The drain end of the transistor M7 is connected to the gate end and drain end of the transistor M10 and the gate end of the transistor M4 via the node Lb. A ground potential VSS is applied to the source ends of each of the transistors M4 and M10.

Here, the voltage generated in the node Lb by the current Ib is supplied to the power-on reset circuit 13 as a constant power supply voltage signal S2.

The power-on reset circuit 13 includes p-channel MOS type transistors M31 and M32, n-channel MOS type transistors M0, M20 to M22, and a current source G2.

The power supply potential VDD is applied to the source end of the transistor M31, and the above-mentioned reference voltage signal S1 is supplied to the gate end. The drain end of the transistor M31 is connected to the drain end of the transistor M0, the drain end of the transistor M20, and the gate end of each of the transistors M22 and M32 via the drive node LQ.

The above-mentioned constant power supply voltage signal S2 is supplied to the gate end of the transistor M0, and the ground potential VSS is applied to the source end thereof.

A ground potential VSS is applied to the source ends of each of the transistors M20 and M21 constituting the first offset adjusting unit CT1. The drain end of the transistor M20 is connected to the drive node LQ. The current source G2 generates a predetermined constant current based on the power supply potential VDD, and supplies this to the gate end and drain end of the transistor M21 and the gate end of the transistor M20.

With this configuration, the offset adjusting unit CT1 draws the adjusting current Io1 having a current value corresponding to the constant current generated by the current source G2 from the drive node LQ via the transistor M20.

A constant power supply voltage VDC generated by the regulator 12 is applied to the source end of the transistor M32 via the output node L0, and the drain end thereof is connected to the drain end of the transistor M22 via the output node Lr. ing. A ground potential VSS is applied to the source end of the transistor M22.

When the voltage value of the drive node LQ is higher than its own threshold voltage, the inverter composed of these transistors M22 and M32 outputs a power-on reset signal POR having a low voltage value VL corresponding to the ground potential VSS. Output via Lr. Further, when the voltage value of the drive node LQ is equal to or less than the threshold voltage, the inverter outputs a power-on reset signal POR having a high voltage value VH corresponding to the constant power supply voltage VDC via the output node Lr.

By the way, the inverter composed of the transistors M22 and M32 functions as a so-called comparator that compares the magnitude between the voltage value of the drive node and the predetermined threshold value by using its own threshold voltage. Therefore, hereinafter, the inverter composed of the transistors M22 and M32 will be referred to as comparators (M22, M32) and will be described.

The operation of generating the constant power supply voltage VDC and the operation of generating the power-on reset signal POR according to the configuration shown in FIG. 2 will be described below with reference to the time chart shown in FIG.

[Constant power supply voltage VDC generation operation]
First, since the power supply potential VDD is in the state of zero volt before the power is turned on, the constant power supply voltage VDC is also in the state of the low voltage value VL of zero volt as shown in FIG.

Then, the power supply potential VDD increases in response to the power-on, and when the potential exceeds a predetermined potential, the voltage value of the reference voltage VR generated by the reference voltage generation unit 11 follows the increase in the power supply potential VDD. To increase.

As a result, the transistor M13 of the regulator 12 causes the current I1 corresponding to the voltage value of the increasing reference voltage VR to flow to the node L1. Then, the current mirror circuit CM1 sends the current Ia corresponding to the current I1 of the node L1 to the node La, and increases the voltage value of the node La. At this time, the transistor Mna sends a current corresponding to the voltage value of the node La to the output node L0. As a result, the voltage of the output node L0, that is, the voltage value of the constant power supply voltage VDC increases as shown in FIG.

During this period, a voltage-separated voltage INN obtained by dividing the constant power supply voltage VDC is supplied to the gate end of the transistor M12. The transistor M12 causes a current I2 corresponding to the voltage dividing voltage INN to flow through the node L2. Then, the current mirror circuit CM2 sends a current Ib corresponding to the current I2 of the node L2 to the node Lb, and increases the voltage of the node Lb. At this time, the transistor M4 draws a current Ic corresponding to the voltage value of the node Lb from the node La. Along with this, a voltage corresponding to the current (Ia-Ic) is generated in the node La.

Therefore, the transistor Mna generates a constant power supply voltage VDC as described above by sending a current corresponding to the voltage value corresponding to the current (Ia-Ic) to the output node L0.

By the way, there is a delay before the voltage value of the reference voltage VR is reflected in the constant power supply voltage VDC. Therefore, during the period of increase of the reference voltage VR immediately after the power is turned on, the voltage value of the reference voltage VR becomes higher than the voltage value of the voltage dividing voltage INN which is the voltage dividing voltage of the constant power supply voltage VDC. Therefore, during this period, the current Ia corresponding to the voltage value of the reference voltage VR becomes larger than the current Ic corresponding to the voltage value of the voltage dividing voltage INN. Therefore, since the current (Ia-Ic) becomes larger than zero, the transistor Mna increases the voltage value of the constant power supply voltage VDC by transmitting the current (Ia-Ic) as shown in FIG.

After that, as shown in FIG. 3, when the power supply potential VDD reaches a steady state at a predetermined constant potential, and the voltage value of the reference voltage VR also reaches the steady state, the voltage value of the reference voltage VR and the voltage division are achieved. The voltage value of the voltage INN becomes equal to that of the voltage value. As a result, the current Ia corresponding to the voltage value of the reference voltage VR becomes equal to the current Ic corresponding to the voltage value of the voltage dividing voltage INN, and the current (Ia-Ic) becomes zero. Therefore, the voltage of the node La becomes a low voltage value, and the transistor Mna is turned off. Therefore, as shown in FIG. 3, the increase of the constant power supply voltage VDC stops at the time point t1, and the high voltage value VH, which is the voltage value in the steady state, is maintained.

[Power-on reset signal POR generation operation]
A reference voltage signal S1 representing the voltage value of the node L1 of the regulator 12, that is, the voltage value of the reference voltage VR is supplied to the gate end of the transistor M31 of the power-on reset circuit 13. Further, a constant power supply voltage signal S2 representing the voltage value of the node Lb of the regulator 12, that is, the voltage value of the divided voltage INN corresponding to the constant power supply voltage VDC is supplied to the gate end of the transistor M0 of the power-on reset circuit 13. Has been done.

As a result, the transistor M31 supplies the current Ir corresponding to the reference voltage VR to the drive node LQ, and the transistor M0 draws the current Ip corresponding to the constant power supply voltage VDC from the drive node LQ. Further, the offset adjusting unit CT1 included in the power-on reset circuit 13 draws the adjusting current Io1 having a predetermined constant current value from the drive node LQ.

Therefore, the drive current Isub represented by the following formula is supplied to the gate ends of the transistors M22 and M32 constituting the comparator.

Isub = Ir-Ip-Io1
Here, as described above, during the period from the time when the power is turned on to the time t1 when the voltage value of the constant power supply voltage VDC reaches the high voltage value VH in the steady state, the voltage value of the reference voltage VR is the voltage divider voltage INN. Higher than the voltage value of. Therefore, during this period, the current Ir corresponding to the voltage value of the reference voltage VR becomes larger than the current Ip corresponding to the voltage dividing voltage INN, and the current value of the drive current Isub becomes larger than zero. The drive current Isub increases the voltage of the drive node LQ (hereinafter referred to as the reset drive voltage PWB).

That is, the voltage value of the reset drive voltage PWB is maintained higher than the threshold voltage of the comparators (M22, M32) during the reset period from the power-on time to the time point t1 shown in FIG. Therefore, during this period, the transistor M32 is turned off and the transistor M22 is turned on, and the comparator generates a power-on reset signal POR having a low voltage value VL as shown in FIG.

After that, when the voltage value of the constant power supply voltage VDC reaches the high voltage value VH as shown in FIG. 3, the voltage value of the reference voltage VR becomes substantially equal to the voltage value of the voltage dividing voltage INN. Therefore, during this period, the current Ir corresponding to the voltage value of the reference voltage VR becomes substantially equal to the current Ip corresponding to the voltage dividing voltage INN.

As a result, the current supply to the drive node LQ is stopped after the time point t1 shown in FIG. 3, so that the voltage of the drive node LQ, that is, the voltage value of the reset drive voltage PWB is lower than the threshold voltage of the comparators (M22, M32). Transition to the low voltage value VL. Therefore, after the time t1 shown in FIG. 3, the transistor M22 is in the off state and the transistor M32 is in the on state, and the comparators (M22, M32) generate a power-on reset signal POR having a high voltage value VH as a voltage value for prompting the reset release. Generate.

As described above, in the power-on reset circuit 13, the current difference acquisition unit including the transistors M0 and M31 supplies the current Ir corresponding to the voltage value of the reference voltage VR to the drive node LQ and also supports the constant power supply voltage VDC. The generated current Ip is pulled out from the drive node LQ. The comparators (M22, M32) generate a power-on reset signal POR based on the comparison result of the magnitude of the voltage value generated in the drive node LQ by the current (Ir-Ip) and the predetermined threshold value.

Therefore, according to the above-mentioned current difference, the fluctuation of the threshold voltage of each transistor due to the manufacturing variation is canceled out. Therefore, even if there are manufacturing variations, it is possible to reliably generate a power-on reset signal POR that transitions from the low voltage value VL state that prompts reset to the high voltage value VH state that prompts reset release. Become.

Further, the power-on reset circuit 13 is provided with an offset adjusting unit CT1 for adjusting the threshold voltage of the comparators (M22, M32).

The offset adjustment unit CT1 draws the adjustment current Io1 corresponding to the constant current generated by the current source G2 from the drive node LQ, thereby relatively increasing the threshold voltage of the comparators (M22, M32) by that amount. That is, the threshold voltage of the comparators (M22, M32) is adjusted according to the amount of constant current generated by the current source G2.

According to the adjustment by the offset adjusting unit CT1, for example, the transistor M32 can be surely kept in the ON state after the reset is released. Therefore, after the time point t1 shown in FIG. 3, the voltage value of the power-on reset signal POR is maintained in the state of the high voltage value VH that surely prompts the reset release.

FIG. 4 is a circuit diagram showing another example of the internal configuration of the regulator 12 and the power-on reset circuit 13. Note that, in FIG. 4, the configuration is the same as that shown in FIG. 2, except that the power-on reset circuit 13 is newly provided with the second offset adjusting unit CT2.

Therefore, the configuration and operation of the offset adjusting unit CT2 will be described below.

As shown in FIG. 4, the offset adjusting unit CT2 has n-channel MOS type transistors M34 and M35. The drain end of the transistor M34 is connected to the drive node LQ. A constant current generated by the current source G2 is supplied to the gate end of the transistor M34, similarly to the gate ends of the transistors M20 and M21 of the offset adjusting unit CT1. The source end of the transistor M34 is connected to the drain end of the transistor M35. A ground potential VSS is applied to the source end of the transistor M35, and a power-on reset signal POR is supplied to the gate end thereof.

With this configuration, in the offset adjusting unit CT2, the transistor M35 is turned off when the power-on reset signal POR is in the low voltage value VL state, that is, during the reset period shown in FIG. Therefore, during this period, the offset adjusting unit CT2 is set to the inactive state, and the power-on reset circuit 13 becomes a circuit substantially equivalent to the configuration shown in FIG.

Further, when the power-on reset signal POR is in the state of the high voltage value VH, that is, after the time point t1 shown in FIG. 3, the transistor M35 of the offset adjusting unit CT2 is turned on. As a result, the adjustment current Io2 having a current amount corresponding to the constant current generated by the current source G2 is drawn from the drive node LQ via the transistors M34 and M35.

That is, although the operation of the offset adjustment unit CT2 is stopped during the reset period, the operation is started immediately after the end of the reset period, and the threshold voltage of the comparators (M22, M32) is changed by the adjustment current Io2.

Therefore, according to the offset adjusting unit CT2, it is possible to give the power-on reset circuit 13 a hysteresis.

Further, after the end of the reset period, the threshold voltage of the comparators (M22, M32) is adjusted by the adjustment current Io1 by the offset adjustment unit CT1 and the adjustment current Io2 by the offset adjustment unit CT2. That is, the adjustment range can be increased as compared with the case where the threshold voltage of the comparators (M22, M32) is adjusted only by the offset adjusting unit CT1.

In the embodiment shown in FIG. 4, two offset adjusting units CT1 and CT2 are provided in the power-on reset circuit 13, but only the offset adjusting unit CT2 of CT1 and CT2 is provided in the power-on reset circuit 13. You can do it. At this time, the offset adjusting unit CT2 is provided with the current source G2 of the offset adjusting unit CT1.

Further, if the power-on reset signal POR that transitions from the low voltage value VL state to the high voltage value VH state can be reliably generated without using the offset adjusting units CT1 and CT2, as shown in FIG. It is not necessary to provide the offset adjusting units CT1 and CT2.

Further, in the embodiment shown in FIG. 2 or 4, an n-channel MOS type transistor is adopted as the differential pair (M12, M13) of the regulator 12, but a p-channel MOS type transistor may be adopted. good.

Further, in the power-on reset circuit 13, the voltage of the node L1 of the regulator 12 is received as a reference voltage signal S1 representing the voltage value of the reference voltage VR, and the voltage of the node Lb of the regulator 12 is received by the voltage value of the constant power supply voltage VDC. Is received as a constant power supply voltage signal S2 representing.

However, the power-on reset circuit 13 may adopt a configuration that directly receives the reference voltage VR and the constant power supply voltage VDC.

In short, the semiconductor device 100 may include the following regulator and power-on reset circuit.

That is, the regulator (12) receives a reference voltage (VR) and generates a constant power supply voltage (VDC) having a voltage value corresponding to the reference voltage according to the power supply. The power-on reset circuit (13) has a first voltage value (VL) that prompts a reset for a predetermined period from the time when the power is turned on, based on a reference voltage and a constant power supply voltage, and is reset after a predetermined period has elapsed from the time when the power is turned on. A power-on reset signal (POR) that transitions to a second voltage value (VH) that prompts release is generated. The power-on reset circuit (13) includes the following current difference acquisition unit and comparator. The current difference acquisition units (M0, M31) supply the first current (Ir) corresponding to the voltage value of the reference voltage to the drive node (LQ), and the second current (Ip) corresponding to the constant power supply voltage. Is pulled out from the drive node. The comparators (M22, M32) obtain a power-on reset signal (POR) based on the result of comparing the magnitudes of the voltage value of the drive node (LQ) and the threshold voltage.

10 Internal circuit 11 Reference voltage generator 12 Regulator 13 Power-on reset circuit 100 Semiconductor device

Claims (9)

A regulator that receives a reference voltage and generates a constant power supply voltage that has a voltage value corresponding to the reference voltage when the power is turned on.
Based on the reference voltage and the constant power supply voltage, it has a first voltage value that prompts a reset for a predetermined period from the time when the power is turned on, and a second voltage that prompts the reset release after the elapse of the predetermined period from the time when the power is turned on. It has a power-on reset circuit that generates a power-on reset signal that transitions to a value.
The power-on reset circuit
With the drive node
A current difference acquisition unit that supplies a first current corresponding to the voltage value of the reference voltage to the drive node and draws a second current corresponding to the constant power supply voltage from the drive node.
A semiconductor device including a comparator that obtains the power-on reset signal based on a comparison result of a magnitude between a voltage of the drive node and a predetermined threshold voltage. The regulator
A voltage divider circuit that obtains a voltage divider by dividing the constant power supply voltage,
A differential pair in which a current corresponding to the reference voltage is passed through the first node and a current corresponding to the voltage dividing voltage is passed through the second node.
A current mirror circuit that supplies a current corresponding to the current flowing through the second node to the third node is included.
The current difference acquisition unit
A first transistor whose control end is connected to the first node and supplies a current corresponding to the voltage of the first node to the drive node as the first current.
The control end is connected to the third node, and includes a second transistor that draws a current corresponding to the voltage of the third node as the second current from the drive node.
The comparator
When the voltage of the drive node is larger than the threshold voltage, the power-on reset signal having a ground potential is output as the first voltage value, and when the voltage of the drive node is equal to or lower than the threshold voltage, the power-on reset signal is output. The semiconductor device according to claim 1, wherein the power-on reset signal having the constant power supply voltage is output as a second voltage value. The semiconductor device according to claim 1 or 2, wherein the semiconductor device includes a first adjusting unit that draws a predetermined first adjusting current from the drive node. The first adjusting unit is
With a current source that produces a given constant current,
The semiconductor device according to claim 3, further comprising a current mirror circuit that generates a current corresponding to the constant current as the first adjustment current. The semiconductor device according to claim 4 , further comprising a second adjusting unit that draws a predetermined second adjusting current from the drive node when the power-on reset signal has the second voltage value. The second adjusting unit is
A third transistor that generates a current corresponding to the constant current as the second adjustment current, and
A fourth transistor that is turned on when the power-on reset signal has the second voltage value and draws the second adjustment current generated by the third transistor from the drive node is included. The semiconductor device according to claim 5. The semiconductor device according to any one of claims 1 to 6, further comprising a reference voltage generating unit that generates the reference voltage when the power is turned on. The semiconductor device according to any one of claims 1 to 7, wherein the threshold voltage is a voltage corresponding to a voltage value of the constant power supply voltage. A power that has a first voltage value that prompts a reset for a predetermined period from the time when the power is turned on, and generates a power-on reset signal that transitions to a second voltage value that prompts the reset release after the elapse of a predetermined period from the time when the power is turned on. It is an on-reset device
A regulator that receives a reference voltage and generates a constant power supply voltage that has a voltage value corresponding to the reference voltage when the power is turned on.
With the drive node
A current difference acquisition unit that supplies a first current corresponding to the voltage value of the reference voltage to the drive node and draws a second current corresponding to the constant power supply voltage from the drive node.
A power-on reset device including a comparator that obtains the power-on reset signal based on a comparison result of magnitudes between a voltage of the drive node and a predetermined threshold voltage.

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