JP6958474B2 - Silicon carbide semiconductor device - Google Patents

Description

The present invention relates to a silicon carbide semiconductor device.

FIG. 7 of Patent Document 1 and its explanatory portion disclose that when switching is performed with a semiconductor device using silicon carbide, a displacement current flows on the source electrode side and a large potential is generated in the p-well under the gate pad. ing. Further, it is also disclosed that the potential of the p-well increases as the displacement current increases, and increases as the dV / dt, which is a variation of the drain voltage with respect to time, increases.

As a method of suppressing the potential difference between the two points under the gate pad, Al or B ion implantation is performed on the wafer surface under the gate pad and the gate built-in resistor to form a p-type region, and the resistance on the wafer surface is reduced. Alternatively, the source wiring may be routed around the gate pad.

Japanese Unexamined Patent Publication No. 2012-109602

In a silicon carbide semiconductor device having a gate built-in resistor, a thick field insulating film of, for example, about 1 μm, which is formed in a field process, exists under the gate built-in resistor formed of polysilicon. When the field insulating film has a pinhole, a thin gate oxide film having a thickness of, for example, several tens of nm, which is formed in the gate process, exists under the gate built-in resistor.

In the semiconductor device shown in Patent Document 1, when a high dV / dt of 100 kV / μsec or more is applied, a large potential difference is generated under the gate built-in resistance due to the displacement current, and the gate oxide film may be deteriorated. High dV / dt means that the switching element is driven at high speed. The contact between the gate built-in resistor and the substrate due to the deterioration of the gate oxide film means that the gate and the source are short-circuited.

The gate pad connected to the gate built-in resistor is formed on a thick interlayer insulating film. Therefore, even if there is a pinhole in the field insulating film, the interlayer insulating film is not destroyed when a large potential is generated in the p-well at high dV / dt. On the other hand, since there is no interlayer insulating film under the gate built-in resistor, special care must be taken not to short-circuit the gate and the source.

Switching elements such as MOSFETs made of silicon carbide cannot sufficiently suppress the potential generated under the gate built-in resistance when high dV / dt is applied. For example, if a pinhole is formed in the field insulating film under the gate built-in resistance and only a thin gate oxide film remains under the gate built-in resistance, the gate oxide film deteriorates when high dV / dt is applied, and the gate and source are damaged. There is a risk of short circuit.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a silicon carbide semiconductor device capable of suppressing a short circuit between a gate and a source.

The silicon carbide semiconductor device according to the first disclosure includes a silicon carbide semiconductor substrate having an n-type drift layer and a p-type well region formed on a part of the surface layer of the drift layer, and the well region. an insulating film provided on the provided on the insulating film, a gate built resistor formed of a polysilicon, an interlayer insulating film formed on the gate internal resistor, is connected to the gate pad The gate contact wiring formed on the interlayer insulating film, the gate wiring provided on the interlayer insulating film apart from the gate contact wiring, the gate contact wiring, and the gate built-in resistance are electrically operated. The first gate contact that connects the gate wiring and the second gate contact that electrically connects the gate wiring and the gate built -in resistor, and the insulating film or the interlayer between the gate built-in resistor and the gate pad in a plan view. It is characterized by including a source wiring formed on an insulating film and a source contact for electrically connecting the source wiring and the well region .

The second disclosed engaging Ru carbonization silicon semiconductor device, the silicon carbide semiconductor substrate, an insulating film provided on the silicon carbide semiconductor substrate is provided over the insulating film, formed of polysilicon A gate built-in resistor, an interlayer insulating film formed on the gate built-in resistor, and a gate pad formed on the interlayer insulating film are provided, and the silicon carbide semiconductor substrate is provided under the gate built-in resistor. A low resistance region provided below the insulating film, a p-shaped well region in contact with the bottom surface of the low resistance region, and n in contact with the bottom surface of the well region, the bottom surface of the low resistance region, or the bottom surface of the insulating film. It comprises a mold drift layer, and the low resistance region has a lower resistance than the well region.
The silicon carbide semiconductor device according to the third disclosure includes a silicon carbide semiconductor substrate having an n-type drift layer and a p-type well region formed on a part of the surface layer of the drift layer, and the well region. The insulating film provided on the above, the gate built-in resistor provided on the insulating film and formed of polysilicon, the interlayer insulating film formed on the gate built-in resistor, and the gate pad are connected. The gate contact wiring formed on the interlayer insulating film, the gate wiring provided on the interlayer insulating film separately from the gate contact wiring, the gate contact wiring, and the gate built-in resistance are electrically operated. The first gate contact that is connected to the gate, the second gate contact that electrically connects the gate wiring and the gate built-in resistance, and the gate built-in resistance between the gate built-in resistance and the gate pad in a plan view. A source wiring having a first portion provided along the line, a second portion extending in a direction different from the first portion and adjacent to the gate built-in resistor, and the first portion and the well region are electrically connected to each other. It is characterized by including a first source contact to be connected and a second source contact for electrically connecting the second portion and the well region.
The silicon carbide semiconductor device according to the fourth disclosure includes a silicon carbide semiconductor substrate having an n-type drift layer and a p-type well region formed on a part of the surface layer of the drift layer, and the well region. The insulating film provided on the above, the gate built-in resistor provided on the insulating film and formed of polysilicon, the interlayer insulating film formed on the gate built-in resistor, and the gate pad are connected. The gate contact wiring formed on the interlayer insulating film, the gate wiring provided on the interlayer insulating film apart from the gate contact wiring, the gate contact wiring, and the gate built-in resistance are electrically operated. A first gate contact is provided, a second gate contact that electrically connects the gate wiring and the gate built-in resistor, and a source wiring, and the source wiring is between the gate contact wiring and the gate wiring. It is characterized by having an immediate upper portion formed via the interlayer insulating film on the gate built-in resistor of the above.
The silicon carbide semiconductor device according to the fifth disclosure includes a silicon carbide semiconductor substrate having an n-type drift layer and a p-type well region formed on a part of the surface layer of the drift layer, and the well region. The insulating film provided on the above, the gate built-in resistor provided on the insulating film and formed of polysilicon, the interlayer insulating film formed on the gate built-in resistor, and the gate pad are connected. The gate contact wiring formed on the interlayer insulating film, the gate wiring provided on the interlayer insulating film apart from the gate contact wiring, the gate contact wiring, and the gate built-in resistor are electrically connected. The gate built-in resistor, the first gate contact, and the second gate are provided with a first gate contact for electrically connecting the gate wiring and the second gate contact for electrically connecting the gate wiring and the gate built-in resistor. By providing a plurality of configurations having contacts, a plurality of the gate built-in resistors are connected in parallel, and a source wiring formed between the plurality of gate built-in resistors in a plan view, the source wiring, and the well region. Alternatively, it is characterized by including a low resistance region having a resistance lower than that of the well region, and a source contact for electrically connecting the well region.
The silicon carbide semiconductor device according to the sixth disclosure includes a silicon carbide semiconductor substrate having an n-type drift layer and a p-type well region formed on a part of the surface layer of the drift layer, and the well region. The insulating film provided on the above, the gate built-in resistor provided on the insulating film and formed of polysilicon, the interlayer insulating film formed on the gate built-in resistor, and the gate pad are connected. The gate contact wiring formed on the interlayer insulating film, the gate wiring provided on the interlayer insulating film separately from the gate contact wiring, the gate contact wiring, and the gate built-in resistance are electrically operated. Auxiliary gate built-in resistor formed of polysilicon which is provided with a first gate contact for connecting the gate wiring and a second gate contact for electrically connecting the gate wiring and the gate built-in resistor, and which is in contact with the insulating film. And the auxiliary gate wiring, the third gate contact that electrically connects the gate wiring and the auxiliary gate built-in resistor, and the fourth gate contact that electrically connects the auxiliary gate wiring and the auxiliary gate built-in resistor. The gate built-in resistor and the auxiliary gate built-in resistor are connected in series, and the source wiring formed between the gate built-in resistor and the auxiliary gate built-in resistor in a plan view, the source wiring, and the said It is characterized by including a well region or a low resistance region having a resistance lower than the well region, and a source contact for electrically connecting the well region.
The silicon carbide semiconductor device according to the seventh disclosure includes a silicon carbide semiconductor substrate having an n-type drift layer and a p-type well region formed on a part of the surface layer of the drift layer, and the well region. The insulating film provided on the above, the gate built-in resistor provided on the insulating film and formed of polysilicon, the interlayer insulating film formed on the gate built-in resistor, and the gate pad are connected. The gate contact wiring formed on the interlayer insulating film, the gate wiring provided on the interlayer insulating film separately from the gate contact wiring, the gate contact wiring, and the gate built-in resistor are electrically connected. The first gate contact to be connected to the gate, the second gate contact to electrically connect the gate wiring and the gate built-in resistor, the gate built-in resistance monitor pad connected to the gate wiring, and the gate built-in resistance monitor pad. A source wiring formed at a position sandwiched between the gate built-in resistor and the source wiring, and a source contact for electrically connecting the source wiring and a well region or a low resistance region having a resistance lower than the well region. It is characterized by that.
The silicon carbide semiconductor device according to the eighth disclosure includes a silicon carbide semiconductor substrate having an n-type drift layer and a p-type well region formed on a part of the surface layer of the drift layer, and the well region. The insulating film provided on the above, the gate built-in resistor provided on the insulating film and formed of polysilicon, the interlayer insulating film formed on the gate built-in resistor, and the gate pad are connected. The gate contact wiring formed on the interlayer insulating film, the gate wiring provided on the interlayer insulating film apart from the gate contact wiring, the gate contact wiring, and the gate built-in resistance are electrically operated. A first gate contact for connecting to the gate, a second gate contact for electrically connecting the gate wiring and the gate built-in resistor, and a source wiring are provided, and the gate built-in resistor is sandwiched between the gate pad and the source wiring. It was provided only at the end of the area.

Other features of the present invention will be clarified below.

According to the present invention, the voltage generated in the well region below the gate built-in resistor can be reduced, and the reliability of the silicon carbide semiconductor device can be improved.

It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 2. FIG. It is sectional drawing of the silicon carbide semiconductor device which concerns on Embodiment 2. FIG. It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 3. FIG. It is sectional drawing of the silicon carbide semiconductor device which concerns on Embodiment 3. FIG. It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 4. FIG. It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 4. FIG. It is sectional drawing of the silicon carbide semiconductor device which concerns on Embodiment 4. FIG. It is sectional drawing of the silicon carbide semiconductor device which concerns on Embodiment 4. FIG. It is sectional drawing of the silicon carbide semiconductor device which concerns on Embodiment 4. FIG. It is sectional drawing of the silicon carbide semiconductor device which concerns on Embodiment 5. FIG. It is sectional drawing of the silicon carbide semiconductor device which concerns on Embodiment 6. It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 7. It is sectional drawing of the silicon carbide semiconductor device which concerns on Embodiment 7. FIG. It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 8. It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 9. FIG. It is sectional drawing of the silicon carbide semiconductor device which concerns on Embodiment 9. FIG. It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 10. It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 11. FIG. It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 12. It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 13. It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 14. It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 15. FIG. It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 15. FIG. It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 16. FIG. It is sectional drawing of the silicon carbide semiconductor device which concerns on Embodiment 16. FIG. It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 17. It is a partially enlarged view of FIG. 28. FIG. 2 is a cross-sectional view taken along the line III-III'of FIG. 29. It is a figure which shows the ion implantation region at the time of forming an n-type region and a source. It is a top view of the silicon carbide semiconductor device which concerns on 1st comparative example. It is sectional drawing of the silicon carbide semiconductor device which concerns on 1st comparative example. It is sectional drawing of the silicon carbide semiconductor device which concerns on 1st comparative example. It is a top view of the silicon carbide semiconductor device which concerns on 2nd comparative example. It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 18. It is a partially enlarged view of FIG. 36. It is a partial plan view of the silicon carbide semiconductor device which concerns on a modification. It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 19. It is a partially enlarged view of FIG. 39. It is a partial plan view of the silicon carbide semiconductor device which concerns on a modification.

The silicon carbide semiconductor device according to the embodiment of the present invention will be described with reference to the drawings. The same or corresponding components may be designated by the same reference numerals and the description may be omitted. The embodiment shows one aspect, and the embodiment does not give a limited interpretation to the invention. The disclosure contents of the embodiments and drawings described below are examples, and the invention should not be construed in a limited manner by these examples.

Embodiment 1.
FIG. 1 is a plan view of the silicon carbide semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view taken along the line AA'of FIG. In FIG. 1, for simplicity, the field insulating film, the interlayer insulating film, and the polysilicon that leads to the gate built-in resistance are excluded. Further, since the gate built-in resistance 20 is embedded inside the silicon carbide semiconductor device 10, it cannot be seen in the plan view. However, for convenience of explanation, the position of the gate built-in resistance 20 in the plan view is shown.

As shown in FIG. 2, the silicon carbide semiconductor device 10 according to the first embodiment includes an n-type drift layer 40. The drift layer 40 is formed, for example, on the n-type substrate 43 shown in FIG. 30 by epitaxial growth or the like. The donor concentration of the drift layer 40 can be, for example, 1 × 10 ¹⁴ cm ^-3 to 1 × 10 ¹⁷ cm ^-3 . The silicon carbide semiconductor substrate 41 has a drift layer 40 and a p-shaped well region 42 formed on a part of the surface layer of the drift layer 40. The acceptor concentration in the well region 42 can be, for example, in the range of 1 × 10 ¹⁴ cm ^-3 to 1 × 10 ¹⁸ cm ^-3 . The impurity concentration and thickness of the well region 42 do not have to be uniform. A field insulating film 47 is provided on the silicon carbide semiconductor substrate 41. That is, a field insulating film 47 is provided as an insulating film on the well region 42. The thickness of the insulating film above the well region 42 is the same as that of the field insulating film 47.

A gate built-in resistance 20 is provided on the field insulating film 47. The gate built-in resistance 20 can be formed of polysilicon that is in contact with the insulating film. An interlayer insulating film 50 is provided on the gate built-in resistance 20 to cover the gate built-in resistance 20 in a plan view. A gate contact wiring 15 and a gate wiring 16 are provided on the interlayer insulating film 50. FIG. 28 shows that the gate contact wiring 15 is connected to the gate pad 14. The gate contact wiring 15 overlaps the gate built-in resistance 20 in a plan view. The gate wiring 16 is provided apart from the gate contact wiring 15. The gate wiring 16 overlaps the gate built-in resistance 20 in a plan view. The gate wiring 16 faces the gate contact wiring 15. For example, the gate wiring 16 and the gate contact wiring 15 can be provided in parallel.

FIG. 2 shows the first gate contact 17a and the second gate contact 17b. The first gate contact 17a is provided, for example, in a through hole of the interlayer insulating film 50, and electrically connects the gate contact wiring 15 and the gate built-in resistance 20. The second gate contact 17b is provided, for example, in the through hole of the interlayer insulating film 50, and electrically connects the gate wiring 16 and the gate built-in resistance 20.

The drift layer 40 described above can be brought into contact with the well region 42 or the bottom surface of the field insulating film 47. A gate oxide film may be formed between the field insulating film 47 and the silicon carbide semiconductor substrate 41.

The gate pad 14 shown in FIG. 1 is a pad provided for installing the gate signal line from the outside of the silicon carbide semiconductor device 10. Therefore, the gate pad 14 has a sufficient area for installing the signal line. The size of the gate pad 14 can be, for example, 30 μm × 30 μm or more. The gate pad 14 can be formed of, for example, aluminum.

The gate contact wiring 15 is made of the same material as the gate pad 14, has a width smaller than one side of the gate pad 14, and is formed by connecting to the gate pad 14. The gate contact wiring 15 has, for example, an elongated linear shape, and one end thereof contacts the side surface of the gate pad 14. The width of the gate contact wiring 15 is preferably, for example, about 10 μm or more and 100 μm or less.

The gate wiring 16 is electrically connected to polysilicon formed in the transistor region of the silicon carbide semiconductor device 10. The width of the gate wiring 16 is preferably, for example, about 10 μm or more and 100 μm or less. The gate wiring 16 may be formed of the same material as the gate pad 14. The gate contact wiring 15 and the gate wiring 16 overlap the gate built-in resistance 20 in a plan view. At these overlapping positions, there are a first gate contact 17a and a second gate contact 17b.

The gate built-in resistance 20 is a polysilicon region including a portion directly below the first gate contact 17a and the second gate contact 17b and a portion sandwiched between the first gate contact 17a and the second gate contact 17b in a plan view. Point to.

The silicon carbide semiconductor device 10 of the first embodiment includes, for example, a source electrode formed on an interlayer insulating film. For example, the source wiring 12 shown in FIG. 28 can be provided. The main body 12A'of the source electrode functions as a source pad provided for installing the current line and the signal line from the outside. A source wiring made of the same material as the main body 12A'can be connected to the main body 12A'. The source wiring is, for example, the protrusion 12D'in FIG. 28. The width of the protruding portion 12D'is preferably 10 μm or more.

In the silicon carbide semiconductor device 10 of the first embodiment, the first gate contact 17a for electrically connecting the gate built-in resistance 20 and the gate pad 14 is formed under the gate contact wiring 15 drawn out from the gate pad 14. NS. Therefore, when a high dV / dt is applied by switching, it is possible to suppress the displacement current generated in the lower well region 42 of the gate pad 14 from flowing to the lower well region 42 of the gate built-in resistance 20. As a result, the potential generated in the well region 42 below the gate built-in resistance 20 can be suppressed, and element destruction due to a short circuit between the gate and the source can be prevented.

Embodiment 2.
FIG. 3 is a plan view of the silicon carbide semiconductor device according to the second embodiment. In FIG. 3, for the sake of simplicity, the field insulating film 47, the interlayer insulating film 50, and the polysilicon connected to the gate built-in resistance 20 are excluded. FIG. 4 is a cross-sectional view taken along the line AA'of FIG. The silicon carbide semiconductor device of the second embodiment has many similarities to the first embodiment, but is characterized in the position of the source wiring 12.

As shown in FIG. 3, the source wiring 12 is provided between the gate built-in resistance 20 and the gate pad 14 in a plan view. For example, in a plan view, the gate built-in resistance 20 does not exist and is adjacent to the gate built-in resistance 20, and is on a line connecting any position of the gate pad 14 and any position of the gate built-in resistance 20 in a plan view. The source wiring 12 can be provided in the. The source contact 13 electrically connects the source wiring 12 and the well region 42.

FIG. 4 shows that the source contact 13 is provided in the through hole of the interlayer insulating film 50. The source wiring 12 is electrically connected to the well region 42 through the source contact 13. Although the source wiring 12 is provided on the interlayer insulating film 50 in FIG. 4, the source wiring 12 may be provided on the field insulating film 47.

In the silicon carbide semiconductor device of the second embodiment, in addition to the first gate contact 17a being formed in the gate contact wiring 15 drawn from the gate pad 14, the displacement current generated in the well region 42 is sourced through the source contact 13. It is pulled out to the wiring 12. Therefore, when a high dV / dt is applied by switching, the potential generated in the well region 42 below the gate built-in resistance 20 can be suppressed. As a result, it is possible to prevent element destruction due to a short circuit between the gate and the source.

In FIG. 3, the planar shapes of the source contact 13, the first gate contact 17a, and the second gate contact 17b are rectangular. However, for example, a plurality of source contacts 13 may be provided so as to form a broken line-shaped source contact as a whole. For example, a plurality of source contacts 13 may be provided discretely and linearly. A plurality of first gate contacts 17a and second gate contacts 17b can also be provided.

Further, in FIG. 3, the source contact 13, the first gate contact 17a, and the second gate contact 17b are provided in parallel, but the above effect can be obtained even if they are not parallel. In the following description, the source contact 13 may be integrally formed in an arbitrary shape, or a plurality of source contacts 13 may be formed discretely, and the first gate contact 17a and the second gate contact 17b may also be integrally formed. Can also be formed discretely in a plurality, and when a plurality of source contacts 13, the first gate contact 17a or the second gate contact 17b are formed discretely, the longitudinal direction when viewed as a whole can be defined. ..

Embodiment 3.
FIG. 5 is a plan view of the silicon carbide semiconductor device according to the third embodiment. In FIG. 5, for the sake of simplicity, the field insulating film 47, the interlayer insulating film 50, and the polysilicon connected to the gate built-in resistance 20 are excluded. FIG. 6 is a cross-sectional view taken along the line AA'of FIG.

FIG. 5 shows two source wirings 12 sandwiching the gate contact wiring 15 and the gate wiring 16 in a plan view. The two source wirings 12 are provided at positions sandwiching the gate built-in resistance 20. The two source wirings 12 are provided along the gate contact wiring 15 and the gate wiring 16. The two source contacts 13 electrically connect the two source wires 12 to the well region 42. The first gate contact 17a, the second gate contact 17b, and the two source contacts 13 are parallel in the longitudinal direction.

In the silicon carbide semiconductor device according to the third embodiment, in addition to the first gate contact 17a being formed in the gate contact wiring 15 drawn from the gate pad 14, the displacement current generated in the well region 42 is two sources. It is pulled out to two source wires 12 through the contact 13. Therefore, when a high dV / dt is applied by switching, the potential generated in the well region 42 below the gate built-in resistance 20 can be suppressed, and as a result, element destruction due to a short circuit between the gate and the source can be prevented.

Embodiment 4.
FIG. 7 is a plan view of the silicon carbide semiconductor device according to the fourth embodiment. In FIG. 7, for the sake of simplicity, the field insulating film 47, the interlayer insulating film 50, and the polysilicon connected to the gate built-in resistance 20 are excluded. The gate built-in resistance 20 and the gate pad 14 face each other. A source wiring 12 and a source contact 13 are provided between the gate built-in resistance 20 and the gate pad 14. The source wiring 12 is provided adjacent to the gate built-in resistance 20 in a place where the gate built-in resistance 20 does not exist. The source wiring 12 is formed at a position sandwiched between the gate pad 14 and the gate built-in resistance 20.

In FIG. 7, the shape of the source contact 13 is one rectangle. However, the shape of the source contact 13 is arbitrary. For example, as shown in FIG. 8, a plurality of source contacts 13 may be provided in a straight line.

FIG. 9 is a cross-sectional view taken along the line AA'of FIG. FIG. 9 shows that the source contact 13 is next to the gate built-in resistance 20. FIG. 10 is a cross-sectional view taken along the line BB'of FIG. There is no source contact 13 in this cross section.

FIG. 11 is a diagram showing a modified example of the cross-sectional view taken along the line AA'of FIG. That is, the cross section along the AA'line of FIG. 8 may be as shown in FIG. 9 or as shown in FIG. FIG. 11 shows the gate 120 in contact with the source 45, the well region 42, and the drift layer 40 via the gate oxide film 48. The material of the gate 120 is, for example, polysilicon. A transistor structure having the above-mentioned elements is formed in the cross section of FIG. The thickness of the gate oxide film 48 and the thickness of the field insulating film 47 may be matched.

The source contact 13 is in contact with the well region 42 of the transistor region through the contact region 46, and is also in contact with the source 45. The contact region 46 can be, for example, a p-type region having an ^{acceptor concentration of 1 × 10 19} cm ^-3 to 1 × 10 ²¹ cm ^-3. The donor concentration of the source 45 can be, for example, 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ²⁰ cm ^-3 . In FIG. 11, the well regions 42 are provided at a plurality of distances, and the portion between the two well regions 42 functions as a path through which the on-current of the transistor flows. The plurality of well regions 42 in FIG. 11 can be connected on the back side of the paper surface or the front side of the paper surface of FIG. Such a transistor structure is not limited to a single cell, and may have a plurality of cells in the same cross section.

The source wiring 12 is electrically connected to the well region 42 by the source contact 13. As shown in FIG. 7 or 8, the source wiring 12 is formed between the gate built-in resistance 20 and the gate pad 14. Therefore, the displacement current generated in the well region 42 below the gate built-in resistance 20 is drawn out to the source wiring 12 through the source contact 13. As a result, when a high dV / dt is applied by switching, the potential generated in the well region 42 below the gate built-in resistance 20 can be suppressed.

Further, since the source wiring 12 and the source contact 13 are formed between the gate built-in resistance 20 and the gate pad 14, the displacement current flowing in the well region 42 below the gate pad 14 is transferred to the well region below the gate built-in resistance 20. It is possible to avoid or suppress the flow to 42. Therefore, the potential generated in the well region 42 below the gate built-in resistance 20 can be suppressed, and element destruction due to a short circuit between the gate and the source can be prevented.

Embodiment 5.
FIG. 12 is a cross-sectional view of the silicon carbide semiconductor device according to the fifth embodiment. In the present embodiment, the field insulating film 47 is provided on the silicon carbide semiconductor substrate 41. A gate built-in resistance 20 made of polysilicon, for example, is provided on the field insulating film 47. An interlayer insulating film 50 is provided on the gate built-in resistance 20. A gate pad 14 is provided on the interlayer insulating film 50. Then, as in the second embodiment, the source wiring 12 and the source contact 13 are provided.

The silicon carbide semiconductor device according to the fifth embodiment is similar to the second embodiment, but the configuration of the silicon carbide semiconductor substrate 41 is different. The silicon carbide semiconductor substrate 41 according to the fifth embodiment includes a low resistance region 146 in contact with the bottom surface of the field insulating film 47 under the gate built-in resistor 20. Since the low resistance region 146 is formed shallower than the well region 42, the well region 42 is in contact with the bottom surface of the low resistance region 146. The low resistance region 146 has a lower resistance than the well region 42. The low resistance region 146 is, for example, a high concentration p-type region. In this case, the acceptor concentration in the low resistance region 146 can be, for example, 1 × 10 ¹⁹ cm ^-3 to 1 × 10 ²¹ cm ^-3 . The low resistance region 146 may be p-type or n-type, but has a lower resistance than the well region 42. For example, the sheet resistance of the low resistance region 146 is made smaller than the sheet resistance of the well region 42. The drift layer 40 is in contact with the bottom surface of the well region 42. The drift layer 40 is in contact with the bottom surface of the low resistance region 146 where there is no well region 42. The drift layer 40 is in contact with the bottom surface of the field insulating film 47 in a place where the well region 42 and the low resistance region 146 are not present.

The source contact 13 electrically connects the source wiring 12 and the low resistance region 146. The source wiring 12 of the present embodiment can be formed on an insulating film or an interlayer insulating film between the gate built-in resistance 20 and the gate pad 14 in a plan view. That is, for example, the source wiring of the present embodiment can be provided at the position of the source wiring 12 of FIGS. 7 and 8. Alternatively, the source wiring of the present embodiment can be provided at the position of the source wiring 12 in FIG. In either case, the source contact 13 is brought into contact with the low resistance region 146. By bringing the source contact 13 into contact with the low resistance region 146, the source wiring 12 and the well region 42 can be electrically connected with a lower resistance. The low resistance region 146 can be provided at any location. The low resistance region 146 can be incorporated into the silicon carbide semiconductor device according to the above-described or later-described embodiment.

Since the silicon carbide semiconductor device according to the fifth embodiment has a low resistance region 146 below the gate built-in resistor 20, it is possible to suppress the generated potential associated with the displacement current when a high dV / dt is applied by switching. Therefore, it is possible to prevent element destruction due to a short circuit between the gate and the source.

Embodiment 6.
FIG. 13 is a cross-sectional view of the silicon carbide semiconductor device according to the sixth embodiment. The silicon carbide semiconductor device of the present embodiment is the same as that of the fifth embodiment in that it includes a low resistance region. However, the present embodiment is different from the fifth embodiment in that the high-concentration n-type region 44 or the p-type low resistance region 146 and the high-concentration n-type region 44 are provided side by side. The high-concentration n-type region 44 is, for example, a high-concentration n-type region having a donor concentration of 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ²⁰ cm ^-3 . The high concentration n-type region 44 can have a lower resistance than the well region 42. For example, the sheet resistance of the high-concentration n-type region 44 is smaller than the sheet resistance of the well region 42. Since the high-concentration n-type region 44 is formed shallower than the well region 42, the bottom surface of the high-concentration n-type region 44 is in contact with the well region 42.

The source wiring 12 is electrically connected to at least one of the well region 42 and the high-concentration n-type region 44 through the source contact 13. A high-concentration p-type region may be provided below the source contact 13 to electrically connect the source wiring 12 and the well region 42 to a lower resistance. A configuration in which the high-concentration n-type region 44 or the p-type low resistance region 146 and the high-concentration n-type region 44 are provided side by side can be provided at any location. The configuration in which the high-concentration n-type region 44 or the p-type low resistance region 146 and the high-concentration n-type region 44 are provided side by side can be incorporated into the silicon carbide semiconductor device according to the above-described or later-described embodiment.

Since the silicon carbide semiconductor device according to the sixth embodiment has a high-concentration n-type region 44 under the gate built-in resistor 20, it is possible to suppress the generated potential associated with the displacement current when a high dV / dt is applied by switching. .. Therefore, it is possible to prevent element destruction due to a short circuit between the gate and the source. In the fifth and sixth embodiments, the source wiring 12 and the source contact 13 are not indispensable configurations.

Embodiment 7.
FIG. 14 is a plan view of the silicon carbide semiconductor device according to the seventh embodiment. In FIG. 14, for the sake of simplicity, the field insulating film 47, the interlayer insulating film 50, and the polysilicon connected to the gate built-in resistance 20 are excluded. The silicon carbide semiconductor device of the present embodiment adopts a structure in which the two source contacts 13 described in the third embodiment face each other with the gate built-in resistance 20 interposed therebetween. The source contact 13 on the right side of this embodiment electrically connects the source wiring 12 or the source pad 112 to the well region 42. Further, the source wiring 12 and the source contact 13 on the left side of the gate built-in resistance 20 are provided between the gate built-in resistance 20 and the gate pad 14. The source contact 13 on the left side electrically connects the source wiring 12 and the well region 42.

FIG. 15 is a cross-sectional view taken along the line AA'of FIG. FIG. 15 shows that there are source contacts 13 on both sides of the gate built-in resistance 20. When a high dV / dt is applied by switching, the displacement current generated in the well region 42 below the gate built-in resistance 20 is drawn out to the source wiring 12 or the source pad 112 through the source contacts 13 provided on both sides of the gate built-in resistance 20. Therefore, the potential generated in the well region 42 below the gate built-in resistance 20 can be suppressed, and element destruction due to a short circuit between the gate and the source can be prevented.

Embodiment 8.
FIG. 16 is a plan view of the silicon carbide semiconductor device according to the eighth embodiment. In FIG. 16, for the sake of simplicity, the field insulating film 47, the interlayer insulating film 50, and the polysilicon connected to the gate built-in resistance 20 are excluded. The source wiring 12 of the present embodiment includes a first portion 12a and a second portion 12b. The first portion 12a is provided between the gate built-in resistance 20 and the gate pad 14 along the gate built-in resistance 20 in a plan view. The second portion 12b is connected to the first portion 12a and extends in a direction different from that of the first portion 12a and is adjacent to the gate built-in resistance 20. The first portion 12a is a portion corresponding to the source wiring 12 of the fourth embodiment. The first source contact 13a electrically connects the first portion 12a with the well region 42. The first portion 12a and the low resistance region may be electrically connected by the first source contact 13a.

The longitudinal direction of the second portion 12b is non-parallel to the longitudinal direction of the first portion 12a. The second portion 12b is provided at a position adjacent to the gate built-in resistance 20. The second portion 12b may be a part of the source pad 112 instead of a part of the source wiring. The second source contact 13b electrically connects the second portion 12b with the well region 42. The second source contact 13b may electrically connect the second portion 12b to the low resistance region.

In this embodiment, the first source contact 13a is provided along one side of the gate built-in resistor 20, and the second source contact 13b is provided along the other side of the gate built-in resistor 20. Therefore, the source contact is provided at a position facing the two sides of the gate built-in resistance 20. Source contacts may be provided at positions facing three or more sides of the gate built-in resistance 20. In other words, it is possible to provide the longest possible source contact along the outer edge of the gate built-in resistor 20.

In the silicon carbide semiconductor device of the eighth embodiment, when a high dV / dt is applied by switching, a displacement current generated in the well region 42 below the gate built-in resistance 20 is provided along the two sides of the gate built-in resistance 20. It is pulled out to the source wiring 12 or the source pad 112 through the two source contacts. Therefore, the potential generated in the well region 42 below the gate built-in resistance 20 can be suppressed, and element destruction due to a short circuit between the gate and the source can be prevented.

Embodiment 9.
FIG. 17 is a plan view of the silicon carbide semiconductor device according to the ninth embodiment. In FIG. 17, for the sake of simplicity, the field insulating film 47, the interlayer insulating film 50, and the polysilicon connected to the gate built-in resistance 20 are excluded. The silicon carbide semiconductor device of the present embodiment includes the source wiring 12A and the source contact 13A between the gate built-in resistor 20 and the gate pad 14, as in the fourth embodiment. The source contact 13A electrically connects the source wiring 12A to the well region 42 or the low resistance region.

Another source wiring 12B or source pad 112 is connected to the source wiring 12A. A source contact may be formed on the source wiring 12B or the source pad 112. A direct upper portion 12c is formed on the gate built-in resistance 20 between the gate contact wiring 15 and the gate wiring 16 via an interlayer insulating film. The immediate upper portion 12c is a part of the source wiring 12C that vertically traverses the gate built-in resistance 20 in a plan view. A source contact 13B is provided in a portion of the source wiring 12C above the immediate upper portion 12c. The longitudinal direction of the source contact 13B is non-parallel to the longitudinal direction of the source contact 13A. The source contact 13A is provided along the left side of the gate built-in resistance 20, whereas the source contact 13B is provided along the upper side of the gate built-in resistance 20. The source contacts 13A and 13B can be provided at positions sandwiching the gate contact wiring 15 by these. The source contact 13B electrically connects the source wiring 12C to the well region 42 or the low resistance region.

FIG. 18 is a cross-sectional view taken along the line AA'of FIG. Immediately above 12c forming a part of the source wiring is provided on the interlayer insulating film 50. In the silicon carbide semiconductor device according to the ninth embodiment, when a high dV / dt is applied by switching, the displacement current generated in the well region 42 below the gate built-in resistance 20 is along two orthogonal sides of the gate built-in resistance 20. It is drawn out to the source wiring 12 or the source pad 112 through the provided source contacts 13A and 13B. Therefore, the potential generated in the well region 42 below the gate built-in resistance 20 can be suppressed, and element destruction due to a short circuit between the gate and the source can be prevented.

Embodiment 10.
FIG. 19 is a plan view of the silicon carbide semiconductor device according to the tenth embodiment. In FIG. 19, for the sake of simplicity, the field insulating film 47, the interlayer insulating film 50, and the polysilicon connected to the gate built-in resistance 20 are excluded. The silicon carbide semiconductor device of the present embodiment includes the source wiring 12A and the source contact 13A between the gate built-in resistor 20 and the gate pad 14, as in the fourth embodiment. The source contact 13A electrically connects the source wiring 12A to the well region 42 or the low resistance region.

Another source wiring 12B or source pad 112 is connected to the source wiring 12A. A source contact may be formed on the source wiring 12B or the source pad 112. Further, as in the ninth embodiment, the source wiring 12C that vertically traverses the gate built-in resistance 20 in a plan view is provided. Immediately above 12c is formed as a part of the source wiring 12C. The source wiring 12D is connected to the source wiring 12C. The source wiring 12D includes an adjacent portion 12d at a position adjacent to the gate pad 14 in a plan view. The adjacent portion 12d can be formed on the field insulating film 47 or the interlayer insulating film 50. The source wirings 12B, 12C and 12D can also be formed as the source pad 112.

A source contact 13B is provided adjacent to the gate pad 14. The source contact 13B penetrates, for example, the field insulating film 47 or the interlayer insulating film 50, and electrically connects the adjacent portion 12d and the well region 42.

In the silicon carbide semiconductor device according to the tenth embodiment, the source wiring 12A electrically connected to the well region 42 through the source contact 13A is formed between the gate built-in resistance 20 and the gate pad 14. Therefore, when a high dV / dt is applied by switching, the displacement current generated in the well region 42 below the gate built-in resistance 20 is drawn out to the source wiring 12 through the source contact 13A. Further, the displacement current generated in the well region 42 below the gate pad 14 is drawn out through the source contact 13B provided adjacent to the gate pad 14. Therefore, the potential generated in the well region 42 below the gate built-in resistance 20 can be suppressed, and element destruction due to a short circuit between the gate and the source can be prevented.

Embodiment 11.
FIG. 20 is a plan view of the silicon carbide semiconductor device according to the eleventh embodiment. In FIG. 20, for the sake of simplicity, the field insulating film 47, the interlayer insulating film 50, and the polysilicon connected to the gate built-in resistance 20 are excluded. In this embodiment, two gate built-in resistors are provided. A gate built-in resistance 20A is provided on the right side of the gate pad 14, and a gate built-in resistance 20B is provided below the gate pad 14. In this way, the two gate built-in resistors are provided in parallel along the two non-parallel sides of the gate pad 14.

A source wiring 12A and a source contact 13A are provided between the gate pad 14 and the gate built-in resistance 20A. The source contact 13A electrically connects the source wiring 12A to the well region 42 or the low resistance region. A source wiring 12B and a source contact 13B are provided between the gate pad 14 and the gate built-in resistance 20B. The source contact 13B electrically connects the source wiring 12B to the well region 42 or the low resistance region. The source wirings 12A and 12B and the source contacts 13A and 13B face the two sides of the gate pad 14 as a whole. The source wiring 12C or the source pad 112 is connected to the source wirings 12A and 12B.

Since the silicon carbide semiconductor device of the eleventh embodiment has a structure having higher symmetry as compared with the configuration of the fourth embodiment, the displacement current flows more symmetrically when a high dV / dt is applied by switching, and the reliability of the device is increased. Is improved. Further, since the two gate built-in resistors 20A and 20B are provided, the gate built-in resistance per one can be reduced when the same resistance value is provided, as compared with the case where one gate built-in resistor 20 is provided as in the fourth embodiment. .. Therefore, the potential generated in the well region 42 below the gate built-in resistors 20A and 20B can be suppressed, and element destruction due to a short circuit between the gate and the source can be prevented.

Embodiment 12.
FIG. 21 is a plan view of the silicon carbide semiconductor device according to the twelfth embodiment. In FIG. 21, for the sake of simplicity, the field insulating film 47, the interlayer insulating film 50, and the polysilicon connected to the gate built-in resistance 20 are excluded. The gate built-in resistance 20A is on the right side of the gate pad 14, and the gate built-in resistance 20B is on the left side of the gate pad 14. The gate built-in resistors 20A and 20B are provided at positions sandwiching the gate pad 14. Two gate built-in resistors 20A and 20B are provided in parallel along two parallel sides of the gate pad 14.

A source wiring 12A and a source contact 13A are provided between the gate pad 14 and the gate built-in resistance 20A. The source contact 13A electrically connects the source wiring 12A to the well region 42 or the low resistance region. A source wiring 12B and a source contact 13B are provided between the gate pad 14 and the gate built-in resistance 20B. The source contact 13B electrically connects the source wiring 12B to the well region 42 or the low resistance region.

Since the silicon carbide semiconductor device of the twelfth embodiment has a structure having higher symmetry as compared with the configuration of the fourth embodiment, the displacement current flows more symmetricly when a high dV / dt is applied by switching, and the reliability of the device is increased. Is improved. Further, since the two gate built-in resistors 20A and 20B are provided, the gate built-in resistance per one can be reduced when having the same resistance value as compared with the case where one gate built-in resistance is provided as in the fourth embodiment. .. Therefore, the potential generated in the well region 42 below the gate built-in resistors 20A and 20B can be suppressed, and element destruction due to a short circuit between the gate and the source can be prevented.

Embodiment 13.
FIG. 22 is a plan view of the silicon carbide semiconductor device according to the thirteenth embodiment. In FIG. 22, for the sake of simplicity, the field insulating film 47, the interlayer insulating film 50, and the polysilicon connected to the gate built-in resistance 20 are excluded. In this embodiment, two gate built-in resistors are provided in series on the wiring connected to the gate pad 14.

The silicon carbide semiconductor device according to the thirteenth embodiment includes a gate contact wiring 15, a gate wiring 16A, and an auxiliary gate wiring 16B. The gate contact wiring 15 faces the gate wiring 16A. Further, the gate wiring 16A and the auxiliary gate wiring 16B face each other.

The gate built-in resistance 20 is provided so as to overlap the gate contact wiring 15 and the gate wiring 16A in a plan view. The gate contact wiring 15 and the gate built-in resistance 20 are electrically connected by the first gate contact 17a. Further, the gate wiring 16A and the gate built-in resistance 20 are electrically connected by the second gate contact 17b.

The auxiliary gate built-in resistance 20S is provided so as to overlap the gate wiring 16A and the auxiliary gate wiring 16B in a plan view. The auxiliary gate built-in resistance 20S can be formed of, for example, polysilicon that is in contact with the insulating film. The gate wiring 16A and the auxiliary gate built-in resistance 20S are electrically connected by a third gate contact 17c. The auxiliary gate wiring 16B and the auxiliary gate built-in resistance 20S are electrically connected by the fourth gate contact 17d. In this way, the gate built-in resistance 20 and the auxiliary gate built-in resistance 20S are connected in series.

A source wiring 12A and a source contact 13A are provided between the gate pad 14 and the gate built-in resistance 20. The source contact 13A connects the source wiring 12A to the well region 42 or the low resistance region. A source wiring 12B and a source contact 13B are provided between the gate built-in resistance 20 and the auxiliary gate built-in resistance 20S in a plan view. The source contact 13B electrically connects the source wiring 12B to the well region 42 or the low resistance region. The low resistance region is a region having a lower resistance than the well region.

In the silicon carbide semiconductor device of the thirteenth embodiment, since the gate built-in resistance 20 and the auxiliary gate built-in resistance 20S are provided in series, one gate built-in resistance is provided as in the fourth embodiment when a high dV / dt is applied by switching. Compared with the case, when the resistance value is the same, the resistance built into each gate can be reduced. Therefore, the potential generated in the well region below the gate built-in resistance 20 and the auxiliary gate built-in resistance 20S can be suppressed. Therefore, it is possible to prevent element destruction due to a short circuit between the gate and the source. In this embodiment, an example in which two gate built-in resistors are provided in series has been described, but three or more gate built-in resistors may be provided in series.

Embodiment 14.
FIG. 23 is a plan view of the silicon carbide semiconductor device according to the fourteenth embodiment. In FIG. 23, for the sake of simplicity, the field insulating film 47, the interlayer insulating film 50, and the polysilicon connected to the gate built-in resistors 20A and 20B are excluded. In this embodiment, two gate built-in resistors are provided in parallel on the wiring connected to the gate pad 14.

Two gate built-in resistors 20A and 20B connect the gate contact wiring 15 and the gate wiring 16. Specifically, the gate built-in resistance 20A is connected to the gate contact wiring 15 by the first gate contact 17a and connected to the gate wiring 16 by the second gate contact 17b. The gate built-in resistance 20B is connected to the gate contact wiring 15 by the third gate contact 17c, and is connected to the gate wiring 16 by the fourth gate contact 17d. As described above, by providing a plurality of configurations having the gate built-in resistance, the first gate contact, and the second gate contact, the plurality of gate built-in resistors are connected in parallel. It can be said that such a configuration is obtained by dividing the gate built-in resistance 20 of the fourth embodiment shown in FIG. 7 into two gate built-in resistances connected in parallel.

A source wiring 12A and a source contact 13A are provided between the gate built-in resistors 20A and 20B and the gate pad 14. The source contact 13A electrically connects the source wiring 12A to the well region 42 or the low resistance region. The source wiring 12B or the source pad 112 is connected to the source wiring 12A. The source wiring 12B or the source pad 112 is formed with a source wiring 12C that vertically traverses the gate built-in resistors 20A and 20B between the gate contact wiring 15 and the gate wiring 16. The source wiring 12C includes a direct upper portion passing through the upper portions of the gate built-in resistors 20A and 20B. A source contact 13B is formed in a portion of the source wiring 12C formed between the gate built-in resistance 20A and the gate built-in resistance 20B in a plan view. The source contact 13B electrically connects the source wiring 12C to a well region or a low resistance region having a resistance lower than that of the well region. In this way, the source contact 13B is provided between the first gate built-in resistance 20A and the second gate built-in resistance 20B.

In the silicon carbide semiconductor device of the fourteenth embodiment, since the two gate built-in resistors 20A and 20B are provided in parallel, each gate built-in resistance has the same resistance value as compared with the case where the gate built-in resistance has one. Can be made smaller. Therefore, when a high dV / dt is applied by switching, the potential generated in the well region below each gate built-in resistor can be suppressed.

Further, as described above, since the source contact 13B for electrically connecting the source wiring 12C and the well region is provided between the gate built-in resistance 20A and the gate built-in resistance 20B, the displacement current is also drawn to the source wiring 12C. .. Therefore, the potential generated in the well region 42 below each gate built-in resistor can be suppressed, and element destruction due to a short circuit between the gate and the source can be prevented. In the present embodiment, an example in which two gate built-in resistors 20A and 20B are provided in parallel and a source contact 13B is formed between them has been described, but the same effect can be obtained even when three or more gate built-in resistors are provided. Obtainable.

Embodiment 15.
FIG. 24 is a plan view of the silicon carbide semiconductor device according to the fifteenth embodiment. In FIG. 24, for the sake of simplicity, the field insulating film 47, the interlayer insulating film 50, and the polysilicon connected to the gate built-in resistors 20A and 20B are excluded. Since the gate built-in resistors 20A and 20B are connected in parallel in this embodiment, they are basically similar to those in the 14th embodiment. The same as in the 14th embodiment is that the source contact 13B is provided between the first gate built-in resistance 20A and the second gate built-in resistance 20B. However, the configurations that provide such source contacts are different.

As shown in FIG. 24, the gate wiring 16 has a portion that protrudes toward the gate contact wiring 15 in a portion facing the gate contact wiring 15. The source wiring 12B and the source contact 13B are provided in the space created by projecting the gate wiring 16 in this way. The source wiring 12B and the source contact 13B are located between the gate built-in resistance 20A and the gate built-in resistance 20B. The source contact 13B electrically connects the source wiring 12B to the well region 42 or the low resistance region. As described above, the source wiring 12B and the source contact 13B are provided between the gate built-in resistance 20A and the gate built-in resistance 20B without providing the source wiring passing over the gate built-in resistors 20A and 20B described in the 14th embodiment.

FIG. 25 is a plan view of a modified example of the silicon carbide semiconductor device according to the fifteenth embodiment. The gate contact wiring 15 has a portion that protrudes toward the gate wiring 16 in a portion that faces the gate wiring 16. The source wiring 12B and the source contact 13B are provided in the space created by projecting the gate contact wiring 15 in this way. The source wiring 12B and the source contact 13B are located between the gate built-in resistance 20A and the gate built-in resistance 20B.

In the silicon carbide semiconductor device of the 15th embodiment, since the two gate built-in resistors 20A and 20B are provided in parallel, each gate has the same resistance value as compared with the case where one gate built-in resistor is provided. The built-in resistance can be reduced. Therefore, when a high dV / dt is applied by switching, the potential generated in the well region 42 below each gate built-in resistor can be suppressed.

Further, as described above, since the source contact 13B for electrically connecting the source wiring 12B and the well region 42 is provided between the gate built-in resistance 20A and the gate built-in resistance 20B, the displacement current is also drawn to the source wiring 12B. Become. As described in the 14th embodiment, three or more gate built-in resistors may be provided in parallel, and a source wiring and a source contact may be provided between the gate built-in resistors.

Embodiment 16.
FIG. 26 is a plan view of the silicon carbide semiconductor device according to the sixteenth embodiment. In FIG. 26, for the sake of simplicity, the field insulating film 47, the interlayer insulating film 50, and the polysilicon connected to the gate built-in resistance 20 are excluded. In a silicon carbide semiconductor device having a gate built-in resistance, a monitor pad for measuring the value of the gate built-in resistance may be provided. The silicon carbide semiconductor device of the present embodiment is based on a configuration similar to any one of the fourth to sixth embodiments, and includes a gate built-in resistance monitor pad 114 for measuring the value of the gate built-in resistance 20.

The gate built-in resistance monitor pad 114 is connected to the gate wiring 16. The gate built-in resistance monitor pad 114 can be formed of, for example, the same material as the gate wiring 16. A source wiring 12B and a source contact 13B are provided at a position sandwiched between the gate built-in resistance monitor pad 114 and the gate built-in resistance 20. The source contact 13B electrically connects the source wiring 12B to a well region or a low resistance region having a resistance lower than that of the well region.

FIG. 27 is a cross-sectional view taken along the line AA'of FIG. 26. Source contacts 13A and source contacts 13B are provided on the left and right sides of the gate built-in resistor 20. When a high dV / dt is applied by switching, the displacement current generated in the well region 42 below the gate built-in resistance 20 is drawn out to the source wiring 12 through the source contacts provided on both sides of the gate built-in resistance 20. Therefore, the potential generated in the well region 42 below the gate built-in resistance 20 can be suppressed, and element destruction due to a short circuit between the gate and the source can be prevented. The gate wiring according to the first to sixteenth embodiments is a wiring to which a gate drive signal of, for example, a SiC-MOSFET is supplied, similarly to the gate wiring of the seventeenth embodiment. Further, the semiconductor device described in the embodiments so far and the semiconductor device described in the following embodiments can be SiC-MOSFET chips. Such MOSFETs can be planar or trench type. Further, the semiconductor device may be an IGBT that employs a MOS structure.

Embodiment 17.
FIG. 28 is a plan view of the silicon carbide semiconductor device 10 according to the seventeenth embodiment. The silicon carbide semiconductor device 10 is a SiC-MOSFET chip. The silicon carbide semiconductor device 10 includes, for example, a source wiring 12 made of aluminum as a material. A gate pad 14 is provided at the chip corner. The gate pad 14 is a portion to which the wire is connected. A gate drive signal is provided from the outside to the gate pad 14 via the wire. The gate wiring 16 is connected to the gate pad 14 via the gate built-in resistors 20A and 20B. Since the gate built-in resistors 20A and 20B are embedded inside the silicon carbide semiconductor device 10, they cannot be seen in the plan view. However, for convenience of explanation, the positions of the gate built-in resistors 20A and 20B in the plan view are shown.

The gate built-in resistors 20A and 20B are resistors that connect the gate pad 14 and the gate wiring 16. The gate wiring 16 is formed along the outer circumference of the chip to surround most of the source wiring 12. The gate built-in resistance can be provided only at the end of the region sandwiched between the gate pad 14 and the source wiring 12.

The source wiring 12 includes a main body portion 12A', an immediate upper portion 12B', a surrounding portion 12C', and a protruding portion 12D'. The main body 12A'is provided in the cell region. Immediately above 12B'is a portion directly above the gate built-in resistance 20B. The surrounding portion 12C'is a portion that surrounds the gate pad 14 by being provided along the outer edge of the chip. The surrounding portion 12C'is connected to the main body portion 12A' via the directly upper portion 12B'. The protruding portion 12D'is a portion sandwiched between the gate pads 14 in a plan view. Since the gate pad 14 is provided in the y-positive direction and the y-negative direction of the protruding portion 12D', the protruding portion 12D'is sandwiched between the gate pads 14. The protruding portion 12D'is provided so as to protrude from the main body portion 12A'in a plan view. The protruding portion 12D'is connected to the main body portion 12A'.

Since the protruding portion 12D'is formed as a part of the source wiring 12, the gate built-in resistance 20B is sandwiched between the protruding portion 12D'and the main body portion 12A' in a plan view. That is, there is a protruding portion 12D'in the y positive direction of the gate built-in resistance 20B, and a main body portion 12A'in the y negative direction of the gate built-in resistance 20B.

FIG. 29 is a partially enlarged view of FIG. 28. The gate pad 14 includes a main body portion 14A, first connection portions 14B and 14D, and second connection portions 14C and 14E. A wire is connected to the main body 14A. The main body portion 14A and the first connecting portions 14B and 14D are connected via the second connecting portions 14C and 14E. The protruding portion 12D', which is a part of the source wiring 12, is sandwiched between the main body portion 14A and the first connecting portion 14B. The protruding portion 12F, which is a part of the source wiring 12, is sandwiched between the main body portion 14A and the first connecting portion 14D.

The gate wiring 16 includes annular portions 16A'and 16C formed along the outer periphery of the chip, a connecting portion 16B'connected to the annular portion 16A', and a connecting portion 16D connected to the annular portion 16C. .. A gate drive signal is provided from the gate pad 14 to the gate wiring 16 via the gate built-in resistors 20A and 20B. A gate voltage is applied to the gate of the unit cell from the annular portions 16A'and 16C and the connecting portions 16B'and 16D.

Above the gate built-in resistance 20A, there is a direct upper portion 12E which is a part of the source wiring 12. Immediately above 12E connects the surrounding portion 12C'and the main body portion 12A'. As described above, there is a gate built-in resistance 20B connecting the first connection portion 14B and the connection portion 16B'in the y negative direction of the gate pad 14, and the first connection portion 14D and the connection portion 16D in the x positive direction of the gate pad 14. There is a gate built-in resistance 20A to connect.

FIG. 30 is a cross-sectional view taken along the line III-III'(source contact hole portion, gate contact hole portion) of FIG. 29. The silicon carbide semiconductor device 10 includes a silicon carbide semiconductor substrate 41 made of silicon carbide as a material. The silicon carbide semiconductor substrate 41 is placed on the n-type substrate 43, the n-type drift layer 40, the p-type well region 42 provided on the n-type drift layer 40, and the p-type well region 42. It is provided with a high-concentration n-type region 44 provided. ^{The high-concentration n-type region 44 is an n +} region in which n-type impurities are doped at a high concentration (1 × 10 ¹⁹ cm ^-3 or more). The n-type impurity concentration in the high-concentration n-type region 44 is larger than the n-type impurity concentration in the n-type drift layer 40. The silicon carbide semiconductor substrate 41 is also provided with an n-type source 45 surrounded by a p-type well region 42. Further, a p-type contact region 46 located on the surface of the silicon carbide semiconductor substrate 41 while being in contact with the high-concentration n-type region 44 is provided. Below the n-type drift layer 40 is an n-type substrate 43.

A field insulating film 47 and a gate oxide film 48 are provided on the silicon carbide semiconductor substrate 41. A gate built-in resistance 20B made of polysilicon is provided on the field insulating film 47. A part of the side surface and the upper surface of the gate built-in resistance 20B is covered with the interlayer insulating film 50. The interlayer insulating film 50 is preferably thicker than the insulating film such as the field insulating film 47. The interlayer insulating film 50 and the field insulating film 47 are preferably thicker than the gate oxide film 48. A plurality of through holes are provided in the interlayer insulating film 50 provided on the gate built-in resistance 20B. The first connection portion 14B, which is a part of the gate pad 14, and the connection portion 16B', which is a part of the gate wiring 16, come into contact with the gate built-in resistance 20B through these through holes.

A plurality of through holes are also formed in the left and right interlayer insulating films 50 of the gate built-in resistance 20B. Through these plurality of through holes, the protruding portion 12D'of the source wiring 12 is connected to the p-type contact region 46 and the high-concentration n-type region 44, and the main body portion 12A'of the source wiring 12 is also connected to the p-type contact region 46 and the p-type contact region 46. It is connected to the high concentration n-type region 44. It is also disclosed in FIG. 30 that the left side portion of the main body portion 12A'is connected to the p-shaped contact region 46 and the source 45.

FIG. 30 shows that the first connection portion 14B of the gate pad 14 and the connection portion 16B'of the gate wiring 16 are connected to the gate built-in resistance 20B. A high-concentration n-type region 44 is provided under the gate built-in resistance 20B via a field insulating film 47. The main body portion 12A'and the protruding portion 12D', which are a part of the source wiring 12, are connected to the high-concentration n-type region 44. In order to suppress a short circuit between the gate and the source, it is necessary that the gate built-in resistance 20B and the high-concentration n-type region 44 are surely insulated by the field insulating film 47.

The back surface structure of the silicon carbide semiconductor device 10 will be described. A drain electrode 62 made of a metal is formed on the lower surface of the ohmic electrode 60 on the back surface of the silicon carbide semiconductor substrate 41. Therefore, the above-mentioned n-type substrate 43 is provided between the n-type drift layer 40 and the ohmic electrode 60. In this way, the silicon carbide semiconductor device for electric power whose cross-sectional view is shown in FIG. 30 is completed. The cross section along the line crossing the gate built-in resistance 20A in the x direction is the same as that in FIG.

FIG. 31 is a diagram showing an ion implantation region when forming the high-concentration n-type region 44 and the source 45. The high-concentration n-type region 44 and the source 45 may be formed by the same ion implantation. Basically, n-type impurities are doped in the regions A and B surrounded by the alternate long and short dash line. The region A includes a portion where the gate built-in resistors 20A and 20B are formed. The area B includes a portion where the main body portion 12A'of the source wiring 12 is formed. In the region B, a MOSFET unit cell is formed as shown in the central portion of FIG. 2 of JP2012-109602A. Instead of forming the source 45 on the entire surface of the region B, the source is partially formed as in the source region 80 of FIG. 3 of JP2012-109602A. In region B, there is a region directly below the source contact holes provided at equal intervals and where n-type impurities are not doped. Further, instead of doping the entire surface of the region A with n-type impurities, there is a region directly below the main body portion 12A', the surrounding portion 12C', the protruding portion 12D', and 12F of the region A in which the n-type impurities are not doped. ..

Here, in order to facilitate the explanation of the technical significance of the silicon carbide semiconductor device according to the 17th embodiment of the present invention, a comparative example will be described. FIG. 32-34 is a diagram of a silicon carbide semiconductor device according to the first comparative example. FIG. 35 is a plan view of the silicon carbide semiconductor device according to the second comparative example. The differences between the first comparative example and the second comparative example from the silicon carbide semiconductor device 10 of the 17th embodiment will be described. A point not particularly mentioned has the same configuration as the silicon carbide semiconductor device 10.

FIG. 32 is a plan view of the silicon carbide semiconductor device according to the first comparative example. The source wiring 12 of the first comparative example includes a main body portion 12A', an immediate upper portion 12B', 12E, and a surrounding portion 12C', but does not include the above-mentioned protruding portions 12D', 12F. The gate built-in resistors 20a and 20b have the same functions as the gate built-in resistors 20A and 20B of the silicon carbide semiconductor device 10.

FIG. 33 is a cross-sectional view taken along the line VI-VI'of FIG. 32. Immediately below the gate built-in resistance 20b, there is a p-type well region 42 via a field insulating film 47. Al or B can be ion-implanted into the semiconductor substrate to form a p-type well region 42, which is ^{a p + region.} The p-shaped well region 42 is formed under the gate pad 14 and the gate built-in resistance 20b. Immediately below the gate built-in resistance 20b, there is no n-type region described above. Further, the source wiring 12 of the first comparative example does not include the protrusion 12D'. Therefore, only the main body portion 12A'of the source wiring 12 is connected to the p-shaped well region 42 directly below the gate built-in resistance 20b.

FIG. 34 is a cross-sectional view of a silicon carbide semiconductor device of the first comparative example in which pinholes are formed in the field insulating film 47. In this case, only a thin gate oxide film 48 is provided between the gate built-in resistance 20b and the p-type well region 42. In this case, the gate oxide film 48 deteriorates at high dV / dt, and the gate and the source may be short-circuited.

On the other hand, in the silicon carbide semiconductor device 10 according to the seventeenth embodiment, for example, N (nitrogen) or P (phosphorus) was ion-implanted into the silicon carbide semiconductor substrate 41 to form a high-concentration n-type region 44. More specifically, on the high-concentration n-type region 44 in contact with the bottom surface of the field insulating film 47, which is an insulating film, the p-type well region 42 in contact with the bottom surface of the high-concentration n-type region 44, and the bottom surface of the well region 42. An n-type drift layer 40 in contact was provided. When the material of the silicon carbide semiconductor substrate 41 is silicon carbide, the resistance is lower in the ^{n +} region than in ^{the p + region.} Therefore, by providing the high-concentration n-type region 44, it is possible to reduce the resistance in the path through which the displacement current flows under the gate pad 14 and the gate built-in resistors 20A and 20B. As a result, it is possible to suppress the potential difference between the gate pad 14 and the gate built-in resistors 20A and 20B and the silicon carbide semiconductor substrate 41 directly underneath, which is caused by the displacement current due to the application of dV / dt.

Next, the significance of the protrusion 12D'provided in the source wiring 12 of the silicon carbide semiconductor device of the 17th embodiment will be described. For example, in a switching operation in which a high dV / dt of 100 kV / μsec or more is applied, even if a high concentration n-type region 44 is formed, the gate is built in due to the displacement current flowing from under the gate pad 14 to the source wiring 12. The generated potential of the p-type well region 42 under the resistance may be 100 V or more. In this case, if there is a pinhole in the field insulating film 47, there is a concern that the gate oxide film 48 may deteriorate.

Therefore, in addition to providing the high-concentration n-type region 44, projecting portions 12F and 12D, which are a part of the source wiring 12, are provided between the main body portion 14A of the gate pad 14 and the gate built-in resistors 20A and 20B. The lower ends of the protrusions 12F and 12D are connected to the p-type contact region 46 and the high-concentration n-type region 44. FIG. 30 shows that the lower end of the protrusion 12D'is connected to the p-type contact region 46 and the high-concentration n-type region 44. The lower end of the protruding portion 12D'is in direct contact not only with the p-type contact region 46 but also with the high-concentration n-type region 44. The portion connecting the protruding portion 12D'and the high-concentration n-type region 44 directly below the protruding portion 12D'is the first contact. Then, the portion connecting the main body portion 12A'of the source wiring 12 and the high-concentration n-type region 44 directly below the main body portion 12A'is referred to as a second contact. The first contact and the second contact sandwich the gate built-in resistance 20B in a plan view.

In FIG. 30, the first contact connecting the protruding portion 12D'and the high-concentration n-type region 44 directly below the protruding portion 12D', the main body portion 12A'of the source wiring 12, and directly below the main body portion 12A' It is shown that the second contact connecting the high-concentration n-type region 44 sandwiches the gate built-in resistor 20B. As a result, two contact portions between the source wiring 12 and the high-concentration n-type region 44 are provided on the left and right sides of the gate built-in resistance 20B. In this way, the displacement current generated when high dV / dt is applied can be drawn from both the main body portion 12A'and the protruding portion 12D'. In FIG. 30, the flow of the displacement current in the p-type well region 42 and the high-concentration n-type region 44 is indicated by arrows. By drawing the displacement current from both the main body portion 12A'and the protruding portion 12D', the potential of the p-type well region 42 can be suppressed.

For example, in the case of the first comparative example shown in FIG. 33, since the source wiring 12 and the silicon carbide semiconductor substrate 41 are not connected under the gate pad 14, the displacement current generated under the gate pad 14 is far away from it. It flows into the connection portion between the main body portion 12A'and the silicon carbide semiconductor substrate 41. Therefore, the potential of the p-type well region 42 becomes high.

On the other hand, in the 17th embodiment, the protruding portions 12D'and 12F sandwiched between the gate pads 14 are provided, and the protruding portions 12D'and 12F are connected to the high-concentration n-type region 44. As a result, the displacement current generated in the p-type well region 42 and the high-concentration n-type region 44 under the gate pad 14 quickly flows to the protrusions 12D'and 12F, which are closer than the main body 12A'. Therefore, the displacement current flowing under the gate built-in resistors 20A and 20B can be suppressed, and the generation of a large potential on the silicon carbide semiconductor substrate 41 under the gate built-in resistors 20A and 20B can be suppressed. Suppressing the generated potential has the effect of preventing deterioration of the gate oxide film 48 when the field insulating film 47 has pinholes or the like.

In this way, by providing the two contacts connecting the high-concentration n-type region 44 and the source wiring 12 so as to sandwich the gate built-in resistance in a plan view, it is possible to prevent the generation of a high potential due to the displacement current. By electrically connecting the high-concentration n-type region 44 and the source wiring 12 at a plurality of locations, it is possible to secure a path through which the displacement current flows and prevent the potential of the silicon carbide semiconductor substrate 41 from increasing. As particularly preferable examples, the protrusions 12D'and 12F have been mentioned.

Next, the positions of the gate built-in resistors 20A and 20B will be discussed. FIG. 35 is a plan view of the silicon carbide semiconductor device according to the second comparative example. The gate built-in resistors 20a and 20b of this silicon carbide semiconductor device are located closer to the center of the chip than the gate built-in resistors 20A and 20B in FIG. 28. That is, the gate built-in resistors 20a and 20b are located farther from the outer edge of the chip than the gate built-in resistors 20A and 20B in FIG. 28.

Since the gate built-in resistors 20a and 20b in FIG. 35 are separated from the chip end, the connection portions 16B'and 16D and the first connection portions 14B and 14D must be longer than in the case of FIG. 28. In the case of the second comparative example, the invalid area must be expanded by that amount.

In the 17th embodiment, by arranging the gate built-in resistors 20A and 20B on the chip end side, the connection portions 16B'and 16D and the first connection portions 14B and 14D can be shortened as compared with the case of the second comparative example. Therefore, it is possible to increase the effective area by increasing the area of the source electrode. When the gate pad 14 is provided along the outer edge of the chip, it is preferable that the positions of the gate built-in resistors 20A and 20B are closer to the edge of the chip than the center of the gate pad 14. FIG. 29 shows that the gate built-in resistance 20A is closer to the chip end by the gate built-in resistance 20A being in the y positive direction with respect to the center of the gate pad 14. It is also shown that the gate built-in resistance 20B is closer to the chip end because the gate built-in resistance 20B is in the x-negative direction from the center of the gate pad 14.

The silicon carbide semiconductor device according to the seventeenth embodiment can be variously modified without losing its characteristics. For example, if it is possible to prevent the potential of the semiconductor substrate immediately below the gate built-in resistors 20A and 20B from becoming too high simply by providing the high-concentration n-type region 44, the protrusions 12D'and 12F may be omitted. Various types of switching elements using silicon carbide can be adopted as the silicon carbide semiconductor device 10. A pressure-resistant holding structure such as a channel stopper, a guard ring, and a field plate may be appropriately provided.

In this embodiment, gate built-in resistors 20A and 20B are provided on the field insulating film 47. Even when an insulating film other than the field insulating film 47 is provided between the gate built-in resistors 20A and 20B and the silicon carbide semiconductor substrate 41, the effect of providing the high-concentration n-type region 44 can be obtained.

These modifications can also be applied to the silicon carbide semiconductor device according to the following embodiment. Since the silicon carbide semiconductor device according to the following embodiment has much in common with the embodiment 17, the differences from the embodiment 17 will be mainly described.

Embodiment 18.
FIG. 36 is a plan view of the silicon carbide semiconductor device according to the eighteenth embodiment. The gate pad 14 is provided at the central upper end of the chip, not at the chip corner. Gate built-in resistors 20C, 20D, 20E, and 20F are connected to the gate pad 14. The gate built-in resistors 20C and 20D are on the right side of the gate pad 14, and the gate built-in resistors 20E and 20F are on the left side of the gate pad 14.

The gate wiring 16 is connected to the gate built-in resistors 20C, 20D, 20E, and 20F. The gate wiring 16 encloses the main body portion 12A'of the source wiring 12 as a whole. The gate wiring 16 includes connection portions 16E and 16G connected to the gate built-in resistance, and an intermediate portion 16F connecting the connection portion 16E and the connection portion 16G. The connection portion 16E is connected to the gate built-in resistors 20C and 20D. The connection portion 16G is connected to the gate built-in resistors 20E and 20F.

The source wiring 12 includes a main body portion 12A', an annular portion 12H, and protruding portions 12I and 12J. The annular portion 12H is an annular portion connected to the main body portion 12A'. The annular portion 12H surrounds the main body portion 12A'and the gate wiring 16. The protrusions 12I and 12J are connected to the annular portion 12H. The protrusions 12I and 12J have the same functions as the protrusions of the first embodiment. That is, the protruding portions 12I and 12J are sandwiched between the gate pads 14 in a plan view. Then, in a plan view, the gate built-in resistors 20E and 20F are sandwiched between the protruding portion 12I and the main body portion 12A'. In a plan view, the gate built-in resistors 20C and 20D are sandwiched between the protruding portion 12J and the main body portion 12A'.

Further, the first contact connecting the protruding portion 12I and the high-concentration n-type region 44 directly below the protruding portion 12I, and the main body portion 12A'and the high-concentration n-type region 44 directly below the main body portion 12A' are connected. The gate built-in resistors 20E and 20F are sandwiched between the second contacts. The first contact connecting the protruding portion 12J and the high-concentration n-type region 44 directly below the protruding portion 12J, and the second contact connecting the main body portion 12A'and the high-concentration n-type region 44 directly below the main body portion 12A'. With two contacts, the gate built-in resistors 20C and 20D are sandwiched in a plan view. As a result, as in the first embodiment, it is possible to prevent the potential of the semiconductor substrate from increasing immediately below the gate pad 14 and in the vicinity thereof due to the generation of the displacement current.

FIG. 37 is an enlarged view of the gate pad 14 of FIG. 36 and its vicinity. The gate pad 14 includes a main body portion 14A, first connection portions 14F and 14H, and second connection portions 14G and 14I. The first connecting portion 14F has an elongated shape extending in the y direction. The gate built-in resistors 20C and 20D are connected only to the end portions of the first connection portion 14F, avoiding the center. The gate built-in resistors 20E and 20F are connected only to the end portions of the first connection portion 14H, avoiding the center. Therefore, all gate built-in resistors are provided only at the end of the region sandwiched between the gate pad 14 and the source wiring 12.

Of the regions sandwiched between the gate pad 14 and the source wiring 12, the region where the generated potential becomes the largest when the displacement current flows is the central portion thereof. Therefore, by arranging the gate built-in resistor while avoiding the central portion thereof, deterioration of the insulating film at the lower portion of the gate built-in resistor can be prevented.

FIG. 38 is a partial plan view of the silicon carbide semiconductor device according to the modified example. Compared with the configuration shown in FIG. 37, the gate built-in resistors 20D and 20F are not provided, and the gate built-in resistors 20C and 20E on the chip end side are provided. Since only the gate built-in resistors 20C and 20E on the chip end side are provided as the gate built-in resistance, the protruding portions 12I and 12J are shorter than those in FIG. 37. The area of the gate pad 14 is increased by shortening the protruding portions 12I and 12J.

In the examples shown in FIGS. 36 and 37, the area of the gate pad 14 is reduced by the amount of the long protrusions 12I and 12J. If the area of the gate pad 14 is insufficient, it may be necessary to increase the size of the gate pad 14 at the expense of the area of the source wiring 12. However, the protrusions 12I and 12J can be shortened by moving the gate built-in resistance toward the chip end side as shown in FIG. 38 according to the modified example. As a result, the area reduction of the gate pad 14 due to the provision of the protrusions 12I and 12J is suppressed. Therefore, the area of the effective region where the source wiring 12 is formed can be kept large. The positions of the gate built-in resistors 20C and 20E are preferably closer to the edge of the chip than to the center of the gate pad 14.

In the eighteenth embodiment, four gate built-in resistors are provided, but five or more or three or less gate built-in resistors may be provided. As shown in FIGS. 36-38, it is preferable that the plurality of gate built-in resistors are provided so as to avoid the central portion of the region sandwiched between the gate pad 14 and the source wiring 12.

Embodiment 19.
FIG. 39 is a plan view of the silicon carbide semiconductor device according to the nineteenth embodiment. The gate pad 14 is provided in the center of the silicon carbide semiconductor device. The gate wiring 16 includes an annular portion 16L, a drawer portion 16H, an intermediate portion 16I, a first connection portion 16J, and a second connection portion 16K in a plan view. The annular portion 16L is a portion surrounding the source wiring 12. The drawer portion 16H is a portion connected to the annular portion 16L and extends in the central direction from the outer edge of the silicon carbide semiconductor device. The drawer portion 16H has an elongated shape extending in the direction parallel to the y-axis.

The intermediate portion 16I is a portion connected to the drawer portion 16H and facing the upper side of the gate pad 14. The first connecting portion 16J is a portion connected to the intermediate portion 16I and facing the right side of the gate pad 14. The second connecting portion 16K is a portion connected to the intermediate portion 16I and facing the left side of the gate pad 14.

As shown in FIG. 40, which is a partially enlarged view of FIG. 39, the source wiring 12 includes a main body portion 12A'and protrusions 12K and 12L connected to the main body portion 12A'. FIG. 40 shows that the first connection portion 14F and the first connection portion 16J of the gate pad 14 are connected by the gate built-in resistors 20G and 20H. It is also shown that the first connection portion 14H and the second connection portion 16K of the gate pad 14 are connected by the gate built-in resistors 20I and 20J.

The center of the region sandwiched between the gate pad 14 and the source wiring 12 is the portion where the generated potential becomes the largest when the displacement current flows. Therefore, by arranging the gate built-in resistors 20G, 20H, 20I, and 20J avoiding the central portion thereof, deterioration of the oxide film at the lower portion of the gate built-in resistance can be prevented.

FIG. 41 is a partial plan view of the silicon carbide semiconductor device according to the modified example. Compared with the configuration shown in FIG. 40, the gate built-in resistors 20G and 20I are not provided, and the gate built-in resistors 20H and 20J are provided. The gate built-in resistors 20H and 20J of the modified example are provided below the gate pad 14 with respect to the center of the gate pad 14. In other words, the gate built-in resistance is arranged at the gate pad end on the side opposite to the side where the gate electrode is pulled from the chip end. As a result, the protruding portions 12K and 12L protruding from the lower side to the upper side of the gate pad 14 can be made shorter than the protruding portions 12K and 12L in FIG. 40. The area of the gate pad 14 is increased by shortening the protruding portions 12K and 12L.

In the examples shown in FIGS. 39 and 40, the area of the gate pad 14 is reduced by the amount of the long protrusions 12K and 12L. If the area of the gate pad 14 is insufficient, it may be necessary to increase the size of the gate pad 14 at the expense of the area of the source wiring 12. However, as shown in FIG. 41 according to the modified example, the protrusions 12K and 12L can be shortened by moving the gate built-in resistors 20H and 20J to the lower side of the gate pad 14. As a result, the area reduction of the gate pad 14 due to the provision of the protruding portions 12K and 12L is suppressed. Therefore, the area of the effective region where the source wiring 12 is formed can be kept large.

In the nineteenth embodiment, four gate built-in resistors are provided, but five or more or three or less gate built-in resistors may be provided. As shown in FIGS. 39-41, it is preferable that the plurality of gate built-in resistors are provided so as to avoid the central portion of the region sandwiched between the gate pad 14 and the source wiring 12.

10 Silicon Carbide Semiconductor Device, 10A Auxiliary Gate Built-in Resistance, 12 Source Wiring,
12a 1st part, 12A source wiring, 12A'main body part, 12b 2nd part, 12B source wiring, 12B'direct upper part, 12c direct upper part, 12C source wiring, 12C' siege part, 12d adjacent part, 12D source wiring, 12D 'Protrusion, 12E just above, 12F protrusion, 12H annular part, 12I protrusion, 12J protrusion, 12K protrusion, 13 source contact, 13a 1st source contact, 13A source contact, 13b 2nd source contact, 13B source Contact, 14 Gate Pad, 14A Main Body, 14B 1st Connection, 14C 2nd Connection, 15 Gate Contact Wiring, 16 Gate Wiring, 17a 1st Gate Contact, 17b 2nd Gate Contact, 17c 3rd Gate Contact, 17d 4th gate contact, 20A, 20B gate built-in resistance, 20S auxiliary gate built-in resistance, 40 drift layer, 41 silicon carbide semiconductor substrate, 42 well region, 43 n type substrate, 44 high concentration n type region, 45 source, 46 contact region , 47 field insulating film, 48 gate oxide film, 50 interlayer insulating film, 60 ohmic electrode, 62 drain electrode, 80 source area, 112 source pad, 114 gate built-in resistance monitor pad, 120 gate, 146 low resistance area

Claims (19)

A silicon carbide semiconductor substrate having an n-type drift layer and a p-type well region formed on a part of the surface layer of the drift layer.
An insulating film provided on the well region and
A gate built-in resistor provided on the insulating film and made of polysilicon,
An interlayer insulating film formed on the gate built-in resistor and
The gate contact wiring, which is connected to the gate pad and formed on the interlayer insulating film,
A gate wiring provided on the interlayer insulating film apart from the gate contact wiring, and
A first gate contact that electrically connects the gate contact wiring and the gate built-in resistance,
A second gate contact that electrically connects the gate wiring and the gate built-in resistance,
The source wiring formed on the insulating film or the interlayer insulating film between the gate built-in resistor and the gate pad in a plan view,
A source contact that electrically connects the source wiring and the well region,
A silicon carbide semiconductor device characterized by being equipped with. Silicon carbide semiconductor substrate and
An insulating film provided on the silicon carbide semiconductor substrate and
A gate built-in resistor provided on the insulating film and made of polysilicon,
An interlayer insulating film formed on the gate built-in resistor and
A gate pad formed on the interlayer insulating film and
The silicon carbide semiconductor substrate is
A low resistance region provided below the insulating film under the gate built-in resistance,
A p-shaped well region in contact with the bottom surface of the low resistance region and
An n-type drift layer in contact with the bottom surface of the well region, the bottom surface of the low resistance region, or the bottom surface of the insulating film is provided.
A silicon carbide semiconductor device characterized in that the low resistance region has a lower resistance than the well region. The source wiring formed on the insulating film or the interlayer insulating film between the gate built-in resistor and the gate pad in a plan view,
The silicon carbide semiconductor device according to claim 2 , further comprising a source contact for electrically connecting the source wiring and the well region. The source wiring formed on the insulating film or the interlayer insulating film between the gate built-in resistor and the gate pad in a plan view,
The silicon carbide semiconductor device according to claim 2, further comprising a source contact for electrically connecting the source wiring and the low resistance region. The silicon carbide semiconductor device according to claim 2 or 4, wherein the low resistance region is p-type. The silicon carbide semiconductor device according to claim 2 or 4, wherein the low resistance region is n-type. In a plan view, the gate contact wiring and the gate wiring are sandwiched between the gate contact wiring and two source wirings provided along the gate wiring.
The silicon carbide semiconductor device according to claim 1, further comprising two source contacts for electrically connecting the two source wirings and the well region. The silicon carbide semiconductor device according to any one of claims 1, 3 or 4, wherein the gate built-in resistor and the gate pad face each other. A silicon carbide semiconductor substrate having an n-type drift layer and a p-type well region formed on a part of the surface layer of the drift layer.
An insulating film provided on the well region and
A gate built-in resistor provided on the insulating film and made of polysilicon,
An interlayer insulating film formed on the gate built-in resistor and
The gate contact wiring, which is connected to the gate pad and formed on the interlayer insulating film,
A gate wiring provided on the interlayer insulating film apart from the gate contact wiring, and
A first gate contact that electrically connects the gate contact wiring and the gate built-in resistance,
A second gate contact that electrically connects the gate wiring and the gate built-in resistance,
In a plan view, a first portion provided between the gate built-in resistance and the gate pad along the gate built-in resistance, and a second portion extending in a direction different from the first portion and adjacent to the gate built-in resistance. With source wiring and
A first source contact that electrically connects the first portion and the well region,
Carbonization silicon semiconductor device you characterized in that and a second source contact for electrically connecting with said well region and said second portion. A silicon carbide semiconductor substrate having an n-type drift layer and a p-type well region formed on a part of the surface layer of the drift layer.
An insulating film provided on the well region and
A gate built-in resistor provided on the insulating film and made of polysilicon,
An interlayer insulating film formed on the gate built-in resistor and
The gate contact wiring, which is connected to the gate pad and formed on the interlayer insulating film,
A gate wiring provided on the interlayer insulating film apart from the gate contact wiring, and
A first gate contact that electrically connects the gate contact wiring and the gate built-in resistance,
A second gate contact that electrically connects the gate wiring and the gate built-in resistance,
Equipped with source wiring
The source wiring, carbonization silicon semiconductor device you characterized in that it has a straight upper portion the formed via an interlayer insulating film on the gate internal resistor between the gate wiring and the gate contact wiring. The source wiring includes an adjacent portion formed on the insulating film or the interlayer insulating film at a position adjacent to the gate pad in a plan view.
The silicon carbide semiconductor device according to claim 10, further comprising a source contact that penetrates the insulating film or the interlayer insulating film and electrically connects the adjacent portion and the well region. The first aspect of claim 1, wherein a plurality of the gate built-in resistors are connected in parallel by providing a plurality of configurations having the gate built-in resistance, the first gate contact, and the second gate contact. Silicon carbide semiconductor device. A resistor with a built-in auxiliary gate made of polysilicon that is in contact with the insulating film,
Auxiliary gate wiring and
A third gate contact that electrically connects the gate wiring and the resistance built into the auxiliary gate,
A claim characterized in that the gate built-in resistance and the auxiliary gate built-in resistance are connected in series by providing a fourth gate contact for electrically connecting the auxiliary gate wiring and the auxiliary gate built-in resistance. The silicon carbide semiconductor device according to 1. A silicon carbide semiconductor substrate having an n-type drift layer and a p-type well region formed on a part of the surface layer of the drift layer.
An insulating film provided on the well region and
A gate built-in resistor provided on the insulating film and made of polysilicon,
An interlayer insulating film formed on the gate built-in resistor and
The gate contact wiring, which is connected to the gate pad and formed on the interlayer insulating film,
A gate wiring provided on the interlayer insulating film apart from the gate contact wiring, and
A first gate contact that electrically connects the gate contact wiring and the gate built-in resistance,
A second gate contact for electrically connecting the gate wiring and the gate built-in resistance is provided.
By providing a plurality of configurations having the gate built-in resistance, the first gate contact, and the second gate contact, the plurality of gate built-in resistors are connected in parallel.
The source wiring formed between the plurality of gate built-in resistors in a plan view,
It said source wiring and said well region or the well region carbonization silicon semiconductor device you comprising: the source contact to be electrically connected to the lower resistance low-resistance region, and the than. A silicon carbide semiconductor substrate having an n-type drift layer and a p-type well region formed on a part of the surface layer of the drift layer.
An insulating film provided on the well region and
A gate built-in resistor provided on the insulating film and made of polysilicon,
An interlayer insulating film formed on the gate built-in resistor and
The gate contact wiring, which is connected to the gate pad and formed on the interlayer insulating film,
A gate wiring provided on the interlayer insulating film apart from the gate contact wiring, and
A first gate contact that electrically connects the gate contact wiring and the gate built-in resistance,
A second gate contact that electrically connects the gate wiring and the gate built-in resistance,
With
A resistor with a built-in auxiliary gate made of polysilicon that is in contact with the insulating film,
Auxiliary gate wiring and
A third gate contact that electrically connects the gate wiring and the resistance built into the auxiliary gate,
By providing the auxiliary gate wiring and the fourth gate contact for electrically connecting the auxiliary gate built-in resistance, the gate built-in resistance and the auxiliary gate built-in resistance are connected in series.
The source wiring formed between the gate built-in resistance and the auxiliary gate built-in resistance in a plan view,
It said source wiring and said well region or the well region carbonization silicon semiconductor device you comprising: the source contact to be electrically connected to the lower resistance low-resistance region, and the than. A silicon carbide semiconductor substrate having an n-type drift layer and a p-type well region formed on a part of the surface layer of the drift layer.
An insulating film provided on the well region and
A gate built-in resistor provided on the insulating film and made of polysilicon,
An interlayer insulating film formed on the gate built-in resistor and
The gate contact wiring, which is connected to the gate pad and formed on the interlayer insulating film,
A gate wiring provided on the interlayer insulating film apart from the gate contact wiring, and
A first gate contact that electrically connects the gate contact wiring and the gate built-in resistance,
A second gate contact that electrically connects the gate wiring and the gate built-in resistance,
A resistance monitor pad with a built-in gate connected to the gate wiring,
The source wiring formed at the position sandwiched between the gate built-in resistance monitor pad and the gate built-in resistance,
It said source wiring and said well region or the well region carbonization silicon semiconductor device you characterized in that and a source contact for electrically connecting the low resistance low-resistance region than. A silicon carbide semiconductor substrate having an n-type drift layer and a p-type well region formed on a part of the surface layer of the drift layer.
An insulating film provided on the well region and
A gate built-in resistor provided on the insulating film and made of polysilicon,
An interlayer insulating film formed on the gate built-in resistor and
The gate contact wiring, which is connected to the gate pad and formed on the interlayer insulating film,
A gate wiring provided on the interlayer insulating film apart from the gate contact wiring, and
A first gate contact that electrically connects the gate contact wiring and the gate built-in resistance,
A second gate contact that electrically connects the gate wiring and the gate built-in resistance,
Equipped with source wiring
The gate built-in resistor is carbonization silicon semiconductor device you characterized in that provided only on the end portion of the sandwiched the gate pad and the source wiring region. The silicon carbide semiconductor device according to any one of claims 1 to 17, wherein the thickness of the insulating film is the same as that of the gate oxide film. The silicon carbide semiconductor device according to any one of claims 1 to 17, wherein the thickness of the insulating film is the same as that of the field insulating film.

Images