JP6959753B2 - Power conversion circuit control device, power conversion device - Google Patents

Description

The present invention relates to a control device for a power conversion circuit and a power conversion device including the control device.

Conventionally, as seen in Patent Document 1, a power conversion circuit including a rectifying unit that converts input AC power into DC power and outputs it by turning a switch on and off so that synchronous rectification is performed is known. ing.

In this power conversion circuit, when the load current value to be supplied from the power conversion circuit to the outside is small, the switch is turned off so that the backflow of the current from the output side to the input side does not occur in the rectifier unit. The off timing of the switch is set based on, for example, the input voltage value and the output voltage value of the power conversion circuit. As a result, the loss generated in the rectifying unit is reduced.

Japanese Unexamined Patent Publication No. 2014-236596

Here, it may not be possible to set an appropriate off-timing of the switch to prevent backflow. For example, the detection accuracy of the sensor that detects the input and output voltage values of the power conversion circuit deteriorates with time, so it may not be possible to set the appropriate off timing of the switch. If an appropriate off-timing cannot be set, the effect of reducing the loss generated in the rectifying unit when synchronous rectification is performed may be reduced.

An object of the present invention is to provide a control device of a power conversion circuit capable of suppressing a decrease in the effect of reducing a loss generated in a rectifying unit when synchronous rectification is performed, and a power conversion device including the control device.

The first invention is applied to a power conversion circuit having a switch and including a rectifying unit that converts input AC power into DC power and outputs it by turning the switch on and off so that synchronous rectification is performed. The rectifier unit includes a backflow detection unit that detects the backflow of current from the output side to the input side, and a correction unit that corrects the off timing of the switch based on the detection result of the backflow detection unit.

In the first invention, the backflow of the current from the output side to the input side is detected by the backflow detection unit in the rectifying unit. The correction unit corrects the off timing of the switch based on the detection result of the backflow detection unit. As a result, it is possible to suppress the occurrence of backflow in the rectifying unit and suppress the decrease in the effect of reducing the loss generated in the rectifying unit when synchronous rectification is performed.

The first invention can be embodied like the second invention. In the second invention, the power conversion circuit includes a switch circuit that converts the input DC power into AC power and outputs the power when the input side switch is turned on and off, and the output side of the switch circuit is the rectifier unit. It is connected to the input side of. The second invention is to turn on the input side switch to supply power from the switch circuit to the rectifying unit, turn on the output side switch of the rectifying unit to perform the synchronous rectification, and then turn on the output side switch. A switch control unit that turns off the output side switch to stop the synchronous rectification at a timing when a delay time has elapsed since the input side switch was turned off to stop the supply of power from the switch circuit to the rectifier unit. The correction unit corrects the off timing of the output side switch by correcting the delay time based on the detection result of the backflow detection unit.

In the third invention, the switch control unit turns on the input side switch to supply power from the switch circuit to the rectifying unit, and turns on the output side switch to perform the synchronous rectification. The output side switch for stopping the synchronous rectification at the timing when the delay time elapses after the operation and then the input side switch is turned off to stop the supply of power from the switch circuit to the rectifying unit. The backflow detection unit alternately repeats the operation of turning off, and after the input side switch is turned off in order to stop the supply of power from the switch circuit to the rectifying unit, the rectifying unit from the switch circuit. The backflow is detected in the determination period until the input side switch is turned on again to supply power to the power, and the correction unit is based on the detection result of the backflow detection unit in the current determination period. , The delay time for determining the next off timing of the output side switch is corrected.

According to the third invention, the off timing of the output side switch immediately after the backflow is detected can be corrected. Therefore, the off timing of the output side switch can be maintained at an appropriate timing each time, and the occurrence of backflow can be accurately suppressed.

Here, as the switch circuit, for example, as in the fourth invention, the input side switch is provided, and when the input side switch is turned on and off, the input DC power is converted into AC power and output. A transformer including a conversion circuit, a primary coil connected to the output side of the conversion circuit, and a transformer having a secondary coil magnetically coupled to the primary coil and connected to the input side of the rectifying unit. Can be used.

In a fifth invention, the power conversion circuit has an output unit that outputs DC power output from the rectifier unit to the outside, a reactor, and a capacitor, and is an electric path that connects the rectifier unit and the output unit. The LC filter provided in the above is provided. In the fifth invention, the backflow detection unit is at least one of a current value flowing through the primary coil, a current value flowing through the secondary coil, a current value flowing through the rectifying unit, and a current value flowing through the reactor. Is acquired as a determination parameter, and the backflow is detected based on the acquired determination parameter.

The current value flowing through the primary coil, the current value flowing through the secondary coil, the current value flowing through the rectifier section, and the current value flowing through the reactor each correlate with the current value flowing from the output section side to the switch circuit side in the rectifier section. Has. Therefore, in the fifth invention, the backflow detection accuracy can be improved by detecting the backflow based on the above-mentioned determination parameter.

The fifth invention can be embodied as in the sixth invention, for example. In the sixth invention, the backflow detection unit detects that the backflow has occurred when the acquired absolute value of the determination parameter becomes smaller than the threshold value, and the threshold value is the current of the output side switch. It is set based on the capacitance and at least one of the allowable upper limit temperatures of the output side switch.

A seventh invention is a power conversion device including the control device of any one of the first to sixth inventions and the power conversion circuit.

The overall block diagram of the power conversion system which concerns on 1st Embodiment. The figure which shows the structure of the pulse generation part and the drive circuit. A time chart showing changes in the current value flowing through the primary coil. The block diagram which shows the processing of the correction value calculation part. A time chart for explaining the effect of the first embodiment. The overall block diagram of the power conversion system which concerns on 2nd Embodiment. The block diagram which shows the processing of the correction value calculation part. The figure which shows the structure of the pulse generation part and the drive circuit which concerns on 3rd Embodiment. The figure which shows the structure of the mask processing part. A time chart for explaining the effect of the third embodiment.

(First Embodiment)
Hereinafter, the first embodiment in which the control device according to the present invention is embodied will be described with reference to the drawings. In this embodiment, the control device constitutes a power conversion system.

As shown in FIG. 1, the power conversion device 10 is a DCDC converter as a switching power supply device. In the present embodiment, the power conversion device 10 is a full-bridge type step-down converter.

The power conversion device 10 includes a first input terminal Ci1 and a second input terminal Ci2 as input units. The positive electrode terminal of the high-voltage storage battery 30 is connected to the first input terminal Ci1, and the negative electrode terminal of the high-voltage storage battery 30 is connected to the second input terminal Ci2.

The power conversion device 10 includes a first output terminal Co1 and a second output terminal Co2 as output units. The positive electrode terminal of the power supply target 40 is connected to the first output terminal Co1, and the negative electrode terminal of the power supply target 40 is connected to the second output terminal Co2.

The power conversion device 10 steps down the voltage (for example, 288V) input from the high-voltage storage battery 30 via the first and second input terminals Ci1 and Ci2, and steps down the stepped-down voltage (for example, 14V) to the first and second output terminals. It is supplied to the power supply target 40 via Co1 and Co2. The high-voltage storage battery 30 is a secondary battery such as a lithium ion storage battery or a nickel-metal hydride storage battery. Further, the power supply target 40 includes a low-voltage storage battery having an output voltage lower than that of the high-voltage storage battery 30 and an electric load. The low-voltage storage battery is, for example, a lead storage battery. The electrical load includes, for example, headlamps and the like.

The power conversion device 10 includes a smoothing capacitor 11, a conversion circuit 12, and a transformer 13. The first input terminal Ci1 is connected to the first end of the smoothing capacitor 11, and the second input terminal Ci2 is connected to the second end. In this embodiment, the conversion circuit 12 and the transformer 13 correspond to the switch circuit.

The conversion circuit 12 includes first to fourth switches Q1 to Q4 corresponding to input side switches, converts the input DC voltage into an AC voltage, and supplies the input DC voltage to the primary coil 13a constituting the transformer 13. In this embodiment, each switch Q1 to Q4 is an N-channel MOSFET. The first, second, third, and fourth switches D1, D2, D3, and D4, which function as freewheel diodes, are reversed in the first, second, third, and fourth switches Q1, Q2, Q3, and Q4. It is connected in parallel. Each diode D1, D2, D3, D4 is, for example, a body diode.

The first input terminal Ci1 is connected to the drains of the first and second switches Q1 and Q2, and the second input terminal Ci2 is connected to the sources of the third and fourth switches Q3 and Q4. The source of the first switch Q1 and the drain of the third switch Q3 are connected, and the source of the second switch Q2 and the drain of the fourth switch Q4 are connected. The first end of the primary coil 13a is connected to the connection points of the first switch Q1 and the third switch Q3, and the second end of the primary coil 13a is connected to the connection points of the second switch Q2 and the fourth switch Q4. Is connected.

The transformer 13 includes a secondary coil 13b. In the present embodiment, the secondary coil 13b includes an intermediate tap Mt.

The power conversion device 10 includes a rectifying unit 14. The rectifying unit 14 has a rectifying function of converting an alternating current output from the secondary coil 13b into a direct current by synchronous rectification. The rectifying unit 14 includes a fifth switch Q5, a sixth switch Q6, a first rectifying diode Da, and a second rectifying diode Db. In the present embodiment, the fifth and sixth switches Q5 and Q6 are N-channel MOSFETs and correspond to output-side switches.

The anode of the first rectifying diode Da is connected to the first end of the secondary coil 13b, and the anode of the second rectifying diode Db is connected to the second end of the secondary coil 13b. The source of the fifth switch Q5 is connected to the anode of the first rectifying diode Da, and the drain of the fifth switch Q5 is connected to the cathode of the first rectifying diode Da. The source of the sixth switch Q6 is connected to the anode of the second rectifying diode Db, and the drain of the sixth switch Q6 is connected to the cathode of the second rectifying diode Db. The first output terminal Co1 is connected to the cathode of the first rectifying diode Da via the first electric path 15a. The second output terminal Co2 is connected to the intermediate tap Mt via the second electric path 15b. The rectifying diodes Da and Db may be body diodes of the switches Q5 and Q6, or may be external diodes for the switches Q5 and Q6.

The power conversion device 10 includes a filter circuit 16 provided between the rectifying unit 14 and the output terminals Co1 and Co2 in the first and second electric paths 15a and 15b. The filter circuit 16 is an LC filter including a reactor 16a and a capacitor 16b. The cathode of the first rectifying diode Da is connected to the first end of the reactor 16a, and the first output terminal Co1 is connected to the second end of the reactor 16a. The first output terminal Co1 side of the first electric path 15a is connected to the first end of the capacitor 16b with respect to the second end of the reactor 16a. A second electric path 15b is connected to the second end of the capacitor 16b.

The power conversion device 10 includes a first voltage detection unit 20, a second voltage detection unit 21, and a primary current detection unit 22. The first voltage detection unit 20 detects the voltage value input from the first and second input terminals Ci1 and Ci2 as the input voltage value Vin. The second voltage detection unit 21 detects the voltage values output from the first and second output terminals Co1 and Co2 as the output voltage value Vout. The primary current detection unit 22 detects the current value flowing through the primary coil 13a as the primary current value Itr.

The power conversion device 10 includes a control device 50 that controls on / off of each switch Q1 to Q6.

The control device 50 includes a command current calculation unit 51. The command current calculation unit 51 includes an FB calculation unit 51a and a digital-to-analog converter (hereinafter referred to as “DAC51b”). The FB calculation unit 51a calculates the command current value Iref as an operation amount for feedback-controlling the output voltage value Vout detected by the second voltage detection unit 21 to the command voltage value Vref. The feedback control in the FB calculation unit 51a may be, for example, proportional integration control.

The DAC 51b converts the command current value Iref as a digital signal into a command current value Id1 as an analog signal and outputs it.

The control device 50 includes a slope generation unit 52, an addition unit 53, a comparator 54, a pulse generation unit 55, and a drive circuit 56.

The slope generation unit 52 generates and outputs a slope signal Islp for gradually increasing the primary current value Itr detected by the primary current detection unit 22. The slope signal Islp changes with the passage of time like a sawtooth wave and is reset at predetermined intervals. The addition unit 53 adds the primary current value Itr and the slope signal Islp, and outputs the added value as the comparison current value Id2.

The comparator 54 outputs a comparison signal ΔI, which is a pulse signal, based on a magnitude comparison between the comparison current value Id2 output from the adder 53 and the command current value Id1 output from the DAC 51b. When the comparison current value Id2 exceeds the command current value Id1, the comparator 54 outputs the comparison signal ΔI of the logic H.

The pulse generation unit 55 generates and outputs each control signal G1 to G6 which is a pulse width modulation signal for turning on / off the switches Q1 to Q6 based on the comparison signal ΔI output from the comparator 54. The drive circuit 56 amplifies the control signals G1 to G6 output from the pulse generation unit 55 and outputs them to the switches Q1 to Q6.

Subsequently, the pulse generation unit 55 and the drive circuit 56 will be described with reference to FIG.

The pulse generation unit 55 includes a reference wave generation unit 55a, a first NOT circuit 55b, and a first dead time generation unit 55c. The drive circuit 56 includes first to fourth drive units 56a to 56d.

The reference wave generation unit 55a generates and outputs a reference clock signal MC. The period of the clock signal MC coincides with the switching period Tsw of each switch Q1 to Q6. In the present embodiment, the duty ratio of the clock signal MC is set to a constant value (for example, 50%).

The first NOT circuit 55b outputs a logic inversion signal of the clock signal MC. The first dead time generation unit 55c turns on the first switch Q1 for a period from the timing when the logic of the clock signal MC switches to H is delayed by the dead time DT to the timing when the logic of the clock signal MC switches to L. The first control signal G1 to be controlled is generated. The first dead time generation unit 55c extends from the timing when the logic of the logic inversion signal of the clock signal MC is switched to H by the dead time DT to the timing when the logic of the logic inversion signal is switched to L. 3 Generates a third control signal G3 that controls the switch Q3 on.

The first drive unit 56a controls the first switch Q1 on and off based on the first control signal G1, and controls the third switch Q3 on and off based on the third control signal G3.

The pulse generation unit 55 includes a toggle circuit unit 55d, a second NOT circuit 55e, and a second dead time generation unit 55f. The toggle circuit unit 55d outputs a toggle signal TC in which the logic is inverted each time the comparison signal ΔI output from the comparator 54 is switched from the logic L to the logic H. For example, when the logic of the currently output toggle signal TC is H, the toggle circuit unit 55d outputs the toggle signal TC of the logic L when the comparison signal ΔI is switched from the logic L to the logic H. As the toggle circuit unit 55d, for example, a T flip-flop may be used.

The second NOT circuit 55e outputs a logic inversion signal of the toggle signal TC. The second dead time generation unit 55f turns on the second switch Q2 for a period from the timing when the logic of the toggle signal TC is switched to H by the dead time DT delay to the timing when the logic of the toggle signal TC is switched to L. A second control signal G2 to be controlled is generated. The second dead time generation unit 55f extends the period from the timing of delaying the dead time DT to the timing at which the logic of the logic inversion signal of the toggle signal TC is switched to H to the timing at which the logic of the logic inversion signal is switched to L. 4 Generates a fourth control signal G4 that controls the switch Q4 on.

The second drive unit 56b controls the second switch Q2 on and off based on the second control signal G2, and controls the fourth switch Q4 on and off based on the fourth control signal G4.

The pulse generation unit 55 includes a delay time calculation unit 55g, a correction value calculation unit 57, and a delay signal generation unit 58. The delay time calculation unit 55g calculates the delay time τ. In the present embodiment, the delay time τ is the time from when the fourth switch Q4 is turned off until the fifth switch Q5 is turned off, and from when the second switch Q2 is turned off until the sixth switch Q6 is turned off. It's time. The delay time τ is set from the viewpoint of preventing the current from flowing back from the drain side to the source side of the fifth and sixth switches Q5 and Q6.

The delay time calculation unit 55g sets the delay time τ to the maximum value in the continuous mode in which the command current value Id1 is equal to or higher than the current threshold value Xth. However, in this case, the delay time τ is set so that the fifth switch Q5 is turned off by the time the third switch Q3 is turned on next time, and the sixth switch Q6 is turned off by the time the first switch Q1 is turned on next time. Will be done.

When the command current value Id1 is smaller than the current threshold Xth in the discontinuous mode, the delay time calculation unit 55g calculates the delay time τ based on the input voltage value Vin, the output voltage value Vout, and the on-time Ton. In the present embodiment, the on-time Ton is the time when both the first switch Q1 and the fourth switch Q4 are turned on, or the time when both the second switch Q2 and the third switch Q3 are turned on. The delay time calculation unit 55g may calculate the delay time τ based on the following equation (eq1), for example. In the following equation (eq1), La indicates the inductance of the reactor 16a.

補正値算出部５７は、補正時間Ｔαを算出する。なお補正値算出部５７については、後に詳述する。遅延信号生成部５８は、比較器５４から出力された比較信号ΔＩの論理がＨに切り替わるタイミングから、遅延時間τから補正時間Ｔαを減算した時間だけ経過したタイミングで、論理Ｈのパルス信号である遅延信号ΔＩｄを出力する。

The correction value calculation unit 57 calculates the correction time Tα. The correction value calculation unit 57 will be described in detail later. The delay signal generation unit 58 is a pulse signal of the logic H at the timing when the logic of the comparison signal ΔI output from the comparator 54 is switched to H and the time obtained by subtracting the correction time Tα from the delay time τ has elapsed. The delay signal ΔId is output.

The pulse generation unit 55 includes a first RS flip-flop 55h and a second RS flip-flop 55i. The first control signal G1 is input to the set input terminal S of the first RS flip-flop 55h, and the delay signal ΔId output from the delay signal generation unit 58 is input to the reset input terminal R. The signal output from the output terminal Q of the first RS flip-flop 55h becomes the fifth control signal G5 that controls the fifth switch Q5. The third drive unit 56c controls the fifth switch Q5 on and off based on the fifth control signal G5.

The third control signal G3 is input to the set input terminal S of the second RS flip-flop 55i, and the delay signal ΔId is input to the reset input terminal R. The signal output from the output terminal Q of the second RS flip-flop 55i becomes the sixth control signal G6 that controls the sixth switch Q6. The fourth drive unit 56d controls the sixth switch Q6 on and off based on the sixth control signal G6. In the present embodiment, the configurations 55a to 55i of the pulse generation unit 55 and the delay signal generation unit 58 other than the configuration for performing the correction described later correspond to the switch control unit.

Here, the delay time τ calculated by the delay time calculation unit 55g may deviate from an appropriate time for preventing backflow. Factors that cause the time to deviate include that the detection accuracy of the first voltage detection unit 20 and the second voltage detection unit 21 decreases due to changes over time. Further, the factor of the time shift includes that the inductance La used for calculating the delay time τ in the above equation (eq1) deviates from the actual inductance of the reactor 16a.

Therefore, in the present embodiment, the pulse generation unit 55 includes a correction value calculation unit 57 and a backflow detection unit 59 in order to calculate an appropriate delay time τ.

First, the backflow detection unit 59 will be described with reference to FIG. FIG. 3 shows changes in the primary current value Itr, the reactor current value IL which is the current value flowing through the reactor 16a, and the comparison signal ΔI. In FIG. 3, the primary current value Itr is defined as the direction in which the primary coil 13a flows from the first end to the second end, and the reactor current value IL is defined as the reactor 16a from the first end to the second end. The direction of flow to is defined as positive.

The backflow detection unit 59 reduces the primary current value Itr in the first determination period Ta from the time t1 when the logic of the comparison signal ΔI switches to H to the time t2 when the third switch Q3 is turned on, and the determination threshold value Is. When it is determined that the value becomes smaller than, it is detected that a backflow has occurred. FIG. 3 shows an example in which the determination threshold value Is in the first determination period Ta is set to a value smaller than 0. Further, the backflow detection unit 59 increases the primary current value Itr in the second determination period Tb from the time t3 when the logic of the comparison signal ΔI switches to H to the time t4 when the first switch Q1 is turned on, and the determination threshold value. When it is determined that the value is larger than Is, it is detected that a backflow has occurred. FIG. 3 shows an example in which the determination threshold value Is in the second determination period Tb is set to a value larger than 0. Incidentally, in the present embodiment, it is assumed that the absolute value of the determination threshold value Is in the first determination period Ta and the absolute value of the determination threshold value Is in the second determination period Tb are equal values.

The absolute value of the determination threshold value Is is set to a larger value as the current capacity of the fifth and sixth switches Q5 and Q6 is larger and the allowable upper limit temperature of the fifth and sixth switches Q5 and Q6 is higher. Just do it. In the present embodiment, the current capacity is the upper limit of the current value that can be passed through the switch. Further, the determination threshold value Is may be set based on at least one of the current capacity and the allowable upper limit temperature of the fifth and sixth switches Q5 and Q6.

Subsequently, the correction value calculation unit 57 will be described.

When the correction value calculation unit 57 acquires information from the backflow detection unit 59 that no backflow has occurred, the correction value calculation unit 57 calculates the correction time Tα as 0. On the other hand, when the correction value calculation unit 57 acquires the information that the backflow has occurred from the backflow detection unit 59, the correction value calculation unit 57 calculates the correction time Tα with the configuration shown in FIG.

Specifically, the correction value calculation unit 57 includes a secondary current calculation unit 57a, a command time calculation unit 57b, a time deviation calculation unit 57c, and a feedback unit 57d.

The secondary current calculation unit 57a calculates the reactor current estimated value Ia based on the determination threshold value Is and the turns ratio of the transformer 13. In the present embodiment, the reactor current estimated value Ia is a reactor current value assumed when the current value flowing through the primary coil 13a becomes the determination threshold value Is.

The command time calculation unit 57b calculates the command time Tref based on the reactor current estimated value Ia, the inductance La of the reactor 16a, and the output voltage value Vout. The command time calculation unit 57b may calculate the command time Tref based on, for example, the following equation (eq2).

時間偏差算出部５７ｃは、フィードバック部５７ｄで算出された補正時間Ｔαを、指令時間算出部５７ｂで算出された指令時間Ｔｒｅｆから減算することで、時間偏差ΔＴを算出する。

The time deviation calculation unit 57c calculates the time deviation ΔT by subtracting the correction time Tα calculated by the feedback unit 57d from the command time Tref calculated by the command time calculation unit 57b.

The feedback unit 57d calculates the correction time Tα as an operation amount for feedback-controlling the time deviation ΔT to 0. The feedback control in the feedback unit 57d may be, for example, proportional integration control.

Incidentally, the correction time Tα may be initialized when the control device 50 is started. In this case, it is possible to prevent the correction time Tα calculated after the control device 50 was started last time from being used after the start this time. Further, in the present embodiment, the correction value calculation unit 57 and the delay signal generation unit 58 for performing correction processing correspond to the correction unit.

FIG. 5 shows an example of the delay time τ correction process according to the present embodiment. FIG. 5 is a time chart showing changes in the clock signal MC, the switches Q1 to Q6, the input current value Iin from the high-voltage storage battery 30 to the conversion circuit 12, the reactor current value IL, the comparison signal ΔI, and the delay signal ΔId.

In the example shown in FIG. 5, the primary determination period Ta is from the time t1 when the logic of the comparison signal ΔI is switched to H and the fourth switch Q4 is turned off to the time t3 when the third switch Q3 is turned on. It is determined that the backflow has occurred because the current value Itr decreases and becomes smaller than the determination threshold value Is. Therefore, the delay time τ used in the period from the time t3 when the third switch Q3 is turned on to the time t6 when the first switch Q1 is turned on is corrected so as to be shortened. The time indicated by the times t4 to t5 is the shortened delay time "τ-Tα". The logic of the delay signal ΔId is switched to H at the time t5, which is the timing when the delay time “τ−Tα” has elapsed from the time t4 when the logic of the comparison signal ΔI is switched to H. As a result, the sixth switch Q6 is turned off at the timing when the reactor current value IL becomes 0 or substantially 0.

Further, in the example shown in FIG. 5, in the second determination period Tb from the time t4 when the logic of the comparison signal ΔI is switched to H and the second switch Q2 is turned off to the time t6 when the first switch Q1 is turned on, 1 The next current value Itr rises and becomes larger than the determination threshold value Is, and it is determined that a backflow has occurred. Therefore, the delay time τ used in the period from the time t6 when the first switch Q1 is turned on to the time t9 when the third switch Q3 is turned on is corrected so as to be shortened. The time indicated by the times t7 to t8 is the shortened delay time “τ-Tα”. At time t8, which is the timing at which the delay time “τ−Tα” has elapsed from the time t7 when the logic of the comparison signal ΔI switches to H, the logic of the delay signal ΔId switches to H. As a result, the fifth switch Q5 is turned off at the timing when the reactor current value IL becomes 0 or substantially 0.

In the present embodiment described in detail above, when the backflow detection unit 59 determines that a backflow of current has occurred from the output terminals Co1 and Co2 sides to the secondary coil 13b side in the rectifying unit 14, the pulse generation unit 55 causes the backflow. The off-timing of the 5th and 6th switches Q5 and Q6 was corrected so that As a result, it is possible to suppress a decrease in the effect of reducing the loss generated in the rectifying unit 14 when synchronous rectification is performed.

The delay time τ calculated by the delay time calculation unit 55g may be shorter than the appropriate delay time. In this case, the fifth switch Q5 or the sixth switch Q6 is turned off at an excessively early timing with respect to the timing when the reactor current value IL becomes 0, and the loss reduction effect by synchronous rectification may be reduced. Even in such a case, according to the present embodiment, the correction time Tα is calculated as a negative value, and the delay time τ is corrected so as to be lengthened. As a result, the fifth switch Q5 or the sixth switch Q6 can be turned off at the timing when the reactor current value IL becomes 0 or substantially 0.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to the drawings, focusing on the differences from the first embodiment. In this embodiment, the backflow determination method is changed.

FIG. 6 shows a power conversion system according to this embodiment. In FIG. 6, the same reference numerals are given to the same configurations as those shown in FIG. 1 above for convenience.

The power conversion device 10 includes a reactor current detection unit 23 that detects the current value flowing through the reactor 16a as the reactor current value IL, and a third voltage detection unit 24 that detects the voltage between the terminals of the reactor 16a as the reactor voltage value VL. ing. The reactor voltage value VL is input to the backflow detection unit 59. The reactor current value IL is input to the correction value calculation unit 57. In the present embodiment, the reactor voltage value VL is defined as positive when the potential of the first end is higher than that of the second end of the reactor 16a.

Subsequently, the backflow detection unit 59 according to the present embodiment will be described.

When it is determined that the reactor voltage value VL is lowered and becomes smaller than the determination threshold value Vth in the first determination period Ta, the backflow detection unit 59 determines that the backflow has occurred. The determination threshold value V th in the first determination period Ta, for example, may be set to a value smaller than 0. Further, when the backflow detection unit 59 determines that the reactor voltage value VL rises and becomes larger than the determination threshold value Vth in the second determination period Tb, it determines that the backflow has occurred. The determination threshold value Vth in the second determination period Tb may be set to a value larger than, for example, 0.

Subsequently, the correction value calculation unit 57 according to the present embodiment will be described with reference to FIG. 7.

The correction value calculation unit 57 includes a multiplication unit 57e, a time deviation calculation unit 57c, and a feedback unit 57d.

The multiplication unit 57e calculates the command time Tref based on the determination threshold value Vth, the inductance La of the reactor 16a, and the reactor current value IL. In the present embodiment, the multiplication unit 57e calculates the command time Tref based on the following equation (eq3). The command time Tref calculated by the multiplication unit 57e is input to the time deviation calculation unit 57c.

以上説明した本実施形態によれば、上記第１実施形態の効果と同様の効果を得ることができる。

According to the present embodiment described above, the same effect as that of the first embodiment can be obtained.

(Third Embodiment)
Hereinafter, the third embodiment will be described with reference to the drawings, focusing on the differences from the first embodiment. In the present embodiment, as shown in FIG. 8, the pulse generation unit 55 includes a mask processing unit 60 instead of the delay time calculation unit 55g and the delay signal generation unit 58. In FIG. 8, the same components as those shown in FIG. 2 above are designated by the same reference numerals for convenience.

The mask processing unit 60 generates and outputs a mask signal Imsk. The output mask signal Imsk is input to the reset input terminals R of the first RS flip-flop 55h and the second RS flip-flop 55i, respectively. The mask signal Imsk is a signal for instructing the fifth switch Q5 or the sixth switch Q6 to be turned off.

FIG. 9 shows a block diagram of processing in the mask processing unit 60.

The exciting current calculation unit 60a calculates the exciting current equivalent value ΔIm of the transformer 13. The exciting current equivalent value ΔIm is defined as the exciting current value of the transformer 13 or its correlation value. The exciting current calculation unit 60a calculates the exciting current equivalent value ΔIm based on parameters selected from, for example, the input voltage value Vin, the output voltage value Vout, the exciting inductance Lm of the transformer 13, and the on-time Ton. In the present embodiment, the exciting current calculation unit 60a calculates the exciting current equivalent value ΔIm based on the input voltage value Vin, the exciting inductance Lm, and the on-time Ton. The exciting current equivalent value ΔIm may be calculated as, for example, a value of “Vin / Lm × Ton” or “Vin / Lm × Ton / 2” or more and less than “Vin / Lm × Ton”.

If the input voltage value Vin and the output voltage value Vout are undefined due to a failure of the first and second voltage detection units 20 and 21, there is a possibility that an appropriate exciting current equivalent value ΔIm cannot be calculated. Therefore, when it is undefined, the exciting current equivalent value ΔIm may be calculated based on the maximum value Vimax assumed as the input voltage value Vin and the maximum value Vomax assumed as the output voltage value Vout.

The digital-to-analog converter 60b converts the exciting current equivalent value ΔIm as a digital signal into an analog signal and outputs it.

The signal generation unit 60c outputs the mask signal Imsk by comparing the magnitude of the absolute value of the primary current value Itr and the excitation current equivalent value ΔIm output from the digital-to-analog converter 60b. Specifically, in the signal generation unit 60c, when the absolute value of the primary current value Itr is smaller than the exciting current equivalent value ΔIm in the period from the time when the fourth switch Q4 is turned off to the time when the third switch Q3 is turned on. The mask signal Imsk of logic H is output to. Further, in the signal generation unit 60c, when the absolute value of the primary current value Itr is smaller than the exciting current equivalent value ΔIm in the period from the time when the second switch Q2 is turned off to the time when the first switch Q1 is turned on. The mask signal Imsk of logic H is output.

When the exciting current calculation unit 60a acquires the information that the backflow has occurred from the backflow detection unit 59, the exciting current calculation unit 60a performs a process of correcting the exciting current equivalent value ΔIm. Specifically, the exciting current calculation unit 60a needs to advance the off timing of the fifth switch Q5 or the sixth switch Q6 as the correction time Tα becomes longer, so that the calculated exciting current equivalent value ΔIm is increased and corrected. As a result, the absolute value of the primary current value Itr decreases and the timing of falling below the exciting current equivalent value ΔIm becomes earlier, and the timing of switching the logic of the mask signal Imsk to H becomes earlier. As a result, the off timing of the 5th switch Q5 or the 6th switch Q6 is advanced, and backflow can be prevented.

FIG. 10 shows an example of the correction process according to the present embodiment. FIG. 10 is a time chart showing changes in the clock signal MC, the switches Q1 to Q6, the input current value Iin, the reactor current value IL, the comparison signal ΔI, and the mask signal Imsk.

In the example shown in FIG. 10, the backflow occurs in the first determination period Ta from the time t1 when the logic of the comparison signal ΔI is switched to H and the fourth switch Q4 is turned off to the time t3 when the third switch Q3 is turned on. It is determined that it has occurred. Therefore, the exciting current equivalent value ΔIm is corrected based on the correction time Tα. Then, the mask signal Imsk of the logic H is output at time t2 to t3 in which the absolute value of the primary current value Itr becomes smaller than the corrected excitation current equivalent value ΔIm. Therefore, the fifth switch Q5 is turned off at time t2. The time t1 to t2 corresponds to the delay time τ of the first embodiment. By correcting the exciting current equivalent value ΔIm, the timing at which the logic of the mask signal Imsk is switched to H is corrected, and the delay time τ is corrected.

Further, in the example shown in FIG. 10, in the second determination period Tb from the time t4 when the logic of the comparison signal ΔI is switched to H and the second switch Q2 is turned off to the time t6 when the first switch Q1 is turned on, 1 The next current value Itr rises and becomes larger than the determination threshold value Is, and it is determined that a backflow has occurred. Therefore, the exciting current equivalent value ΔIm is corrected based on the correction time Tα. Then, the mask signal Imsk of the logic H is output at times t5 to t6 in which the absolute value of the primary current value Itr becomes smaller than the corrected excitation current equivalent value ΔIm. Therefore, the sixth switch Q6 is turned off at time t5. The time t4 to t5 corresponds to the delay time τ of the first embodiment.

According to the present embodiment described above, the same effect as that of the first embodiment can be obtained.

(Other embodiments)
Each of the above embodiments may be modified as follows.

-As the determination parameters used for determining whether or not the current has flowed back, instead of the primary current value Itr and the reactor voltage value VL, for example, the voltage value between the terminals of the primary coil 13a and the current value flowing through the secondary coil 13b. Any one of the detection values of the inter-terminal voltage of the secondary coil 13b, the current value flowing through the fifth and sixth switches Q5 and Q6, the inter-terminal voltage value, and the reactor current value IL may be used. The determination parameters include the primary current value Itr, the reactor voltage value VL, the voltage value between the terminals of the primary coil 13a, the current value flowing through the secondary coil 13b, the voltage between the terminals of the secondary coil 13b, and the fifth and fifth. At least one or more of the current value flowing through the 6 switches Q5 and Q6, the voltage value between terminals, and the reactor current value IL may be used.

In the first and second embodiments, the delay time τ in the discontinuous mode is based on, for example, at least one of the reactor current value IL, the duty ratio of the clock signal MC, the switching cycle Tsw, and the command current value Iref. It may be calculated. Further, the switching frequency fs (= 1 / Tsw) may be used instead of the switching cycle Tsw.

-In the first embodiment, as shown in FIG. 4, a configuration in which the correction time Tα is linearly changed is used, but the present invention is not limited to this. For example, when it is determined that a backflow has occurred, a configuration in which the correction time Tα is changed in steps may be used.

-In the first embodiment, the determination threshold value Is may be set to, for example, 0.

The power conversion circuit is not limited to the configuration shown in FIG. 1, and may be, for example, the configuration shown in FIG. 10 of Patent Document 1. In this case, the switch circuit will have one input side switch. The rectifying unit 14 may also be provided with one output side switch.

Further, the power conversion circuit is not limited to the step-down converter, and may be a boost converter or a step-up / down converter. Further, the power conversion circuit is not limited to an insulated type having a transformer, and may be a non-insulated type not provided with a transformer.

10 ... power converter, 12 ... conversion circuit, 13 ... transformer, 14 ... rectifier, 50 ... control device.

Claims (4)

Switch circuit (12, 13) and
With an output side switch (Q5, Q6) and a rectifier unit (14) that converts input AC power into DC power and outputs it by turning the output side switch on and off so that synchronous rectification is performed. ,
Output units (Co1, Co2) that output DC power output from the rectifier unit to the outside, and
A reactor (16a) provided in an electric path (15a, 15b) connecting the rectifying unit and the output unit, and
In the control device (50) of the power conversion circuit applied to the power conversion circuit including
The switch circuit
A conversion circuit (12) having input side switches (Q1 to Q4) and converting input DC power into AC power and outputting it by turning the input side switch on and off.
A transformer (13) having a primary coil (13a) connected to the output side of the conversion circuit and a secondary coil (13b) magnetically coupled to the primary coil and connected to the input side of the rectifier unit. And have
An operation of turning on the input side switch (Q1 or Q3) to supply power from the switch circuit to the rectifying unit and turning on the output side switch (Q5 or Q6) to perform the synchronous rectification. After that, at the timing when the delay time elapses after the input side switch (Q4 or Q2) is turned off to stop the supply of power from the switch circuit to the rectifier unit, the output is to stop the synchronous rectification. A switch control unit that alternately repeats the operation of turning off the side switch,
The input side switch is turned off to stop the supply of power from the switch circuit to the rectifying unit, and then the input side switch is turned on again to supply power from the switch circuit to the rectifying unit. After the input side switch is turned off and the absolute value of the current value (Itr) flowing through the primary coil begins to decrease during the determination period (Ta, Tb), the current value flowing through the primary coil, When the determination parameter, which is either the current value flowing through the secondary coil, the current value flowing through the rectifying section, or the current value flowing through the reactor crosses the threshold value (Ith), the rectifying section is from the output side to the input side. A backflow detector that detects the occurrence of backflow of current to
When the backflow is detected by the backflow detection unit during the determination period, the current estimated value of the reactor calculated based on the threshold value, the inductance (La) of the reactor, and the voltage value (Vout) of the output unit. ), A correction time (Tα) which is a correction value of the delay time is calculated, and a correction unit for correcting the next off timing of the output side switch based on the calculated correction time is provided. Circuit controller. Switch circuit (12, 13) and
And an output-side switch (Q5, Q6), by the output-side switch to synchronous rectification is performed is off, the rectifying unit for converting an AC power input to DC power (14) ,
Output units (Co1, Co2) that output DC power output from the rectifier unit to the outside, and
A reactor (16a) provided in an electric path (15a, 15b) connecting the rectifying unit and the output unit, and
The control apparatus of a power conversion circuit that apply to the power conversion circuit comprising a (50),
The switch circuit
A conversion circuit (12) having input side switches (Q1 to Q4) and converting input DC power into AC power and outputting it by turning the input side switch on and off.
A transformer (13) having a primary coil (13a) connected to the output side of the conversion circuit and a secondary coil (13b) magnetically coupled to the primary coil and connected to the input side of the rectifier unit. And have
An operation of turning on the input side switch (Q1 or Q3) to supply power from the switch circuit to the rectifying unit and turning on the output side switch (Q5 or Q6) to perform the synchronous rectification. After that, at the timing when the delay time elapses after the input side switch (Q4 or Q2) is turned off to stop the supply of power from the switch circuit to the rectifier unit, the output is to stop the synchronous rectification. A switch control unit that alternately repeats the operation of turning off the side switch,
The input side switch is turned off to stop the supply of power from the switch circuit to the rectifying unit, and then the input side switch is turned on again to supply power from the switch circuit to the rectifying unit. After the input side switch is turned off and the absolute value of the current value flowing through the primary coil begins to decrease during the determination period (Ta, Tb), the voltage value between terminals (VL) of the reactor, the said. When the determination parameter, which is either the voltage value between the terminals of the primary coil or the voltage value between the terminals of the secondary coil, crosses the threshold value (Vth), the backflow of current from the output side to the input side in the rectifying unit A backflow detector that detects the occurrence of
When the backflow is detected by the backflow detection unit in the determination period, it is a correction value of the delay time based on the threshold value, the inductance (La) of the reactor, and the current value (IL) flowing through the reactor. calculating corrected time (T [alpha), on the basis of the calculated correction time, the control equipment of the power conversion circuit and a correcting unit that corrects the next off timing of the output-side switch. Before SL threshold control device for a power conversion circuit according to claim 1 or 2 is set based on at least one of the upper allowable temperature limit of the current capacity and the output-side switch of the output-side switch. A power conversion device (10) comprising the control device according to any one of claims 1 to 3 and the power conversion circuit.

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