JP6964564B2 - Semiconductor device - Google Patents

Description

The techniques disclosed herein relate to semiconductor devices.

In a semiconductor device including a junction field effect transistor (JFET) and a metal-oxide-semicon field effect transistor (that is, MOSFET) in which a drain terminal is connected to a source terminal of the JFET. When the junction potential (Vj) and the source voltage (Vs) are short-circuited (short-circuited), the drain voltage (Vd) increases as the drain voltage (Vd) rises while the MOSFET is kept on. When it exceeds a certain value, the drain current (Id) becomes too large and saturates (that is, an overcurrent state occurs). In this state, MOSFET element destruction (specifically, short-circuit destruction) occurs due to self-heating or the like.

Therefore, conventionally, the element destruction of the MOSFET has been prevented by taking measures such as detecting an overcurrent state and lowering the gate voltage (Vg) (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2012-191320

Due to the low on-resistance of the semiconductor element, the rise of the drain current (Id) when the drain voltage (Vd) rises becomes steeper. Further, as the on-resistance of the semiconductor element is lowered, the current value of the drain current (Id) itself becomes large.

Therefore, the time during which the overcurrent state is allowed is shorter as long as the element is not destroyed. For this reason, there is essentially a trade-off between lowering the on-resistance of the semiconductor element and protecting the overcurrent of the semiconductor element, and it has been difficult to improve both at the same time.

The technique disclosed in the present specification has been made in order to solve the above-mentioned problems, and provides a technique for achieving both overcurrent protection and low on-resistance in a semiconductor device. It is the purpose.

A first aspect of the technique disclosed in the present specification is a first conductive type first semiconductor layer and a second conductive type first semiconductor layer formed on the surface layer of the first semiconductor layer. The diffusion region, the first conductive type second diffusion region formed on the surface layer of the first diffusion region, and the first semiconductor layer formed from the upper surface of the second diffusion region. A trench, a gate oxide film formed in the trench, a gate electrode formed in the trench surrounded by at least a part of the gate oxide film, and an upper surface of the first diffusion region. A top electrode formed over the upper surface of the second diffusion region, a second conductive type third diffusion region formed in contact with the lower surface of the trench from below the trench, and the above. It is provided with a first voltage applying portion for applying a voltage to the third diffusion region, which is electrically independent of the top electrode, and the third diffusion region is outside the trench and includes the lower surface of the trench and the lower surface of the trench. The second, which is formed along one side surface and is formed in contact with the lower surface of the first diffusion region, and is formed on the surface layer of the first diffusion region with which the third diffusion region is in contact. diffusion region of the Ru is connected to the gate electrode and electrically.

According to a first state like the techniques disclosed herein, by the potential of the third diffusion region and the upper electrode is controlled independently by the first voltage applying unit that electrically independent , It is possible to achieve both low on-resistance of semiconductor devices and overcurrent protection.

Also, the objectives, features, aspects and advantages of the technology disclosed herein will be further clarified by the detailed description and accompanying drawings set forth below.

It is sectional drawing which shows typically the example of the structure of the semiconductor device which concerns on embodiment. It is a figure which shows the equivalent circuit of the structure shown in FIG. It is a figure which shows the example of each terminal voltage in the operating state of a semiconductor device. It is a figure which shows the example of each terminal voltage in the operating state of a semiconductor device. It is a figure which shows the example of each terminal voltage in the operating state of a semiconductor device. It is a figure which shows the circuit of the semiconductor device which concerns on embodiment. It is sectional drawing which shows typically the example of the structure of the semiconductor device which concerns on embodiment. It is sectional drawing which shows typically the example of the structure of the semiconductor device which concerns on embodiment. It is sectional drawing which shows typically the example of the structure of the semiconductor device which concerns on embodiment. It is a figure which shows the circuit of the semiconductor device which concerns on embodiment. It is sectional drawing which shows typically the example of the structure of the semiconductor device which concerns on embodiment. It is sectional drawing which shows typically the example of the structure of the semiconductor device which concerns on embodiment. It is sectional drawing which shows typically the example of the structure of the semiconductor device which concerns on embodiment. It is sectional drawing which shows typically the example of the structure of the semiconductor device which concerns on embodiment. It is sectional drawing which shows typically the example of the structure of the semiconductor device which concerns on embodiment. It is sectional drawing which shows typically the example of the structure of the semiconductor device which concerns on embodiment. It is sectional drawing which shows typically the example of the structure of the semiconductor device which concerns on embodiment. It is a figure which shows the equivalent circuit of the structure shown in FIG. It is a figure which shows the example of each terminal voltage in the operating state of a semiconductor device. It is sectional drawing which shows the example of the form of the Vj terminal which concerns on embodiment. It is a top view which shows the example of the form of the Vj terminal which concerns on embodiment.

Hereinafter, embodiments will be described with reference to the attached drawings.

It should be noted that the drawings are shown schematically, and for convenience of explanation, the configuration is omitted or the configuration is simplified as appropriate. Further, the interrelationship between the sizes and positions of the configurations and the like shown in different drawings is not always accurately described and can be changed as appropriate. Further, even in a drawing such as a plan view which is not a cross-sectional view, hatching may be added to facilitate understanding of the contents of the embodiment.

Further, in the description shown below, similar components are illustrated with the same reference numerals, and their names and functions are also the same. Therefore, detailed description of them may be omitted to avoid duplication.

Also, in the description described below, a specific position and direction such as "top", "bottom", "left", "right", "side", "bottom", "front" or "back". Even if terms that mean are used, these terms are used for convenience to facilitate understanding of the content of the embodiments and have nothing to do with the direction in which they are actually implemented. It doesn't.

Also, even if ordinal numbers such as "first" or "second" may be used in the description described below, these terms should be used to understand the content of the embodiment. It is used for convenience for ease of use, and is not limited to the order that can occur due to these ordinals.

<First Embodiment>
Hereinafter, the semiconductor device according to the present embodiment will be described. For convenience of explanation, first, an example of the configuration of a semiconductor device in which the junction potential (Vj) and the source voltage (Vs) are short-circuited will be described.

FIG. 17 is a cross-sectional view schematically showing an example of the configuration of the semiconductor device according to the present embodiment. Further, FIG. 18 is a diagram showing an equivalent circuit having the structure shown in FIG. Further, FIG. 19 is a diagram showing an example of each terminal voltage in the operating state of the semiconductor device.

As an example is shown in FIG. 17, the semiconductor device according to the present embodiment includes an n + type semiconductor substrate 1, an n− type semiconductor layer 2 formed on the upper surface of the n + type semiconductor substrate 1, and n−. The p-type diffusion region 3 formed on the surface layer of the type semiconductor layer 2, the n + type diffusion region 4 formed on the surface layer of the p-type diffusion region 3, and n− from the upper surface of the n + type diffusion region 4. A p-type diffusion region 6 formed in contact with the lower surface of the trench 100 from below the trench 100 extending into the semiconductor layer 2 of the mold, a gate oxide film 101 formed in the trench 100, and a gate in the trench 100. A gate electrode 5 formed surrounded by an oxide film 101, a source electrode 7 formed straddling the upper surface of a p-type diffusion region 3 and an upper surface of an n + type diffusion region 4, an n + type semiconductor substrate 1 A drain electrode 8 formed in contact with the lower surface of the surface is provided.

Here, the p-type diffusion region 6 is electrically connected to the source electrode 7. Further, the p-type diffusion region 6 is used to prevent the gate oxide film 101 formed on the upper surface of the p-type diffusion region 6 from being destroyed by the electric field between the gate and the drain.

FIG. 18 is a diagram showing an equivalent circuit having the structure shown in FIG. As an example shown in FIG. 18, the semiconductor device according to the present embodiment includes a junction field effect transistor (JFET) 200 and a metal-oxide film-semiconductor field effect transistor (JFET) in which a drain terminal is connected to a source terminal of the JFET 200. It includes a metal-axis-semiconductor field-effect transistor, that is, a MOSFET) 201.

The JFET 200 is formed so as to have a p-type diffusion region 6 as a gate electrode. Further, the MOSFET 201 is formed as having a gate electrode 5.

As an example is shown in FIG. 17, the p-type diffusion region 6 (junction potential (Vj)) and the p-type diffusion region 3 (source voltage (Vs)) are short-circuited (short-circuited). The following relational expression always holds.

Here, consider a case where the drain voltage (Vd) rises while the ON state of the MOSFET 201 is maintained, that is, a case where a short-circuit state is reached. FIG. 19 is a diagram showing an example of each terminal voltage in such a case. In FIG. 19, the vertical axis represents the drain current (Id) or the junction potential (Vj), and the horizontal axis represents the drain voltage (Vd).

As an example is shown in FIG. 19, when the drain voltage (Vd) exceeds a certain value, the drain current (Id) becomes too large and saturates (that is, an overcurrent state occurs). In this state, element destruction (specifically, short-circuit destruction) of the MOSFET 201 occurs due to self-heating or the like.

Therefore, conventionally, the element destruction of the MOSFET 201 has been prevented by taking measures such as detecting an overcurrent state and quickly lowering the gate voltage (Vg).

Due to the low on-resistance of the semiconductor element, the rise of the drain current (Id) when the drain voltage (Vd) rises becomes steeper. Further, as the on-resistance of the semiconductor element is lowered, the current value of the drain current (Id) itself becomes large.

Therefore, the time during which the overcurrent state is allowed is shorter as long as the element is not destroyed. For this reason, there is essentially a trade-off between lowering the on-resistance of the semiconductor element and protecting the overcurrent of the semiconductor element, and it has been difficult to improve both at the same time.

<About the configuration of semiconductor devices>
FIG. 1 is a cross-sectional view schematically showing an example of a configuration of a semiconductor device according to the present embodiment. As an example is shown in FIG. 1, the semiconductor device according to the present embodiment includes an n + type semiconductor substrate 1, an n− type semiconductor layer 2 formed on the upper surface of the n + type semiconductor substrate 1, and n−. The p-type diffusion region 3 formed on the surface layer of the type semiconductor layer 2, the n + type diffusion region 4 formed on the surface layer of the p-type diffusion region 3, and n− from the upper surface of the n + type diffusion region 4. A p-type diffusion region 6 formed in contact with the lower surface of the trench 100 from below the trench 100 extending into the semiconductor layer 2 of the mold, a gate oxide film 101 formed in the trench 100, and a gate in the trench 100. A gate electrode 5 formed surrounded by an oxide film 101, a source electrode 7 formed straddling the upper surface of a p-type diffusion region 3 and an upper surface of an n + type diffusion region 4, an n + type semiconductor substrate 1 A drain electrode 8 formed in contact with the lower surface of the semiconductor device and a Vj terminal for applying a voltage to the p-type diffusion region 6 are provided. The voltage applied to the Vj terminal from the outside is the voltage applied to the p-type diffusion region 6.

Here, the p-type diffusion region 6 is not electrically connected to the source electrode 7. That is, the junction potential (Vj) applied to the p-type diffusion region 6 can be controlled independently of the source voltage (Vs) via the Vj terminal.

Further, FIG. 20 is a cross-sectional view showing an example of the form of the Vj terminal according to the present embodiment. As an example is shown in FIG. 20, a p-type diffusion region 3a is formed on the front side of the surface layer of the n-type semiconductor layer 2, and a source electrode 7 (here, here) is formed on the upper surface of the p-type diffusion region 3a. (Not shown) is formed.

On the other hand, as shown in FIG. 20, a p-type diffusion region 3b is formed on the inner side of the surface layer of the n-type semiconductor layer 2, and is formed on the side wall of the trench 100 in contact with the p-type diffusion region 3b. By forming the p-type diffusion region 6, the p-type diffusion region 6 located on the lower surface of the trench 100 and the Vj terminal (not shown here) are connected.

Further, FIG. 21 is a plan view showing an example of the form of the Vj terminal according to the present embodiment. In FIG. 20, the formation region of the p-type diffusion region 3a and the formation region of the p-type diffusion region 3b are divided into a front side and a back side in the surface layer of the n-type semiconductor layer 2. As an example is shown in FIG. 21, intricately intricate forming regions may be formed while being separated from each other.

FIG. 2 is a diagram showing an equivalent circuit having the structure shown in FIG. The JFET 200 in FIG. 2 is formed so as to have a p-type diffusion region 6 as a gate electrode. A voltage is applied to the gate terminal of the JFET 200 via the Vj terminal.

The Vj terminal of the JFET 200 is not connected to the source terminal of the trench gate type MOSFET 201 and is electrically independent. That is, in the JFET 200, since the p-type diffusion region 6 and the p-type diffusion region 3 are not electrically connected, the junction potential (Vj) can be controlled independently of the source voltage (Vs).

FIG. 3 is a diagram showing an example of each terminal voltage in the operating state of the semiconductor device. In FIG. 3, the vertical axis represents the drain current (Id) or the junction potential (Vj), and the horizontal axis represents the drain voltage (Vd).

As shown in FIG. 3, the junction potential increases when the drain current (Id) increases as the drain voltage (Vd) of the MOSFET 201 rises and the drain current (Id) becomes an overcurrent state. (Vj) is changed from 0V to a negative bias.

Then, the drain current (Id) decreases due to the increase in the JFET resistance, so that the overcurrent state is eliminated. Therefore, overcurrent protection is possible.

As described above, in the normal operation of the MOSFET 201 (specifically, the on operation and the off operation), the conventional characteristic of the junction potential (Vj) = 0V is maintained, and the MOSFET 201 is joined only when the MOSFET 201 is in an overcurrent state. By changing the potential (Vj) in the negative bias direction, the JFET resistance can be increased, and as a result, the drain current (Id) can be decreased. Therefore, it is possible to achieve both low on-resistance of the semiconductor device and protection of overcurrent of the semiconductor device.

Further, conventionally, the normal operation of the MOSFET and the suppression control of the drain current (Id) in the overcurrent state are performed by controlling the gate voltage (Vg) having a high input impedance. Therefore, the capacitive coupling between the gate and the drain has become a factor that destabilizes the overcurrent protection.

However, according to this embodiment, the gate voltage (Vg) that controls the normal operation of the MOSFET 201 and the junction potential (Vj) that controls the operation for overcurrent protection can be controlled separately. Therefore, the stability of operation can be improved.

Further, in the operation for overcurrent protection, it is possible to enhance the effect of suppressing the drain current (Id) by interlocking the control for lowering the junction potential (Vj) with the control for lowering the gate voltage (Vg). be.

<Second Embodiment>
The semiconductor device according to this embodiment will be described. In the following description, components similar to the components described in the above-described embodiment will be illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate. ..

<About the configuration of semiconductor devices>
FIG. 4 is a diagram showing an example of each terminal voltage in the operating state of the semiconductor device. In FIG. 4, the vertical axis represents the drain current (Id) or the junction potential (Vj), and the horizontal axis represents the drain voltage (Vd).

As an example is shown in FIG. 4, in the normal operation of the MOSFET 201, the JFET resistance is lowered by changing the junction potential (Vj) in the positive bias direction. On the other hand, the drain current (Id) increases as the drain voltage (Vd) of the MOSFET 201 rises, and when the drain current (Id) becomes an overcurrent state, the junction potential (Vj) becomes negative from 0 V. Change to bias.

When the junction potential (Vj) is positive bias, the electric field in the vicinity of the MOSFET 201 becomes stronger in the off state of the MOSFET 201. Therefore, the withstand voltage of the MOSFET 201 may decrease.

However, by setting the junction potential (Vj) to 0 V or a negative bias in the off state of the MOSFET 201, it is possible to avoid a decrease in the withstand voltage of the MOSFET 201.

As described above, according to the present embodiment, it is possible to achieve both low on-resistance of the semiconductor device and protection of overcurrent of the semiconductor device.

Further, when the positive bias of the junction potential (Vj) during the normal operation of the MOSFET 201 is increased to the extent that the hole injection operation occurs, the resistance of the n-type semiconductor layer 2 in the vicinity of the JFET 200 is lowered by the conductivity modulation effect. Then, the on-resistance of the MOSFET 201 is further reduced.

<Third embodiment>
The semiconductor device according to this embodiment will be described. In the following description, components similar to the components described in the above-described embodiment will be illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate. ..

<About the configuration of semiconductor devices>
FIG. 5 is a diagram showing an example of each terminal voltage in the operating state of the semiconductor device. In FIG. 5, the vertical axis represents the drain current (Id) or the junction potential (Vj), and the horizontal axis represents the drain voltage (Vd).

As an example is shown in FIG. 5, the junction potential (Vj) is set to a negative bias when the MOSFET 201 is off, and the negative bias of the junction potential (Vj) is reduced when the MOSFET 201 is on. Then, when the drain current (Id) of the MOSFET 201 becomes an overcurrent state, the negative bias of the junction potential (Vj) is increased again.

From the viewpoint of protecting the gate oxide film 101 in the off state of the MOSFET 201, the JFET resistance cannot be set below a certain value in the structure of the junction potential (Vj) = 0V.

However, in the structure according to the present embodiment, the electric field shielding effect can be enhanced by setting the junction potential (Vj) to a negative bias in the off state of the MOSFET 201. Therefore, a JFET having a smaller resistance can be adopted.

In the example shown in the first embodiment, the positive bias of the junction potential (Vj) of the MOSFET 201 in the on state is limited to the drain voltage (Vd) or less.

In the example shown in the second embodiment, there is no limitation on the positive bias of the junction potential (Vj), but if the junction potential (Vj) is increased above a specific value, hole injection occurs. This is effective from the viewpoint of reducing the on-resistance of the MOSFET 201, but there are concerns about an increase in turn-off time and turn-off loss due to residual holes, and a risk of growth of crystal defects due to electron hole recombination.

In the example shown in the third embodiment, a large potential change with almost no limitation is possible within the range of the negative bias of the junction potential (Vj). Therefore, it is possible to achieve both low on-resistance of the semiconductor device and protection of overcurrent of the semiconductor device.

<Fourth Embodiment>
The semiconductor device according to this embodiment will be described. In the following description, components similar to the components described in the above-described embodiment will be illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate. ..

<About the configuration of semiconductor devices>
FIG. 6 is a diagram showing a circuit of a semiconductor device according to the present embodiment. As shown in FIG. 6, in the semiconductor device, the JFET 200, the MOSFET 201 to which the source terminal and the drain terminal of the JFET 200 are connected, the anode terminal is connected to the gate terminal of the JFET 200, and the cathode terminal is the gate of the MOSFET 201. It includes a diode 202 connected to a terminal. In this structure, a diode 202 is added between the Vj terminal of the JFET 200 and the gate terminal of the MOSFET 201.

FIG. 7 is a cross-sectional view schematically showing an example of the configuration of the semiconductor device according to the present embodiment. As an example is shown in FIG. 7, the semiconductor device according to the present embodiment includes an n + type semiconductor substrate 1, an n− type semiconductor layer 2, a p type diffusion region 3, and an n + type diffusion region 4. The p-type diffusion region 6A formed outside the trench 100 along the lower surface and one side surface of the trench 100 and reached the p-type diffusion region 3, the gate oxide film 101, and the gate electrode. 5, a source electrode 7, a drain electrode 8, and a Vj terminal are provided.

Here, the gate electrode 5 is electrically connected to the n + type diffusion region 4 formed on the surface layer of the p-type diffusion region 3 in which the p-type diffusion region 6A is in contact. The n + type diffusion region 4 is formed apart from the gate oxide film 101 on the surface layer of the p-type diffusion region 3 in which the p-type diffusion region 6A is in contact.

In this structure, since the pn junction formed between the p-type diffusion region 3 and the n + -type diffusion region 4 in contact with the p-type diffusion region 6A is used as the diode 202, the diode is formed. There is no need to add a new manufacturing process. The junction potential (Vj) does not have to be connected to the outside.

Assuming that the forward bias rising voltage of the diode 202 is Vf, the following relational expression holds in the off state of the MOSFET 201.

Therefore, the junction potential (Vj) is also negatively biased along with the negative bias of the gate voltage (Vg), and as a result, the overcurrent protection operation becomes possible.

As described above, according to the configuration of the present embodiment, the potential control of the junction potential (Vj) can be performed only by controlling the gate voltage (Vg).

During the turn-on operation of the MOSFET 201, Vf can be increased to the maximum gate voltage (Vg) + Vf, but conversely, in the direction in which the junction potential (Vj) decreases, the voltage is not clamped to the withstand voltage of the diode 202, so the junction potential (Vj) ) Becomes a negative bias. Therefore, the JFET resistance may increase and the on-resistance of the MOSFET 201 may deteriorate.

Countermeasures against this include a method of adjusting the withstand voltage Vb of the diode 202 to control the junction potential (Vj) to 0 V or higher, a method of adding an antiparallel diode and clamping with the Vf of the diode, or FIG. There is a method of voltage clamping by the punch-through voltage between the p-type diffusion region 3 and the p-type diffusion region 6A in the same manner as the withstand voltage Vb.

In the ON state of MOSFET 201, the following holds.

<Fifth Embodiment>
The semiconductor device according to this embodiment will be described. In the following description, components similar to the components described in the above-described embodiment will be illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate. ..

<About the configuration of semiconductor devices>
FIG. 8 is a cross-sectional view schematically showing an example of the configuration of the semiconductor device according to the present embodiment. As an example is shown in FIG. 8, the semiconductor device according to the present embodiment includes an n + type semiconductor substrate 1, an n− type semiconductor layer 2, a p type diffusion region 3, and an n + type diffusion region 4. The gate oxide film 101B formed in the trench 100 extending from the upper surface of the n + type diffusion region 4 into the n− type semiconductor layer 2 and the portion of the trench 100 excluding the lower surface are surrounded by the gate oxide film 101B. A p-type diffusion region 6B formed by contacting the lower surface of the trench 100 from below the trench 100 and the upper surface of the gate electrode 5B in contact with the lower surface of the gate electrode 5B, and a source. It includes an electrode 7, a drain electrode 8, and a Vj terminal.

The gate electrode 5B is, for example, n-type polysilicon. Therefore, a pn junction is formed on the surface in contact with the p-type diffusion region 6B (an n-type region is formed at least below the gate electrode 5B in FIG. 8).

In this structure, the pn junction formed between the gate electrode 5B and the p-type diffusion region 6B is used as the diode 202 (see FIG. 6).

According to the structure of the present embodiment, it is not necessary to reduce the region functioning as the channel of the MOSFET in order to form the diode, so that the deterioration of the on-resistance of the MOSFET 201 is suppressed.

The problem that the junction potential (Vj) during the turn-on operation of the MOSFET 201 becomes a negative bias can be dealt with in the same manner as the method shown in the fourth embodiment.

<Sixth Embodiment>
The semiconductor device according to this embodiment will be described. In the following description, components similar to the components described in the above-described embodiment will be illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate. ..

<About the configuration of semiconductor devices>
FIG. 9 is a cross-sectional view schematically showing an example of the configuration of the semiconductor device according to the present embodiment. As an example is shown in FIG. 9, the semiconductor device according to the present embodiment includes an n + type semiconductor substrate 1, an n− type semiconductor layer 2, a p type diffusion region 3, and an n + type diffusion region 4. , The p-type diffusion region 6, the gate oxide film 101, the gate electrode 5, the source electrode 7, the drain electrode 8, the Vj terminal, and the diode 203 connected to the Vj terminal and the gate electrode 5. Be prepared.

Here, in the diode 203, the anode terminal is connected to the p-type diffusion region 6, and the cathode terminal is connected to the gate electrode 5. Further, the diode 203 is a diode 203 in which a plurality of diode elements are connected in series.

The number of diodes 203 connected in series can be changed according to the required characteristics of the semiconductor device. Further, the diode 203 may be formed of an n-type polysilicon used for a gate electrode or the like in the element structure of the MOSFET and a pn diode composed of a p-type region in contact with the polysilicon.

The problem that the junction potential (Vj) during the turn-on operation of the MOSFET 201 becomes a negative bias can be dealt with in the same manner as the method shown in the fourth embodiment.

<7th embodiment>
The semiconductor device according to this embodiment will be described. In the following description, components similar to the components described in the above-described embodiment will be illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate. ..

<About the configuration of semiconductor devices>
FIG. 10 is a diagram showing a circuit of a semiconductor device according to the present embodiment. As shown in FIG. 10, in the semiconductor device, the JFET 200, the MOSFET 201 to which the source terminal and the drain terminal of the JFET 200 are connected, the anode terminal is connected to the Vj terminal, and the cathode terminal is connected to the Vjout terminal. The diode 204 and the capacitor 205 connected to the anode terminal of the diode 204 and the gate terminal of the MOSFET 201 are provided.

FIG. 11 is a cross-sectional view schematically showing an example of the configuration of the semiconductor device according to the present embodiment. As an example is shown in FIG. 11, the semiconductor device according to the present embodiment includes an n + type semiconductor substrate 1, an n− type semiconductor layer 2, a p type diffusion region 3, and an n + type diffusion region 4. A p-type diffusion region 6A, a gate oxide film 101, a gate electrode 5, a source electrode 7, a drain electrode 8, and a Vj terminal are provided.

Here, the n + type diffusion region 4 formed on the surface layer of the p-type diffusion region 3 with which the p-type diffusion region 6A contacts is connected to the Vjout terminal. The n + type diffusion region 4 is formed apart from the gate oxide film 101 on the surface layer of the p-type diffusion region 3 in which the p-type diffusion region 6A is in contact.

The Vjout terminal is electrically independent of the gate electrode 5. Further, a voltage is applied to the n + type diffusion region 4 via the Vjout terminal.

When a constant potential is applied to the Vjout terminal and the forward bias rising voltage of the added diode 204 is Vf, the gate voltage (Vg) is applied to the added capacitance (capacitor 205) when the gate voltage (Vg) becomes high potential. ) -Vf-Vjout voltage is maintained. Then, the junction potential (Vj) changes at a voltage Vjout-Vf lower than the gate voltage (Vg).

For example, assuming that Vjout = 0V and the gate voltage (Vg) is driven between V1 and 0, the junction potential (Vj) = Vf when the MOSFET 201 is on and the junction potential (Vj) = when the MOSFET 201 is off. It is negatively biased with Vf-V1.

As described above, according to the configuration of the present embodiment, the potential control of the junction potential (Vj) as shown in FIG. 4 and the potential control of the junction potential (Vj) as shown in FIG. 4 according to the voltage value V1 of the gate voltage (Vg) are shown in FIG. It is possible to control the potential of the junction potential (Vj) as described above.

In this structure, the pn junction formed between the p-type diffusion region 3 and the n + -type diffusion region 4 in contact with the p-type diffusion region 6A is used as the diode 204. Further, in this structure, the gate oxide film 101 is used as a capacitance (capacitor 205).

Therefore, it is not necessary to add a new manufacturing process for forming these. However, both the diode and the capacitance may be added to the outside.

<Eighth Embodiment>
The semiconductor device according to this embodiment will be described. In the following description, components similar to the components described in the above-described embodiment will be illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate. ..

<About the configuration of semiconductor devices>
FIG. 12 is a cross-sectional view schematically showing an example of the configuration of the semiconductor device according to the present embodiment. As an example is shown in FIG. 12, the semiconductor device according to the present embodiment is, for example, an application example of an insulated gate bipolar transistor, that is, an IGBT, and the p + type semiconductor layer 9 and the semiconductor layer 9 An n-type buffer layer 10 formed on the upper surface of the p + -type semiconductor layer 9, an n-type semiconductor layer 2 formed on the upper surface of the n-type buffer layer 10, a p-type diffusion region 3, and n +. The mold diffusion region 4, the p-type diffusion region 6 formed in contact with the lower surface of the trench 100 from below the trench 100, the gate oxide film 101 formed in the trench 100, and gate oxidation in the trench 100. A gate electrode 5 formed by being surrounded by a film 101, an emitter electrode 7C formed straddling the upper surface of a p-type diffusion region 3 and an upper surface of an n + type diffusion region 4, and a p + type semiconductor layer 9. It includes a collector electrode 8C formed in contact with the lower surface and a Vj terminal.

Here, the impurity concentration of the n-type buffer layer 10 is higher than the impurity concentration of the n-type semiconductor layer 2.

In the IGBT, the increase in the on-resistance due to the JFET resistance is a problem as in the MOSFET, but in the IGBT, there is another problem in addition to the problem.

In the IGBT, it is necessary to accumulate the hole injection from the collector electrode 8C in the n-type semiconductor layer 2 in the on state, but the p-type diffusion region 6 is short-circuited (that is, short-circuited) with the emitter electrode 7C. Then, the hole flows out through the p-type diffusion region 6. Then, since the hole accumulation is inhibited, the on-resistance is significantly deteriorated.

According to the structure of the present embodiment, since the p-type diffusion region 6 is positively biased when the IGBT is on, not only the JFET resistance is lowered, but also the hole in the p-type diffusion region 6 is potentially reduced. The inflow is suppressed. As a result, even in the IGBT, it is possible to achieve both low on-resistance and overcurrent protection.

<9th embodiment>
The semiconductor device according to this embodiment will be described. In the following description, components similar to the components described in the above-described embodiment will be illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate. ..

<About the configuration of semiconductor devices>
FIG. 13 is a cross-sectional view schematically showing an example of the configuration of the semiconductor device according to the present embodiment. As an example is shown in FIG. 13, the semiconductor device according to the present embodiment is, for example, an application example of the IGBT, which is a p + type semiconductor layer 9, an n-type buffer layer 10, and an n-type semiconductor layer. 2, p-type diffusion region 3, n + -type diffusion region 4, p-type diffusion region 6A, gate oxide film 101, gate electrode 5, emitter electrode 7C, collector electrode 8C, and Vj terminal. And.

Here, the gate electrode 5 is electrically connected to the n + type diffusion region 4 formed on the surface layer of the p-type diffusion region 3 in which the p-type diffusion region 6A is in contact. The n + type diffusion region 4 is formed apart from the gate oxide film 101 on the surface layer of the p-type diffusion region 3 in which the p-type diffusion region 6A is in contact.

According to the structure of the present embodiment, in the ON state of the IGBT, the junction potential (Vj) is higher than that of the emitter electrode 7C by Vf, which is the forward bias rising voltage of the diode added by the p-type diffusion region 6A. It becomes an electric potential. As a result, even in the IGBT, it is possible to achieve both low on-resistance and overcurrent protection.

<10th Embodiment>
The semiconductor device according to this embodiment will be described. In the following description, components similar to the components described in the above-described embodiment will be illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate. ..

<About the configuration of semiconductor devices>
FIG. 14 is a cross-sectional view schematically showing an example of the configuration of the semiconductor device according to the present embodiment. As shown in FIG. 14, the semiconductor device according to the present embodiment is, for example, an application example of the IGBT, which is a p + type semiconductor layer 9, an n-type buffer layer 10, and an n-type semiconductor layer. 2, p-type diffusion region 3, n + -type diffusion region 4, gate oxide film 101B, gate electrode 5B, p-type diffusion region 6B, emitter electrode 7C, collector electrode 8C, and Vj terminal. And.

According to the structure of the present embodiment, in the ON state of the IGBT, the junction potential (Vj) is higher than that of the emitter electrode 7C by Vf, which is the forward bias rising voltage of the diode added by the p-type diffusion region 6B. Since it becomes an electric potential, the inflow of holes is suppressed.

As a result, even in the IGBT, it is possible to achieve both low on-resistance and overcurrent protection. In addition, since it is not necessary to reduce the region that functions as a channel in order to form the diode, deterioration of the on-resistance is suppressed.

<11th Embodiment>
The semiconductor device according to this embodiment will be described. In the following description, components similar to the components described in the above-described embodiment will be illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate. ..

<About the configuration of semiconductor devices>
FIG. 15 is a cross-sectional view schematically showing an example of the configuration of the semiconductor device according to the present embodiment. As shown in FIG. 15, the semiconductor device according to the present embodiment is, for example, an application example of the IGBT, which is a p + type semiconductor layer 9, an n-type buffer layer 10, and an n-type semiconductor layer. 2, p-type diffusion region 3, n + -type diffusion region 4, p-type diffusion region 6, gate oxide film 101, gate electrode 5, emitter electrode 7C, collector electrode 8C, and diode 203. And a Vj terminal.

Here, in the diode 203, the anode terminal is connected to the Vj terminal, and the cathode terminal is connected to the gate electrode 5. Further, the diode 203 is a diode 203 in which a plurality of diode elements are connected in series.

In the structure of this embodiment, the diode 203 is added to the outside. Therefore, it is possible to increase Vf by series connection, and it is possible to suppress the inflow of holes into the p-type diffusion region 6. Therefore, even in the IGBT, it is possible to achieve both low on-resistance and overcurrent protection.

<12th Embodiment>
The semiconductor device according to this embodiment will be described. In the following description, components similar to the components described in the above-described embodiment will be illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate. ..

<About the configuration of semiconductor devices>
FIG. 16 is a cross-sectional view schematically showing an example of the configuration of the semiconductor device according to the present embodiment. As an example is shown in FIG. 16, the semiconductor device according to the present embodiment is, for example, an application example of an IGBT, which is a p + type semiconductor layer 9, an n-type buffer layer 10, and an n-type semiconductor layer. 2, p-type diffusion region 3, n + -type diffusion region 4, p-type diffusion region 6A, gate oxide film 101, gate electrode 5, emitter electrode 7C, collector electrode 8C, and Vj terminal. And.

Here, the n + type diffusion region 4 formed on the surface layer of the p-type diffusion region 3 with which the p-type diffusion region 6A contacts is connected to the Vjout terminal. The n + type diffusion region 4 is formed apart from the gate oxide film 101 on the surface layer of the p-type diffusion region 3 in which the p-type diffusion region 6A is in contact.

According to the structure of the present embodiment, it is possible to achieve both low on-resistance and overcurrent protection even in the IGBT.

Further, the flow of holes into the p-type diffusion region 6A can be adjusted by Vjout.

Further, in the plurality of embodiments described above, the case where an element such as a switching element or a diode element is formed of silicon has been shown, but these (specifically, at least an n-type semiconductor layer 2) have been shown. ) May be formed by a wide bandgap semiconductor having a larger bandgap than silicon.

Here, the wide-gap semiconductor generally refers to a semiconductor having a forbidden band width of about 2 eV or more, and is a group 3 nitride such as gallium nitride (GaN), a group 2 oxide such as zinc oxide (ZnO), and selenium. Group 2 chalcogenides such as zinc (ZnSe), diamonds, silicon carbide and the like are known.

The switching element or diode element formed of such a wide bandgap semiconductor has high withstand voltage resistance and high allowable current density. Therefore, the switching element or the diode element can be miniaturized. Then, by using such a miniaturized switching element or diode element, the semiconductor module in which these elements are incorporated can be miniaturized.

Further, since the switching element or diode element formed of the wide bandgap semiconductor has high heat resistance, it is possible to reduce the size of the heat radiation fins of the heat sink or to air-cool the water-cooled portion. Therefore, the semiconductor module in which these elements are incorporated can be miniaturized.

Further, since the switching element or the diode element formed by the wide bandgap semiconductor has a low power loss, the efficiency of the switching element or the diode element can be improved. Therefore, it is possible to improve the efficiency of the semiconductor module in which these elements are incorporated.

It is desirable that both the switching element and the diode element are formed of the wide bandgap semiconductor, but one of the elements may be formed of the wide bandgap semiconductor.

<About the effect caused by the above-described embodiment>
Next, an example of the effect produced by the above-described embodiment will be shown. In the following description, the effect is described based on the specific configuration shown in the embodiment described above, but to the extent that the same effect occurs, the examples in the present specification. May be replaced with other specific configurations indicated by.

Further, the replacement may be made across a plurality of embodiments. That is, it may be the case that the respective configurations shown in the examples in different embodiments are combined to produce the same effect.

According to the embodiment described above, the semiconductor device includes a first conductive type first semiconductor layer, a second conductive type first diffusion region, and a first conductive type second. The diffusion region, the trench 100, the gate oxide film 101, the gate electrode 5, the upper surface electrode, the second conductive type third diffusion region, and the first voltage application portion are provided. Here, the first semiconductor layer corresponds to, for example, the n-type semiconductor layer 2. The first diffusion region corresponds to, for example, the p-type diffusion region 3. The second diffusion region corresponds to, for example, the n + type diffusion region 4. The top electrode corresponds to, for example, the source electrode 7 or the emitter electrode 7C. The third diffusion region corresponds to, for example, at least one of a p-type diffusion region 6, a p-type diffusion region 6A, and a p-type diffusion region 6B. Further, the first voltage application unit corresponds to, for example, a Vj terminal. The p-type diffusion region 3 is formed on the surface layer of the n-type semiconductor layer 2. The n + type diffusion region 4 is formed on the surface layer of the p-type diffusion region 3. The trench 100 is formed by reaching the n− type semiconductor layer 2 from the upper surface of the n + type diffusion region 4. The gate oxide film 101 is formed in the trench 100. The gate electrode 5 is formed in the trench 100 so as to be at least partially surrounded by the gate oxide film 101. The source electrode 7 is formed so as to straddle the upper surface of the p-type diffusion region 3 and the upper surface of the n + type diffusion region 4. The p-shaped diffusion region 6 is formed in contact with the lower surface of the trench 100 from below the trench 100. The Vj terminal is electrically independent of the source electrode 7. Further, the Vj terminal is configured to apply a voltage to the p-type diffusion region 6.

According to such a configuration, the junction potential (Vj) of the p-type diffusion region 6 is controlled independently via the Vj terminal electrically independent of the source electrode 7, so that the semiconductor device is low on. Both resistance and overcurrent protection can be achieved at the same time.

In addition to these configurations, other configurations whose examples are shown in the present specification can be omitted as appropriate. That is, if at least these configurations are provided, the effects described above can be produced.

However, the present specification is not mentioned when at least one of the other configurations illustrated in the present specification is appropriately added to the above-described configuration, that is, as the above-described configuration. Similar effects can be produced even if other configurations, for example, are added as appropriate.

Further, according to the embodiment described above, the p-type diffusion region 6A is formed outside the trench 100 along the lower surface and one side surface of the trench 100. Further, the p-type diffusion region 6A is formed in contact with the lower surface of the p-type diffusion region 3. Then, the n + type diffusion region 4 formed on the surface layer of the p-type diffusion region 3 with which the p-type diffusion region 6A is in contact is electrically connected to the gate electrode 5. According to such a configuration, the junction potential (Vj) can be indirectly changed by controlling the gate voltage (Vg). Then, by controlling the junction potential (Vj), it is possible to achieve both low on-resistance of the semiconductor device and overcurrent protection of the semiconductor device. Further, since the p-type diffusion region 6A can be diverted by deforming the p-type diffusion region 6, it is not necessary to add a separate manufacturing process to form the p-type diffusion region 6A.

Further, according to the embodiment described above, the gate electrode 5B is formed so as to reach the lower surface of the trench 100. Further, the p-type diffusion region 6B is formed in contact with the lower surface of the gate electrode 5B. According to such a configuration, it is not necessary to reduce the region functioning as the channel of the MOSFET in order to form the diode, so that the deterioration of the on-resistance of the MOSFET is suppressed.

Further, according to the embodiment described above, the semiconductor device includes a diode 203 in which the cathode terminal is connected to the gate electrode 5 and the anode terminal is connected to the Vj terminal. According to such a configuration, for example, when a pn diode composed of n-type polysilicon used for a gate electrode in a MOSFET element structure and a p-type region in contact with the n-type polysilicon is used, a diode characteristic or a forward bias voltage or the like is used. Can be easily adjusted by increasing the number of stages of the diode.

Further, according to the embodiment described above, the p-type diffusion region 6A is formed outside the trench 100 along the lower surface and one side surface of the trench 100. Further, the p-type diffusion region 6A is formed in contact with the lower surface of the p-type diffusion region 3. Then, the n + type diffusion region 4 formed on the surface layer of the p-type diffusion region 3 with which the p-type diffusion region 6A contacts is connected to the second voltage application portion. Here, the second voltage application unit corresponds to, for example, the Vjout terminal. The Vjout terminal is configured to apply a voltage to the n + type diffusion region 4, which is electrically independent of the gate electrode 5. According to such a configuration, the pn junction formed between the p-type diffusion region 3 and the n + -type diffusion region 4 in contact with the p-type diffusion region 6A is used as a diode, and a gate oxide film is further formed. Since 101 can be used as a capacitance (capacitor), there is no need to add a separate manufacturing process to form the diode and capacitor.

Further, according to the embodiment described above, the semiconductor device includes a first conductive type second semiconductor layer, a second conductive type third semiconductor layer, and a bottom electrode. Here, the second semiconductor layer corresponds to, for example, the buffer layer 10. Further, the third semiconductor layer corresponds to, for example, the p + type semiconductor layer 9. The bottom electrode corresponds to, for example, the collector electrode 8C. The buffer layer 10 has a higher impurity concentration than the n-type semiconductor layer 2 formed on the lower surface of the n-type semiconductor layer 2. The p + type semiconductor layer 9 is formed on the lower surface of the buffer layer 10. The collector electrode 8C is formed on the lower surface of the p + type semiconductor layer 9. According to such a configuration, the junction potential (Vj) of the p-type diffusion region 6 is independently controlled by the Vj terminal, which is an electrode different from the emitter electrode 7C, so that the semiconductor device has a low on-resistance and an excess. It is possible to achieve both current protection. Further, by increasing the junction potential (Vj), it is possible to prevent the hole from flowing into the p-type diffusion region 6. Therefore, low on-resistance of the semiconductor device is realized.

Further, according to the embodiment described above, at least the n-type semiconductor layer 2 is made of a wide bandgap semiconductor. A switching element or diode element formed of a wide bandgap semiconductor has high withstand voltage resistance and high allowable current density. Therefore, the switching element or the diode element can be miniaturized. Then, by using such a miniaturized switching element or diode element, the semiconductor module in which these elements are incorporated can be miniaturized.

Further, according to the embodiment described above, the semiconductor device includes a trench gate type MOSFET 201, a JFET 200, and a Vj terminal. Here, in the JFET 200, the source terminal is connected to the drain terminal of the MOSFET 201. The Vj terminal is configured to apply a voltage to the gate terminal of the JFET 200. Further, the Vj terminal is electrically independent of the source terminal. According to such a configuration, the junction potential (Vj) of the JFET 200 is controlled independently via the Vj terminal that is electrically independent of the source terminal, thereby achieving low on-resistance and overcurrent protection of the semiconductor device. Can be compatible with each other.

Further, according to the embodiment described above, when the current flowing through the MOSFET 201 becomes an overcurrent state in the ON state of the MOSFET 201, the voltage applied to the gate terminal of the JFET 200 is lowered via the Vj terminal. According to such a configuration, the drain current (Id) decreases due to the increase in the JFET resistance, so that the overcurrent state is eliminated. Therefore, overcurrent protection is possible.

Further, according to the embodiment described above, no voltage is applied to the gate terminal of the JFET 200 via the Vj terminal in the off state of the MOSFET 201. Further, in the ON state of the MOSFET 201, a positive bias is applied to the gate terminal of the JFET 200 via the Vj terminal. Further, when the current flowing through the MOSFET 201 becomes an overcurrent state, a negative bias is applied to the gate terminal of the JFET 200 via the Vj terminal. According to such a configuration, it is possible to achieve both low on-resistance of the semiconductor device and protection of overcurrent of the semiconductor device. Further, when the positive bias of the junction potential (Vj) during the normal operation of the MOSFET 201 is increased to the extent that the hole injection operation occurs, the resistance of the n-type semiconductor layer 2 in the vicinity of the JFET 200 is lowered by the conductivity modulation effect. Then, the on-resistance of the MOSFET 201 is further reduced.

Further, according to the embodiment described above, the first negative bias is applied to the gate terminal of the JFET 200 via the Vj terminal in the off state of the MOSFET 201. Further, in the ON state of the MOSFET 201, a second negative bias is applied to the gate terminal of the JFET 200 via the Vj terminal. Further, when the current flowing through the MOSFET 201 becomes an overcurrent state, a third negative bias is applied to the gate terminal of the JFET 200 via the Vj terminal. Here, the first negative bias is a voltage lower than that of the second negative bias. Further, the first negative bias is a voltage higher than that of the third negative bias. According to such a configuration, a large potential change with almost no limitation is possible within the range of the negative bias of the junction potential (Vj). Therefore, it is possible to achieve both low on-resistance of the semiconductor device and protection of overcurrent of the semiconductor device.

Further, according to the embodiment described above, the semiconductor device includes a diode 202 in which the cathode terminal is connected to the gate terminal of the MOSFET 201 and the anode terminal is connected to the Vj terminal. According to such a configuration, the potential control of the junction potential (Vj) can be performed only by controlling the gate voltage (Vg).

Further, according to the embodiment described above, the semiconductor device includes a Vjout terminal connected to the Vj terminal, a diode 204, and a capacitor 205. The cathode terminal of the diode 204 is connected to the Vjout terminal. Further, the anode terminal of the diode 204 is connected to the Vj terminal. The capacitor 205 is connected between the gate terminal of the MOSFET 201 and the anode terminal of the diode 204. According to such a configuration, the junction potential (Vj) can be controlled by the gate voltage (Vg), and the change of the junction potential (Vj) can be controlled by Vjout.

<About the modified example in the above-described embodiment>
In the embodiments described above, the materials, materials, dimensions, shapes, relative arrangement relationships, implementation conditions, etc. of each component may also be described, but these are one example in all aspects. However, it is not limited to those described in the present specification.

Therefore, innumerable variants and equivalents for which examples are not shown are envisioned within the scope of the techniques disclosed herein. For example, when transforming, adding or omitting at least one component, or when extracting at least one component in at least one embodiment and combining it with the components of another embodiment. Shall be included.

Further, as long as there is no contradiction, "one or more" components described as being provided in the above-described embodiment may be provided.

Further, each component in the above-described embodiment is a conceptual unit, and within the scope of the technology disclosed in the present specification, one component is composed of a plurality of structures. And the case where one component corresponds to a part of a structure, and further, the case where a plurality of components are provided in one structure.

In addition, each component in the above-described embodiment shall include a structure having another structure or shape as long as it exhibits the same function.

In addition, the description in the present specification is referred to for all purposes relating to the present technology, and none of them is recognized as a prior art.

Further, in the above-described embodiment, when a material name or the like is described without being specified, the material contains other additives, for example, an alloy, etc., as long as there is no contradiction. It shall be included.

Further, in the above-described embodiment, the first conductive type is n-type and the second conductive type is p-type, but conversely, the first conductive type is p-type. It is assumed that the second conductive type may be n type.

1 Semiconductor substrate, 2n-type semiconductor layer, 3,3a, 3b, 6,6A, 6Bp type diffusion region, 4n + type diffusion region, 5,5B gate electrode, 7 source electrode, 7C emitter electrode, 8 drain electrode, 8C collector electrode, 9 p + type semiconductor layer, 10 buffer layer, 100 trench, 101, 101B gate oxide film, 200 JFET, 201 MOSFET, 202, 203, 204 diode, 205 condenser.

Claims (10)

The first conductive type first semiconductor layer and
A second conductive type first diffusion region formed on the surface layer of the first semiconductor layer, and
A first conductive type second diffusion region formed on the surface layer of the first diffusion region,
A trench formed by reaching the first semiconductor layer from the upper surface of the second diffusion region, and
The gate oxide film formed in the trench and
A gate electrode formed in the trench, at least partially surrounded by the gate oxide film,
An upper surface electrode formed so as to straddle the upper surface of the first diffusion region and the upper surface of the second diffusion region.
A second conductive type third diffusion region formed in contact with the lower surface of the trench from below the trench,
It is provided with a first voltage applying portion for applying a voltage to the third diffusion region, which is electrically independent of the top electrode.
The third diffusion region is formed outside the trench along the lower surface of the trench and one side surface, and is formed in contact with the lower surface of the first diffusion region.
The second diffusion region formed on the surface layer of the first diffusion region with which the third diffusion region contacts is electrically connected to the gate electrode.
Semiconductors devices. The first conductive type first semiconductor layer and
A second conductive type first diffusion region formed on the surface layer of the first semiconductor layer, and
A first conductive type second diffusion region formed on the surface layer of the first diffusion region,
A trench formed by reaching the first semiconductor layer from the upper surface of the second diffusion region, and
The gate oxide film formed in the trench and
A gate electrode formed in the trench, at least partially surrounded by the gate oxide film,
An upper surface electrode formed so as to straddle the upper surface of the first diffusion region and the upper surface of the second diffusion region.
A second conductive type third diffusion region formed in contact with the lower surface of the trench from below the trench,
It is provided with a first voltage applying portion for applying a voltage to the third diffusion region, which is electrically independent of the top electrode.
Further comprising a diode in which the cathode terminal is connected to the gate electrode and the anode terminal is connected to the first voltage application portion.
Semi conductor device. The first conductive type first semiconductor layer and
A second conductive type first diffusion region formed on the surface layer of the first semiconductor layer, and
A first conductive type second diffusion region formed on the surface layer of the first diffusion region,
A trench formed by reaching the first semiconductor layer from the upper surface of the second diffusion region, and
The gate oxide film formed in the trench and
A gate electrode formed in the trench, at least partially surrounded by the gate oxide film,
An upper surface electrode formed so as to straddle the upper surface of the first diffusion region and the upper surface of the second diffusion region.
A second conductive type third diffusion region formed in contact with the lower surface of the trench from below the trench,
It is provided with a first voltage applying portion for applying a voltage to the third diffusion region, which is electrically independent of the top electrode.
The third diffusion region is formed outside the trench along the lower surface of the trench and one side surface, and is formed in contact with the lower surface of the first diffusion region.
The second diffusion region formed on the surface layer of the first diffusion region in contact with the third diffusion region is electrically independent of the gate electrode and applies a voltage to the second diffusion region. Connected to the second voltage application part for
Semi conductor device. A first conductive type second semiconductor layer having a higher impurity concentration than the first semiconductor layer, which is formed on the lower surface of the first semiconductor layer,
A second conductive type third semiconductor layer formed on the lower surface of the second semiconductor layer, and
A lower surface electrode formed on the lower surface of the third semiconductor layer is further provided.
The semiconductor device according to any one of claims 1 to 3. At least the first semiconductor layer is made of a wide bandgap semiconductor.
The semiconductor device according to any one of claims 1 to 4. Trench gate type MOSFET and
A JFET whose source terminal is connected to the drain terminal of the MOSFET,
It is provided with a first voltage application unit for applying a voltage to the gate terminal of the JFET, which is electrically independent of the source terminal of the MOSFET.
A diode in which the cathode terminal is connected to the gate terminal of the MOSFET and the anode terminal is connected to the first voltage application portion is further provided.
Semi conductor device. Trench gate type MOSFET and
A JFET whose source terminal is connected to the drain terminal of the MOSFET,
It is provided with a first voltage application unit for applying a voltage to the gate terminal of the JFET, which is electrically independent of the source terminal of the MOSFET.
A second voltage application unit connected to the first voltage application unit and
A diode in which the cathode terminal is connected to the second voltage application unit and the anode terminal is connected to the first voltage application unit.
A capacitor connected between the gate terminal of the MOSFET and the anode terminal of the diode is further provided.
Semi conductor device. When the current flowing through the MOSFET becomes an overcurrent state in the ON state of the MOSFET, the voltage applied to the gate terminal of the JFET is lowered via the first voltage application unit.
The semiconductor device according to claim 6 or 7. In the OFF state of the MOSFET, no voltage is applied to the gate terminal of the JFET via the first voltage application unit.
In the ON state of the MOSFET, a positive bias is applied to the gate terminal of the JFET via the first voltage application unit, and the positive bias is applied.
When the current flowing through the MOSFET becomes an overcurrent state, a negative bias is applied to the gate terminal of the JFET via the first voltage application unit.
The semiconductor device according to any one of claims 6 to 8. In the OFF state of the MOSFET, a first negative bias is applied to the gate terminal of the JFET via the first voltage application unit.
In the ON state of the MOSFET, a second negative bias is applied to the gate terminal of the JFET via the first voltage application unit, and the second negative bias is applied.
When the current flowing through the MOSFET becomes an overcurrent state, a third negative bias is applied to the gate terminal of the JFET via the first voltage application unit.
The first negative bias is a voltage lower than that of the second negative bias.
The first negative bias is a higher voltage than the third negative bias.
The semiconductor device according to any one of claims 6 to 8.

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