JP6965222B2 - Semiconductor device - Google Patents

Description

Embodiments of the present invention relate to semiconductor devices.

In a multi-beam type electron beam drawing apparatus, a plurality of electron beams are simultaneously irradiated to a sample. A blanking aperture array (BAA) is used to individually control the irradiation and non-irradiation of a plurality of electron beams to a sample. The semiconductor layer of BAA is provided with a plurality of through holes for passing a plurality of electron beam beams. Each through hole has a pair of electrodes, and the electric field generated between the electrodes deflects each electron beam independently.

For example, as the number of electron beams increases, it is required to shorten the arrangement pitch of the through holes. However, when the arrangement pitch of the through holes is shortened, the deflection accuracy of the electron beam is lowered due to the influence of the electric field generated by the electrodes of the through holes adjacent to each other.

Japanese Unexamined Patent Publication No. 2012-79475

An object to be solved by the present invention is to provide a semiconductor device for improving the deflection accuracy of an electron beam.

The semiconductor device of one aspect of the present invention includes a first semiconductor layer having a first substrate region in which the potential is fixed, a second semiconductor layer having a second substrate region in which the potential is fixed, and the above-mentioned first. It has a plurality of first conductive layers provided between the semiconductor layer 1 and the second semiconductor layer and laminated in a first direction from the first semiconductor layer toward the second semiconductor layer. A second layer provided between the first multilayer wiring layer, the first multilayer wiring layer, and the second semiconductor layer, and having a plurality of second conductive layers laminated in the first direction. A second transistor having a multilayer wiring layer, a first impurity region in the first semiconductor layer, and a second impurity region in the second semiconductor layer. The first semiconductor layer, the first multilayer wiring layer, the second multilayer wiring layer, the first hole penetrating the second semiconductor layer, and the first semiconductor layer, said. A first multilayer wiring layer, a second multilayer wiring layer, a second hole penetrating the second semiconductor layer, and a first electrode provided in the first multilayer wiring layer. A second electrode, which is provided in the first multilayer wiring layer and faces the first electrode with the first hole in between.

The schematic diagram of the semiconductor device of 1st Embodiment. An enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment. FIG. 3 is a schematic cross-sectional view during manufacturing of the semiconductor device of the first embodiment. FIG. 3 is a schematic cross-sectional view during manufacturing of the semiconductor device of the first embodiment. FIG. 3 is a schematic cross-sectional view during manufacturing of the semiconductor device of the first embodiment. FIG. 3 is a schematic cross-sectional view during manufacturing of the semiconductor device of the first embodiment. FIG. 3 is a schematic cross-sectional view during manufacturing of the semiconductor device of the first embodiment. FIG. 3 is a schematic cross-sectional view during manufacturing of the semiconductor device of the first embodiment. The explanatory view of the operation of the semiconductor device of 1st Embodiment. An enlarged schematic cross-sectional view of a part of the semiconductor device of the second embodiment.

In the present specification, the same or similar members may be designated by the same reference numerals and duplicate description may be omitted.

In the present specification, in order to indicate the positional relationship of parts and the like, the upper direction of the drawing may be described as "upper" and the lower direction of the drawing may be described as "lower". In the present specification, the concepts of "upper" and "lower" do not necessarily indicate the relationship with the direction of gravity.

(First Embodiment)
The semiconductor device of the first embodiment is provided between the first semiconductor layer, the second semiconductor layer, the first semiconductor layer and the second semiconductor layer, and is provided from the first semiconductor layer to the second semiconductor layer. A first multilayer wiring layer having a plurality of first conductive layers laminated in a first direction toward the semiconductor layer of the above, and a first multilayer wiring layer provided between the first multilayer wiring layer and the second semiconductor layer. A first having a second multilayer wiring layer having a plurality of second conductive layers laminated in one direction, a first gate electrode, and a first impurity region in the first semiconductor layer. A second transistor having a transistor, a second gate electrode, and a second impurity region in the second semiconductor layer, a first semiconductor layer, a first multilayer wiring layer, and a second multilayer. A first hole penetrating the wiring layer and the second semiconductor layer, and a first semiconductor layer, a first multilayer wiring layer, a second multilayer wiring layer, and a second semiconductor layer penetrating the second semiconductor layer. The second hole, the first electrode provided in the first multilayer wiring layer, and the first electrode provided in the first multilayer wiring layer and facing the first electrode with the first hole in between. A second electrode is provided.

FIG. 1 is a schematic view of the semiconductor device of the first embodiment. FIG. 1A is a top view and FIG. 1B is a cross-sectional view. FIG. 1 (b) is a cross-sectional view taken along the line AA'of FIG. 1 (a).

The semiconductor device of the first embodiment is, for example, BAA100 used in a multi-beam type electron beam drawing device. The multi-beam electron beam drawing apparatus draws a pattern on a sample using a plurality of electron beams.

The BAA100 has a function of individually deflecting each of a plurality of electron beams. For example, by combining the BAA100 and the aperture that shields the electron beam, it is possible to independently control the irradiation and non-irradiation of each electron beam to the sample.

As shown in FIG. 1, the BAA 100 has a plurality of through holes 101 in the central portion. An electron beam passes through each of the through holes 101. FIG. 1A illustrates a case where a total of 121 through holes 101, 11 in the horizontal direction and 11 in the vertical direction, are arranged in an array. However, the number of through holes 101 and the shape of the arrangement are not limited to the above-mentioned form.

The diameter of the through hole 101 is, for example, 3 μm or more and 20 μm or less. The arrangement pitch of the through holes 101 is, for example, 20 μm or more and 40 μm or less.

An electrode pad 102 is provided on the upper surface of the BAA 100. The electrode pad 102 is provided to apply a voltage to the BAA 100 from the outside. The electrode pad 102 is electrically connected to, for example, a control circuit of BAA100 (not shown) or an electrode for deflection control (not shown).

FIG. 2 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment. FIG. 2 includes a cross section of the two through holes 101.

The BAA 100 includes a first semiconductor layer 10, a second semiconductor layer 20, a first multilayer wiring layer 30, a second multilayer wiring layer 40, a first transistor TR1, and a second transistor TR2. The BAA100 includes a first electrode E1, a second electrode E2, a third electrode E3, a fourth electrode E4, a fifth electrode E5, a sixth electrode E6, a seventh electrode E7, and an eighth electrode E8. To be equipped with. The BAA100 also has a first through hole 101a (first hole) and a second through hole 101b (second hole).

The first semiconductor layer 10 has a p-type first substrate region 11, an n ⁺ -type first source / drain region 12 (first impurity region), and a p ⁺ -type first contact region 13. .. The second semiconductor layer 20 has a p-type second substrate region 21, an n ⁺ -type second source / drain region 22 (second impurity region), and a p ⁺ -type second contact region 23. ..

The first multilayer wiring layer 30 has a first conductive layer 31, a first gate electrode 32, a first contact plug 33, a first connection pad 34, and a first interlayer insulating layer 35. The second multilayer wiring layer 40 has a second conductive layer 41, a second gate electrode 42, a second contact plug 43, a second connection pad 44, and a second interlayer insulating layer 45.

The first semiconductor layer 10 is, for example, single crystal silicon. The p-type first substrate region 11 is silicon containing p-type impurities. The n ⁺ type first source / drain region 12 is silicon containing n-type impurities. The p ⁺ type first contact region 13 is silicon containing p-type impurities.

The potential of the first semiconductor layer 10 is, for example, the ground potential. The potential of the p-type first substrate region 11 is, for example, the ground potential.

The second semiconductor layer 20 is, for example, single crystal silicon. The p-type second substrate region 21 is silicon containing p-type impurities. The n ⁺ type second source / drain region 22 is silicon containing n type impurities. The p ⁺ type second contact region 23 is silicon containing p-type impurities.

The potential of the second semiconductor layer 20 is, for example, the ground potential. The potential of the p-type second substrate region 21 is, for example, the ground potential.

The first multilayer wiring layer 30 is provided between the first semiconductor layer 10 and the second semiconductor layer 20. The first multilayer wiring layer 30 has a plurality of first conductive layers 31. The first conductive layer 31 is laminated in the first direction from the first semiconductor layer 10 toward the second semiconductor layer 20. The first direction is the direction perpendicular to the surface of the first semiconductor layer. The number of layers of the first conductive layer 31 is, for example, 3 layers or more and 20 layers or less.

A first interlayer insulating layer 35 is provided between the first conductive layers 31. The first interlayer insulating layer 35 is, for example, silicon oxide.

A part of the first conductive layer 31 functions as wiring. The first conductive layer 31 is, for example, a metal.

The first contact plug 33 is formed between the first semiconductor layer 10 and the first conductive layer 31, between the first conductive layer 31 and the first conductive layer 31, and between the first conductive layer 31 and the first conductive layer 31. It is provided between the connection pad 34 of 1. The first contact plug 33 is formed between the first semiconductor layer 10 and the first conductive layer 31, between the first conductive layer 31 and the first conductive layer 31, and between the first conductive layer 31 and the first conductive layer 31. It has a function of electrically connecting to the connection pad 34 of 1. The first contact plug 33 is, for example, metal.

The first connection pad 34 comes into contact with the second connection pad 44. The first connection pad 34 is electrically connected to the second connection pad 44. The first connection pad 34 is, for example, metal.

The first gate electrode 32 is a conductor. The first gate electrode 32 is, for example, polycrystalline silicon containing conductive impurities.

The second multilayer wiring layer 40 is provided between the first multilayer wiring layer 30 and the second semiconductor layer 20. The second multilayer wiring layer 40 has a plurality of second conductive layers 41. The second conductive layer 41 is laminated in the first direction from the first semiconductor layer 10 toward the second semiconductor layer 20. The number of layers of the second conductive layer 41 is, for example, 5 layers or more and 20 layers or less.

A second interlayer insulating layer 45 is provided between the second conductive layers 41. The second interlayer insulating layer 45 is, for example, silicon oxide.

A part of the second conductive layer 41 functions as wiring. The second conductive layer 41 is, for example, a metal.

The second contact plug 43 is formed between the second semiconductor layer 20 and the second conductive layer 41, between the second conductive layer 41 and the second conductive layer 41, and between the second conductive layer 41 and the second conductive layer 41. It is provided between the connection pad 44 of 2. The second contact plug 43 is formed between the second semiconductor layer 20 and the second conductive layer 41, between the second conductive layer 41 and the second conductive layer 41, and between the second conductive layer 41 and the second conductive layer 41. It has a function of electrically connecting to and from the connection pad 44 of 2. The second contact plug 43 is, for example, metal.

The second connection pad 44 comes into contact with the first connection pad 34. The second connection pad 44 is electrically connected to the first connection pad 34. The second connection pad 44 is, for example, metal.

By electrically connecting the second connection pad 44 and the first connection pad 34, the first conductive layer 31 and the second conductive layer 41 are electrically connected.

The second gate electrode 42 is a conductor. The second gate electrode 42 is, for example, polycrystalline silicon containing conductive impurities.

The first through hole 101a penetrates the first semiconductor layer 10, the first multilayer wiring layer 30, the second multilayer wiring layer 40, and the second semiconductor layer 20.

The second through hole 101b penetrates the first semiconductor layer 10, the first multilayer wiring layer 30, the second multilayer wiring layer 40, and the second semiconductor layer 20.

The first electrode E1, the second electrode E2, the fifth electrode E5, and the sixth electrode E6 are provided in the first multilayer wiring layer 30. The first electrode E1, the second electrode E2, the fifth electrode E5, and the sixth electrode E6 have a laminated structure including a plurality of first conductive layers 31. The first electrode E1, the second electrode E2, the fifth electrode E5, and the sixth electrode E6 are composed of a plurality of first conductive layers 31 connected by the first contact plug 33.

The first electrode E1 and the second electrode E2 face each other with the first through hole 101a interposed therebetween. The first electrode E1 and the second electrode E2 are exposed on the side surface of the first through hole 101a, for example.

The first electrode E1 is electrically connected to the first semiconductor layer 10. The first electrode E1 is ^{electrically connected to the p +} type first contact region 13. The potential of the first electrode E1 is the ground potential.

The second electrode E2 is ^{electrically connected to the n +} type first source / drain region 12. The potential of the second electrode E2 changes. The potential of the second electrode E2 changes, for example, between a ground potential and a predetermined positive potential.

The fifth electrode E5 and the sixth electrode E6 face each other with the second through hole 101b interposed therebetween. The fifth electrode E5 and the sixth electrode E6 are exposed on the side surface of the second through hole 101b, for example.

The fifth electrode E5 is electrically connected to the first semiconductor layer 10. The fifth electrode E5 is ^{electrically connected to the p +} type first contact region 13. The potential of the fifth electrode E5 is the ground potential.

The sixth electrode E6 is ^{electrically connected to the n +} type second source / drain region 22. The potential of the sixth electrode E6 changes. The potential of the sixth electrode E6 changes, for example, between a ground potential and a predetermined positive potential.

The third electrode E3, the fourth electrode E4, the seventh electrode E7, and the eighth electrode E8 are provided in the second multilayer wiring layer 40. The third electrode E3, the fourth electrode E4, the seventh electrode E7, and the eighth electrode E8 have a laminated structure including a plurality of second conductive layers 41. The third electrode E3, the fourth electrode E4, the seventh electrode E7, and the eighth electrode E8 are composed of a plurality of second conductive layers 41 connected by the second contact plug 43.

The third electrode E3 and the fourth electrode E4 face each other with the first through hole 101a interposed therebetween. The third electrode E3 and the fourth electrode E4 are exposed on the side surface of the first through hole 101a, for example.

The third electrode E3 is electrically connected to the second semiconductor layer 20. The third electrode E3 is ^{electrically connected to the p +} type second contact region 23. The potential of the third electrode E3 is the ground potential.

The fourth electrode E4 is ^{electrically connected to the n +} type first source / drain region 12. The fourth electrode E4 is electrically connected to the second electrode E2. The potential of the fourth electrode E4 changes. The potential of the fourth electrode E4 changes, for example, between a ground potential and a predetermined positive potential.

The seventh electrode E7 and the eighth electrode E8 face each other with the second through hole 101b interposed therebetween. The seventh electrode E7 and the eighth electrode E8 are exposed on the side surface of the second through hole 101b, for example.

The seventh electrode E7 is electrically connected to the second semiconductor layer 20. The seventh electrode E7 is ^{electrically connected to the p +} type second contact region 23. The potential of the seventh electrode E7 is the ground potential.

The eighth electrode E8 is connected to the n ⁺ type second source / drain region 22. The eighth electrode E8 is electrically connected to the fourth electrode E4. The potential of the eighth electrode E8 changes. The potential of the eighth electrode E8 changes, for example, between a ground potential and a predetermined positive potential.

The first transistor TR1 has a first gate electrode 32 and a pair of n ⁺ type first source / drain regions 12. A first gate insulating film (not shown) is provided between the first gate electrode 32 and the first semiconductor layer 10. The first transistor TR1 is an n-channel type transistor having electrons as carriers.

The first transistor TR1 has, for example, a function of controlling the potential applied to the second electrode E2 and the fourth electrode E4. In addition to the first transistor TR1, the first semiconductor layer 10 and the first multilayer wiring layer 30 include a large number of transistors that control the BAA100. Further, for example, a p-channel type transistor is also included in addition to the n-channel type transistor. The first transistor TR1 may be a p-channel type transistor.

The second transistor TR2 has a second gate electrode 42 and a pair of n ⁺ type second source / drain regions 22. A second gate insulating film (not shown) is provided between the second gate electrode 42 and the second semiconductor layer 20. The second transistor TR2 is an n-channel type transistor whose carrier is an electron.

The second transistor TR2 has, for example, a function of controlling the potential applied to the sixth electrode E6 and the eighth electrode E8. In addition to the second transistor TR2, the second semiconductor layer 20 and the second multilayer wiring layer 40 include a large number of transistors that control the BAA100. Further, for example, a p-channel type transistor is also included in addition to the n-channel type transistor. The second transistor TR2 may be a p-channel type transistor.

Next, an example of the method for manufacturing the semiconductor device of the first embodiment will be described. 3, FIG. 4, FIG. 5, FIG. 6, FIG. 7, and FIG. 8 are schematic cross-sectional views during manufacturing of the semiconductor device of the first embodiment.

First, a plurality of first semiconductor chips SC1 are formed on the first wafer (FIG. 3). The first semiconductor chip SC1 has a first semiconductor layer 10 and a first multilayer wiring layer 30.

Next, a plurality of second semiconductor chips SC2 are formed on the second wafer (FIG. 4). The second semiconductor chip SC2 has a second semiconductor layer 20 and a second multilayer wiring layer 40.

Next, the first wafer and the second wafer are bonded by a known wafer bonding process so that the first multilayer wiring layer 30 and the second multilayer wiring layer 40 are in contact with each other. Next, the second semiconductor layer 20 is thinned by grinding (FIG. 5).

Next, holes 101x are formed in the second semiconductor layer 20 and the second multilayer wiring layer 40 by using a lithography method and a reactive ion etching method (FIG. 6).

Next, the support substrate 52 is attached to the second semiconductor layer 20 using the adhesive layer 50. The support substrate 52 is, for example, quartz glass. Next, the first semiconductor layer 10 is thinned by grinding.

Next, using a lithography method and a reactive ion etching method, the first through hole 101a and the second through hole 101b are used so as to reach the hole 101x in the first semiconductor layer 10 and the first multilayer wiring layer 30. (Fig. 7).

Next, the first interlayer insulating layer 35 and the second interlayer insulating layer 35 and the second conductive layer 41 are exposed on the side surfaces of the first through hole 101a and the second through hole 101b so that the first conductive layer 31 and the second conductive layer 41 are exposed on the side surfaces of the first through hole 101a and the second through hole 101b. The interlayer insulating layer 45 is etched (FIG. 8). Etching is performed by, for example, wet etching.

Next, the support substrate 52 is peeled off. Next, the bonded first wafer and the second wafer are separated into pieces by dicing, and the BAA100 in which the first semiconductor chip SC1 and the second semiconductor chip SC2 are bonded is manufactured.

Hereinafter, the operation and effect of the semiconductor device of the first embodiment will be described.

FIG. 9 is an explanatory diagram of the operation of the semiconductor device of the first embodiment. FIG. 9 is an explanatory diagram of deflection control of the electron beam of BAA100.

Focus on the electron beam EB1 passing through the first through hole 101a. The first electrode E1 and the third electrode E3 are electrically connected to the first semiconductor layer 10 and the second semiconductor layer 20 having a ground potential. Therefore, the first electrode E1 and the third electrode E3 have a ground potential.

The second electrode E2 facing the first electrode E1 and the fourth electrode E4 facing the third electrode E3 are electrically connected. The second electrode E2 and the fourth electrode E4 have a predetermined positive potential under the control of, for example, the first transistor TR1.

In this case, an electric field in the direction indicated by the white arrow is generated in the first through hole 101a. The electron beam EB1 is deflected by the electric field generated in the first through hole 101a.

Next, attention is paid to the electron beam EB2 passing through the second through hole 101b. The fifth electrode E5 and the seventh electrode E7 are electrically connected to the first semiconductor layer 10 and the second semiconductor layer 20 at the ground potential. Therefore, the fifth electrode E5 and the seventh electrode E7 have a ground potential.

The sixth electrode E6 facing the fifth electrode E5 and the eighth electrode E8 facing the seventh electrode E7 are electrically connected. The sixth electrode E6 and the eighth electrode E8 have a ground potential under the control of, for example, the second transistor TR2.

In this case, no electric field is generated in the second through hole 101b. Therefore, the electron beam EB2 travels straight without being deflected.

Generally, when the arrangement pitch of the through holes is shortened, the deflection accuracy of the electron beam is lowered due to the influence of the electric field generated by the electrodes of the through holes adjacent to each other. Therefore, it is desired to reduce the influence of the electric field generated by the electrodes of the adjacent through holes.

In the BAA100 of the first embodiment, the first electrode E1, the second electrode E2, the third electrode E3, the fourth electrode E4, the fifth electrode E5, the sixth electrode E6, and the seventh electrode E7 The eighth electrode E8 is sandwiched between the first semiconductor layer 10 and the second semiconductor layer 20 having a fixed potential. Therefore, for example, the electric field generated by the electrode of the first through hole 101a is shielded by the first semiconductor layer 10 and the second semiconductor layer 20. Therefore, the influence of the electric field generated by the electrode of the first through hole 101a on the electric field of the second through hole 101b adjacent to the first through hole 101a is reduced. Therefore, the deflection accuracy of the electron beam of BAA100 is improved.

The first conductive layer 31 and the second conductive layer 41 existing between the first through hole 101a and the second through hole 101b also have an electric field shielding effect. Therefore, the deflection accuracy of the electron beam of BAA100 is improved.

Further, in the BAA100 of the first embodiment, the potential of the electrode can be fixed to the ground potential by the semiconductor layer immediately below the electrode. Further, both the first semiconductor layer 10 and the second semiconductor layer 20 above and below the electrode make it possible to fix the potential of the electrode to the ground potential. Therefore, the ground potential of the electrode is stable, and the deflection accuracy of the electron beam of BAA100 is improved.

When the arrangement pitch of the through holes is shortened, the area of the semiconductor layer that can be used for forming the transistor is also reduced. Therefore, for example, in order to secure the area of the semiconductor layer required for forming the transistor, it is possible that the reduction of the arrangement pitch of the through holes is limited.

In the BAA 100 of the first embodiment, the transistor is formed by using the second semiconductor layer 20 in addition to the first semiconductor layer 10. For example, the area of the semiconductor layer that can be used to form a transistor is doubled as compared with BAA, which has a semiconductor layer on only one side of the electrode. Therefore, it becomes easy to reduce the arrangement pitch of the through holes.

The first electrode E1 and the second electrode E2 are preferably exposed on the side surface of the first through hole 101a. The third electrode E3 and the fourth electrode E4 are preferably exposed on the side surface of the first through hole 101a. The fifth electrode E5 and the sixth electrode E6 are preferably exposed on the side surface of the second through hole 101b. The seventh electrode E7 and the eighth electrode E8 are preferably exposed on the side surface of the second through hole 101b.

By reducing the area of the insulating layer on the side surface of the first through hole 101a and the side surface of the second through hole 101b, the charge-up of the side surface of the first through hole 101a and the side surface of the second through hole 101b is suppressed. Will be done. Therefore, the deflection accuracy of the electron beam of BAA100 is improved.

As described above, according to the semiconductor device of the first embodiment, the electric field shielding effect is improved by sandwiching the electrodes between the upper and lower two semiconductor layers. Therefore, the deflection accuracy of the electron beam is improved. Further, it becomes possible to form a transistor in two upper and lower semiconductor layers, and it becomes easy to reduce the arrangement pitch of the through holes.

(Second Embodiment)
The semiconductor device of the second embodiment is different from the first embodiment in that the first electrode and the third electrode are not electrically connected to each other. Hereinafter, some descriptions of the contents overlapping with the first embodiment will be omitted.

The semiconductor device of the second embodiment is the BAA 200 used in the multi-beam type electron beam drawing device as in the semiconductor device of the first embodiment.

FIG. 10 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the second embodiment. FIG. 10 includes a cross section of the two through holes 101.

The BAA 200 includes a first semiconductor layer 10, a second semiconductor layer 20, a first multilayer wiring layer 30, a second multilayer wiring layer 40, a first transistor TR1, and a second transistor TR2. The BAA100 includes a first electrode E1, a second electrode E2, a third electrode E3, a fourth electrode E4, a fifth electrode E5, a sixth electrode E6, a seventh electrode E7, and an eighth electrode E8. To be equipped with. The BAA100 also has a first through hole 101a (first hole) and a second through hole 101b (second hole).

The first semiconductor layer 10 has a p-type first substrate region 11, an n ⁺ -type first source / drain region 12 (first impurity region), and a p ⁺ -type first contact region 13. .. The second semiconductor layer 20 has a p-type second substrate region 21, an n ⁺ -type second source / drain region 22 (second impurity region), and a p ⁺ -type second contact region 23. ..

The first multilayer wiring layer 30 has a first conductive layer 31, a first gate electrode 32, a first contact plug 33, and a first interlayer insulating layer 35. The second multilayer wiring layer 40 has a second conductive layer 41, a second gate electrode 42, a second contact plug 43, and a second interlayer insulating layer 45.

In BAA200, the first conductive layer 31 and the second conductive layer 41 are not electrically connected.

The second electrode E2 and the fourth electrode E4 are not electrically connected. The second electrode E2 is ^{electrically connected to the n +} type first source / drain region 12. The fourth electrode E4 is ^{electrically connected to the n +} type second source / drain region 22. The potential of the second electrode E2 and the potential of the fourth electrode E4 are controlled independently.

The sixth electrode E6 and the eighth electrode E8 are not electrically connected. The sixth electrode E6 is ^{electrically connected to the n +} type first source / drain region 12. The eighth electrode E8 is ^{electrically connected to the n +} type second source / drain region 22. The potential of the sixth electrode E6 and the potential of the eighth electrode E8 are controlled independently.

As described above, according to the semiconductor device of the second embodiment, the electric field shielding effect is improved by sandwiching the electrodes between the upper and lower two semiconductor layers as in the first embodiment.

In the first and second embodiments, the case where the first semiconductor layer 10 and the second semiconductor layer 20 are single crystal silicon has been described as an example, but the first semiconductor layer 10 and the second semiconductor layer 20 have been described. May be other semiconductor material such as single crystal silicon carbide.

In the first and second embodiments, the case where the BAA of the present invention is used for a multi-beam type electron beam drawing apparatus has been described as an example, but the BAA of the present invention can be used, for example, a multi-beam type electron beam inspection apparatus. It can be used for other multi-beam type electron beam exposure apparatus.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. For example, the components of one embodiment may be replaced or modified with the components of another embodiment. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

10 First semiconductor layer 12 First source / drain region (first impurity region)
20 Second semiconductor layer 22 Second source / drain region (second impurity region)
30 First multilayer wiring layer 31 First conductive layer 32 First gate electrode 40 Second multilayer wiring layer 41 Second conductive layer 42 Second gate electrode 100 BAA (semiconductor device)
101a First through hole (first hole)
101b Second through hole (second hole)
200 BAA (semiconductor device)
E1 1st electrode E2 2nd electrode E3 3rd electrode E4 4th electrode E5 5th electrode E6 6th electrode E7 7th electrode E8 8th electrode TR1 1st transistor TR2 2nd transistor

Claims (12)

A first semiconductor layer having a first substrate region with a fixed potential,
A second semiconductor layer having a second substrate region with a fixed potential,
A plurality of first conductive layers provided between the first semiconductor layer and the second semiconductor layer and laminated in a first direction from the first semiconductor layer toward the second semiconductor layer. With a first multilayer wiring layer having
A second multilayer wiring layer provided between the first multilayer wiring layer and the second semiconductor layer and having a plurality of second conductive layers laminated in the first direction.
A first transistor having a first impurity area in the first semiconductor layer,
A second transistor having a second impurity area in said second semiconductor layer,
The first semiconductor layer, the first multilayer wiring layer, the second multilayer wiring layer, and the first hole penetrating the second semiconductor layer.
The first semiconductor layer, the first multilayer wiring layer, the second multilayer wiring layer, and the second hole penetrating the second semiconductor layer.
The first electrode provided in the first multilayer wiring layer and
A second electrode provided in the first multilayer wiring layer and facing the first electrode with the first hole in between, and a second electrode.
A semiconductor device equipped with. The first electrode has a laminated structure including the first conductive layer, and has a laminated structure.
The semiconductor device according to claim 1, wherein the second electrode has a laminated structure including the first conductive layer. The semiconductor device according to claim 1 or 2, wherein the first electrode is electrically connected to the first semiconductor layer. The semiconductor device according to any one of claims 1 to 3, wherein the second electrode is electrically connected to the first impurity region. A third electrode provided in the second multilayer wiring layer and electrically connected to the first electrode, and a third electrode.
A fourth electrode provided in the second multilayer wiring layer, electrically connected to the second electrode, and facing the third electrode with the first hole in between, and a fourth electrode.
The semiconductor device according to any one of claims 1 to 4, further comprising. The third electrode has a laminated structure including the second conductive layer, and has a laminated structure.
The semiconductor device according to claim 5, wherein the fourth electrode has a laminated structure including the second conductive layer. The semiconductor device according to claim 5 or 6, wherein the third electrode is electrically connected to the second semiconductor layer. A fifth electrode provided in the first multilayer wiring layer and
A sixth electrode provided in the first multilayer wiring layer and facing the fifth electrode with the second hole in between, and a sixth electrode.
A seventh electrode provided in the second multilayer wiring layer and electrically connected to the fifth electrode,
An eighth electrode provided in the second multilayer wiring layer, electrically connected to the sixth electrode, and facing the seventh electrode with the second hole interposed therebetween.
The semiconductor device according to any one of claims 5 to 7, further comprising. The semiconductor device according to claim 8, wherein the fifth electrode is electrically connected to the first semiconductor layer. The semiconductor device according to claim 8 or 9, wherein the eighth electrode is electrically connected to the second impurity region. The semiconductor device according to any one of claims 1 to 10, wherein the first electrode and the second electrode are exposed on the side surface of the first hole. The semiconductor device according to any one of claims 1 to 11, wherein the potentials of the first substrate region and the second substrate region are ground potentials.

Images