JP6975560B2 - Storage device - Google Patents

Description

One form of the invention disclosed in the specification, drawings, and claims of the present application (hereinafter referred to as the present specification and the like) relates to a semiconductor device, an operation method thereof, a method of use thereof, a method of manufacturing the same, and the like. It should be noted that one embodiment of the present invention is not limited to the illustrated technical field.

In the present specification and the like, the semiconductor device is a device utilizing semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip equipped with an integrated circuit, and an electronic component in which the chip is housed in a package are examples of semiconductor devices. Further, the storage device, the display device, the light emitting device, the lighting device, the electronic device, and the like are themselves semiconductor devices, and may have a semiconductor device.

In recent years, as the amount of data handled increases, a storage device having a larger capacity is required. NAND flash memory is known as a large-capacity storage device having a low bit unit price because the number of wires and electrodes per memory cell is small. NAND flash memory has reached the limit of high integration due to the arrangement of memory cells in a two-dimensional plane, and is being replaced by a technique for arranging memory cells in three dimensions (see, for example, Patent Document 1).

A transistor having a metal oxide in a channel forming region (hereinafter, may be referred to as a “metal oxide transistor”, an “oxide semiconductor transistor”, or an “OS transistor”) is known. The OS transistor can be stacked on the Si transistor. Various semiconductor devices that combine Si transistors and OS transistors have been proposed (see, for example, Non-Patent Document 1).

Japanese Unexamined Patent Publication No. 2011-96340

T. Onuki et al. , "Embedded Memory and ARM Corex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated with 65-nm CMOS,". VLSI Circuits Digi. Tech. Papers, Jun. 2016, pp. 124-125.

An object of one embodiment of the present invention is to provide a new storage device, to shorten the data reading time, to improve the performance of the semiconductor device incorporating the storage device, and the like.

One embodiment of the present invention does not need to solve all of these problems. The description of multiple issues does not prevent the existence of each other's issues. Issues other than those listed are self-evident from the description of the present specification and the like, and these issues can also be issues of one form of the present invention.

The description of multiple issues does not preclude the existence of each other's issues. One embodiment of the present invention does not have to solve all of the illustrated problems. In addition, problems other than those listed are naturally clarified from the description of the present specification and the like, and such problems can also be problems of one aspect of the present invention.

(1) One embodiment of the present invention is a storage device having a memory cell array, in which first to M (M is an integer of 2 or more) local bit lines are provided per global bit line, and the local bit line is a local bit line. The first to M circuits are electrically connected, the k (k is an integer of 1 to M) circuit has a first transistor and a buffer amplifier, and the first transistor is a k local bit line. Controlling the continuity with the global bit line, the buffer amplifier amplifies the current of the kth local bit line and outputs it to the global bit line, and the on / off of the first transistor of the first to M circuits is independent of each other. It is controlled, and the active state of the buffer amplifiers of the first to M circuits is controlled independently of each other.

(2) In the above-mentioned mode (1), the first to M circuits are stacked on the memory cell array.

(3) In the above-mentioned form (1) or (2), the buffer amplifier is a source follower circuit.

(4) In the above-mentioned embodiment (3), the source follower circuit has the second to fourth transistors, and the second to fourth transistors are connected in series between the first power supply line and the second power supply line. Electrically connected, the gate of the third transistor of the k-circuit is electrically connected to the k-local bit line, and the input of the bias voltage to the second transistor of the first to M circuits is independent of each other. The on / off of the fourth transistor of the first to M circuits is controlled independently of each other.

(5) In the above-mentioned form (4), each semiconductor layer of the first to fourth transistors has a metal oxide.

In the present specification and the like, ordinal numbers such as "first", "second", and "third" may be used to indicate an order. Alternatively, it may be used to avoid confusion of components. In these cases, the use of ordinal numbers does not limit the number of components. For example, one embodiment of the present invention can be described by substituting "first" with "second" or "third".

In the present specification and the like, when it is described that X and Y are connected, the case where X and Y are electrically connected and the case where X and Y are functionally connected. It is assumed that the case and the case where X and Y are directly connected are disclosed in the present specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or a sentence, and a connection relationship other than the connection relationship shown in the figure or the text is also described in the figure or the text. It is assumed that X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

Transistors have three terminals called gates, sources, and drains. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as sources or drains are the input and output terminals of the transistor. One of the two input / output terminals becomes a source and the other becomes a drain depending on the high and low potentials given to the conductive type (n-channel type and p-channel type) of the transistor and the three terminals of the transistor. Therefore, in the present specification and the like, the terms source and drain can be used interchangeably. Further, in the present specification and the like, two input / output terminals other than the gate may be referred to as a first terminal, a second terminal and the like.

A node can be paraphrased as a terminal, wiring, an electrode, a conductive layer, a conductor, an impurity region, or the like, depending on a circuit configuration, a device structure, or the like. In addition, terminals, wiring, etc. can be paraphrased as nodes.

The voltage often indicates the potential difference between a potential and a reference potential (eg, ground potential (GND) or source potential). Therefore, it is possible to paraphrase voltage as electric potential. The electric potential is relative. Therefore, even if it is described as GND, it may not necessarily mean 0V.

In the present specification, words and phrases indicating arrangements such as "above" and "below" may be used for convenience in order to explain the positional relationship between configurations with reference to the drawings. Further, the positional relationship between the configurations changes appropriately depending on the direction in which each configuration is depicted. Therefore, it is not limited to the words and phrases explained in the specification, and can be appropriately paraphrased according to the situation.

In the present specification and the like, the words "membrane" and "layer" can be interchanged with each other in some cases or depending on the situation. For example, it may be possible to change the term "conductive layer" to the term "conductive layer". For example, it may be possible to change the term "insulating film" to the term "insulating layer".

According to one embodiment of the present invention, it becomes possible to provide a new storage device, shorten the data reading time, and improve the performance of the semiconductor device incorporating the storage device.

The description of multiple effects does not preclude the existence of other effects. Moreover, one embodiment of the present invention does not necessarily have to have all of the illustrated effects. In addition, problems, effects, and novel features other than the above with respect to one embodiment of the present invention will be self-evident from the description and drawings of the present specification.

A: A functional block diagram showing a configuration example of a storage device. B: A circuit diagram showing a configuration example of a memory cell string. A, B: Schematic diagram showing an example of a bit line hierarchical structure of a memory cell array. A: A circuit diagram showing a configuration example of a bit line dividing circuit. B: A timing chart showing an operation example of the bit line dividing circuit. A circuit diagram schematically showing an example of a three-dimensional structure of a memory cell array. A: A circuit diagram showing a configuration example of an AND circuit. B: A circuit diagram showing a configuration example of an OR circuit. A circuit diagram showing a configuration example of a charge pump circuit. AE: Schematic diagram showing a configuration example of a removable storage device. A functional block diagram showing a configuration example of an information processing system. AD: Schematic diagram showing a configuration example of an electronic device. A, B: Cross-sectional view showing a configuration example of an OS transistor. A, B: Cross-sectional view showing a configuration example of an OS transistor. The cross-sectional view which shows the structural example of the OS transistor. The cross-sectional view which shows the structural example of the OS transistor.

Hereinafter, embodiments of the present invention will be described. However, it is easily understood by those skilled in the art that one form of the present invention is not limited to the following description, and that the form and details of the present invention can be variously changed without departing from the spirit and scope thereof. Will be done. Therefore, one embodiment of the present invention is not construed as being limited to the description of the embodiments shown below.

The plurality of embodiments shown below can be combined as appropriate. Further, when a plurality of configuration examples (including production method examples, operation method examples, usage method examples, etc.) are shown in the embodiment, each configuration example is appropriately combined, and other implementations are performed. It is also possible to appropriately combine with one or more configuration examples described in the above-mentioned form.

In the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in the signal, voltage, or current due to noise, or variations in the signal, voltage, or current due to timing deviation.

[Embodiment 1]
FIG. 1A shows a configuration example of a NAND non-volatile storage device. The storage device 100 shown in FIG. 1A has a control circuit 105, a memory cell array 120, and a peripheral circuit.

The control circuit 105 comprehensively controls the entire storage device 100, writes data, and reads data. The control circuit 105 processes a command signal from the outside to generate a control signal of a peripheral circuit. As peripheral circuits, a row decoder 111, a row driver 112, a write / read (W / R) circuit 115, a column decoder 116, a source line driver 117, an input / output circuit 118, and a local bit line selection circuit 119 are provided. These circuits can be appropriately discarded depending on the configuration of the memory cell array 120, the driving method, and the like.

The memory cell array 120 has a plurality of memory strings 130, a word line WL1-WL4, a selection gate line SGD, SGS, and a local bit line LBL. FIG. 1B shows an example of a circuit configuration of the memory string 130. The memory string 130 has selection transistors ST1 and ST2, and memory cells 11_1-11_4. Each of the memory cells 11_1-11_4 is composed of a memory transistor MT1.

There are no particular restrictions on the memory transistor MT1. The memory transistor MT1 may be an FG type memory transistor including a floating gate (FG), or an insulator trap type (typically, MONOS type) memory transistor having a charge storage layer made of an insulator.

The gates of the selection transistors ST1 and ST2 are electrically connected to the selection gate lines SGS and SGD, respectively. The gates of the memory transistors MT1 to MT4 are electrically connected to the word lines WL1 to WL4, respectively. The local bit line LBL extends in the column direction, and the word lines WL1 to WL4, the selection gate lines SGS, and SGD extend in the row direction.

When the memory cells 11_1-11_4 are not distinguished, they are described as the memory cells 11. The same applies to the signs of other elements. Further, as a code for distinguishing the elements, "a", "b" and the like may be used in addition to "_1".

The semiconductor layer of the transistor constituting the memory string 130 can be formed of a metal oxide, silicon, or the like. By using a metal oxide semiconductor, the memory string 130 can be configured with an OS transistor having good on-current characteristics.

Since the bandgap of the metal oxide is 2.5 eV or more, the OS transistor has a minimum off current. As an example, when the voltage between the source and drain is 3.5 V and the room temperature (25 ° C) is normal, the off current per 1 μm of channel width is less ^{than 1 × 10 -20} A, 1 × 10 ^-22 A, or 1 × 10. It can be less than ^-24A. That is, the on / off current ratio of the drain current can be set to 20 digits or more and 150 digits or less.

The energy gap of the metal oxide is as large as 2.5 eV or more or 3.0 eV or more. Since metal oxides are less likely to excite electrons and have a large effective mass of holes, OS transistors may be less likely to undergo avalanche breakdown than general Si transistors. As a result, for example, hot carrier deterioration caused by avalanche breakdown may be suppressed. By suppressing hot carrier deterioration, it is possible to drive an OS transistor with a high drain voltage.

For example, by forming the semiconductor layer of the memory string 130 with a metal oxide, it is possible to apply a high voltage to the floating node of the memory transistor MT1, so that the memory transistor MT1 can maintain more states. It is possible.

The metal oxides applied to the semiconductor layer are Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide, and In-M-Zn oxide (M is: Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf) and the like. In addition, oxides containing indium and zinc include aluminum, gallium, ittrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. , Or one selected from magnesium and the like, or a plurality of species may be contained.

In order to improve the reliability and electrical characteristics of the OS transistor, the metal oxide applied to the semiconductor layer is preferably a metal oxide having a crystal portion such as CAAC-OS or nc-OS. CAAC-OS is an abbreviation for c-axis-aligned crystalline metallic oxide semiconductor. nc-OS is an abbreviation for nanocrystalline metal oxide semiconductor ductor.

CAAC-OS has a c-axis orientation and has a distorted crystal structure in which a plurality of nanocrystals are connected in the ab plane direction. The strain refers to a region where the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another lattice arrangement is aligned in the region where a plurality of nanocrystals are connected.

Although nanocrystals are basically hexagonal, they are not limited to regular hexagonal shapes and may have non-regular hexagonal shapes. In addition, in distortion, it may have a lattice arrangement such as a pentagon and a heptagon. In CAAC-OS, a clear grain boundary (also referred to as grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and that the bond distance between atoms changes due to the substitution of metal elements. It is thought that this is the reason.

CAAC-OS has a layered crystal structure in which a layer having indium and oxygen (hereinafter, In layer) and a layer having elements M, zinc, and oxygen (hereinafter, (M, Zn) layer) are laminated. It tends to have a layered structure). Indium and the element M can be replaced with each other, and when the element M of the (M, Zn) layer is replaced with indium, it can be expressed as a (In, M, Zn) layer. Further, when the indium of the In layer is replaced with the element M, it can also be expressed as a (In, M) layer.

The nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, nc-OS may be indistinguishable from an amorphous metal oxide semiconductor depending on the analysis method.

The memory string 130 provided in the memory cell array 120 is not particularly limited, and a memory string having a circuit configuration other than that shown in FIG. 1B may be provided in the memory cell array 120.

The row decoder 111 decodes the address data input from the outside and determines the row to be accessed. The row driver 112 inputs the voltage required for writing, reading, and erasing data to the selection gate lines SGS, SGD, SGL, and word line WL according to the decoding result of the row decoder 111.

The source line driver 117 drives the source line SL.

The column decoder 116 decodes the address data input from the outside and determines the column to be accessed. The W / R circuit 115 adjusts the write voltage to be accessed, detects the voltage read from the memory cell array 120, and the like. For example, the W / R circuit 115 includes a sense amplifier for detecting the voltage of the global bit line.

The input / output circuit 118 temporarily holds the write data input from the outside, temporarily holds the data read from the memory cell array 120, and the like.

As the bit line structure of the storage device 100, a hierarchical bit line structure layered by a local bit line and a global bit line is adopted. The hierarchical bit line structure of the storage device 100 will be described with reference to FIGS. 2A and 2B.

(Comparative example)
For comparison, FIG. 2B shows a schematic perspective view of a memory cell array in which bit lines are not layered. A bit line BL is provided in each column of the NAND cell array 191. A plurality of memory strings are electrically connected to the bit line BL. The bit line BL is electrically connected to the W / R circuit 192.

In NAND flash memory, in order to reduce the bit unit price, memory cells are three-dimensionally stacked to reduce the chip area and increase the density of memory cells. However, the three-dimensional structure of the NAND cell array has the disadvantage that it takes time to read. The current drive of the memory transistor of the memory string is lower than that of the planar transistor. At the time of reading, the current of the selected memory transistor passes through the plurality of memory transistors. Therefore, it takes time for the voltage of the bit line BL to reach a value capable of data determination (for example, 0/1 determination).

(Bit line hierarchy)
Therefore, in the present embodiment, in order to improve the read speed, the bit line BL is divided into a plurality of local bit line LBLs, and a circuit for selecting and driving the local bit line LBL is laminated on the NAND cell array. FIG. 2A shows a schematic perspective view of the memory cell array 120. FIG. 2A shows an example in which one bit line BL is divided into two local bit lines LBLa and LBLb.

The memory cell array 120 has a hierarchical structure and is roughly classified into a NAND cell array 122, a circuit section 124, and a global bit line section 126.

A plurality of memory strings 130 are arranged in the NAND array 122. Local bit lines LBLa, LBLb, word lines WL1-WL4, source line SL, selection gate lines SGS, and SGD are provided according to the arrangement of the memory string 130. The global bit line unit 126 is provided with a global bit line GBL. The global bit line GBP is electrically connected to the W / R circuit 115.

The W / R circuit 115 inputs a write voltage to the global line GBL, amplifies the voltage of the global bit line GBL, performs data determination, temporarily stores data to be written to the NAND cell array 122, and reads data from the NAND cell array 122. Temporarily store the data. Further, when the memory cell 11 is a multi-valued memory cell, the W / R circuit 115 decodes the write data and generates the write voltage, encodes the voltage of the global bit line GBL, and generates the read data. It has a function.

The circuit unit 124 is provided with one bit line dividing circuit 140 per global bit line GBL. The bit line dividing circuit 140 selects a local bit line LBL that is conductive on the global bit line GBL.

<< Bit line division circuit >>
The bit line dividing circuit 140 will be described with reference to FIGS. 3A and 3B. FIG. 3A is a circuit diagram showing a configuration example of the bit line dividing circuit 140, and FIG. 3B is a timing chart showing an operation example of the bit line dividing circuit 140.

The bit line dividing circuit 140 has two circuits 141. The circuit 141 is a unit circuit of the bit line dividing circuit 140. Circuit 141 has four transistors M10-M13.

Here, when distinguishing between the two circuits 141, the one electrically connected to the local bit line LBLA is referred to as a circuit 141a, and the other is referred to as a circuit 141b. Further, in order to distinguish the elements of the circuits 141a and 141b, "a" and "b" may be added to the reference numerals.

Transistors M10-M13 are OS transistors having a back gate. A voltage Vbg is input to each of the back gates of the transistors M10 to M13. By changing the voltage Vbg, the threshold voltage of the transistors M10-M13 can be changed. The back gate of the transistor M10 may be electrically connected to the gate, source, or drain. The same applies to the transistors M11-M13.

The OS transistor is a storage type transistor having a large number of electrons as carriers. Therefore, the influence of DIBL (Drain-Induced Barrier Lowering), which is one of the short-channel effects, is smaller than that of an inverting transistor (typically, a Si transistor) having a pn junction. That is, the OS Langista has higher resistance to the short channel effect than the Si transistor.

Since the OS transistor has high resistance to the short channel effect, it is possible to make the gate insulating thicker than the transistor such as Si silicon. For example, even in a fine transistor having a channel length and a channel width of 50 nm or less, a thick gate insulator of about 10 nm can be provided. By thickening the gate insulating material, the parasitic capacitance can be reduced, so that the operating speed of the circuit can be improved. Further, by making the gate insulating material thicker, the leakage current is reduced, which leads to a reduction in static current consumption.

As the channel length becomes finer, the drain electric field becomes stronger, but as mentioned above, the OS transistor is less likely to undergo avalanche breakdown than the Si transistor.

That is, by increasing the thickness of the gate insulating material, the withstand voltage of the gate insulating material can be increased, and the OS transistor can be driven with a higher gate voltage. By suppressing hot carrier deterioration, it becomes possible to drive an OS transistor with a high drain voltage without lengthening the channel length. Therefore, the reliability of the circuit can be improved by configuring the circuit to which the high voltage is input with the OS transistor. By reducing the channel length without degrading the reliability of the OS transistor, the degree of integration of the circuit can be increased.

Therefore, by configuring the bit line dividing circuit 140 with an OS transistor, it is possible to stack a plurality of bit line dividing circuits 140 on the NAND cell array 122 without an area penalty.

The transistor M10 functions as a transfer transistor. The transistor M10 of the circuit 141a is electrically connected to the gate write control line GWEa, and the transistor M10 controls the conduction between the local bit line LBLA and the global bit line GBL.

The gate of the transistor M10 of the circuit 141b is electrically connected to the write control line GWEb, and the transistor M10 controls the conduction between the local bit line LBLb and the global bit line GBL.

In the circuit 141a, the transistors M11-M13 are connected in series between a power supply line for supplying a ground potential (hereinafter referred to as a ground line) and a power supply line for supplying a voltage VHM (hereinafter, may be referred to as a VHM line). Is electrically connected to. The transistor M11-M13 constitutes the source follower circuit 142a. The gates of the transistors M11 to M13 are electrically connected to the bias control line RBIa, the local bit line LBLa, and the read control line GREA, respectively. The source of the transistor M12 is electrically connected to the global bit line GBL. The transistor M11 constitutes a current source for the source follower circuit 142a. The transistor M13 controls the activation of the source follower circuit 142a.

The transistors M11-M13 of the circuit 141b also constitute the source follower circuit 142b. The source follower circuit 142b is electrically connected to the bias control line RBIa, the local bit line LBLa, and the read control line GREA.

The source follower circuit 142a functions as a buffer amplifier that amplifies the current flowing through the local bit line LBLA. Therefore, during the read operation, the current flowing through the memory cell 11 electrically connected to the local bit line LBLA can be amplified by the source follower circuit 142a and input to the global bit line GBL. The source follower circuit 142b also functions in the same manner as the source follower circuit 142a.

The write control lines GWEa and GWEb, the read control lines GREA and GREb, and the bias control lines RBIa and RBIb are driven by the local bit line selection circuit 119.

An operation example of the bit line dividing circuit 140 will be described with reference to FIG. 3B when the memory cell 11 electrically connected to the local bit line LBLA is the access target.

In the writing operation, the writing control line GWEa is set to "H", and the other control lines GWEb, GREa, GReb, RBIa, and RBIb are maintained at "L". The transistor M10 of the circuit 141b is off, and the source follower circuits 142a and 142b are inactive. Since the transistor M10 of the circuit 141a is turned on and the global bit line GBL and the local bit line LBLA are conducted, the voltage of the global bit line GBL is input to the local bit line LBLA.

In the read operation, the read control line GREA is set to “H”, and the bias voltage Vb is input to the bias control line RBIa. “L” is maintained for the other control lines GWEa, GWEb, GREb, and RBIb. Each transistor M10 of the circuits 141a and 141b is off, and the source follower circuit 142b is in an inactive state.

In the source follower circuit 142a, the bias voltage Vb is input to the gate of the transistor M11, and the transistor M13 is turned on. Therefore, the source follower circuit 142a is activated and drives the global bit line GBP. Since the drain current corresponding to the voltage of the local bit line LBLA flows through the transistor M12, the voltage of the global bit line GBL changes.

That is, the data transmission from the memory cell 11 to the global bit line GBL is performed by the source follower circuit 142a, which has a higher current drive capability than the memory cell 11. As a result, the time required for the voltage of the global bit line GBL to reach the voltage at which the data can be determined is shortened, so that the time required for reading the data can be reduced.

The bit line dividing circuit 140 supports data reading when the memory cell 11 is a multi-valued memory cell. Since the current flowing through the source follower circuit 142a changes according to the voltage of the local bit line LBLa, the source follower circuit 142a inputs the current corresponding to the voltage level held by the memory cell 11 to the global bit line GBL. Can be done.

As mentioned above, NAND flash memory has a low bit unit price, but its operating speed is low. Therefore, the NAND flash memory is located at a lower level of the storage hierarchy and is mainly used as storage. The operating speed of the NAND flash memory is 1/1000 (10 ^-3 ) of the DRAM used as the main memory. Therefore, in a computing system, access to NAND flash memory results in a significant degradation in processor performance. According to this embodiment, the operating speed of the NAND flash memory can be improved, so that the deterioration of the processor performance can be reduced.

As an example of the bit line hierarchy structure, an example in which two local bit lines are provided for each global bit line has been described, but the number of local bit lines of the global bit line may be 2 or more. Another example of the bit line hierarchical structure will be described with reference to FIG. FIG. 4 is a diagram schematically showing an example of a three-dimensional structure of a memory cell array in a circuit diagram.

The memory cell array 150 shown in FIG. 4 is provided with four local bit lines per global bit line. Similar to the memory cell array 120, the components of the memory cell array 150 are roughly classified into a NAND cell array 152, a circuit section 154, and a global bit line section 156.

In the NAND cell array 152, four local bit lines LBLa-LBLd are provided for each row. A plurality of memory strings 130 are electrically connected to the local bit lines LBLa-LBLd. The global bit line unit 156 is provided with a global bit line GBL.

The circuit unit 154 is provided with a bit line dividing circuit 145 for each global bit line GBL. The bit line dividing circuit 145 has circuits 141a-141d, and is electrically connected to a write control line GWEa-GWed, a read control line GREA-GRed, and a bias control line RBIa-RBId.

The operation of the bit line dividing circuit 145 is the same as that of the bit line dividing circuit 140. During the write operation, any one of the local bit lines LBLa-LBLd is selected by the bit line dividing circuit 145, and the selected local bit line LBL is electrically connected to the global bit line GBL. During the read operation, the source follower circuit electrically connected to the local bit line LBL to be read is activated.

As the number of bit line divisions increases, the number of bit line division circuits increases. Therefore, it is preferable to determine the number of bit line divisions so that an area penalty does not occur.

<< OS Transistor Circuit >>
A part of the peripheral circuit of the storage device 100 can be configured by a circuit composed of an OS transistor.

It is difficult to control the conductive type of a metal oxide semiconductor by doping like silicon. For example, a metal oxide containing indium (for example, indium oxide) or a metal oxide containing zinc (for example, zinc oxide) can produce an n-type semiconductor, but cannot produce a p-type semiconductor. At present, a p-channel type OS transistor having characteristics at a practical level has not been manufactured.

First, as an example of an OS transistor circuit, a dynamic logic circuit composed of only n-channel transistors will be described.

(AND circuit)
FIG. 5A shows an example of a 4-input AND circuit. In the AND circuit 170 shown in FIG. 5A, the transistors M51 and M40 are located between the power supply line for voltage VDD1 (hereinafter referred to as VDD1 line) and the power supply tight wire for voltage VSS (hereinafter referred to as VSS line). -M42 and M52 are electrically connected in series. The gates of the transistors M40-M43 are electrically connected to the nodes A0-A3, respectively. The gates of the transistors M51 and M52 are electrically connected to the nodes PRE and PREB. Here, the connection node between the transistor M43 and the transistor M52 is referred to as a node Y.

A transistor M51, capacitive elements C53, and C51 are electrically connected in series between a power supply line for voltage VDD2 (hereinafter referred to as a VDD2 line) and a VSS line. The voltage VDD2 is a voltage higher than the voltage VDD1. The connection node between the capacitive element C53 and the capacitive element C51 is electrically connected to the node Y, and the connection node between the transistor M53 and the capacitive element C53 is electrically connected to the node OUT. The back gate of the transistor M53 is electrically connected to the node BSG. The bootstrap circuit 175 is composed of the transistor M53 and the capacitive element C53.

In the precharge period, the nodes PRE and PREB are set to "H" and "L". In the evaluation period, the nodes PRE and PREB are set to "L" and "H". In the evaluation period, the logical product of the nodes A0 to A3 is calculated, and the data corresponding to the calculation result is output from the node OUT.

By configuring the AND circuit 170 with an OS transistor having a minimum off current, it is possible to prevent the electric charge from leaking from the capacitive element C51, so that there is no restriction on the drive frequency of the AND circuit 170. The bootstrap circuit 175 may be provided as appropriate. The threshold voltage of the OS transistor may be higher than that of the Si transistor. By boosting the node Y by the bootstrap circuit 175, the influence of the threshold voltage of the transistors M40-M43 on the output signal of the node OUT can be reduced.

Since the threshold voltage of the transistor M53 can be changed by the voltage of the node BSG, the amplitude of the output signal of the node OUT can be changed. Therefore, the voltage of the node BSG may be set according to the circuit electrically connected to the node OUT.

(OR circuit)
FIG. 5B shows an example of a 4-input OR circuit. In the OR circuit 171 the transistors M45 to M48 are electrically connected in parallel between the source of the transistor M51 and the node Y. Nodes A0-A3 are electrically connected to the gates of the transistors M45-M48, respectively. In the precharge period, the nodes PRE and PREB are set to "H" and "L". In the evaluation period, the nodes PRE and PREB are set to "L" and "H". In the evaluation period, the logical sum of the nodes A0 to A3 is calculated, and the data corresponding to the calculation result is output from the node OUT.

The OS transistor circuit can be stacked on a peripheral circuit composed of Si transistors, and can be provided in the circuit unit 124 together with the bit line dividing circuit 140. For example, the OS transistor circuit can be laminated in the region where the routing wiring is formed in order to make the NAND transistor 122 and the peripheral circuit conductive.

In the transistor M51, the back gate may be electrically connected to the source or drain, or a voltage may be input to the back gate from the outside as in the transistor M53. Alternatively, the transistor M51 may be configured by an OS transistor having no back gate. The same applies to the transistors constituting the AND circuit 170 and the OR circuit 171.

An analog circuit can be configured by an OS transistor. As an example, an example of a charge pump circuit is shown in FIG.

The charge pump circuit 173 shown in FIG. 6 has four OS transistors, four capacitive elements, and two inverter circuits. The inverter circuit is composed of Si transistors. When the clock signal is active, the charge pump circuit 173 steps down the ground voltage to generate a negative voltage Vcp. For example, the negative voltage Vcp is input to the back gate of the transistors M10-M13 of the bit line dividing circuit 140. The step-up charge pump circuit may be configured by the OS transistor.

As described above, the storage device according to the present embodiment is provided with a bit line dividing circuit, and the reading time can be shortened by layering the bit lines. Further, by stacking the bit line dividing circuit on the NAND cell array, it becomes possible to layer the bit lines without an area penalty.

The storage device to which the bit line dividing circuit of the present embodiment can be applied is not limited to the NAND flash memory, and can be applied to various storage devices.

[Embodiment 2]
In the present embodiment, the electronic components, electronic devices, and the like having the above-mentioned storage device will be described.

The above-mentioned storage device can be applied to, for example, a storage device of various electronic devices (for example, an information terminal, a smartphone, an electronic book terminal, a digital camera (including a video camera), a recording / playback device, a navigation system, etc.). Alternatively, the storage device 100 is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive). 7A-7D show some configuration examples of removable storage devices.

FIG. 7A is a schematic diagram of the USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. The substrate 1104 is provided with a circuit constituting the storage device 100. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. A storage device 100 is incorporated in the memory chip 1105. A processor, a work memory, an ECC (error detection and correction) circuit, and the like are incorporated in the controller chip 1106.

FIG. 7B is a schematic diagram of the appearance of the SD card, and FIG. 7C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The board 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The above-mentioned storage device is incorporated in the memory chip 1114. A processor, a work memory, an ECC circuit, and the like are incorporated in the controller chip 1115.

By providing the memory chip 1114 on the back surface side of the substrate 1113, the capacity of the SD card 1110 can be increased. Further, a wireless chip having a wireless communication function may be provided on the substrate 1113. As a result, the data of the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110.

FIG. 7D is a schematic diagram of the appearance of the SSD, and FIG. 7E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152 and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. A storage device 100 is incorporated in the memory chip 1154. By providing the memory chip 1155 on the back surface side of the substrate 1153, the capacity of the SSD 1150 can be increased. A work memory is built in the memory chip 1155. For example, a DRAM chip may be used for the memory chip 1155. A processor, an ECC circuit, and the like are incorporated in the controller chip 1156. The controller chip 1156 may also be provided with a storage device that functions as a work memory.

For example, the SSD 1150 is applied to storage devices of various computing systems (personal computers, workstations, servers, supercomputers, etc.).

Next, with reference to FIG. 8, an information processing system in which the storage device 100 is incorporated will be described. The information processing system 1500 shown in FIG. 8 includes a host device 1510, a storage device 1520, an output device 1531, and an input device 1532.

As the storage device 1520, the storage device 100 can be applied. The storage device 1520 is used, for example, as a storage device for the host device 1510, and stores various data (for example, programs, video data, acoustic data, etc.).

The host device 1510 has a function of controlling the entire information processing system 1500. The host device 1510 includes a processor 1511, a memory unit 1512, an I / F (interface) 1513, and a bus 1514. The processor 1511, the memory unit 1512, and the I / F 1513 are interconnected by the bus 1514. The processor 1511 functions as an arithmetic unit and a control unit, and controls various devices in the information processing system 1500 according to a program such as firmware. As the processor 1511, a CPU, a microprocessor (MPU), an FPGA, a GPU, or the like can be used. The memory unit 1512 includes a storage device (for example, DRAM) that functions as a main memory. The memory unit 1512 stores a program executed by the processor 1511, data processed by the processor 1511, and the like. The memory unit 1512 may have a storage device 100. Further, the processor 1511 may have a storage device 100.

The host device 1510 communicates with the output device 1531, the input device 1532, and the storage device 1520 via the I / F 1513. For example, the input signal from the input device 1532 is transmitted to the processor 1511 via the I / F 1513 and the bus 1514.

A plurality of output devices 1531 can be provided in the information processing system 1500. The output device 1531 includes a display device, a speaker, a vibration device, a light emitting device (for example, an LED lamp) and the like. A plurality of input devices 1532 can be provided in the information processing system 1500. The input device 1532 includes a touch sensor, a keyboard, a mouse, an operation button, a microphone (voice input device), a camera (imaging device), and various sensors (illumination sensor, color temperature sensor, infrared sensor, ultraviolet sensor, acceleration sensor, temperature). Sensors, pressure sensors, etc.).

The information processing system 1500 may have a mode in which the storage device 1520 and the host device 1510 are housed in one housing, or may be a mode in which a plurality of devices connected by wire or wirelessly are configured. .. For example, as the former aspect, there are a notebook PC (personal computer), a tablet-type information terminal, an electronic book terminal, a smartphone, a mobile phone, an audio terminal, a recording / playback device, and the like. The latter form includes a set of desktop PC, keyboard, mouse and monitor. Further, there are an AV (acoustic video) system including a recording / playback device, an audio device (speaker, an amplifier, etc.), and a television device, a surveillance system including a surveillance camera, a display device, and a storage device for recording.

9A-9D schematically show an electronic device including an information processing system 1500 or a storage device 100.

FIG. 9A shows a configuration example of a tablet-type information terminal. The information terminal 2010 shown in FIG. 9A has a housing 2011, a display unit 2012, an illuminance sensor 2013, a camera 2015, and an operation button 2016. A storage device 100, a processor, and the like are incorporated in the housing 2011.

The display unit 2012 is composed of a display system incorporating a touch sensor. The information terminal 2010 can be operated by touching the display unit 2012 with a stylus pen 2017 (or an electronic pen), a finger, or the like. Functions of the information terminal 2010 include voice calls, video calls using the camera 2015, e-mail, notebooks, Internet connections, music playback, and the like.

FIG. 9B shows a configuration example of a PC (personal computer). The PC 2030 shown in FIG. 9B has a housing 2031, a display unit 2032, an illuminance sensor 2034, a camera 2035, and a keyboard 2036. The keyboard 2036 may be configured to be removable from the housing 2031. When the keyboard 2036 is attached to the housing 2031, the PC 2030 can be used as a node-type PC. With the keyboard 2036 attached / detached from the housing 2031, the PC 2030 can be used as a tablet PC.

A controller for the display unit 2032, a storage device 100, a processor, and the like are incorporated in the housing 2031.

The robot 2100 shown in FIG. 9C includes an illuminance sensor 2101, a microphone 2102, an upper camera 2103, a speaker 2104, a display unit 2105, a lower camera 2106, an obstacle sensor 2107, a moving mechanism 2108, a processor 2110, and a storage device 2111. The storage device 100 can be adapted to the storage device 2111.

The display unit 2105 displays various information. The display unit 2105 may be equipped with a touch panel. Using the microphone 2102 and the speaker 2104, the user can communicate with the robot 2100 by voice. The upper camera 2103 and the lower camera 2106 image the surroundings of the robot 2100. For example, the voice emitted from the speaker 2104 by the robot 2100 is selected based on the user information taken by the upper camera 2103.

The robot 2100 can be moved by the moving mechanism 2108. The obstacle sensor 2107 can detect the presence or absence of an obstacle in the moving direction of the robot 2100. The robot 2100 recognizes the surrounding environment by using the upper camera 2103, the lower camera 2106, and the obstacle sensor 2107, and can move safely and independently.

The flying object 2120 shown in FIG. 9D has a processor 2121, a storage device 2122, a camera 2123, and a propeller 2124. The storage device 100 can be applied to the storage device 2122.

The automobile 2140 shown in FIG. 9D is equipped with various sensors such as an infrared radar, a near infrared radar, a millimeter wave radar, and a laser radar. The automobile 2140 can analyze the image taken by the camera 2141 and the data acquired by the sensor, determine the surrounding conditions such as the presence or absence of the guardrail 2150 and pedestrians, and perform automatic driving. Various electronic components such as the above-mentioned storage device are incorporated in the automobile 2140.

[Embodiment 3]
In this embodiment, the OS transistor will be described with reference to FIGS. 10A-13. The OS transistor according to this embodiment can be used in the above-mentioned storage device.

FIG. 10A is a top view showing a configuration example of the OS transistor 400. In the top view of FIG. 10A, some elements are omitted for the sake of clarity of the figure. FIG. 10B is a cross-sectional view taken along the line X1-X2 of FIG. 10A, and is a cross-sectional view taken along the channel length of the OS transistor. FIG. 11A is a cross-sectional view taken along the line Y3-Y4 of FIG. 10A, and is a cross-sectional view taken along the channel width direction of the OS transistor. FIG. 11B is a cross-sectional view taken along the line Y5-Y6 of FIG. 10A. FIG. 12 is a partially enlarged view of FIG. 10B.

The OS transistor 400 is formed on the insulator layer 410. The OS transistor 400 is covered with an insulator layer 418, an insulator layer 419, and an insulator layer 420. The element indicated by 411-416, 422, 425-427 is an insulator.

Although the insulator layer 410 is shown as a single-layer structure in FIG. 10B and the like, it may have a multi-layer structure composed of a plurality of layers. This also applies to other factors.

A semiconductor layer 440 of the OS transistor 400 is provided on the insulator layer 416. The semiconductor layer 440 is composed of a metal oxide layer 441-443. The metal oxide layer 441-443 is composed of the above-mentioned In-M-Zn oxide and the like. The semiconductor layer 440 is provided with layers 447A and 447B. The configuration of the semiconductor layer 440 will be described later.

The gate of the OS transistor 400 is composed of the conductor layer 460, and the back gate is composed of the conductor layer 461. The conductor layer 460 overlaps with the semiconductor layer 440 via the insulator layer 422 and the metal oxide layer 444. The conductor layer 461 overlaps with the semiconductor layer 440 via the insulator layer 414-415. Conductor layers 462A and 462B are provided in contact with the layers 447A and 447B. The conductor layer 463 is provided in contact with the conductor layer 461. The conductor layers 462A and 462B function as plugs, and the conductor layer 463 functions as wiring.

The conductor layer 460 has a conductor layer 469 and a conductor layer 470. The conductor layer 463 has conductor layers 471 and 472. The conductor layers 462A and 462B have conductor layers 473 and 474, respectively. The conductor layer 463 has a conductor layer 475 and 476.

The gate insulating layer on the bottom gate side is composed of an insulator layer 414, 415, 416. The gate insulating layer on the front gate side is composed of an insulator layer 422.

An insulator layer 425 is provided in contact with the upper surface of the conductor layer 460, and an insulator layer 426 is provided on the insulator layer 425. An insulator layer 427 is provided in contact with the side surface of the conductor layer 460.

The conductive layer 471,473,475, impurities (e.g., hydrogen atom, hydrogen molecules, water molecules, nitrogen atom, a nitrogen molecule, nitric oxide molecule _(N 2 O, NO, etc. NO _2), copper atoms) diffusion of It is preferable to use a conductive material having a function of suppressing the above. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, oxygen atom, oxygen molecule, etc.). In the present specification, the function of suppressing the diffusion of impurities or oxygen is a function of suppressing the diffusion of any one or all of the above impurities or the above oxygen. For example, examples of the conductive material having a function of suppressing the diffusion of impurities or oxygen include tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like.

The conductor layer 472 is preferably a conductive material having a resistivity lower than that of the conductor layer 471, for example, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. The same applies to the conductor layers 474 and 476.

In the conductor layer 461, since the conductor layer 471 has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor layer 472 from being oxidized and the conductivity from being lowered. The same applies to the conductor layers 462A, 462B, and 463.

It is preferable to use copper for the conductor constituting the wiring such as the conductor layer 476. On the other hand, since copper is easily diffused, it may diffuse into the semiconductor layer 440 to deteriorate the electrical characteristics of the OS transistor 400. Therefore, when copper is used for the conductor layer 476, it is preferable to use a material such as aluminum oxide or hafnium oxide having low copper permeability for the insulator layer 412 to suppress the diffusion of copper.

As for the conductor layer 469, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities or oxygen, similarly to the conductor layer 471. For the conductor layer 470, a conductive material having a resistivity lower than that of the conductor layer 469 is used. For example, as the conductor layer 470, a conductive material containing titanium, tungsten, copper, or aluminum as a main component can be used.

The conductor layer 461 is arranged so as to overlap the semiconductor layer 440 and the conductor layer 460. In the channel width direction, the conductor layer 461 preferably has an end extending outward from the end of the metal oxide layer 442 (see FIG. 11A). With such a configuration, the channel forming region of the OS transistor 400 can be electrically surrounded by the electric field of the gate (conductor layer 460) and the electric field of the back gate (conductor layer 461). Therefore, the on-current of the OS transistor 400 can be increased.

The conductor layer 461, the insulator layer 412, and the insulator layer 413 may not be provided. In that case, a part of the conductor layer 463 may function as a back gate.

For the insulator layer 425, it is preferable to use an insulating material having a function of suppressing the permeation of impurities or oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. As a result, it is possible to suppress the oxidation of the conductor layer 460. Further, it is possible to prevent impurities such as water or hydrogen from above the insulator layer 425 from being mixed into the semiconductor layer 440 via the conductor layer 460 and the insulator layer 422.

The insulator layer 426 preferably functions as a hard mask. By providing the insulator layer 426, when the conductor layer 460 is processed, the side surface of the conductor layer 460 is substantially vertical, specifically, the angle formed by the side surface of the conductor layer 460 and the surface of the substrate is 75 degrees or more. It can be 100 degrees or less, preferably 80 degrees or more and 95 degrees or less. By processing the conductor layer 460 into such a shape, the insulator layer 427 to be formed next can be formed into a desired shape.

By using an insulating material having a function of suppressing the permeation of impurities such as water or hydrogen and oxygen in the insulator layer 426, the function of the barrier layer may also be used. In that case, the insulator layer 425 may not be provided.

The insulator layers 410 and 412 preferably function as a barrier layer against the above impurities. This preferably suppresses impurities from being mixed into the OS transistor 400 from the substrate side. For example, it is preferable to use aluminum oxide or the like as the insulator layer 410 and silicon nitride or the like as the insulator layer 412. Further, an insulator that functions as a barrier layer may be provided on the insulator layer 420. As a result, it is possible to prevent impurities from being mixed into the OS transistor 400 from above the insulator layer 420.

As a result, it is possible to suppress the diffusion of impurities such as hydrogen and water from the insulator layer 410 side to the OS transistor 400. Alternatively, it is possible to prevent oxygen contained in the insulator layer 416 or the like from diffusing toward the insulating layer 410 side of the insulator layer 410 and the insulator layer 412.

Since the insulator layers 411, 413, and 420 function as interlayer films, the dielectric constant is preferably lower than that of the insulator layer 410 or the insulator layer 412. By providing an interlayer film having a low dielectric constant, it is possible to reduce the parasitic capacitance generated between the wirings.

For example, as the insulator layer 411, the insulator layer 413, and the insulator layer 420, silicon oxide, silicon nitride nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconate oxide, lead zirconate titanate (PZT). , Strontium titanate (SrTiO ₃ ) or (Ba, Sr) TiO ₃ (BST) and other insulators can be used in a single layer or in a laminated manner. Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon nitride nitride, or silicon nitride may be laminated on the above insulator.

Next, the semiconductor layer 440 will be described.

It is preferable that the energy at the lower end of the conduction band of the metal oxide layer 441 and the metal oxide layer 443 is higher than the energy at the lower end of the conduction band of the metal oxide layer 442. In other words, it is preferable that the electron affinity of the metal oxide layer 441 and the metal oxide layer 443 is smaller than the electron affinity of the metal oxide layer 442.

At the junction of the metal oxide layer 441, the metal oxide layer 442, and the metal oxide layer 443, it is preferable that the lower end of the conduction band changes gently. In other words, it is preferable that the lower ends of the conduction bands at the junction of the metal oxide layer 441, the metal oxide layer 442, and the metal oxide layer 443 are continuously changed or continuously bonded. In order to do so, the defect level density of the mixed layer formed at the interface between the metal oxide layer 441 and the metal oxide layer 442 and the interface between the metal oxide layer 442 and the metal oxide layer 443 is determined. It should be low.

At this time, the main path of the carrier is the metal oxide layer 442. By forming the metal oxide layer 441 and the metal oxide layer 443 as described above, the interface between the metal oxide layer 441 and the metal oxide layer 442 and the interface between the metal oxide layer 442 and the metal oxide layer 443 are configured. The defect level density in can be reduced. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and the OS transistor 400 can obtain a high on-current.

In order to form a mixed layer having a low defect level density, for example, the metal oxide layer 441 and the metal oxide layer 442, the metal oxide layer 442 and the oxide semiconductor 443 contain a common metal element other than oxygen as a main component. And. When the metal oxide layer 442 is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide or the like can be used as the metal oxide layer 441 and the metal oxide layer 443. can. For example, when the metal oxide layer 441-443 is an In-Ga-Zn oxide layer, the atomic number ratio of Ga to In in the metal oxide layer 441 is the atom of Ga to In in the metal oxide layers 442 and 443. It is preferably larger than the number ratio.

As shown in FIG. 12, the semiconductor layer 440 has regions 480, 481a, 481b, 482a, 482b. Region 480 functions as a channel forming region. The regions 481a and 481b function as a source region and a drain region. The regions 482a and 482b have regions that overlap with the insulator layer 427. At least one of the regions 482a and 482b may have a region overlapping with the conductor layer 460.

The regions 481a and 481b are regions where the oxygen concentration is low and the resistance is lowered. The region 480 is a high resistance region having a higher oxygen concentration and a lower carrier density than the regions 481a and 481b. The region 482a has a higher oxygen concentration and a lower carrier density than the region 481a, and has a lower oxygen concentration and a higher carrier density than the region 480. That is, the region 482a has a higher resistance than the region 481a and a lower resistance than the region 480. The region 482b is the same as that of the region 482a.

By providing the regions 482a and 482b, a high resistance region is not formed between the regions 481a and 481b that function as the source region and the drain region and the region 480 in which the channel is formed, so that the on-current and mobility of the transistor are not formed. Can be increased. Further, by having the regions 482a and 482b, the regions 481a and 481b do not overlap with the gate (conductor layer 460) in the channel length direction, respectively, so that the parasitic capacitance of the gate is reduced. Further, by having the regions 482a and 482b, the leakage current at the time of non-conduction can be reduced.

In FIG. 12, the boundary of each region is displayed substantially perpendicular to the upper surface of the semiconductor layer 440, but the present invention is not limited to this. Further, in the semiconductor layer 440, it may be difficult to clearly detect the boundary of each region. The concentrations of metal elements detected in each region and impurity elements such as hydrogen and nitrogen are not limited to gradual changes in each region, but are continuously changing (also referred to as gradation) in each region. You may. That is, it suffices that the concentration of the metal element and the concentration of the impurity element such as hydrogen and nitrogen decreases as the region is closer to the channel formation region.

By selectively reducing the resistance of the semiconductor layer 440, a desired function can be imparted to each region of the semiconductor layer 440. That is, it is possible to provide an OS transistor 400 that satisfies the requirements of circuit design.

In order to selectively reduce the resistance of the semiconductor layer 440, at least one of a metal element that enhances conductivity and an impurity may be added to a predetermined region. For example, metal elements that enhance conductivity include aluminum, titanium, tantalum, tungsten, and chromium. The impurities include elements that form oxygen deficiency or elements that are captured by oxygen deficiency. Specifically, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, and noble gas elements (typically). Examples include argon) and the like.

By increasing the content of the metal elements that enhance the conductivity, the elements that form oxygen deficiencies, or the elements that are captured by the oxygen deficiencies in the regions 481a and 481b, the carrier density of the regions 481a and 481b is increased and the resistance is low. Can be achieved.

In order to reduce the resistance of the regions 481a and 481b, for example, a metal-containing film (hereinafter referred to as a metal-containing film) may be formed in contact with the regions 481a and 481b. It is preferable to form the metal-containing film after forming the insulator layer 427.

That is, when the low resistance region is formed in the semiconductor layer 440, the conductor layer 460 that functions as a gate electrode and the insulator layer 427 are used as masks to reduce the resistance of the semiconductor layer 440 in a self-aligned manner. Therefore, when a plurality of OS transistors 400 are formed at the same time, it is possible to reduce the variation in electrical characteristics between the transistors. For example, the width of the conductor layer 460 can be set to the minimum processing dimension, and the OS transistor 400 is miniaturized.

Examples of the metal-containing film include a metal film, an oxide film containing a metal element, and a nitride film containing a metal element. The thickness of the metal-containing film may be, for example, 10 nm or more and 200 nm or less. The film formation of the film containing a metal element can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

When the semiconductor layer 440 and the metal-containing film come into contact with each other, the component of the film having the metal element and the component of the semiconductor layer 440 form a metal compound to form regions 481a and 481b, resulting in low resistance. Further, a part of oxygen in the semiconductor layer 440 located at or near the interface between the semiconductor layer 440 and the film having the metal element is absorbed by the layers 447A and 447B, and oxygen deficiency is formed in the semiconductor layer 440. The resistance may be lowered to form regions 481a and 481b.

Further, it is preferable to perform the heat treatment in an atmosphere containing nitrogen with the semiconductor layer 440 and the metal-containing film in contact with each other. By the heat treatment, from the film having the metal element, the metal element which is a component of the film having the metal element becomes the semiconductor layer 440, or the metal element which is the component of the semiconductor layer 440 becomes the film having the metal element. It diffuses and the semiconductor layer 440 and the film having the metal element form a metal compound to reduce the resistance. In this way, layers 447A and 447B are formed between the semiconductor layer 440 and the film having the metal element. At that time, the metal element of the semiconductor layer 440 and the metal element of the film having the metal element may be alloyed. Therefore, layers 447A and 447B may contain alloys. The alloy is in a relatively stable state and does not deteriorate the reliability of the OS transistor 400.

The heat treatment may be performed, for example, at 250 ° C. or higher and 650 ° C. or lower, preferably 300 ° C. or higher and 500 ° C. or lower, and more preferably 320 ° C. or higher and 450 ° C. or lower. The heat treatment is performed in a nitrogen or inert gas atmosphere. Further, the heat treatment may be performed in a reduced pressure state. Further, after the heat treatment is performed in an atmosphere of nitrogen or an inert gas, the heat treatment may be performed in an atmosphere containing an oxidizing gas.

Further, when hydrogen in the semiconductor layer 440 diffuses into the regions 481a and 481b and enters the oxygen deficiency existing in the regions 481a and 481b, it becomes a relatively stable state. Hydrogen in the oxygen deficiency present in the region 480 escapes from the oxygen deficiency by heat treatment at 250 ° C. or higher, diffuses into the regions 481a and 481b, enters the oxygen deficiency existing in the regions 481a and 481b, and is relatively stable. It becomes a state. Therefore, by the heat treatment, the regions 481a and 481b have lower resistance, and the region 480 has higher purity (reduction of impurities such as water and hydrogen) to have higher resistance.

In the regions 480, 482a and 482b, the addition of the metal element is suppressed by the presence of the conductor layer 460 and the insulator layer 427. Further, in the regions 480, 482a and 482b, the oxygen atoms in the semiconductor layer 440 are suppressed from being absorbed by the metal-containing film described above.

Oxygen deficiency may occur in these regions 481a due to the absorption of oxygen in the regions 481a. When hydrogen in the semiconductor layer 440 enters the oxygen deficiency, the carrier density in the region 481a increases. Therefore, the region 481a has a low resistance. The regions 481b, 482a, and 482b may also have low resistance.

When the metal-containing film has a property of absorbing hydrogen, hydrogen in the semiconductor layer 440 is absorbed into the film in the above heat treatment. Therefore, hydrogen, which is an impurity in the semiconductor layer 440, can be reduced. Since the metal-containing film is later removed by etching, most of the hydrogen absorbed from the semiconductor layer 440 is removed.

If impurities and oxygen deficiency are present in the channel forming region of the OS transistor, the electrical characteristics are liable to fluctuate and the reliability may be lowered. Further, when the channel formation region contains oxygen deficiency, the OS transistor tends to have a normally-on characteristic. Therefore, it is preferable that oxygen deficiency in the region 480 where the channel is formed is reduced as much as possible.

The insulator layer 427 is preferably an insulator containing more oxygen (also referred to as excess oxygen) than oxygen satisfying the stoichiometric composition. By diffusing the excess oxygen contained in the insulator layer 427 into the region 480, oxygen deficiency in the region 480 can be reduced and the region 480 can be made highly resistant.

In order to provide an excess oxygen region in the insulator layer 427, an oxide may be formed as the insulator layer 418 in contact with the insulator layer 427 by a sputtering method. By using the sputtering method for forming the oxide, it is possible to form an insulator having few impurities such as water or hydrogen. When the sputtering method is used, it is preferable to form a film using, for example, a facing target type sputtering apparatus. In the facing target type sputtering device, the film formation surface can be formed without being exposed to the high electric field region between the facing targets, so that the film formation surface is less likely to be damaged by plasma, so that the film formation can be performed. It is preferable because the film formation damage to the semiconductor layer 440 can be reduced when the insulator to be the insulator layer 418 is formed. A film forming method using a facing target type sputtering apparatus can be referred to as VDSP (Vapor Deposition SP) (registered trademark).

For the insulator layer 427, it is preferable to use silicon oxide, silicon oxide nitride, silicon nitride oxide, or silicon oxide having pores. Materials such as silicon oxide tend to form excess oxygen regions. On the other hand, as compared with the above-mentioned materials such as silicon oxide, even if the oxide film using the sputtering method is formed on the semiconductor layer 440, the semiconductor layer 440 tends to be less likely to form an excess oxygen region. .. Therefore, by providing the insulator layer 427 having the excess oxygen region around the region 480, the excess oxygen of the insulator layer 427 can be effectively supplied to the region 480.

In order to reduce the oxygen deficiency of the semiconductor layer 440, it is preferable that the insulator layer 416 and the insulator layer 422 also have more oxygen excess regions than oxygen satisfying the stoichiometric composition, like the insulator layer 427.

When the insulator layer 416 has an excess oxygen region, the insulator layer 415 has a function of suppressing the diffusion of at least one oxygen (for example, oxygen atom, oxygen molecule, etc.) (the oxygen is difficult to permeate). Is preferable. Since the insulator layer 415 has a function of suppressing the diffusion of oxygen, the oxygen in the excess oxygen region of the insulator layer 416 is efficiently supplied to the semiconductor layer 440 without diffusing to the insulator layer 414 side. be able to. Further, it is possible to prevent the conductor layer 461 from reacting with oxygen in the excess oxygen region of the insulator layer 416.

The insulating layer 415 is a so-called aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, Sr) TiO ₃ (BST). It is preferable to use an insulator containing a high-k material in a single layer or in a laminate. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for an insulator that functions as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials having a function of suppressing diffusion of impurities and oxygen (the oxygen is difficult to permeate). As the insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like. When the insulator layer 415 is formed by using such a material, the insulator layer 415 releases oxygen from the semiconductor layer 440 and mixes impurities such as hydrogen from the peripheral portion of the OS transistor 400 into the semiconductor layer 440. Functions as a layer that suppresses.

Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon nitride nitride, or silicon nitride may be laminated on the above insulator.

It is preferable that the insulator layer 418 also has a function of suppressing the diffusion of oxygen like the insulator layer 415. It is preferable to use aluminum oxide for the insulator layer 418. Aluminum oxide may extract hydrogen in the semiconductor layer 440 by performing a heat treatment in a state close to the semiconductor layer 440. When the layers 447A and 447B are provided between the semiconductor layer 440 and the aluminum oxide, the aluminum oxide absorbs the hydrogen in the layers 447A and 447B, and the hydrogen-reduced layers 447A and 447B are semiconductors. It may absorb hydrogen in layer 440. Therefore, the hydrogen concentration in the semiconductor layer 440 can be reduced. Further, by performing heat treatment in a state where the insulator layer 418 and the semiconductor layer 440 are in close proximity to each other, oxygen may be supplied from the insulator layer 418 to the semiconductor layer 440 and the insulator layer 416.

(Other configuration examples of OS transistors)
FIG. 13 shows a partially enlarged view of the OS transistor in the channel length direction. The OS transistor 402 shown in FIG. 13 is a modification of the OS transistor 400, and is provided with an insulator layer 429 instead of the insulator layer 427. For other configurations, the description of FIGS. 10 to 12 is referred to.

The insulator layer 429 is preferably an insulator having a function of suppressing the permeation of impurities or oxygen. That is, the insulator layer 429 functions as a side barrier that protects the gate electrode and the side surface of the gate insulator. The insulator layer 429 can cover the sides of the insulator layer 422, the metal oxide layer 444, and the conductor layer 460. Therefore, it is possible to prevent impurities such as hydrogen and water from being mixed into the semiconductor layer 440 from the ends of the insulator layer 422 and the metal oxide layer 444. Therefore, the formation of oxygen deficiency at the interface between the semiconductor layer 440 and the insulator layer 422 is suppressed, and the reliability of the OS transistor 402 can be improved.

For example, the insulator layer 429 is preferably formed by using the ALD method. By using the ALD method, a dense thin film can be formed. For the insulator layer 429, for example, aluminum oxide, hafnium oxide, or the like is preferably used. When aluminum oxide is provided as the insulator layer 429 by using the ALD method, the film thickness of the insulator layer 429 is preferably 0.5 nm or more and 3.0 nm or less.

11, 11_1, 11_2, 11_3, 11_4: Memory cell,
100: Storage device, 105: Control circuit, 111: Row decoder, 112: Row driver, 116: Column decoder, 117: Source line driver, 118: Input / output (I / O) circuit, 119: Local bit line selection circuit,
120, 150, 190: Memory cell array, 122, 152, 192: NAND cell array, 124, 154: Circuit section, 126, 156: Global bit line section, 130: Memory string,
140, 145: Bit line dividing circuit,
141, 141a, 141b, 141c, 141d: circuit,
142a, 142b: Source follower circuit,
170: AND circuit, 171: OR circuit, 173: Charge pump circuit, 175: Bootstrap circuit,
MT1: Memory transistor, ST1, ST2: Selective transistor,
WL1, WL2, WL3, WL4: Word line,
SL: source line, SGD, SGS: selection gate line,
BL: Bit line,
GBP: Global Bit Line,
LBL, LBLa, LBBb, LBLc, LBLd: local bit line,
GWEa, GWEb, GWEc, GWEd: write control line,
GREEa, GREEb, GREEc, GRed: Read control line,
RBIa, RBIb, RBIc, RBId: Bias control lines A0, A1, A2, A3, OUT, PRE, PREB, Y: Node, C51, C53: Capacitive element, M10, M11, M12, M13, M40, M41, M42, M45, M46, M47, M48, M51, M52, M53: Transistor,

Claims (6)

A storage device having a memory cell array
A first local bit line to an M (M is an integer of 2 or more) local bit lines are provided per global bit line.
The first circuit to the M circuit are electrically connected to the first local bit line to the M local bit line, respectively.
The k-th (k is an integer of 1 to M) circuit has a first transistor and a buffer amplifier.
The first transistor controls the conduction between the k-th local bit line and the global bit line, and controls the conduction between the k-th local bit line and the global bit line.
The buffer amplifier amplifies the current of the k-th local bit line and outputs it to the global bit line.
The on / off of the first transistor of the first circuit to the M circuit is controlled independently of each other.
The active states of the buffer amplifiers of the first circuit to the M circuit are controlled independently of each other .
The first circuit to the second M circuit, a storage device which is characterized that you have been stacked on the NAND cell array to said memory cell array has. Oite to claim 1,
The buffer amplifier is a storage device characterized by being a source follower circuit. In claim 2 ,
The source follower circuit has a second transistor to a fourth transistor, and has a second transistor to a fourth transistor.
The second transistor to the fourth transistor are electrically connected in series between the first power supply line and the second power supply line.
The gate of the third transistor of the k-circuit is electrically connected to the k-local bit line.
The input of the bias voltage to the second transistor of the first circuit to the M circuit is controlled independently of each other.
A storage device characterized in that the on / off of the fourth transistor of the first circuit to the M circuit is controlled independently of each other. In claim 3 ,
A storage device in which each of the semiconductor layers of the first transistor to the fourth transistor has a metal oxide. In any one of claims 1 to 4 ,
The memory cell array has a plurality of memory strings and has a plurality of memory strings.
A storage device, wherein each of the plurality of memory strings is provided with a memory cell electrically connected in series. In claim 5 ,
A storage device characterized in that the semiconductor layer of the transistor constituting the memory string has a metal oxide.

Images