JP6980174B2

JP6980174B2 - Printed wiring board

Info

Publication number: JP6980174B2
Application number: JP2017066651A
Authority: JP
Inventors: 真弘深谷
Original assignee: Aisin Seiki Co Ltd; Aisin Corp
Current assignee: Aisin Corp
Priority date: 2017-03-30
Filing date: 2017-03-30
Publication date: 2021-12-15
Anticipated expiration: 2037-03-30
Also published as: JP2018170402A

Description

本発明は、プリント配線基板に係り、例えば、コア層の両面側に配線用の各層が配置されたプリント基板に関する。 The present invention relates to a printed wiring board, and for example, relates to a printed circuit board in which each layer for wiring is arranged on both sides of a core layer.

電子機器の普及に伴い、回路を構成する電子部品同士を接続する配線や、各電子部品に信号を伝送する配線や、電力を供給する配線が配設されたプリント配線基板が広く使用されている。
このプリント配線基板では、プリント配線基板上に配置する他の回路配線との干渉を避けるために、配線層を多層化することで配線層を変更している。異なる層に形成された配線を電気的に接続する場合には、ビア接続が使用されている。
例えば、多層化したプリント配線基板において、電源生成回路と電源供給先回路とを、各層を貫通する電源ビアとグランドビアで接続する技術が提案されている（特許文献１参照）。 With the widespread use of electronic devices, printed wiring boards in which wiring for connecting electronic components constituting a circuit, wiring for transmitting signals to each electronic component, and wiring for supplying electric power are widely used. ..
In this printed wiring board, the wiring layer is changed by making the wiring layer multi-layered in order to avoid interference with other circuit wiring arranged on the printed wiring board. Via connections are used to electrically connect wires formed in different layers.
For example, in a multi-layered printed wiring board, a technique has been proposed in which a power generation circuit and a power supply destination circuit are connected by a power supply via and a ground via penetrating each layer (see Patent Document 1).

図４は、従来のプリント配線基板における電源ビアとグランドビアの配置状態を表した説明図である。
図４（ａ）は、プリント配線基板１００の断面を、（ｂ）は第５層目の電源配線の平面を表したものである。
プリント配線基板１００は、コア層１１０の両側面に第１から第３層の配線層１１１〜１１３と、第４から第６層の配線層１１４〜１１６が形成され、第１配線層１１１には電源供給元回路１５０と電源供給先回路１６０とが配置されている。また第５配線層１１５には、干渉回避のために配線層を変更した電源配線１２５が配置されている。 FIG. 4 is an explanatory diagram showing the arrangement state of the power supply via and the ground via in the conventional printed wiring board.
FIG. 4A shows a cross section of the printed wiring board 100, and FIG. 4B shows a plane of the power supply wiring of the fifth layer.
In the printed wiring board 100, the wiring layers 111 to 113 of the first to third layers and the wiring layers 114 to 116 of the fourth to sixth layers are formed on both side surfaces of the core layer 110, and the first wiring layer 111 is formed with the wiring layers 114 to 116. A power supply source circuit 150 and a power supply destination circuit 160 are arranged. Further, in the fifth wiring layer 115, a power supply wiring 125 having a modified wiring layer for avoiding interference is arranged.

図４（ａ）に示すように、プリント配線基板１００には、電源供給元回路１５０側と電源供給先回路１６０側に、第１配線層１１１から第６配線層１１６までを貫通する電源ビア１２０が形成され、電源ビア１２０は第５配線層１１５の電源配線１２５と接続されている。図４（ａ）では示されていないが、各電源ビア１２０は複数形成されている。
また、基板全体を貫通する複数のグランドビア（以下ＧＮＤビアという）１３０が、電源ビア１２０に対し交互に並べて近接配置されている。
このように、電源ビア１２０とＧＮＤビア１３０とを、全層にわたって交互に並べて近接配置しているので、点線領域Ａで示すように、電源ビア１２０とＧＮＤビア１３０とを流れる電流が並走し、これにより電源供給用の電源ビア１２０の配線インダクタンスを低減させることができる。 As shown in FIG. 4A, the printed wiring board 100 has a power supply via 120 penetrating from the first wiring layer 111 to the sixth wiring layer 116 on the power supply source circuit 150 side and the power supply destination circuit 160 side. Is formed, and the power supply via 120 is connected to the power supply wiring 125 of the fifth wiring layer 115. Although not shown in FIG. 4A, a plurality of power supply vias 120 are formed.
Further, a plurality of ground vias (hereinafter referred to as GND vias) 130 penetrating the entire substrate are alternately arranged in close proximity to the power supply via 120.
In this way, since the power supply via 120 and the GND via 130 are arranged alternately and close to each other over all the layers, the current flowing through the power supply via 120 and the GND via 130 runs in parallel as shown by the dotted line region A. As a result, the wiring inductance of the power supply via 120 for power supply can be reduced.

しかし、電源ビア１２０とＧＮＤビア１３０とを全層並べて近接配置しているため、図４（ｂ）に示すように、配線層における電源配線１２５にもＧＮＤビア１３０用の貫通孔（ビア孔）が形成されることになる。その結果、電源供給用の配線面積（パターン領域の面積）が減少することになり、配線インピーダンスが増加するという問題がある。
また、図示しないが、第３配線層や第４配線層以外の層に設けられるＧＮＤ配線においてもＧＮＤビア１３０が電源ビア１２０と交互に配置されて貫通する。ＧＮＤビア１３０はビア孔の内周面をめっきにより形成されている。このため、電源ビア１２０とＧＮＤビア１３０が交互に配置された領域において、複数のＧＮＤビア１３０の内側の面積分が減少することになり、ＧＮＤ配線での配線インピーダンスも増加している。 However, since the power supply via 120 and the GND via 130 are arranged close to each other in all layers, as shown in FIG. 4B, the power supply wiring 125 in the wiring layer also has a through hole (via hole) for the GND via 130. Will be formed. As a result, the wiring area for power supply (the area of the pattern region) is reduced, and there is a problem that the wiring impedance is increased.
Further, although not shown, the GND vias 130 are alternately arranged and penetrate the power supply vias 120 in the GND wiring provided in the layers other than the third wiring layer and the fourth wiring layer. The GND via 130 is formed by plating the inner peripheral surface of the via hole. Therefore, in the region where the power supply vias 120 and the GND vias 130 are alternately arranged, the area inside the plurality of GND vias 130 is reduced, and the wiring impedance in the GND wiring is also increased.

特開２０１３−４８３０号公報Japanese Unexamined Patent Publication No. 2013-4830

本発明は、電源供給用の電源ビアの配線インダクタンスを低減すると共に、配線層における配線インピーダンスの増加を抑制することを目的とする。 An object of the present invention is to reduce the wiring inductance of a power supply via for power supply and to suppress an increase in wiring impedance in a wiring layer.

（１）請求項１に記載の発明では、コア層と、前記コア層の一方の面側に形成された第１配線層から第ｍ配線層と、前記コア層の他方の面側に形成された第ｍ＋１配線層から第ｎ配線層と、前記第１配線層に形成された、電源供給元回路が接続される第１電源配線と、前記第１配線層に形成された、電源供給先回路が接続される第２電源配線と、前記第２配線層から第ｎ配線層のうちのいずれかの配線層に形成され、前記第１電源配線の投影領域と前記第２電源配線の投影領域を含み、両投影領域を接続する第３電源配線と、前記第１電源配線から、少なくとも前記コア層を貫通し、前記第ｍ＋１配線層と前記第３電源配線のうち前記第ｎ配線層側に位置する配線層まで貫通する複数の第１電源ビアと、前記第２電源配線から、少なくとも前記コア層を貫通し、前記第ｍ＋１配線層と前記第３電源配線のうち前記第ｎ配線層側に位置する配線層まで貫通する複数の第２電源ビアと、前記コア層を貫通する複数の第１ＧＮＤビアと、前記コア層を貫通する複数の第２ＧＮＤビアと、前記第１電源配線の投影領域を含む領域に対応して、前記第１ＧＮＤビアの両端が位置する配線層に形成された第１ＧＮＤ配線、第２ＧＮＤ配線と、前記第２電源配線の投影領域を含む領域に対応して、前記第２ＧＮＤビアの両端が位置する配線層に形成された第３ＧＮＤ配線、第４ＧＮＤ配線と、を備え、前記第１電源ビアと前記第１ＧＮＤビア、及び、前記第２電源ビアと前記第２ＧＮＤビアは、少なくとも前記コア層を含む第ｍ配線層と第ｍ＋１配線層間において近接配置され、前記第１ＧＮＤビアと前記第２ＧＮＤビアは、前記第３電源配線が形成されている配線層を貫通しておらず、前記第１ＧＮＤビアと前記第２ＧＮＤビアとは異なるＧＮＤビアが、前記第１ＧＮＤビアと前記第２ＧＮＤビアが貫通していない配線層間において、前記第１電源ビアと前記第２電源ビアと隔離配置されている、ことを特徴とするプリント配線基板を提供する。
（２）請求項２に記載の発明では、コア層と、前記コア層の一方の面側に形成された第１配線層から第ｍ配線層と、前記コア層の他方の面側に形成された第ｍ＋１配線層から第ｎ配線層と、前記第１配線層に形成された、電源供給元回路が接続される第１電源配線と、前記第１配線層に形成された、電源供給先回路が接続される第２電源配線と、前記第２配線層から第ｎ配線層のうちのいずれかの配線層に形成され、前記第１電源配線の投影領域と前記第２電源配線の投影領域を含み、両投影領域を接続する第３電源配線と、前記第１電源配線から、少なくとも前記コア層を貫通し、前記第ｍ＋１配線層と前記第３電源配線のうち前記第ｎ配線層側に位置する配線層まで貫通する複数の第１電源ビアと、前記第２電源配線から、少なくとも前記コア層を貫通し、前記第ｍ＋１配線層と前記第３電源配線のうち前記第ｎ配線層側に位置する配線層まで貫通する複数の第２電源ビアと、前記コア層を貫通する複数の第１ＧＮＤビアと、前記コア層を貫通する複数の第２ＧＮＤビアと、前記第１電源配線の投影領域を含む領域に対応して、前記第１ＧＮＤビアの両端が位置する配線層に形成された第１ＧＮＤ配線、第２ＧＮＤ配線と、前記第２電源配線の投影領域を含む領域に対応して、前記第２ＧＮＤビアの両端が位置する配線層に形成された第３ＧＮＤ配線、第４ＧＮＤ配線と、を備え、前記第１電源ビアと前記第１ＧＮＤビア、及び、前記第２電源ビアと前記第２ＧＮＤビアは、少なくとも前記コア層を含む第ｍ配線層と第ｍ＋１配線層間において近接配置され、他の配線層間において前記第１ＧＮＤビアと前記第２ＧＮＤビアとは異なるＧＮＤビアが、前記第１電源ビアと前記第２電源ビアとは隔離配置されており、前記第１ＧＮＤビアと前記第２ＧＮＤビアは、前記コア層を含む第ｍ配線層と第ｍ＋１配線層間にだけ形成されている、ことを特徴とするプリント配線基板を提供する。
（３）請求項３に記載の発明では、コア層と、前記コア層の一方の面側に形成された第１配線層から第ｍ配線層と、前記コア層の他方の面側に形成された第ｍ＋１配線層から第ｎ配線層と、前記第１配線層に形成された、電源供給元回路が接続される第１電源配線と、前記第１配線層に形成された、電源供給先回路が接続される第２電源配線と、前記第２配線層から第ｎ配線層のうちのいずれかの配線層に形成され、前記第１電源配線の投影領域と前記第２電源配線の投影領域を含み、両投影領域を接続する第３電源配線と、前記第１電源配線から、少なくとも前記コア層を貫通し、前記第ｍ＋１配線層と前記第３電源配線のうち前記第ｎ配線層側に位置する配線層まで貫通する複数の第１電源ビアと、前記第２電源配線から、少なくとも前記コア層を貫通し、前記第ｍ＋１配線層と前記第３電源配線のうち前記第ｎ配線層側に位置する配線層まで貫通する複数の第２電源ビアと、前記コア層を貫通する複数の第１ＧＮＤビアと、前記コア層を貫通する複数の第２ＧＮＤビアと、前記第１電源配線の投影領域を含む領域に対応して、前記第１ＧＮＤビアの両端が位置する配線層に形成された第１ＧＮＤ配線、第２ＧＮＤ配線と、前記第２電源配線の投影領域を含む領域に対応して、前記第２ＧＮＤビアの両端が位置する配線層に形成された第３ＧＮＤ配線、第４ＧＮＤ配線と、を備え、前記第１電源ビアと前記第１ＧＮＤビア、及び、前記第２電源ビアと前記第２ＧＮＤビアは、少なくとも前記コア層を含む第ｍ配線層と第ｍ＋１配線層間において近接配置され、前記第１ＧＮＤビアと前記第２ＧＮＤビアは、前記第３電源配線が形成されている配線層の、前記コア層から見て一つ内側の配線層まで貫通しており、前記第１ＧＮＤビアと前記第２ＧＮＤビアとは異なるＧＮＤビアが、前記第１ＧＮＤビアと前記第２ＧＮＤビアが貫通していない配線層間において、前記第１電源ビアと前記第２電源ビアと隔離配置されている、ことを特徴とするプリント配線基板を提供する。
（４）請求項４に記載の発明では、前記プリント配線基板は、複数の素子が配置され、前記配線層には各素子間を接続する配線が形成されている、ことを特徴とする請求項１、請求項２、又は請求項３に記載のプリント配線基板を提供する。
（５）請求項５に記載の発明では、前記第１電源ビアと前記第１ＧＮＤビアとは、交互に並んで近接配置され、前記第２電源ビアと前記第２ＧＮＤビアとは、交互に並んで近接配置されている、ことを特徴とする請求項１から請求項４のうちの何れか１の請求項に記載のプリント配線基板を提供する。 (1) In the invention according to claim 1, the core layer is formed on one surface side of the core layer, from the first wiring layer to the m wiring layer formed on one surface side of the core layer, and on the other surface side of the core layer. The first power supply wiring to which the power supply source circuit is connected, which is formed in the first m + 1 wiring layer to the nth wiring layer, and the power supply destination circuit formed in the first wiring layer. The second power supply wiring to which is connected and the projection area of the first power supply wiring and the projection area of the second power supply wiring formed in any of the wiring layers from the second wiring layer to the nth wiring layer. It is located on the nth wiring layer side of the m + 1 wiring layer and the third power supply wiring, including at least the core layer from the third power supply wiring connecting both projection regions and the first power supply wiring. A plurality of first power supply vias penetrating to the wiring layer and at least the core layer from the second power supply wiring, and located on the nth wiring layer side of the m + 1 wiring layer and the third power supply wiring. comprising a plurality of second power supply via penetrating up wiring layer, a plurality of first 1GND vias through the core layer, and a plurality of second 2GND vias through the core layer, the projection area of the first power supply wiring The second GND via corresponds to a region including a projection region of the first GND wiring, the second GND wiring, and the second power supply wiring formed in the wiring layer where both ends of the first GND via correspond to the region. The first power supply via and the first GND via, and the second power supply via and the second GND via are at least the above. The first GND via and the second GND via are arranged close to each other between the mth wiring layer including the core layer and the m + 1 wiring layer, and the first GND via and the second GND via do not penetrate the wiring layer on which the third power supply wiring is formed, and the first A GND via different from the 1 GND via and the 2nd GND via is isolated from the 1st power supply via and the 2nd power supply via in the wiring layer where the 1st GND via and the 2nd GND via do not penetrate. Provided is a printed wiring board characterized by the above.
(2) In the invention according to claim 2, the core layer is formed on one surface side of the core layer, the first wiring layer to the m wiring layer formed on one surface side of the core layer, and the other surface side of the core layer. The first power supply wiring to which the power supply source circuit is connected, which is formed in the first m + 1 wiring layer to the nth wiring layer, and the power supply destination circuit formed in the first wiring layer. The second power supply wiring to which is connected and the projection area of the first power supply wiring and the projection area of the second power supply wiring formed in any of the wiring layers from the second wiring layer to the nth wiring layer. It is located on the nth wiring layer side of the m + 1 wiring layer and the third power supply wiring, including at least the core layer from the third power supply wiring connecting both projection regions and the first power supply wiring. A plurality of first power supply vias penetrating to the wiring layer and at least the core layer from the second power supply wiring, and located on the nth wiring layer side of the m + 1 wiring layer and the third power supply wiring. Includes a plurality of second power supply vias penetrating to the wiring layer, a plurality of first GND vias penetrating the core layer, a plurality of second GND vias penetrating the core layer, and a projection area of the first power supply wiring. The second GND via corresponds to a region including a projection region of the first GND wiring, the second GND wiring, and the second power supply wiring formed in the wiring layer where both ends of the first GND via correspond to the region. The first power supply via and the first GND via, and the second power supply via and the second GND via are at least the above. The GND vias that are arranged close to each other between the m wiring layer including the core layer and the m + 1 wiring layer and are different from the first GND via and the second GND via in the other wiring layers are the first power supply via and the second power supply via. Provided is a printed wiring substrate characterized in that the first GND via and the second GND via are formed only between the m wiring layer including the core layer and the m + 1 wiring layer. do.
(3) In the invention according to claim 3, the core layer is formed on one surface side of the core layer, the first wiring layer to the m wiring layer formed on one surface side of the core layer, and the other surface side of the core layer. The first power supply wiring to which the power supply source circuit is connected, which is formed in the first m + 1 wiring layer to the nth wiring layer, and the power supply destination circuit formed in the first wiring layer. The second power supply wiring to which is connected and the projection area of the first power supply wiring and the projection area of the second power supply wiring formed in any of the wiring layers from the second wiring layer to the nth wiring layer. It is located on the nth wiring layer side of the m + 1 wiring layer and the third power supply wiring, including at least the core layer from the third power supply wiring connecting both projection regions and the first power supply wiring. A plurality of first power supply vias penetrating to the wiring layer and at least the core layer from the second power supply wiring, and located on the nth wiring layer side of the m + 1 wiring layer and the third power supply wiring. Includes a plurality of second power supply vias penetrating to the wiring layer, a plurality of first GND vias penetrating the core layer, a plurality of second GND vias penetrating the core layer, and a projection area of the first power supply wiring. The second GND via corresponds to a region including a projection region of the first GND wiring, the second GND wiring, and the second power supply wiring formed in the wiring layer where both ends of the first GND via correspond to the region. The first power supply via and the first GND via, and the second power supply via and the second GND via are at least the above. The first GND via and the second GND via are arranged close to each other between the mth wiring layer including the core layer and the m + 1 wiring layer, and the first GND via and the second GND via are one of the wiring layers in which the third power supply wiring is formed, as viewed from the core layer. A GND via that penetrates to the inner wiring layer and is different from the first GND via and the second GND via is the first power supply via between the wiring layers that the first GND via and the second GND via do not penetrate. And the printed wiring board characterized by being isolated from the second power supply via.
(4) The invention according to claim 4, wherein a plurality of elements are arranged in the printed wiring board, and wiring connecting each element is formed in the wiring layer. 1. The printed wiring board according to claim 2 or 3 is provided.
(5) In the invention according to claim 5, the first power supply via and the first GND via are arranged side by side alternately and close to each other, and the second power supply via and the second GND via are arranged side by side alternately. The printed wiring board according to any one of claims 1 to 4, wherein the printed wiring boards are arranged in close proximity to each other.

本発明によれば、第１電源ビアと第１ＧＮＤビア、及び、第２電源ビアと第２ＧＮＤビアは、少なくともコア層を含む第ｍ配線層と第ｍ＋１配線層間において近接配置されているので、電源供給用の電源ビアの配線インダクタンスを低減し、他の配線層間において隔離配置されているので、配線層における配線インピーダンスの増加を抑制することができる。 According to the present invention, the first power supply via and the first GND via, and the second power supply via and the second GND via are arranged close to each other at least between the m wiring layer including the core layer and the m + 1 wiring layer. Since the wiring inductance of the power supply via for supply is reduced and the wiring inductance is isolated between the other wiring layers, it is possible to suppress an increase in the wiring impedance in the wiring layer.

本実施形態において配置される各回路の状態を表したプリント配線基板全体の平面図である。It is a top view of the whole printed wiring board which shows the state of each circuit arranged in this embodiment. 本実施形態のプリント配線基板における電源ビアとＧＮＤビアの配置状態を表した断面図と平面図である。It is sectional drawing and the plan view which showed the arrangement state of the power source via and the GND via in the printed wiring board of this embodiment. 本実施形態におけるプリント配線基板の一部における各層を分解して表した斜視図である。It is a perspective view which showed by disassembling each layer in a part of the printed wiring board in this embodiment. 従来のプリント配線基板における電源ビアとグランドビアの配置状態を表した断面図と平面図である。It is sectional drawing and the plan view which showed the arrangement state of the power source via and the ground via in the conventional printed wiring board.

以下、本発明のプリント配線基板における好適な実施の形態について、図１から図３を参照して詳細に説明する。
（１）実施形態の概要
本実施形態のプリント配線基板は、コア層の一方の面側に第１配線層〜第ｍ配線層が、他方の面側に第ｍ＋１配線層〜第ｎ配線層が配置される。
コア層の両面に配置される第ｍ配線層と第ｍ＋１配線層間において、複数の電源ビアとＧＮＤビアを近接配置する。複数の電源ビアとＧＮＤビアの近接配置は、両者を交互に並立させることが好ましい。ここで近接配置とは、両ビア間の距離（中心間ではなく、外周面間の距離をいう、以下同じ）が１ｍｍ以下、好ましくは０．８ｍｍ以下であることをいう。 Hereinafter, preferred embodiments of the printed wiring board of the present invention will be described in detail with reference to FIGS. 1 to 3.
(1) Outline of the Embodiment In the printed wiring board of the present embodiment, the first wiring layer to the m wiring layer are on one surface side of the core layer, and the m + 1 wiring layer to the nth wiring layer are on the other surface side. Be placed.
A plurality of power supply vias and GND vias are arranged close to each other between the mth wiring layer and the m + 1 wiring layer arranged on both sides of the core layer. It is preferable that the plurality of power supply vias and the GND vias are arranged in close proximity to each other alternately. Here, the proximity arrangement means that the distance between both vias (meaning the distance between the outer peripheral surfaces, not between the centers, the same applies hereinafter) is 1 mm or less, preferably 0.8 mm or less.

そして、第ｍ−１配線層と第ｍ配線層間、及び、第ｍ配線層と第ｍ＋１配線層間において、電源ビアは、コア層から他の配線層まで同軸上に延長形成されている。
一方、ＧＮＤビアは、電源配線及び／又はＧＮＤ配線（第ｍ配線と第ｍ＋１配線を除く）が形成された配線層までは、コア層のＧＮＤビアが同軸上に延長されることはない。すなわち、ＧＮＤビアについては、電源配線、ＧＮＤ配線が形成されている配線層の１つ内側（コア層側）の配線層まで、コア層のＧＮＤビアと同軸上に延長形成することが可能である。ただし、本実施形態のＧＮＤビアは第ｍ配線層と第ｍ＋１配線層間だけに形成されている。
第１配線層〜第ｍ配線層と、第ｍ＋１配線層〜第ｎ配線層の各配線層間のうち、コア層を貫通するＧＮＤビアが形成されていない、当該各配線層間に対し、ＧＮＤビアは電源ビアと近接配置せずに、離れた位置に隔離配置して形成される。
ここで、隔離配置とは両ビア間の距離がビア孔の径をｓｍｍとした場合、径を１０×ｓｍｍ以上離れている場合、又は、２ｍｍ以上離れている場合の少なくとも一方を満たす場合をいう。
なお、電源ビアについては、第１配線層から第ｎ配線層まで貫通形成されることが好ましい。 The power supply via is coaxially formed from the core layer to the other wiring layer between the m-1 wiring layer and the m wiring layer, and between the m wiring layer and the m + 1 wiring layer.
On the other hand, in the GND via, the GND via of the core layer is not coaxially extended to the wiring layer in which the power supply wiring and / or the GND wiring (excluding the mth wiring and the m + 1 wiring) is formed. That is, for the GND via, it is possible to extend and form the power supply wiring and the wiring layer on the inner side (core layer side) of the wiring layer on which the GND wiring is formed coaxially with the GND via of the core layer. .. However, the GND via of the present embodiment is formed only between the m-th wiring layer and the m + 1 wiring layer.
Of the wiring layers of the first wiring layer to the m wiring layer and the m + 1 wiring layer to the nth wiring layer, the GND vias that penetrate the core layer are not formed. It is not placed close to the power supply via, but is isolated and formed at a remote location.
Here, the isolated arrangement means that the distance between the two vias satisfies at least one of the cases where the diameter of the via hole is smm, the diameter is separated by 10 × smm or more, or the distance is separated by 2 mm or more. ..
The power supply via is preferably formed through from the first wiring layer to the nth wiring layer.

本実施形態によれば、電源ビアに対し、ＧＮＤビアを、コア層を含む第ｍ配線層と第ｍ＋１配線層間のみで近接配置することで、配線インダクタンスを抑えつつ、配線層の配線インピーダンスを低減することができる。 According to the present embodiment, by arranging the GND vias close to the power supply via only between the m wiring layer including the core layer and the m + 1 wiring layer, the wiring impedance of the wiring layer is reduced while suppressing the wiring inductance. can do.

（２）実施形態の詳細
図１は本実施形態において配置される各回路の状態を表したプリント配線基板１全体の平面図である。
図１はプリント配線基板の１例であり、プリント配線基板が使用される各種電子機器を構成する、ＤＲＡＭ、Ｆｌａｓｈメモリなどの他、ＵＳＢ等の外部接続端子などの各種素子が配置されている。プリント配線基板には、後述する配線層（図示しない）が絶縁体を介して複数層配設され、各配線層に形成された配線によって各素子間が接続されている。
またプリント配線基板１には、電源供給元回路５０と、電源供給先回路６０が配置されている。
本実施形態では、電源供給元回路５０から電源供給先回路６０に電力を供給するための電源ビアとＧＮＤビアの配置に特徴がある。そのため、以下の説明では、図１において電源供給元回路５０と電源供給先回路６０を含む、点線領域Ｐを中心に説明する。 (2) Details of the Embodiment FIG. 1 is a plan view of the entire printed wiring board 1 showing the state of each circuit arranged in the present embodiment.
FIG. 1 is an example of a printed wiring board, in which various elements such as an external connection terminal such as USB are arranged in addition to a DRAM, a Flash memory, and the like constituting various electronic devices in which the printed wiring board is used. A plurality of wiring layers (not shown) described later are arranged on the printed wiring board via an insulator, and each element is connected by wiring formed in each wiring layer.
Further, a power supply source circuit 50 and a power supply destination circuit 60 are arranged on the printed wiring board 1.
In this embodiment, the arrangement of the power supply via and the GND via for supplying power from the power supply source circuit 50 to the power supply destination circuit 60 is characteristic. Therefore, in the following description, the dotted line region P including the power supply source circuit 50 and the power supply destination circuit 60 will be mainly described in FIG.

図２は、本実施形態のプリント配線基板１における電源ビア２０とＧＮＤビア３０の配置状態を表した断面図（ａ）と、平面を表した説明図（ｂ）である。
図２（ａ）に示すように、プリント配線基板１の最上層である第１配線層１１には電源供給元回路５０と電源供給先回路６０が配設されている。
本実施形態のプリント配線基板１は、コア層１０を挟んでその一方の面側に第１配線層１１〜第３配線層１３が形成され、他方の面側に第４配線層１４〜第６配線層１６が形成されている。すなわち、本実施形態では第ｍ配線層として第３配線層１３が形成され、第ｎ配線層として第６配線層１６が形成されている。 FIG. 2 is a cross-sectional view (a) showing an arrangement state of a power supply via 20 and a GND via 30 in the printed wiring board 1 of the present embodiment, and an explanatory view (b) showing a plane.
As shown in FIG. 2A, a power supply source circuit 50 and a power supply destination circuit 60 are arranged on the first wiring layer 11, which is the uppermost layer of the printed wiring board 1.
In the printed wiring board 1 of the present embodiment, the first wiring layers 11 to 3 are formed on one surface side of the core layer 10 and the fourth wiring layers 14 to 6 are formed on the other surface side. The wiring layer 16 is formed. That is, in the present embodiment, the third wiring layer 13 is formed as the mth wiring layer, and the sixth wiring layer 16 is formed as the nth wiring layer.

コア層１０は、プリント配線基板１内でコア材を使用している層であり、本実施形態ではガラス・エポキシ樹脂（ＦＲ−４）が使用されているが、グリーンシート（セラミック基板）等の各種公知の材料を使用することができる。
本実施形態のコア層の一方の面には第３配線層が形成され、他方の面には第４配線層が形成されている。 The core layer 10 is a layer in which a core material is used in the printed wiring board 1, and glass / epoxy resin (FR-4) is used in this embodiment, but a green sheet (ceramic substrate) or the like is used. Various known materials can be used.
A third wiring layer is formed on one surface of the core layer of the present embodiment, and a fourth wiring layer is formed on the other surface.

第１配線層１１から第３配線層１３の各層間、及び、第４配線層１４から第６配線層１６の各層間には、絶縁材が配設されている。絶縁材としては、多層基板かビルドアップ基板かにより、プリプレグという接着シートを使用する等の各製造方法に応じた絶縁材が使用される。
第１配線層１１〜第６配線層１６には各素子を接続するための配線が形成されている。配線は銅箔で形成されている。 An insulating material is disposed between each layer of the first wiring layer 11 to the third wiring layer 13 and each layer of the fourth wiring layer 14 to the sixth wiring layer 16. As the insulating material, depending on whether it is a multilayer board or a build-up board, an insulating material corresponding to each manufacturing method such as using an adhesive sheet called prepreg is used.
Wiring for connecting each element is formed in the first wiring layer 11 to the sixth wiring layer 16. The wiring is made of copper foil.

本実施形態は、プリント配線基板１を構成する各層の中で配線インダクタンスへの影響度が高いのがコア層１０である点に着目して電源ビア２０とＧＮＤビア３０を配設している。
すなわち、図２（ａ）に示すように、本実施形態のプリント配線基板１には、第１配線層１１から第６配線層１６までを貫通する、電源供給元回路５０側の電源ビア２０（第１電源ビア）と、電源供給先回路６０側の電源ビア２０（第２電源ビア）が形成されている。また、コア層１０を含む第３配線層１３と第４配線層１４とを貫通する、電源供給元回路５０側のＧＮＤビア３０（第１ＧＮＤビア）と、電源供給先回路６０側のＧＮＤビア３０（第２ＧＮＤビア）が形成されている。電源ビア２０とＧＮＤビア３０はともに、銅メッキにより形成されている。
なお、図２（ａ）では、電源ビア２０とＧＮＤビア３０が１本ずつ表示されているが、実際は後述するように、複数の電源ビア２０と複数のＧＮＤビア３０が交互に並べて近接配置されている。 In this embodiment, the power supply via 20 and the GND via 30 are arranged by paying attention to the fact that the core layer 10 has a high degree of influence on the wiring inductance among the layers constituting the printed wiring board 1.
That is, as shown in FIG. 2A, the printed wiring board 1 of the present embodiment has a power supply via 20 on the power supply source circuit 50 side that penetrates from the first wiring layer 11 to the sixth wiring layer 16. The first power supply via) and the power supply via 20 (second power supply via) on the power supply destination circuit 60 side are formed. Further, a GND via 30 (first GND via) on the power supply source circuit 50 side and a GND via 30 on the power supply destination circuit 60 side penetrating the third wiring layer 13 including the core layer 10 and the fourth wiring layer 14. (2nd GND via) is formed. Both the power supply via 20 and the GND via 30 are formed by copper plating.
In FIG. 2A, the power supply via 20 and the GND via 30 are displayed one by one, but in reality, as will be described later, the plurality of power supply vias 20 and the plurality of GND vias 30 are arranged in close proximity to each other. ing.

一方詳細は後述するが、第３配線層１３と第４配線層１４間以外の他の配線層間では、ＧＮＤビア３０を、電源ビア２０と交互に並べて近接配置せず、電源ビア２０から所定距離だけ離れた位置に隔離配置して形成している。 On the other hand, although the details will be described later, in the wiring layers other than between the third wiring layer 13 and the fourth wiring layer 14, the GND vias 30 are not arranged in close proximity to the power supply vias 20 and are arranged at a predetermined distance from the power supply vias 20. It is formed by being isolated and placed only at a distance.

また、図２に示すように、電源供給元回路５０側の電源ビア２０と、電源供給先回路６０側の電源ビア２０とを接続する電源配線２５（第３電源配線）が、第５配線層１５に形成されている。これにより、電源供給元回路５０と電源供給先回路６０とが、両側の電源ビア２０と第５配線層１５の電源配線２５を介して接続され、図中に矢印で示すように電流Ｉが流れる。 Further, as shown in FIG. 2, the power supply wiring 25 (third power supply wiring) connecting the power supply via 20 on the power supply source circuit 50 side and the power supply via 20 on the power supply destination circuit 60 side is the fifth wiring layer. It is formed at 15. As a result, the power supply source circuit 50 and the power supply destination circuit 60 are connected via the power supply vias 20 on both sides and the power supply wiring 25 of the fifth wiring layer 15, and the current I flows as shown by an arrow in the figure. ..

本実施形態によれば、複数の電源ビア２０に対し、複数のＧＮＤビア３０を、コア層１０を挟む第３配線層１３と第４配線層１４の間で近接配置することで、配線インダクタンスを従来と同様に抑制することができる。配線インダクタンスへの影響が高いコア層１０において、点線領域Ａで示すように、電源ビア２０とＧＮＤビア３０とを流れる電流が並走し、これにより電源供給用の電源ビア２０の配線インダクタンスが低減されるためである。 According to the present embodiment, a plurality of GND vias 30 are arranged close to each other of the plurality of power supply vias 20 between the third wiring layer 13 and the fourth wiring layer 14 sandwiching the core layer 10, thereby providing wiring inductance. It can be suppressed in the same manner as before. In the core layer 10 having a high influence on the wiring inductance, as shown by the dotted line region A, the current flowing through the power supply via 20 and the GND via 30 runs in parallel, whereby the wiring inductance of the power supply via 20 for power supply is reduced. This is because it is done.

さらに、他の配線層である第１配線層１１、第２配線層１２、第５配線層１５、第６配線層１６には、電源ビア２０の近傍にはＧＮＤビア３０が配置されていないので、ＧＮＤビア３０用のビア孔が存在しないため、配線面積の減少による配線インピーダンスの増加を抑制することができる。
すなわち、図２（ｂ）に示されるように、第５配線層１５に形成された電源配線２５には、ＧＮＤビア３０による面積減少がないため、図４（ｂ）に示した従来の電源配線１２５に比べて配線インピーダンスを低減することができる。また、ＧＮＤビア３０が形成されないため、配線インピーダンスの低減効果に代えて、電源配線２５の形成面積を小さくすることも可能である。
なお、ＧＮＤビア３０による面積減少としては、各ＧＮＤビア３０には電源配線２５との短絡を回避するために、ビア径よりも大きな径のクリアランス２９（後述する）が形成されているため、クリアランス２９の面積分である。 Further, in the other wiring layers such as the first wiring layer 11, the second wiring layer 12, the fifth wiring layer 15, and the sixth wiring layer 16, the GND via 30 is not arranged in the vicinity of the power supply via 20. Since there is no via hole for the GND via 30, it is possible to suppress an increase in wiring impedance due to a decrease in wiring area.
That is, as shown in FIG. 2 (b), since the power supply wiring 25 formed in the fifth wiring layer 15 does not have an area reduction due to the GND via 30, the conventional power supply wiring shown in FIG. 4 (b). The wiring impedance can be reduced as compared with 125. Further, since the GND via 30 is not formed, it is possible to reduce the formation area of the power supply wiring 25 in place of the effect of reducing the wiring impedance.
As for the area reduction due to the GND via 30, each GND via 30 is formed with a clearance 29 (described later) having a diameter larger than the via diameter in order to avoid a short circuit with the power supply wiring 25. It is the surface integral of 29.

図３はプリント配線基板１の一部における各層を分解して表した斜視図である。
なお、図３では電源ビア２０とＧＮＤビア３０を複数配置した場合について示しているが、１例であり実際の数は、供給する電力によって設計される。また、第１〜第６の配線層１１〜１６及びコア層１０を示す領域は、図１で示した点線領域Ｐに対応した範囲を切り取って表したもので、実際にはより大きな広がりをもって形成されている。
第２配線層１２には、図３に示した領域内において、配線は形成されていない。 FIG. 3 is a perspective view showing each layer of a part of the printed wiring board 1 in an exploded manner.
Note that FIG. 3 shows a case where a plurality of power supply vias 20 and GND vias 30 are arranged, but this is an example, and the actual number is designed according to the power to be supplied. Further, the regions showing the first to sixth wiring layers 11 to 16 and the core layer 10 are represented by cutting out the range corresponding to the dotted line region P shown in FIG. 1, and are actually formed with a larger spread. Has been done.
No wiring is formed in the second wiring layer 12 in the region shown in FIG.

最初に各配線層に形成される配線について説明する。
第１配線層１１には、電源供給元回路５０に接続された電源配線２１（第１電源配線）と、電源供給先回路６０に接続された電源配線２２（第２電源配線）が形成されている。 First, the wiring formed in each wiring layer will be described.
In the first wiring layer 11, a power supply wiring 21 (first power supply wiring) connected to the power supply source circuit 50 and a power supply wiring 22 (second power supply wiring) connected to the power supply destination circuit 60 are formed. There is.

第３配線層１３と第４配線層１４のそれぞれには、電源供給元回路５０側にＧＮＤ配線３２（第１ＧＮＤ配線）とＧＮＤ配線３４（第２ＧＮＤ配線）が形成され、電源供給先回路６０側にＧＮＤ配線３３（第３ＧＮＤ配線）とＧＮＤ配線３５（第４ＧＮＤ配線）が形成されている。
各ＧＮＤ配線３２〜３５は、同一サイズに形成されると共に、矢印ｍで示すように、図３に示す領域外まで延長形成されている。但し、図３では同一方向に延長する場合について示しているが、実際には他の配線との関係で別々の方向に形成される場合もある。
各ＧＮＤ配線３２〜３５は、後述するようにコア層１０を貫通する電源ビア２０とＧＮＤビア３０が形成されるので、当該ビアの形成領域よりも広く形成されている。 In each of the third wiring layer 13 and the fourth wiring layer 14, a GND wiring 32 (first GND wiring) and a GND wiring 34 (second GND wiring) are formed on the power supply source circuit 50 side, and the power supply destination circuit 60 side. The GND wiring 33 (third GND wiring) and the GND wiring 35 (fourth GND wiring) are formed therein.
The GND wirings 32 to 35 are formed to have the same size and are extended to the outside of the region shown in FIG. 3 as shown by the arrow m. However, although FIG. 3 shows a case of extending in the same direction, it may actually be formed in different directions in relation to other wiring.
Since the power supply via 20 and the GND via 30 penetrating the core layer 10 are formed in each GND wiring 32 to 35 as described later, they are formed wider than the formation region of the via.

第５配線層１５には、図２（ａ）でも説明した電源配線２５が、電源ビア２０側からＧＮＤビア３０側にわたって形成されている。
この電源配線２５は、電源供給元回路５０側の電源配線２１を第５配線層１５に投影した投影領域と、電源供給先回路６０側の電源配線２２を第５配線層１５に投影した投影領域の両投影領域以上の領域を含み、両投影領域を接続する配線である。
なお、電源配線２５は、図３の表示領域内に形成されているが、この領域外に電力供給対象が存在する場合には、当該領域外まで延長形成するようにしてもよい。
本実施形態の第６配線層１６には、図３に示した領域内において配線は形成されていない。 In the fifth wiring layer 15, the power supply wiring 25 described in FIG. 2A is formed from the power supply via 20 side to the GND via 30 side.
The power supply wiring 25 has a projection area in which the power supply wiring 21 on the power supply source circuit 50 side is projected onto the fifth wiring layer 15, and a projection area in which the power supply wiring 22 on the power supply destination circuit 60 side is projected on the fifth wiring layer 15. It is a wiring that includes areas above both projection areas and connects both projection areas.
The power supply wiring 25 is formed in the display area of FIG. 3, but if a power supply target exists outside this area, it may be extended to the outside of the area.
No wiring is formed in the region shown in FIG. 3 in the sixth wiring layer 16 of the present embodiment.

図３に示すように、複数の電源ビア２０は、電源配線２１と電源配線２２のそれぞれから、第６配線層１６まで貫通して形成されている。
なお、電源ビア２０は、第３配線層１３と第４配線層１４に形成された各グランド配線３２〜３５を貫通するが、両者が短絡しないようにするためのクリアランス２９が設けられている。
クリアランス２９は、ビア孔の直径がＲ（例えば０．３ｍｍ）である場合に、これよりも僅かに大きい直径Ｒ＋α（例えば０．５ｍｍ）の無配線領域がＧＮＤ配線３２〜３５に形成される。
無配線領域は、例えば第３配線層１３のＧＮＤ配線３２、３３について説明すると次のように形成される。すなわち、ＧＮＤ配線３２、３３の対象領域外の領域と、対象領域内で各電源ビア２０に対応する直径Ｒ＋αの円形領域にマスクパターンを形成した後、銅めっきにより配線を形成する。その後、マスクパターンをリフトアップすることで、ＧＮＤ配線３２、３３とクリアランス２９が形成される。 As shown in FIG. 3, the plurality of power supply vias 20 are formed so as to penetrate from each of the power supply wiring 21 and the power supply wiring 22 to the sixth wiring layer 16.
The power supply via 20 penetrates the ground wirings 32 to 35 formed in the third wiring layer 13 and the fourth wiring layer 14, but is provided with a clearance 29 to prevent the two from being short-circuited.
In the clearance 29, when the diameter of the via hole is R (for example, 0.3 mm), a non-wiring region having a diameter R + α (for example, 0.5 mm) slightly larger than this is formed in the GND wirings 32 to 35.
The non-wiring region is formed as follows, for example, when the GND wirings 32 and 33 of the third wiring layer 13 are described. That is, after forming a mask pattern in a region outside the target region of the GND wirings 32 and 33 and a circular region having a diameter R + α corresponding to each power supply via 20 in the target region, the wiring is formed by copper plating. After that, by lifting up the mask pattern, the GND wirings 32 and 33 and the clearance 29 are formed.

一方、複数のＧＮＤビア３０は、第３層のＧＮＤ配線３２とＧＮＤ配線３３のそれぞれから、コア層１０を貫通して第４層のＧＮＤ配線３４とＧＮＤ配線３５まで貫通して形成されている。
図３に示すように、複数のＧＮＤビア３０のそれぞれは、複数の電源ビア２０に対して交互に並べて近接配置されている。 On the other hand, the plurality of GND vias 30 are formed from each of the GND wiring 32 and the GND wiring 33 of the third layer, penetrating the core layer 10 and penetrating the GND wiring 34 and the GND wiring 35 of the fourth layer. ..
As shown in FIG. 3, each of the plurality of GND vias 30 is arranged in close proximity to the plurality of power supply vias 20 in an alternating manner.

本実施形態のプリント配線基板１によれば、電源供給元回路５０からの電流Ｉは、電源配線２１から電源ビア２０を通り、第５配線層１５に形成された電源配線２５を経由して、電源ビア２０を通り、電源配線２２から電源供給先回路６０に供給される。
この電流Ｉの流れにおいて、コア層１０を挟む第３配線層１３と第４配線層１４の間で電源ビア２０とＧＮＤビア３０が近接配置されることで、図２で説明したように、配線インダクタンスが低減される。
また、ＧＮＤビア３０の形成がコア層１０を含む（挟む）第３配線層１３と第４配線層１４間に限定されているので、第５層の電源配線２５の面積が狭くならず、その結果配線インピーダンスを下げることができる。なお、配線インピーダンスをそのままとし、その代わりに電源配線の面積を小さくすることで、他の配線用の領域を広く確保するようにしてもよい。 According to the printed wiring board 1 of the present embodiment, the current I from the power supply source circuit 50 passes from the power supply wiring 21 through the power supply via 20 and via the power supply wiring 25 formed in the fifth wiring layer 15. It passes through the power supply via 20 and is supplied from the power supply wiring 22 to the power supply destination circuit 60.
In the flow of the current I, the power supply via 20 and the GND via 30 are arranged close to each other between the third wiring layer 13 and the fourth wiring layer 14 sandwiching the core layer 10, so that wiring is performed as described with reference to FIG. Inductance is reduced.
Further, since the formation of the GND via 30 is limited between the third wiring layer 13 including (sandwiching) the core layer 10 and the fourth wiring layer 14, the area of the power supply wiring 25 of the fifth layer is not narrowed, and the area thereof is not narrowed. As a result, the wiring impedance can be lowered. It should be noted that the wiring impedance may be left as it is, and instead, the area of the power supply wiring may be reduced to secure a wide area for other wiring.

以上本実施形態のプリント配線基板１について説明したが、本発明は本実施形態に限定されず各種変形することが可能である。
例えば、説明した実施形態では、配線層を６層としたが、８層としてもよい。すなわち、第１配線層から第ｍ配線層と、第ｍ＋１から第ｎ配線層において、ｍ＝３、ｎ＝６としたが、ｍ＝４、ｎ＝８としてもよく、それ以上であってもよい。層数ｎとｍの関係については、ビルドアップ法によるプリント配線基板である場合にはｍ＝ｎ／２であるが、配線が形成された絶縁層をプリプレグで接着することで配線を積層したプリント配線基板の場合には、ｍ≠ｎ／２であってもよい。 Although the printed wiring board 1 of the present embodiment has been described above, the present invention is not limited to the present embodiment and can be variously modified.
For example, in the described embodiment, the wiring layer is 6 layers, but 8 layers may be used. That is, in the first wiring layer to the m wiring layer and from the m + 1 to the nth wiring layer, m = 3 and n = 6, but m = 4 and n = 8 may be set, and even more than that. good. Regarding the relationship between the number of layers n and m, m = n / 2 in the case of a printed wiring board by the build-up method, but the printed wiring is laminated by adhering the insulating layer on which the wiring is formed with a prepreg. In the case of a wiring board, m ≠ n / 2 may be set.

また説明した実施形態では、第５配線層１５に電源配線２５を形成する場合を一例として説明したが、これらの配線は、第１配線層１１、第３配線層１３と第４配線層１４を除く他の配線層に配置するようにしてもよい。 Further, in the described embodiment, the case where the power supply wiring 25 is formed on the fifth wiring layer 15 has been described as an example, but these wirings include the first wiring layer 11, the third wiring layer 13, and the fourth wiring layer 14. It may be arranged in another wiring layer except.

また、説明した実施形態では、コア層１０を挟む第３配線層１３と第４配線層１４の間で電源ビア２０とＧＮＤビア３０を近接配置し、他の配線層間では隔離配置される場合について説明した。
これに対して、コア層１０に形成したＧＮＤビア３０を、同軸上で更に、第３配線層１３、第４配線層１４以外の配線層まで延長形成するようにしてもよい。この場合、ＧＮＤビア３０を延長形成するための条件としては、延長した途中や端部の配線層において、電源ビア２０とＧＮＤビア３０が形成される領域内に、他のＧＮＤ配線や電源配線が存在しないことが条件である。
すなわち、第ｑ配線層（２≦ｑ≦ｍ−２、又は、ｍ＋２≦ｑ≦ｎ）に電源配線又はＧＮＤ配線が形成されている場合、第ｑ＋１（ｑ≦ｍ−２の場合）配線層まで、又は、第ｑ−１（ｍ＋３≦ｑの場合）配線層まで、ＧＮＤビア３０を延長形成する。そして、ＧＮＤビア３０用のＧＮＤ配線を、第ｍ配線層、第ｍ＋１配線層ではなく、延長形成したＧＮＤビア３０の両端が位置する配線層（第ｑ＋１配線層、又は／及び、第ｑ−１配線層）に形成する。
これにより、電源配線やＧＮＤ配線の配線インピーダンスを下げると共に、配線インダクタンスをより下げることができる。 Further, in the above-described embodiment, the power supply via 20 and the GND via 30 are arranged close to each other between the third wiring layer 13 and the fourth wiring layer 14 sandwiching the core layer 10, and are isolated between the other wiring layers. explained.
On the other hand, the GND via 30 formed on the core layer 10 may be further extended coaxially to the wiring layers other than the third wiring layer 13 and the fourth wiring layer 14. In this case, as a condition for extending the GND via 30, another GND wiring or a power supply wiring is provided in the region where the power supply via 20 and the GND via 30 are formed in the wiring layer in the middle of the extension or at the end. The condition is that it does not exist.
That is, when the power supply wiring or the GND wiring is formed in the qth wiring layer (2≤q≤m-2 or m + 2≤q≤n), up to the q + 1 (in the case of q≤m-2) wiring layer. , Or, the GND via 30 is extended to the q-1th (in the case of m + 3 ≦ q) wiring layer. Then, the GND wiring for the GND via 30 is not the mth wiring layer and the m + 1th wiring layer, but the wiring layer (q + 1 wiring layer or / and the q-1th) in which both ends of the GND via 30 are extended and formed. It is formed in the wiring layer).
As a result, the wiring impedance of the power supply wiring and the GND wiring can be lowered, and the wiring inductance can be further lowered.

例えば、図３において、電源配線２５を、第５配線層１５ではなく第６配線層１６に形成した場合（ｑ＝６の場合）、ＧＮＤビア３０を第３配線層１３から第５配線層（＝ｑ−１配線層）１５まで貫通形成する。すなわち、ＧＮＤビア３０を、第４配線層１４から第５配線層１５まで延長形成する。
そして、第４配線層に形成したＧＮＤ配線３４、３５を延長先の第５配線層１５に形成する。
これにより、電源配線２５の配線インピーダンスを実施形態と同様に下げると共に、配線インダクタンスを実施形態よりも下げることができる。 For example, in FIG. 3, when the power supply wiring 25 is formed on the sixth wiring layer 16 instead of the fifth wiring layer 15 (when q = 6), the GND via 30 is formed on the third wiring layer 13 to the fifth wiring layer (when q = 6). = Q-1 wiring layer) Through formation up to 15. That is, the GND via 30 is extended from the fourth wiring layer 14 to the fifth wiring layer 15.
Then, the GND wirings 34 and 35 formed in the fourth wiring layer are formed in the fifth wiring layer 15 to be extended.
As a result, the wiring impedance of the power supply wiring 25 can be lowered as in the embodiment, and the wiring inductance can be lowered as compared with the embodiment.

また、図３において、第１配線層１１に電源配線２１が形成され、第２配線層１２には配線（電源配線、ＧＮＤ配線を含む）が形成されていないので、ＧＮＤビア３０を第３配線層１３から第２配線層１２まで延長形成するようにしてもよい。
そして、ＧＮＤ配線３２、３３を第３配線層１３ではなく、第２配線層１２に形成する。
この場合にも、電源配線２５の配線インピーダンスを実施形態と同様に下げると共に、配線インダクタンスを実施形態よりも下げることができる。 Further, in FIG. 3, since the power supply wiring 21 is formed in the first wiring layer 11 and the wiring (including the power supply wiring and the GND wiring) is not formed in the second wiring layer 12, the GND via 30 is connected to the third wiring. The extension may be formed from the layer 13 to the second wiring layer 12.
Then, the GND wirings 32 and 33 are formed not on the third wiring layer 13 but on the second wiring layer 12.
Also in this case, the wiring impedance of the power supply wiring 25 can be lowered as in the embodiment, and the wiring inductance can be lowered as compared with the embodiment.

１プリント配線基板
１０コア層
１１〜１６第１配線層〜第６配線層
２０電源ビア
２１、２２、２５電源配線
２９クリアランス
３０ＧＮＤビア
３２〜３５ＧＮＤ配線
５０電源供給元回路
６０電源供給先回路 1 Printed wiring board 10 Core layer 11-16 1st wiring layer to 6th wiring layer 20 Power supply via 21, 22, 25 Power supply wiring 29 Clearance 30 GND via 32 to 35 GND wiring 50 Power supply source circuit 60 Power supply destination circuit

Claims

With the core layer
From the first wiring layer to the m wiring layer formed on one surface side of the core layer,
From the m + 1 wiring layer formed on the other surface side of the core layer to the nth wiring layer,
The first power supply wiring formed in the first wiring layer to which the power supply source circuit is connected and
The second power supply wiring formed in the first wiring layer to which the power supply destination circuit is connected and
A third wiring layer formed in any of the nth wiring layers from the second wiring layer, including a projection area of the first power supply wiring and a projection area of the second power supply wiring, and connecting both projection areas. Power wiring and
A plurality of first power supply vias penetrating at least the core layer from the first power supply wiring and penetrating the m + 1 wiring layer and the wiring layer located on the nth wiring layer side of the third power supply wiring.
A plurality of second power supply vias that penetrate at least the core layer from the second power supply wiring and penetrate to the m + 1 wiring layer and the wiring layer located on the nth wiring layer side of the third power supply wiring .
A plurality of first 1GND vias through said core layer,
A plurality of second GND vias penetrating the core layer,
The first GND wiring and the second GND wiring formed in the wiring layer where both ends of the first GND via correspond to the region including the projection region of the first power supply wiring.
The third GND wiring and the fourth GND wiring formed in the wiring layer where both ends of the second GND via correspond to the region including the projection region of the second power supply wiring.
Equipped with
The first power supply via and the first GND via, and the second power supply via and the second GND via are arranged close to each other at least between the m wiring layer including the core layer and the m + 1 wiring layer.
The first GND via and the second GND via do not penetrate the wiring layer in which the third power supply wiring is formed.
A GND via different from the first GND via and the second GND via is isolated from the first power supply via and the second power supply via in the wiring layer where the first GND via and the second GND via do not penetrate. Yes,
A printed wiring board characterized by that.

With the core layer
From the first wiring layer to the m wiring layer formed on one surface side of the core layer,
From the m + 1 wiring layer formed on the other surface side of the core layer to the nth wiring layer,
The first power supply wiring formed in the first wiring layer to which the power supply source circuit is connected and
The second power supply wiring formed in the first wiring layer to which the power supply destination circuit is connected and
A third wiring layer formed in any of the nth wiring layers from the second wiring layer, including a projection area of the first power supply wiring and a projection area of the second power supply wiring, and connecting both projection areas. Power wiring and
A plurality of first power supply vias penetrating at least the core layer from the first power supply wiring and penetrating the m + 1 wiring layer and the wiring layer located on the nth wiring layer side of the third power supply wiring.
A plurality of second power supply vias that penetrate at least the core layer from the second power supply wiring and penetrate to the m + 1 wiring layer and the wiring layer located on the nth wiring layer side of the third power supply wiring.
A plurality of first GND vias penetrating the core layer,
A plurality of second GND vias penetrating the core layer,
The first GND wiring and the second GND wiring formed in the wiring layer where both ends of the first GND via correspond to the region including the projection region of the first power supply wiring.
The third GND wiring and the fourth GND wiring formed in the wiring layer where both ends of the second GND via correspond to the region including the projection region of the second power supply wiring.
Equipped with
The first power supply via and the first GND via, and the second power supply via and the second GND via are arranged close to each other at least between the m wiring layer including the core layer and the m + 1 wiring layer.
GND vias different from the first GND via and the second GND via are arranged separately from the first power supply via and the second power supply via in the other wiring layers.
The first GND via and the second GND via are formed only between the m wiring layer including the core layer and the m + 1 wiring layer.
A printed wiring board characterized by that.

With the core layer
From the first wiring layer to the m wiring layer formed on one surface side of the core layer,
From the m + 1 wiring layer formed on the other surface side of the core layer to the nth wiring layer,
The first power supply wiring formed in the first wiring layer to which the power supply source circuit is connected and
The second power supply wiring formed in the first wiring layer to which the power supply destination circuit is connected and
A third wiring layer formed in any of the nth wiring layers from the second wiring layer, including a projection area of the first power supply wiring and a projection area of the second power supply wiring, and connecting both projection areas. Power wiring and
A plurality of first power supply vias penetrating at least the core layer from the first power supply wiring and penetrating the m + 1 wiring layer and the wiring layer located on the nth wiring layer side of the third power supply wiring.
A plurality of second power supply vias that penetrate at least the core layer from the second power supply wiring and penetrate to the m + 1 wiring layer and the wiring layer located on the nth wiring layer side of the third power supply wiring.
A plurality of first GND vias penetrating the core layer,
A plurality of second GND vias penetrating the core layer,
The first GND wiring and the second GND wiring formed in the wiring layer where both ends of the first GND via correspond to the region including the projection region of the first power supply wiring.
The third GND wiring and the fourth GND wiring formed in the wiring layer where both ends of the second GND via correspond to the region including the projection region of the second power supply wiring.
Equipped with
The first power supply via and the first GND via, and the second power supply via and the second GND via are arranged close to each other at least between the m wiring layer including the core layer and the m + 1 wiring layer.
The first GND via and the second GND via penetrate to the inner wiring layer of the wiring layer on which the third power supply wiring is formed, which is one inside from the core layer.
A GND via different from the first GND via and the second GND via is isolated from the first power supply via and the second power supply via in the wiring layer where the first GND via and the second GND via do not penetrate. Yes,
A printed wiring board characterized by that.

A plurality of elements are arranged in the printed wiring board, and wiring connecting each element is formed in the wiring layer.
The printed wiring board according to claim 1, claim 2, or claim 3.

The first power supply via and the first GND via are alternately arranged side by side in close proximity to each other.
The second power supply via and the second GND via are alternately arranged side by side in close proximity to each other.
The printed wiring board according to claim 1, wherein the printed wiring board is characterized in that.