JP6984762B2 - Arithmetic processing unit and control method of arithmetic processing unit - Google Patents

Description

The present invention relates to an arithmetic processing unit and a control method for the arithmetic processing unit.

Deep learning, which is becoming more important these days, requires a huge amount of calculation and memory consumption. When the amount of calculation and the amount of memory consumed increase, the calculation load and the memory load increase, and the learning time becomes long. Therefore, in order to reduce the amount of calculation and memory consumption and shorten the learning time, it is desirable to use a method of performing calculation with the lowest possible accuracy while maintaining learning and inference ability. In such a method, an operation using a fixed point is often performed.

However, as a problem raised when the calculation is performed with low accuracy, the rounded value of the calculation result tends to be biased to a certain fixed value with low accuracy. If the rounded values are biased, there is a problem that learning does not proceed easily from that point.

In order to eliminate the value bias in such low accuracy, there is a conventional technique that introduces stochastic rounding. This is the probability according to the value lower than the digit to be rounded in the calculation result before rounding, and the rounded value is either a truncated value or a value obtained by adding 1 to the rounded value. It is a technique to make the expected value of the rounding result equal to the value before rounding by selecting. For example, when the calculation result 1.8 is rounded to an integer, if probabilistic rounding is used, 2 is obtained with a probability of 80% and 1 is obtained with a probability of 20% as the rounding result. As a result, the expected value of the rounding result is 1.8, which is the same as the value before rounding.

Here, in deep learning, product-sum accumulation operations are often used for matrix elements. The product-sum accumulation operation is an operation in the form of C'= C + A × B, and is an operation in which the product of the next element is accumulated in the calculation result up to a certain point in time. At this time, while the cumulative operation is continued, the cumulative result is generally held at a value having a accuracy considerably higher than the number of inputs to the multiplication. For example, when A and B, which are the number of inputs to multiplication in the above equation, are 16 bits wide, A × B, which is the result of multiplication, is 32 bits. At this time, the cumulative register that stores the cumulative result of the multiplication result is preferably large enough to store the cumulative result of the 32-bit value, and may be, for example, 40 bits wide.

From the above, when the multiplication result is rounded, the accuracy may be significantly reduced. Therefore, in the hardware that executes deep learning, a process is performed in which the result of the product-sum cumulative operation, which has more bits than the number of inputs to multiplication, is probabilistically rounded and the result is output with low accuracy. Is desirable.

When performing rounding, there is a method of adding some number to the lower digit that will be discarded by rounding to generate a carry when desired, and obtaining the desired rounding result in the upper digit depending on the rounding position. .. This method is also effective in stochastic rounding. Therefore, a conventional technique has been proposed in which probabilistic rounding is performed by adding to the lower digits by utilizing the addition circuit in the product-sum calculator. Further, there is a conventional technique of adding the output from the random noise circuit to the fractional part of the data and executing the rounding process. Further, as a device for rounding the cumulative register, there is a conventional technique in which a rounding circuit receives a value from a random number generator and uses it for determining rounding.

U.S. Patent Application Publication No. 2017/0220341 U.S. Patent Application Publication No. 2017/01029220 Japanese Unexamined Patent Publication No. 03-63722 Japanese Patent Publication No. 2004-506365

However, in the prior art using an adder circuit in a multiply-accumulate calculator for stochastic rounding, rounding is performed on the multiplication result. As mentioned earlier, the bit width of the input value to the multiplication result is generally much narrower than the bit width of the cumulative register of the multiplication result. Therefore, rounding the value of the cumulative register with low precision by rounding the multiplication result may result in an inappropriate rounding value. Further, in the conventional technique of making the rounding circuit judge the rounding by using the value obtained from the random number generator, a large-scale modification to the rounding circuit is added. Rounding by the rounding circuit has a critical path for floating point arithmetic. Therefore, if a large-scale modification is made to the rounding circuit for probabilistic rounding, it may cause a deterioration in the delay of the critical path of the existing operation. That is, it is difficult to make a large-scale modification to the floating-point multiply-accumulate unit.

The disclosed technique has been made in view of the above, and an object of the present invention is to provide an arithmetic processing unit and a control method of the arithmetic processing unit that execute appropriate stochastic rounding with a simple configuration.

In one embodiment of the arithmetic processing unit and the control method of the arithmetic processing unit disclosed in the present application, the random number generation unit generates a random number. The random number moving unit moves the position of the random number so that the head of the random number coincides with the rounding position of the number of rounding targets based on the position where the number of rounding targets is arranged and the decimal point position information of the output data. The adding unit adds the random number moved by the random number moving unit and the number of rounding targets arranged at the predetermined positions. The output unit outputs data in a predetermined range including significant digits of a predetermined digit from the rounding position in the addition result by the addition unit as the output data.

In one aspect, the invention can perform appropriate stochastic rounding with a simple configuration.

FIG. 1 is a diagram showing an overall configuration diagram of an information processing apparatus. FIG. 2 is a circuit diagram of a product-sum calculator. FIG. 3 is a diagram showing an outline of the calculation of the stochastic rounding process by the product-sum calculator according to the embodiment. FIG. 4 is a diagram for explaining the digit alignment shift of random numbers. FIG. 5 is a diagram for explaining the alignment of the added value by the normalized shifter. FIG. 6 is a diagram showing a specific example of the stochastic rounding process. FIG. 7 is a flowchart of the entire process executed by the product-sum calculation unit. FIG. 8 is a flowchart of the stochastic rounding process by the product-sum calculator according to the embodiment.

Hereinafter, examples of the arithmetic processing unit and the control method of the arithmetic processing unit disclosed in the present application will be described in detail with reference to the drawings. The following embodiments do not limit the arithmetic processing unit and the control method of the arithmetic processing unit disclosed in the present application.

FIG. 1 is an overall configuration diagram of an information processing device. The information processing apparatus 50 includes a PCI (Peripheral Component Interconnect) card 1 and a host computer 2. The PCI card 1 and the host computer 2 are connected by a PCI bus, and data is transmitted to and received from each other.

The host computer 2 performs overall management, for example, when performing deep learning. When executing deep learning, the host computer 2 instructs the PCI card 1 to execute a predetermined operation in deep learning such as a convolution operation.

The PCI card 1 receives an instruction from the host computer 2, executes an operation, and outputs the operation result to the host computer 2. As shown in FIG. 1, the PCI card 1 has a plurality of processing units 10, an overall instruction control unit 11, a memory controller 12, a memory 13, and a PCI control unit 14. This PCI card 1 corresponds to an example of a "arithmetic processing unit".

The PCI control unit 14 receives from the host computer 2 an operation command instructing execution of an operation and an input of operation data used in the operation. Then, the PCI control unit 14 outputs the acquired calculation instruction and calculation data to the memory controller 12.

Further, the PCI control unit 14 receives the input of the calculation result for the instructed calculation from the memory controller 12. Then, the PCI control unit 14 outputs the calculation result to the host computer 2. Specifically, the PCI control unit 14 issues an instruction to read the calculation result in the memory 13 to the memory controller 12, and outputs the read data to the host computer 2 via self-confidence.

The memory controller 12 receives input of calculation instructions and calculation data used in the calculation from the PCI control unit 14. Then, the memory controller 12 stores the acquired calculation instruction and calculation data in the memory 13.

Further, the memory controller 12 receives an instruction from the general instruction control unit 11 to store the calculation data used when executing the calculation in the vector register 111. Then, the memory controller 12 stores the designated arithmetic data in the designated vector register 111. Here, when the memory controller 12 transmits data to the processing unit 10 in the subsequent stage among the processing units 10 arranged in series, the memory controller 12 bypasses the product-sum calculation unit 100 and outputs the calculation data to the multiplexer 103.

Further, when the operation is completed, the whole instruction control unit 11 receives a notification of the completion of the operation from the whole instruction control unit 11 and instructs the memory controller 12 by a predetermined instruction to serialize the operation result in the vector register 111. A chain of processing units 10 arranged in line with each other is pulled out and stored in the memory 13.

The general instruction control unit 11 manages the entire operation instructed to be executed by the host computer 2. The general instruction control unit 11 receives an instruction from the host computer 2 via the PCI control unit 14, reads the entire instruction sequence stored in the memory 13 one after another, and executes the instruction. The whole instruction includes an instruction to transfer an operation instruction sequence from the memory 13 to the operation instruction buffer 102, an instruction to store operation data from the memory 13 in the vector register 111, and an operation instruction sequence stored in the operation instruction buffer 102 to control the operation instruction. There are an instruction to start execution in the unit 101, an instruction to store the operation result stored in the vector register 111 in the memory 13, an instruction to end the execution of the instruction sequence, and the like.

The general instruction control unit 11 causes the processing unit 10 to execute the operation instruction sequence. When the processing unit is made to execute the calculation, the general instruction control unit 11 instructs the memory controller 12 to acquire the calculation data used when executing the calculation. Further, when the calculation in the processing unit 10 is completed, the general instruction control unit 11 instructs the memory controller 12 to store the calculation result. Further, when all the processing of the operation instructed to be executed is completed, the general instruction control unit 11 notifies the memory controller 12 of the completion of the operation.

Next, the processing unit 10 will be described. As shown in FIG. 1, a plurality of processing units 10 are mounted on one PCI card 1. A plurality of each processing unit 10 are connected in parallel and in series. The number of processing units 10 is 128 in a certain sun. The processing unit 10 includes a product-sum calculation unit 100, a calculation instruction control unit 101, a calculation instruction buffer 102, and a multiplexer 103.

The arithmetic instruction control unit 101 manages and controls the execution processing of the arithmetic instruction. The arithmetic instruction control unit 101 receives an instruction to execute the arithmetic instruction sequence from the general instruction control unit 11. Here, the instruction that can be executed by the processing unit 10 is called an arithmetic instruction in comparison with the whole instruction. The instruction includes an arithmetic instruction in a narrow sense that causes the product-sum calculation unit to perform an operation, and a general-purpose register (illustrated). Operation instructions, branch instructions, repeat instructions, instructions to stop the execution of the instruction sequence, etc. are included.

Then, the arithmetic instruction control unit 101 sequentially acquires the arithmetic instructions stored in the arithmetic instruction buffer 102. Next, the operation instruction control unit 101 instructs the vector register 111 to output the operation data specified by the acquired operation instruction. Further, the arithmetic instruction control unit 101 outputs an instruction to execute the arithmetic to the multiply-accumulate arithmetic unit 112 according to the acquired arithmetic instruction. After that, the arithmetic instruction control unit 101 loops the arithmetic using the arithmetic result in the multiply-accumulate arithmetic unit 112.

Then, when the operation is completed, the operation instruction control unit 101 performs a product-sum operation together with an instruction to execute the probabilistic rounding process and the decimal point position information which is information indicating which bit of the cumulative register is set as the output decimal point position. Output to the device 112. The decimal point position information represents the decimal point position calculated from the learning result so as to keep the weight parameter of each layer in the neural network as effective as possible within the range of the operable bit width. This value is a value determined in the process of executing the deep learning program, and is a variable value for the information processing apparatus 50. After that, when instructed by the memory controller 12, the calculation result of the stochastic rounding process stored in the vector register 111 is stored in the memory 13 via the chain of the processing unit and the memory controller 12.

The arithmetic instruction control unit 101 is, for example, VECTOR. h. Issue instructions such as accstrnd ELE #, QNUM, and DST #. Here, QNUM represents decimal point position information. Further, ELE # is a number indicating which element is to be stochastically rounded when there are registers of a plurality of elements in the multiply-accumulate arithmetic unit 112. DST # represents the number of the register that stores the result of stochastic rounding. When this instruction is executed, the bit range corresponding to the QNUM of the element of the fixed-point cumulative register specified by ELE # is probabilistically rounded based on the value lower than the specified range, and the result is fixed-point. The value is stored in the register specified by DST #.

The operation instruction buffer 102 is a storage area for storing an operation instruction sequence. The arithmetic instruction buffer 102 stores the arithmetic instruction sequence input from the memory controller 12 in the order of input from the instructed address. After that, in response to the operation instruction acquisition request from the operation instruction control unit 101, the operation instruction buffer 102 outputs the operation instruction of the requested address to the operation instruction control unit 101.

The product-sum calculation unit 100 has a vector register 111 and a product-sum calculation unit 112. However, the vector register 111 included in the product-sum calculation unit 100 corresponds to a part of the entire vector register mounted on the processing unit 10.

The vector register 111 receives the input of the calculation data used when executing the calculation from the memory controller 12, and stores the input calculation data. After that, the vector register 111 receives an instruction from the arithmetic instruction control unit 101 and outputs the arithmetic data used in the arithmetic to the multiply-accumulate arithmetic unit 112. Further, in the case of the product-sum accumulation operation, after the loop processing of the operation by the product-sum calculation unit 112 is completed, the vector register 111 receives the input of the calculation result subjected to the stochastic rounding processing from the product-sum calculation unit 112. Then, when an instruction to output to the memory 13 is received from the memory controller 12, the vector register 111 outputs the calculation result of the product-sum calculation unit 112 to which the stochastic rounding process is performed to the multiplexer 103.

The product-sum calculation unit 112 receives an instruction to execute a calculation from the calculation instruction control unit 101. Then, the product-sum calculation unit 112 executes the product-sum calculation using the calculation data input from the vector register 111. After that, the product-sum calculation unit 112 outputs the calculation result to the vector register 111. When the cumulative operation is instructed by the instruction, the multiply-accumulate operation unit 112 holds the cumulative operation result in a register (accumulator) in the operation unit and uses it in the subsequent cumulative operation instruction. The product-sum calculator 112 repeats the product-sum operation on the value input from the vector register 111 until the product-sum cumulative operation is completed.

After that, when the loop processing of the product-sum accumulation operation is completed, the product-sum calculation unit 112 receives an instruction to execute the stochastic rounding process from the operation instruction control unit 101. At that time, the multiply-accumulate arithmetic unit 112 receives the input of the decimal point position information from the arithmetic instruction control unit 101. Then, the multiply-accumulate arithmetic unit 112 uses a circuit that performs the product-sum operation as the stochastic rounding target number, which is held in the internal register, as the calculation result for which the loop processing is completed. Perform rounding. After that, the product-sum calculation unit 112 outputs the calculation result after the stochastic rounding process to the vector register 111 and stores it.

Here, with reference to FIG. 2, the function of performing the stochastic rounding of the multiply-accumulate calculator 112 will be described in detail. FIG. 2 is a circuit diagram of a product-sum calculator.

The product-sum calculation unit 112 includes a random number generation circuit 121, a power generation unit 122, a multiplexer 123 and 124, a multiplier 125, an exponential code calculation unit 126, a digit shifter 127, a multiplexer 128, and an adder 129. Further, the multiply-accumulate arithmetic unit 112 includes a fixed-point register 130, a digit loss prediction unit 131, a shift amount calculation unit 132, a multiplexer 133, a normalized shifter 134, and a rounding circuit 135. Here, the multiply-accumulate calculator 112 performs two processes, that is, an actual arithmetic process requested by the host computer 2 such as convolution, and a process of calculating a stochastic rounding value of the arithmetic result. Therefore, the actual operation process is called an actual operation, and the process of calculating the stochastic rounding value of the operation result is called a stochastic rounding process.

The operation of each part in the actual calculation will be described. In the case of an actual operation, the multiplexer 124 receives an input of one of the operation data to be multiplied. Further, the multiplexer 123 receives the input of the other arithmetic data to be multiplied. In this case, the multiplexers 123 and 124 output the arithmetic data to the multiplier 125. The multiplier 125 multiplies the two arithmetic data input from the multiplexers 123 and 124. Then, the multiplier 125 outputs the multiplication result to the adder 129.

On the other hand, the exponential code calculation unit 126 receives inputs of three calculation data used for the actual calculation from the vector register 111. Then, the exponential code calculation unit 126 calculates a shift amount for digitizing the mantissa of the product and the addition when the operation instruction is a floating-point product-sum operation. In the case of a fixed-point arithmetic instruction, the exponential code arithmetic unit 126 calculates the shift amount for digit matching. In the case of a fixed-point arithmetic instruction, the exponential code arithmetic unit 126 sets a constant built in the hardware in advance so that the digit of the multiplication result matches the digit of the multiplication result as the shift amount of the digit shifter. Further, the exponential code calculation unit 126 calculates the code of the calculation result. Then, the exponential code calculation unit 126 performs a shift amount for digitizing the remaining calculation data other than the calculation data input to the multiplexers 123 and 124, the calculation data (addition), and the multiplication result of the multiplier 125. Output to the digit shifter 127.

Further, when the operation instruction is a floating-point product-sum operation, the exponential code calculation unit 126 receives an input of a digit loss amount prediction result from the digit loss amount prediction unit 131. Then, the exponential code calculation unit 126 calculates the left shift amount used for normalizing the mantissa of the calculation result from the acquired digit loss amount. Normalization of the mantissa is to adjust (shift) the bit position of the entire mantissa so that the most significant digit of the mantissa is 1. After that, the exponential code calculation unit 126 outputs the calculated left shift amount to the multiplexer 133.

The digit loss amount obtained by the digit loss amount prediction unit 131 may include an error within a fixed range from the true digit loss amount depending on the circuit configuration. By seeing whether or not the mantissa is normalized correctly as a result of shifting the specified amount in the normalized shifter 134, it is possible to know whether or not there is an error in the predicted loss amount. If the normalized shifter 134 finds that there is an error in the amount of loss of digits, it makes an additional shift for adjustment and notifies the exponential code calculation unit that there is an error in the prediction. When the index code calculation unit 126 receives the error notification from the normalization shifter 134, the exponential code calculation unit 126 calculates an exponent in consideration of an additional shift for error adjustment. On the other hand, when the normalization shifter 134 does not receive the notification with an error, the exponential code calculation unit 126 calculates the exponent when there is no additional shift. Further, the exponential code calculation unit 126 receives a notification from the rounding circuit 135 when a carry occurs due to rounding of the mantissa, and adjusts the exponent. The exponential code calculation unit 126 outputs the finally obtained code and exponent, and concatenates this with the rounding result of the mantissa output from the rounding circuit 135, which will be described later, to complete the floating-point arithmetic result. The calculation result is output to the vector register 111.

The digit shifter 127 shifts the calculation data input from the exponential code calculation unit 126 by the shift amount specified by the exponential code calculation unit 126. Then, the calculated data obtained by digit matching is output to the multiplexer 128.

The multiplexer 128 selects the input from the digit shifter 127 for floating point real operations. In the fixed-point cumulative operation, if the number is in the middle of accumulation, the number to be added does not need to be digit-adjusted, so the input from the fixed-point register 130 is selected. In the fixed-point cumulative operation, in the case of the first accumulation, the input from the digit shifter 127 is selected in order to select the number input to the multiply-accumulate unit 112 from the vector register 111 as an addition. Then, the multiplexer 128 outputs the arithmetic data input from the digit shifter 127 to the adder 129.

The adder 129 receives the input of the multiplication result of the two arithmetic data from the multiplier 125. Further, the adder 129 receives the input of the remaining arithmetic data (adder) digitized from the multiplexer 128. Then, the adder 129 adds the multiplication result of the two arithmetic data and the remaining arithmetic data (addition) digitized. Then, the adder 129 outputs the addition result to the normalized shifter 134 and the digit loss prediction unit 131. Here, the adder 129 actually uses two numbers of the addition result signal and the carry signal to perform a two-step addition of carry-save addition and carry propagation addition, but in this embodiment, this 2 is performed. The sum of the steps of addition is simply called addition. Then, in reality, the adder 129 outputs the result of the carry-save storage addition to the carry-down amount prediction unit 131.

The digit loss prediction unit 131 receives the input of the result during addition from the adder 129. Then, the digit loss prediction unit 131 predicts the digit loss amount from the acquired addition intermediate result. After that, the digit loss prediction unit 131 outputs the predicted digit loss amount to the exponential code calculation unit 126.

In the case of an actual operation, the multiplexer 133 selects an input from the exponential code calculation unit 126. Then, the multiplexer 133 outputs the left shift amount input from the exponential code calculation unit 126 to the normalized shifter 134.

The normalized shifter 134 receives an input of the addition result from the adder 129. Further, the normalized shifter 134 receives an input of a left shift amount from the multiplexer 133. Then, the normalized shifter 134 shifts the addition result to the left according to the input left shift amount and adjusts the output position. After that, the normalized shifter 134 outputs the operation result shifted to the left to the rounding circuit 135. Here, if it is found that there is an error in the prediction of the amount of digit loss due to the alignment by the left shift, the normalized shifter 134 performs an additional shift for error adjustment and notifies the exponential code calculation unit 126 of the error. Send.

The rounding circuit 135 receives the input of the calculation result from the normalized shifter 134. Then, the rounding circuit 135 performs rounding in a predetermined number of digits. After that, the rounding circuit 135 outputs the calculation result rounded by a predetermined digit to the vector register 111.

Next, the operation of each part in the stochastic rounding process will be described. In the case of the stochastic rounding process, the random number generation circuit 121 generates an n-bit uniform random number. Then, the random number generation circuit 121 outputs the generated random number to the multiplexer 123. Here, the random number generated by the random number generation circuit 121 does not have to be a truly uniform random number, but may be a pseudo-random number within a range that can withstand practical use.

The random number generation circuit 121 uses, for example, an LFSR (Linear Feedback Shift Register) arranged in the product-sum calculator 112. For example, when the LFSR is used, in this embodiment, the internal state of the LFSR is updated every time the stochastic rounding instruction is executed, and the LFSR outputs a new random number value when the next stochastic rounding instruction is issued.

However, the random number generation circuit 121 is not limited to the LFSR, and may be a pseudo-random number generation circuit having higher randomness, or a circuit that acquires random bits from fluctuations in the environment. Further, the random number generation circuit 121 may be a circuit attached to each product-sum calculation unit 112, or may be a circuit shared by a plurality of product-sum calculation units 112. This random number generation circuit 121 corresponds to an example of a “random number generation unit”.

Here, how to select the number of bits of a random number will be described. When rounding is performed stochastically, the value of the bit lower than the rounding position in the number of stochastic rounding targets is finally discarded. For example, when the number of bits of a random number is n and the number of bits to be discarded is m, if the random number is uniform, and if n is the same as or more than m, the expected value after stochastic rounding is stochastic. The value can be equal to the number of rounding targets. However, even when m is large, if the relationship of n ≧ m is to be maintained, the number of bits to be calculated increases, and the circuit for performing digit matching and addition increases accordingly. If the circuit becomes too large, it becomes difficult to store the arithmetic circuit of the number of bits to be used in the hardware of the existing multiply-accumulate arithmetic unit 112. In that case, it is not preferable to take measures such as adding an arithmetic circuit for stochastic rounding to the insufficient part because the circuit amount increases.

Therefore, if the relationship of n ≧ m is not maintained and n may be smaller than m, a method of keeping n in the number of bits that can be stored in the existing multiply-accumulate unit 112 can be considered. In that case, among the m bits to be discarded, the bits lower than the n bits below the rounded position are not added to the random number and do not contribute to the result after rounding. The expected value after rounding deviates from the value before rounding by that amount. However, since the deviation of the expected value is reduced to about half each time n is increased by 1, if n is increased to some extent or more, the deviation due to the large m becomes sufficiently small, which does not pose a problem in practical use. Therefore, it is preferable that an appropriate value of n is determined according to practical requirements and the amount of existing arithmetic circuits.

In the case of stochastic rounding, the multiplexer 123 selects an n-bit uniform random number input from the random number generation circuit 121. Then, the multiplexer 123 outputs an n-bit uniform random number to the multiplier 125.

The exponentiation generation unit 122 receives an input of a stochastic rounding instruction from the arithmetic instruction control unit 101. At the same time, the power generation unit 122 acquires the decimal point position information of the operand included in the stochastic rounding instruction. Then, the power generation unit 122 generates a power of 2 according to the position to be rounded by using the decimal point position information. Here, the position to be rounded corresponds to a digit in which the digit one above the digit is a significant digit. After that, the power generation unit 122 outputs the generated power of 2 to the multiplexer 124.

In the case of stochastic rounding, the multiplexer 124 selects a power of 2 input from the power generation unit 122. Then, the multiplexer 124 outputs a power of 2 to the multiplier 125.

The multiplier 125 receives an input of an n-bit uniform random number from the multiplexer 123. Further, the multiplier 125 receives an input of a power of 2 according to the position to be rounded from the multiplexer 124. Then, the multiplier 125 multiplies the acquired power of 2 by the acquired random number to align the first digit of the random number with the position to be rounded in the stochastic rounding target number.

Here, with reference to FIG. 3, the outline of the calculation of the stochastic rounding process by the product-sum calculator 112 according to the present embodiment will be described. FIG. 3 is a diagram showing an outline of the calculation of the stochastic rounding process by the product-sum calculator according to the embodiment. The position P in the number of stochastic rounding targets 200 represents the rounding position. Further, the range L is a range used as a calculation result.

First, the random number generation circuit 121 generates a random number 201, which is an n-bit uniform random number. Then, the random number 201 is multiplied by a power of 2 by the multiplier 125, and the random number 201 is left-shifted so that the head of the random number 201 coincides with the rounding position P of the stochastic rounding target number 200. At this time, the random number 201 is a random number having n-bit digits lower than the rounded position.

Here, with reference to FIG. 4, the digit alignment shift of the random number will be described in more detail. FIG. 4 is a diagram for explaining the digit alignment shift of random numbers. Here, the case where the random number 201 is a 12-bit random number and a random number having 3 bits after the decimal point will be described. Further, the case where the decimal point position of the fixed decimal accumulator 211 (stochastic rounding target number) is immediately to the right of the least significant bit will be described.

The multiplier 125 shifts the random number by multiplying the random number 201 by 2 ^ E, which is a power of 2. Here, the decimal point position information is represented as QNUM, and E = QNUM-9. When QNUM = 0, all the digits of the random number are buried below the least significant bit of the fixed decimal accumulator 211. Further, when QNUM = 12, the lowest digit of the random number is at the position corresponding to the lowest digit of the fixed decimal accumulator 211. In this case, the position D represents the decimal point position.

In FIG. 4, the frame 210 represents a shift of the random number 201 by the multiplier 125 that performs multiplication of 24 bits × 24 bits with single precision. In FIG. 4, the 12-bit random number 201A is the position when QNUM = 0. Here, the least significant digit of the multiplier 125 in this case corresponds to 2 ^ -8 in terms of a fixed decimal number of 16 bits. When QNUM = 0, E = -9, and the multiplier 125 performs a process of multiplying 2 ^ -9, but the multiplier 125 does not have a circuit of that digit. However, when QNUM = 0, all the digits of the random number are buried below the least significant bit of the fixed decimal accumulator 211, and rounding is rounded down, so it is not necessary to add the random numbers. Therefore, when QNUM = 0, the multiplier 125 sets 2 ^ E, which is the value to be multiplied, to 0.

When QNUM = 1, E = -8, and the multiplier 125 multiplies the 12-bit random number 201A by 2 ^ -8 and shifts the 12-bit random number 201A to obtain the 12-bit random number 201B. Further, when QNUM = 8, E = -1, and the multiplier 125 multiplies the 12-bit random number 201 by 2 ^ -1 and shifts the 12-bit random number 201A to obtain the 12-bit random number 201C. Further, when QNUM = 24, E = 15, and the multiplier 125 multiplies the 12-bit random number 201 by 2 ^ 15 and shifts the 12-bit random number 201A to obtain the 12-bit random number 201D.

That is, when the data 213 which is the lowest 16 bits of the fixed decimal accumulator 211 is used as the output result, QNUM = 0. Further, when the data 212 which is 16 bits on the uppermost side of the fixed decimal accumulator 211 is used as the output result, QNUM = 24. That is, the QNUM given by the instruction determines which position or more of the fixed decimal accumulator 211 is to be a significant digit. Then, in the case of FIG. 4, the multiplier 125 is the lowest significant digit in the fixed decimal accumulator 211 by multiplying the random number 201 by the power of 2 obtained from the QNUM having a value between 0 and 24. Align the first position of the random number 201 with the digit one digit below.

The explanation will be continued by returning to FIG. The multiplier 125 outputs a random number obtained by adding the first digit to the digit one below the lowest digit of the significant digit which is the multiplication result to the adder 129. This multiplier 125 corresponds to an example of a "random number moving unit".

The fixed-point register 130 is a cumulative register (accumulator) used in the product-sum accumulation operation. The fixed-point register 130 stores the number of stochastic rounding targets to be stochastic rounded. The number of stochastic rounding targets is the calculation result calculated in the actual calculation. Since the multiplication result is added to the value of the cumulative register in the cumulative operation, the fixed-point register 130 has a bit width sufficient to set the value of the cumulative register. Then, in the case of the stochastic rounding process, the fixed-point register 130 outputs the number of stochastic rounding targets to the multiplexer 128.

In the case of stochastic rounding, the multiplexer 128 selects the number of stochastic rounding targets input from the fixed-point register 130. Then, the multiplexer 128 outputs the number of stochastic rounding targets to the adder 129.

The adder 129 receives an input of a random number obtained by adding the first digit to the digit one below the least significant digit of the significant digit from the multiplier 125. Further, the adder 129 receives an input of the number of stochastic rounding targets from the multiplexer 128. Then, the adder 129 adds a random number to the number of stochastic rounding targets. As a result, the number of stochastic rounding targets is stochastically rounded up according to the number of digits below the beginning of the random number. That is, the adder 129 performs stochastic rounding by adding a random number to the number of stochastic rounding targets. After that, the adder 129 outputs the addition result to the normalized shifter 134. This adder 129 is an example of an "adder".

Here, with reference to FIG. 3, the process of stochastic rounding by the adder 129 will be further described. The number of stochastic rounding targets 200 is provided by the fixed-point register 130. Then, the range L represents a range of numerical values to be used as a result of the rounding process. The adder 129 adds the random number 201 whose head position is shifted to P, which is the rounding position, to the stochastic rounding target number 200 by the multiplier 125. Here, when the lowest digit of the stochastic rounding target number 200 is higher than the least significant digit of the random number 201, the adder 129 adds a bit of a value of 0 to the stochastic rounding target number 200 to obtain the least significant digit. Add after matching. By this addition, an added value 202 in which a carry M1 is probabilistically generated according to the value below the rounding position P is obtained.

Here, the carry occurs stochastically according to the value below. This is because, as described above, the expected value of the stochastic rounding result may deviate from the value before rounding depending on how the number of bits n of the random number is selected, and the deviation amount differs depending on the value of n. In this embodiment, n = 12 is determined based on the number of multiply-accumulate bits that can be stored in the existing multiply-accumulate unit 112 for single-precision floating point and the practicality based on the convergence simulation of deep learning. In this case, the deviation of the expected value after rounding is about 0.00025 at the maximum. However, the number of bits of the random number is not limited to this, and it is preferable that an arbitrary reasonable number of bits of 1 or more is selected according to the balance between the requirements expected for the calculation and the existing circuit and the allowable amount of additional circuits. ..

The explanation will be continued by returning to FIG. The shift amount calculation unit 132 receives the input of the decimal point position information from the operation instruction control unit 101. Then, the shift amount calculation unit 132 calculates the shift amount according to the decimal point position information. Specifically, the shift amount calculation unit 132 shifts from the position where the valid data is arranged among the data output from the adder 129 to the position of the valid data in the output of the normalized shifter. The amount is calculated as QNUM. After that, the shift amount calculation unit 132 outputs the calculated shift amount to the multiplexer 133.

In the case of the stochastic rounding process, the multiplexer 133 selects the shift amount input from the shift amount calculation unit 132. Then, the multiplexer 133 outputs the shift amount to the normalized shifter 134.

The normalized shifter 134 receives an input of the number of stochastic rounding targets subjected to the stochastic rounding process from the adder 129. Further, the normalized shifter 134 receives an input of a shift amount from the multiplexer 133. Then, the normalized shifter 134 shifts the number of stochastic rounding targets according to the shift amount. Specifically, the normalized shifter 134 is left so that the digit immediately above the rounding position of the input target number is moved to the least significant digit of the valid number output from the multiply-accumulate unit 112. Make a shift. The normalized shifter 134 outputs the number of stochastic rounding targets subjected to the left shift to the rounding circuit 135. This normalized shifter 134 is an example of a "moving part".

For example, in FIG. 3, the normalized shifter 134 shifts the added value 202 so that the lowest digit of the range L used as the calculation result in the added value 202 matches the lowest digit of the output data, and shifts the shift value. It is set to 203.

Here, the alignment of the added value by the normalized shifter 134 will be described with reference to FIG. FIG. 5 is a diagram for explaining the alignment of the added value by the normalized shifter.

In FIG. 5, the case of the following conditions is described as an example. A 40-bit addition value 202 is output from the adder 129. The value output from the adder 129 corresponds to the position from the bit 16 to the bit 55 of the intermediate bus before the output of the normalized shifter 134. Further, 16-bit data of the values is output. Then, bits 48 to 63 of the calculation result bus for which data is output from the normalized shifter 134 are output as data.

The normalized shifter 134 shifts the addition value 202 to the left. As a result, the normalized shifter 134 moves the 16 bits of the addition value 202 from the bit 48 of the calculation result bus to the output position 214 corresponding to the bit 63.

For example, in FIG. 5, when the value representing the decimal point position information is QNUM and QNUM = 0, it is assumed that the 16-bit data 213 on the lowest side of the fixed decimal accumulator 211 is the output target. In this case, if QNUM = 0, the normalized shifter 134 moves the data 213 from bits 16 to 32 of the intermediate result bus from bit 48 of the operation result bus to the output position 214 of bit 63. In this case, the left shift amount is 32. Further, when QNUM = 24, it is assumed that the 16-bit data 212 on the uppermost side of the fixed decimal accumulator 211 is the output target. In this case, if QNUM = 24, the normalized shifter 134 moves the data 212 from the bits 40 to 55 of the intermediate result bus from the bit 48 of the operation result bus to the output position 214 of the bit 63. In this case, the left shift amount is 8. That is, in the example of FIG. 5, the normalized shifter 134 executes the left shift by using the left shift amount obtained as “32-QNUM” by the shift amount calculation unit 132.

The explanation will be continued by returning to FIG. The rounding circuit 135 receives an input of the number of stochastic rounding targets to which the left shift is applied from the normalized shifter 134. Then, in the case of the stochastic rounding process, the rounding circuit 135 cuts off the digits below the predetermined digit of the input stochastic rounding target number. Then, the rounding circuit 135 outputs the number of stochastic rounding targets in which the digits below the predetermined digit are cut off. The output from the rounding circuit 135 is sent to the vector register 111 as output data. The call rounding circuit 135 is an example of an “output unit”.

For example, in FIG. 3, the rounding circuit 135 performs a truncation M2 on a digit lower than the range L used in the shift value 203. Then, the range 204 of the data output from the rounding circuit 135, which is a digit higher than the range L to be used, is not included in the output data 205 and is discarded. Then, the output data 205 is sent to the vector register 111.

Here, the rounding circuit 135 is a circuit for ordinary floating-point arithmetic. In normal rounding of floating-point operations, the rounding circuit 135 is based on the rounding bit or sticky bit obtained from the lower digit, the value of the least significant rounding digit, the positive or negative of the operation result, and the specified rounding mode. Perform one of the following two processes. The first process is a process in which the rounding circuit 135 outputs the value cut off below the rounding position of the input value as it is. The second process is a process in which the rounding circuit 135 adds 1 to the value cut off below the rounding position of the input value and outputs the input value. When performing the stochastic rounding process, the rounding circuit 135 is logically designated to always select the first process described above.

Next, with reference to FIG. 6, the stochastic rounding process will be described using specific data. FIG. 6 is a diagram showing a specific example of the stochastic rounding process. FIG. 6 describes a case where processing is performed using a bus having a width of 64 bits. Further, the position of each data is represented as [x: y], where x represents the most significant bit and y represents the least significant bit.

In this case, the arithmetic instruction control unit 101 outputs QNUM = 16 as the decimal point position information. The number of stochastic rounding targets 300 output from the fixed-point register 130 is located at [55:16]. Here, bit 15 or less corresponds to the decimal point. Then, out of the number of stochastic rounding targets 300, bits 31 or less are rounded, and [47:32] is the range in which [47:32] is used.

The random number 301 generated by the random number generation circuit 121 is logically arranged so that the number after the decimal point is bit 15 or less, and is located at a place surrounded by a broken line. Actually, the random number 301 is arranged as an initial position on the circuit at the position when QNUM = 0. Specifically, the position when QNUM = 0 is the position where the first bit of the random number 301 comes to the bit next to the least significant bit of the stochastic rounding target number 300. Then, the power generation unit 122 obtains 2 ^ 7 as a power of 2 corresponding to QNUM = 16. The multiplier 125 multiplies the random number by 2 ^ 7 to shift the random number 301 to the position of [31:20].

The adder 129 adds a bit with a value of 0 to the random number 301 located at [31:20] so that the number of stochastic rounding targets 300 and the least significant bit match, and adds to the number of stochastic rounding targets 300. , The addition value 302 is calculated. The added value 302 is located at [55:16]. Here, the output range 303 is [63:48].

Therefore, the normalized shifter 134 shifts the stochastic rounding target number 300 so that the data in the range [47:32] used in the stochastic rounding target number 300 is located at [63:48].

After that, the rounding circuit 135 cuts off and discards bits 49 or less in the stochastic rounding target number 300 after the shift. Further, the bits 64 or more in the stochastic rounding target number 300 after the shift are not output and are discarded. As a result, the remaining 16-bit output data 304 is output as a calculation result.

Next, with reference to FIG. 7, the overall flow of processing executed by the product-sum calculation unit 100 will be described. FIG. 7 is a flowchart of the entire process executed by the product-sum calculation unit.

The product-sum calculation unit 100 executes the product-sum calculation in the actual calculation using the product-sum calculation device 112 (step S1).

Then, the product-sum calculation unit 100 determines whether or not the product-sum cumulative operation has been completed (step S2). When the product-sum accumulation operation is not completed (step S2: negation), the product-sum calculation unit 100 returns to step S1 and repeats the product-sum operation.

On the other hand, when the product-sum accumulation calculation is completed (step S2: affirmative), the product-sum calculation unit 100 executes the stochastic rounding process using the product-sum calculation unit 112 (step S3).

After that, according to the instruction from the memory controller 12, the calculation result stored in the vector register 111 is output to the memory 13 via the chain of the processing unit and the memory controller 12 (step S4).

Next, with reference to FIG. 8, the flow of the stochastic rounding process by the product-sum calculator according to the present embodiment will be described. FIG. 8 is a flowchart of the stochastic rounding process by the product-sum calculator 112 according to the embodiment. The process shown in the flowchart of FIG. 8 corresponds to an example of the process performed in step S3 of FIG.

The random number generation circuit 121 acquires a uniform random number of n digits (step S101). Then, the random number generation circuit 121 outputs the generated random number to the multiplier 125 via the multiplexer 123.

Further, the power generation unit 122 generates a power of 2 according to the QNUM (step S102). Then, the random number generation circuit 121 outputs the generated power of 2 to the multiplier 125 via the multiplexer 124.

The multiplier 125 receives a random number input from the random number generation circuit 121. Further, the multiplier 125 receives an input of a power of 2 corresponding to the QNUM from the multiplexer 124. Then, the multiplier 125 multiplies the random number by a power of 2 and shifts the random number so that the head of the random number is located at the rounded position (step S103). After that, the multiplier 125 outputs the multiplication result to the adder 129.

The adder 129 acquires the number of stochastic rounding targets stored in the fixed-point register 130 via the multiplexer 128 (step S104).

Further, the adder 129 receives the input of the multiplication result from the multiplier 125. Then, the adder 129 adds the multiplication result by the multiplier 125 to the number of stochastic rounding targets and executes the probabilistic rounding (step S105). After that, the adder 129 outputs an addition result representing the number of stochastic rounding targets subjected to the stochastic rounding process to the normalized shifter 134.

The shift amount calculation unit 132 calculates the shift amount according to the decimal point position information acquired from the operation instruction control unit 101 (step S106). Then, the shift amount calculation unit 132 outputs the calculated shift amount to the normalized shifter 134 via the multiplexer 133.

The normalized shifter 134 receives an input of an addition result representing the number of stochastic rounding targets subjected to the stochastic rounding process from the adder 129. Further, the normalized shifter 134 receives an input of the shift amount from the shift amount calculation unit 132. Then, the addition result is shifted to the left by the shift amount (step S107). Then, the normalized shifter 134 rounds the left-shifted value and outputs it to the circuit 135.

The rounding circuit 135 receives an input of a left-shifted value from the normalized shifter 134. Then, the rounding circuit 135 cuts off the predetermined digit or less of the left-shifted value and discards the bits of the output range or less (step S108).

After that, a predetermined number of bits is output as a result from the lower order from the rounding circuit 135 (step S109).

The product-sum calculator 112 according to the present embodiment adds a random number generation circuit 121, a power generation circuit 122, a shift amount calculation unit 132, and multiplexers 123, 124, and 133 to a circuit that performs floating-point arithmetic. Then, the probabilistic rounding process using the fixed point is executed.

As described above, the multiply-accumulate unit 112 according to the present embodiment can execute fixed-point stochastic rounding by adding a small amount of circuits to the circuit used for the floating-point product-sum operation. Become. Further, the multiply-accumulate calculator 112 according to the present embodiment performs stochastic rounding on the cumulative calculation result of multiplication. Therefore, an appropriate stochastic rounding can be performed with a simple configuration.

1 PCI card 2 Host computer 10 Processing unit 11 Overall instruction control unit 12 Memory controller 13 Memory 14 PCI control unit 50 Information processing device 100 Multiply-accumulate operation unit 101 Operation instruction control unit 102 Operation instruction buffer 103 multiplexer 111 Vector register 112 Multiply-accumulate operation Instrument 121 Random generator circuit 122 Memory generator
125 Multiplier 126 Exponential sign calculation unit 127 Digit shifter 129 Adder 130 Fixed-point register 131 Digit drop amount prediction unit 132 Shift amount calculation unit 134 Normalization shifter 135 Rounding circuit 123, 124, 128, 133 Multiplexer

Claims (5)

A random number generator that generates random numbers, and a random number generator
A random number moving unit that moves the position of the random number so that the beginning of the random number matches the rounding position of the number of rounding targets based on the predetermined position where the number of rounding targets is arranged and the decimal point position information of the output data.
An addition unit that adds the random number moved by the random number movement unit and the number of rounding targets arranged at the predetermined positions, and an addition unit.
An arithmetic processing unit including an output unit that outputs data in a predetermined range including significant figures of a predetermined digit from the rounded position in the addition result by the addition unit as the output data. Further provided is a moving unit that moves the significant digit of the predetermined digit from the rounding position in the addition result by the addition unit so as to match the output position of the predetermined digit.
The claim is characterized in that the output unit discards and outputs a value other than the output position of the addition result in which the significant digit of the predetermined digit is moved from the rounding position so as to match the output position. Item 1. The arithmetic processing unit according to item 1. A power generation unit for obtaining a power of 2 for matching the beginning of the random number with the rounding position of the rounding target number based on the position where the rounding target number is arranged and the decimal point position information of the output data. Further prepare,
The random number generation unit generates a random number represented by a binary number, and the random number moving unit moves the position of the random number by multiplying the random number by the power obtained by the power generation unit. The arithmetic processing apparatus according to claim 1. The random number moving unit multiplies the two input data to perform a floating point operation.
The arithmetic processing apparatus according to claim 1, wherein the addition unit adds data input to a multiplication result by the random number movement unit to perform a floating-point operation. Generate random numbers,
Based on the predetermined position where the number of rounding targets is placed and the decimal point position information of the output data, the position of the random number is moved so that the beginning of the random number matches the rounding position of the number of rounding targets.
The moved random number and the number of rounding targets placed at the predetermined positions are added.
A control method of an arithmetic processing unit, characterized in that data including significant digits of a predetermined digit is output as the output data from the rounded position of the addition result.

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