JP6984787B2 - Semiconductor devices and their manufacturing methods - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the same.

In high-frequency FETs that require high output, it is necessary to ensure high heat dissipation in order to ensure the reliability of the transistor. Therefore, as a package for high-frequency FET, a metal package having copper or a metal compound of copper as a metal base is selected. For mounting a semiconductor chip and a substrate constituting a matching circuit on this package, for example, gold-tin solder having high thermal conductivity is used. Further, when high reliability is required, airtightness in the package after sealing is required, and for example, gold-tin solder is used for sealing.

Japanese Patent Application Laid-Open No. 62-194651

When soldering for mounting or sealing, solder debris was generated and sometimes moved around in the package after sealing. This solder debris short-circuits between the wirings of the high-frequency circuit as a conductive foreign substance, which deteriorates the product characteristics and causes defects such as burning of the semiconductor chip.

It has been proposed to form a polyimide resin layer on the upper surface of the inside of the package in order to adhere foreign substances such as dust floating in the package (see, for example, Patent Document 1). However, foreign matter that is heavier than dust, such as solder dust, falls to the bottom surface inside the package and cannot be adhered. Therefore, it was not possible to suppress the occurrence of defects.

The present invention has been made to solve the above-mentioned problems, and an object thereof is to obtain a semiconductor device capable of suppressing the occurrence of defects and a method for manufacturing the same.

The semiconductor device according to the present invention is mounted on a package having a base plate and a frame joined to the outer peripheral portion of the main surface of the base plate by a first solder on the main surface of the base plate, and is a semiconductor chip. A second solder, which is applied to a region of the main surface of the base plate where the electronic component is not mounted and has a lower melting point than the first solder, and a third solder on the frame. It is provided with a cap that is joined by the solder and seals the electronic component, and the second solder is exposed inside the package so as to face the cap .

In the present invention, the second solder having a low melting point is applied to the region of the main surface of the base plate where the electronic components are not mounted. With this second solder, the solder debris inside the package can be fixed and immobile. Therefore, it is possible to prevent a short circuit between the wirings of the high frequency circuit and suppress the occurrence of defects.

It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 1. FIG. It is a top view which shows the inside of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 2. FIG. It is a top view which shows the back surface of the cap which concerns on Embodiment 2. FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 3. FIG. It is a top view which shows the back surface of the cap which concerns on Embodiment 3. FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 4. FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 4. FIG.

The semiconductor device and the manufacturing method thereof according to the embodiment will be described with reference to the drawings. The same or corresponding components may be designated by the same reference numerals and the description may be omitted.

Embodiment 1.
FIG. 1 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 2 is a plan view showing the inside of the semiconductor device according to the first embodiment. The semiconductor device according to this embodiment is a package for high frequency FET.

The package 1 has a base plate 2 and a ceramic terminal 3 and a frame 4 joined to the outer peripheral portion of the main surface of the base plate 2. The electronic component 5 is mounted on the main surface of the base plate 2 by the solder 6. The electronic component 5 includes a semiconductor chip 7 such as a high-frequency amplifier that amplifies a signal, and a substrate 8 on which a matching circuit of the high-frequency amplifier is printed. The semiconductor chip 7 and the substrate 8 are connected by a wire 9. The substrate 8 is connected to the lead 10 of the ceramic terminal 3 by a wire 11.

The solder 12 is applied to the region of the main surface of the base plate 2 where the electronic component 5 is not mounted, and is exposed inside the package 1. The back surface of the cap 13 is joined to the upper surface of the frame 4 by solder 14 to seal the electronic component 5. Solder 12 has a lower melting point than solders 6 and 14. For example, the solders 6 and 14 are gold-tin solder, and the solder 12 is tin-silver-copper solder.

In the sealing step, the package 1 is placed on the heat station 15 and heated with the package 1 facing down with respect to the cap 13. As a result, the solder 12 is melted without melting the solder 6. When joining the cap 13 to the frame 4, the cap 13 is scribed on the upper surface of the frame 4 in order to blend the solder 14. At this time, the solder debris 16 generated from the solder 14 falls on the main surface of the base plate 2 inside the package 1 and becomes a conductive foreign substance that may affect the characteristics and reliability of the product. However, since the molten solder 12 fixes the solder scraps 16, the solder scraps 16 can be immobile. Therefore, it is possible to prevent deterioration of product characteristics or burnout of the semiconductor chip, which occurs due to a short circuit between the wirings of the high frequency circuit, and suppress the occurrence of defects. Further, even when the semiconductor device is vibrated in a high acceleration environment and a PIND test for detecting conductive foreign matter inside the package is performed, the occurrence of defects can be suppressed.

Even after sealing, by raising the temperature of the package 1 to a temperature at which the solder 12 is melted without melting the solder 6, the remaining solder debris 16 that cannot be captured at the time of sealing can be fixed. This makes it possible to immobilize the detected conductive foreign matter even when the foreign matter is detected in the PIND test.

Embodiment 2.
FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment. FIG. 4 is a plan view showing the back surface of the cap according to the second embodiment. In this embodiment, the solder 14 is applied to the entire back surface of the cap 13. The solder 14 is, for example, gold tin solder.

In the sealing step, the cap 13 is placed on the heat station 15 with the back surface facing up and heated to melt the solder 14, and the frame 4 is joined to the back surface of the cap 13 with the solder 14 to seal the electronic component 5. do. The solder 14 is exposed inside the package 1 and fixes the solder debris 16 generated from the solder 6 at the time of mounting the electronic component 5 and the solder debris 17 generated from the solder 14 at the time of sealing. As a result, the solder scraps 16 and 17 can be made immobile, so that the occurrence of defects can be suppressed as compared with the first embodiment. Other configurations and effects are the same as those in the first embodiment.

Embodiment 3.
FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the third embodiment. FIG. 6 is a plan view showing the back surface of the cap according to the third embodiment. In the present embodiment, the solder 14 is applied to the outer peripheral portion of the back surface of the cap 13, and the solder 18 having a melting point lower than that of the solder 14 is applied to the central portion of the back surface. For example, the solder 14 is gold-tin solder, and the solder 18 is tin-silver-copper solder.

Similar to the second embodiment, the solder scraps 16 and 17 can be fixed by the solders 14 and 18 melted in the sealing step. Further, even after the sealing step, the cap 13 is placed on the heat station 15 and heated with the cap 13 facing down with respect to the package 1 without melting the solder 6 and the solder 14. 18 is melted. As a result, the solder scraps 16 and 17 that cannot be captured at the time of sealing and remain can be fixed after sealing. Therefore, it is possible to suppress the occurrence of defects as compared with the second embodiment. Other configurations and effects are the same as those in the second embodiment.

Embodiment 4.
7 and 8 are cross-sectional views showing a manufacturing process of the semiconductor device according to the fourth embodiment. The semiconductor chip 7 and the substrate 8 are mounted on the plate 19 by solder 20. The plate 19 is made of the same material as the base plate 2, for example. As shown in FIG. 7, the plate 19 is joined to the main surface of the base plate 2 by the solder 6. Then, as shown in FIG. 8, it is sealed with the cap 13. By using the plate 19, the high frequency circuit composed of the semiconductor chip 7 and the substrate 8 is made higher than the main surface of the base plate 2.

The semiconductor chip 7 and the substrate 8 can be soldered to the plate 19 outside the package. Therefore, the solder debris generated during soldering can be removed outside the package. Further, since the plate 19 is larger in size than the semiconductor chip 7 and the substrate 8, it is easy to mount the plate 19 on the base plate 2.

Further, the characteristics of the high frequency circuit can be confirmed before the plate 19 is mounted on the base plate 2. Therefore, if the semiconductor chip 7 is insufficient in capacity, it can be discarded in the state of the plate 19. Compared to discarding the product incorporated in the expensive high-frequency FET package, the loss due to disposal can be suppressed.

The plate 19 may be made of a material different from that of the base plate 2, but it is preferable to select a material having a similar coefficient of linear expansion. As a result, it is possible to eliminate the difference in linear expansion coefficient between the base plate 2 and the plate 19 that occurs due to the temperature rise during soldering, and to avoid the destruction of the solder 6. Other configurations and effects are the same as those in the first embodiment. Further, the configuration of the fourth embodiment may be combined with the second or third embodiment.

1 package, 2 base plates, 4 frames, 5 electronic components, 6,12,14,18,20 solder, 7 semiconductor chips, 13 caps, 15 heat stations, 16,17 solder scraps

Claims (10)

A package having a base plate and a frame joined to the outer peripheral portion of the main surface of the base plate,
An electronic component mounted on the main surface of the base plate by a first solder and having a semiconductor chip,
A second solder, which is applied to a region of the main surface of the base plate where the electronic components are not mounted and has a melting point lower than that of the first solder,
The frame is provided with a cap that is joined by a third solder to seal the electronic component .
The second solder is a semiconductor device characterized in that it is exposed inside the package so as to face the cap. Said second solder, the semiconductor device according to claim 1, characterized in that to fix the front Symbol solder residue generated from the third solder. A package having a base plate and a frame joined to the outer peripheral portion of the main surface of the base plate,
An electronic component mounted on the main surface of the base plate by a first solder and having a semiconductor chip,
The back surface is provided with a cap which is joined to the frame by a second solder to seal the electronic component.
The second solder is applied to the entire surface of the back surface of the cap .
A semiconductor device characterized in that the second solder is exposed inside the package and the solder debris generated from the first solder is fixed. A package having a base plate and a frame joined to the outer peripheral portion of the main surface of the base plate,
An electronic component mounted on the main surface of the base plate by a first solder and having a semiconductor chip,
A cap whose back surface is joined to the frame by a second solder to seal the electronic component,
A semiconductor device comprising a third solder, which is applied to a region of the back surface of the cap that is not joined to the frame and has a melting point lower than that of the second solder. The semiconductor device according to claim 4 , wherein the third solder is exposed inside the package and adheres to the solder debris generated from the first solder or the second solder. The electronic component has a plate on which the semiconductor chip is mounted.
The semiconductor device according to any one of claims 1 to 5 , wherein the plate is joined to the main surface of the base plate by the first solder. The process of joining the frame to the outer periphery of the main surface of the base plate to form a package,
A step of applying a first solder and a second solder having a melting point lower than that of the first solder to the main surface of the base plate.
A step of mounting an electronic component having a semiconductor chip on the main surface of the base plate by the first solder.
A sealing step of joining the cap to the frame with a third solder to seal the electronic component is provided.
In the sealing step, the second solder is melted without melting the first solder .
A method for manufacturing a semiconductor device, wherein the second solder is exposed inside the package so as to face the cap. In the sealing step, the cap is scribed on the upper surface of the frame, and the solder debris generated from the third solder falls on the melted second solder, and the second solder fixes the solder debris. The method for manufacturing a semiconductor device according to claim 7 , wherein the semiconductor device is manufactured. The process of joining the frame to the outer periphery of the main surface of the base plate to form a package,
A step of mounting an electronic component having a semiconductor chip on the main surface of the base plate with a first solder,
The process of applying the second solder to the entire back surface of the cap,
The cap is placed on a heat station with the back surface facing up and heated to melt the second solder, and the frame is joined to the back surface of the cap with the second solder to attach the electronic component. A method for manufacturing a semiconductor device, which comprises a step of sealing. The process of joining the frame to the outer periphery of the main surface of the base plate to form a package,
A step of mounting an electronic component having a semiconductor chip on the main surface of the base plate with a first solder,
A process of applying a second solder to the outer peripheral portion of the back surface of the cap and a third solder having a melting point lower than that of the second solder to the center portion of the back surface.
A sealing step of joining the back surface of the cap to the frame with the second solder to seal the electronic component.
After the sealing step, the cap is placed on a heat station and heated with the cap down with respect to the package, without melting the first solder and the second solder. A method for manufacturing a semiconductor device, which comprises a third step of melting solder.

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