JP6985846B2 - Signal processing device and signal processing method - Google Patents

Description

The present invention relates to a signal processing apparatus and a signal processing method.

With the recent increase in image quality and frame rate of image sensors, there is a demand for a technique for reading image data acquired by an image sensor at high speed. For example, it has been proposed to read out image data at high speed by serially transmitting a plurality of image data in parallel. Patent Document 1 discloses a technique for adjusting synchronization for image data serially transmitted in parallel.

Japanese Unexamined Patent Publication No. 2009-267969

However, the proposed technique may not always be able to transmit signals satisfactorily.
An object of the present invention is to provide a signal processing device and a signal processing method capable of transmitting signals satisfactorily.

According to one aspect of the embodiment, a plurality of first lanes, a first transmission means driven by the first driving means, and a plurality of first transmitting means for supplying a signal including a control code to each of the plurality of first lanes. A first link comprising a first processing means for generating a first detection signal based on the number of the first lanes in which the control code is detected, and a plurality of second lanes. A second transmission means driven by the second driving means to supply a signal including a control code to each of the plurality of second lanes, and the first of the plurality of second lanes in which the control code is detected. A second link comprising a second processing means for generating a second detection signal based on the number of two lanes, and transmission in the plurality of first lanes based on the first detection signal and the second detection signal. Provided is a signal processing device comprising a plurality of signals to be generated and a adjusting means for adjusting the timing of the plurality of signals transmitted in the plurality of second lanes.

According to the present invention, it is possible to provide a signal processing device and a signal processing method capable of transmitting signals satisfactorily.

It is a block diagram which shows a part of the signal processing apparatus by 1st Embodiment. It is a block diagram which shows the transmission data processing circuit. It is a block diagram which shows the skew adjustment circuit in a link. It is a figure which shows the example of the operation of the skew adjustment circuit in a link. It is a block diagram which shows the data processing circuit. It is a block diagram which shows the control code detection part in a lane. It is a figure which shows the example of the operation of the control code detection part in a lane. It is a block diagram which shows the skew adjustment circuit between links. It is a figure which shows the example of the operation of the skew adjustment circuit between links. It is a block diagram which shows the signal processing apparatus by 1st Embodiment. It is a figure which shows the example of the operation of the skew adjustment circuit in a link. It is a block diagram which shows the transmission data processing circuit. It is a block diagram which shows the control code detection part in a lane.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following embodiments.

[First Embodiment]
The signal processing apparatus and the signal processing method according to the first embodiment will be described with reference to FIGS. 1 to 11. FIG. 10 is a block diagram showing a signal processing device 1001 according to the present embodiment. Here, a case where the signal processing device 1001 according to the present embodiment is an image pickup device will be described as an example, but the present invention is not limited thereto.

As shown in FIG. 10, the signal processing device 1001 according to the present embodiment includes an image pickup element 100, an image processing unit 140, a system control unit 1003, an operation unit 1004, and a display unit 1005. The signal processing device 1001 is provided with an image pickup optical system (lens unit) 1002. Further, the signal processing device 1001 is provided with a storage unit 1006. The image pickup optical system 1002 and the storage unit 1006 may be detachable from the main body (body) of the signal processing device 1001 or may not be detachable.

The system control unit 1003 controls each unit of the signal processing device 1001 and controls the entire signal processing device 1001. The image pickup device 100 is, for example, a CCD image sensor or a CMOS image sensor. An optical image of a subject formed by the image pickup optical system 1002 is formed on the image pickup surface (not shown) of the image pickup element 100. The image pickup surface of the image pickup element 100 is provided with a pixel unit (image acquisition means) 105 (see FIG. 1). A plurality of photoelectric conversion elements (photodiodes) (not shown) for converting an optical image of a subject into an electric signal are two-dimensionally arranged in the pixel unit 105. The image pickup device 100 generates an analog pixel signal by photoelectric conversion of an optical image of a subject formed by the image pickup optical system 1002, and performs analog / digital conversion on the analog pixel signal to perform a digital pixel signal. Generate (image data). The image data acquired by the image pickup device 100 is transmitted to the image processing unit 140 by, for example, high-speed serial communication.

The image processing unit 140 performs predetermined image processing on the image data acquired by the image pickup element 100, and performs compression processing or the like on the image data that has undergone image processing. The image sensor 100 and the image processing unit 140 are integrated on different chips.

The operation unit 1004 is for the user to perform an operation on the signal processing device 1001. For example, an operation for performing shooting is performed by the user via the operation unit 1004. Further, the operation of changing the display angle of view of the image acquired by shooting is performed by the user via the operation unit 1004. The display unit 1005 displays, for example, a live view image or an image acquired by shooting. Further, the operation menu is displayed on the display unit 1005. In addition, information or the like indicating the setting state of the signal processing device 1001 is displayed on the display unit 1005. The image acquired by the signal processing device 1001 is stored in the storage unit 1006 in a predetermined file format.

FIG. 1 is a block diagram showing a signal processing device according to the present embodiment. FIG. 1 shows an extracted image sensor 100, an oscillator 101, and an image processing unit 140 among various components provided in the signal processing device 1001.

The image pickup device 100 includes timing generators (TG: Timing Generator) 102 to 104, pixel units 105, transmission data processing circuits 106 and 107, and parallel serial converters 108 to 113. The image pickup device 100 further includes PLLs (Phase Locked Loop) 114 and 115, and transmission drivers 116 to 121. These components of the image pickup device 100 are integrated in the first chip.

The image processing unit 140 includes a synchronization signal generator (SSG: Sync Signal Generator) 122, reception drivers 123 to 128, serial parallel converters 129 to 134, and in-link skew adjustment circuits 135 and 136. The image processing unit 140 further includes a data processing circuit 137, 138, an interlink skew adjusting circuit 139, and a clock transfer circuit 141. These components of the image processing unit 140 are integrated in a second chip (image processing chip) different from the first chip.

In the present embodiment, the pixel signal (image signal) output from the pixel unit 105 is, for example, two processing paths, that is, the first processing path 150 which is the processing path of the link A and the processing path of the link B. It is processed in parallel with the second processing path 151. The first processing path 150 includes a transmission data processing circuit 106, parallel serial converters 108 to 110, PLL 114, transmission drivers 116 to 118, reception drivers 123 to 125, and serial parallel converters 129 to 131. There is. The first processing path 150 is further provided with an in-link skew adjusting circuit 135 and a data processing circuit 137. The second processing path 151 includes a transmission data processing circuit 107, parallel serial converters 111 to 113, PLL 115, transmission drivers 119 to 121, reception drivers 126 to 128, and serial parallel converters 132 to 134. There is. The second processing path 151 is further provided with an in-link skew adjusting circuit 136 and a data processing circuit 138. The clock transfer circuit 141 is shared by the first processing path 150 and the second processing path 151.

The link A is provided with, for example, three lanes for transmitting signals, and the link B is also provided with, for example, three lanes for transmitting signals. The parallel-serial converter 108, the transmission driver 116, the reception driver 123, and the serial-parallel converter 129 are provided in the first lane Lane A1 of the link A. The parallel-serial converter 109, the transmission driver 117, the reception driver 124, and the serial-parallel converter 130 are provided in the second lane Lane A2 of the link A. The parallel-serial converter 110, the transmission driver 118, the reception driver 125, and the serial-parallel converter 131 are provided in the third lane Lane A3 of the link A. The parallel serial converter 111, the transmission driver 119, the reception driver 126, and the serial parallel converter 132 are provided in the first lane Lane B1 of the link B. The parallel-serial converter 112, the transmission driver 120, the reception driver 127, and the serial-parallel converter 133 are provided in the second lane Lane B2 of the link B. The parallel-serial converter 113, the transmission driver 121, the reception driver 128, and the serial-parallel converter 134 are provided in the third lane Lane B3 of the link B.

The oscillator 101 supplies a clock signal (reference clock) that serves as a reference for the operation of the signal processing device 1001 to each functional block of the image pickup device 100 and each functional block of the image processing unit 140. As shown in FIG. 1, the clock signals output from the oscillator 101 are input to the timing generators 102 to 104, the transmission data processing circuits 106, 107, PLL 114, 115, and the synchronization signal generator 122, respectively. The clock signal output from the oscillator 101 is appropriately supplied not only to these functional blocks but also to other functional blocks. Each functional block of the image pickup device 100 and each functional block of the image processing unit 140 operates according to a clock signal supplied from the oscillator 101. The synchronization signal generator 122 outputs the horizontal synchronization signal HD and the vertical synchronization signal VD so as to synchronize with the clock signal supplied from the oscillator 101. The timing generator (driving means) 102 is a drive pulse signal (drive signal) for driving each functional block of the image pickup device 100 based on the horizontal sync signal HD and the vertical sync signal VD supplied from the sync signal generator 122. To generate.

The pixel unit 105 is arranged on the image pickup surface of the image pickup device 100. As described above, a plurality of photoelectric conversion elements for converting an optical image of a subject into an electric signal are two-dimensionally arranged in the pixel unit 105. The pixel signal obtained by the photoelectric conversion element is output to a signal line (not shown) according to the drive pulse signal supplied from the timing generator 102. The pixel signal output to the signal line is amplified by an amplifier (not shown). The analog pixel signal amplified by the amplifier is converted into a digital pixel signal by an A / D converter (not shown). The digital pixel signal thus obtained is output from the pixel unit 105. The pixel signal output from the pixel unit 105 is processed in parallel by the first processing path 150, which is the processing path of the link A, and the second processing path 151, which is the processing path of the link B. Here, the case where there are two links will be described as an example, but the number of processing routes is not limited to two. Further, here, a case where the link A is provided with three lanes and the link B is also provided with three lanes will be described as an example, but the number of lanes provided for each of the links A and B is three. It is not limited to one.

The timing generator 103 generates a timing signal based on the horizontal synchronization signal HD and the vertical synchronization signal VD supplied from the timing generator 102, and the generated timing signal is used in the transmission data processing circuit 106 provided in the first processing path 150. Supply to. The timing generator 104 generates a timing signal based on the horizontal synchronization signal HD and the vertical synchronization signal VD supplied from the timing generator 102, and the generated timing signal is used as a transmission data processing circuit 107 provided in the second processing path 151. Supply to. The timing generator 103 is arranged at an optimum position for driving each part of the first processing path 150. On the other hand, the timing generator 104 is arranged at an optimum position for driving each part of the second processing path 151. Therefore, the wiring length between the timing generator 102 and the timing generator 103 is different from the wiring length between the timing generator 102 and the timing generator 104. Since the wiring lengths are different in this way, the timing signal supplied from the timing generator 103 to each part of the first processing path 150 and the timing signal supplied from the timing generator 104 to each part of the second processing path 151. Does not synchronize. Therefore, each part of the first processing path 150 and each part of the second processing path 151 operate asynchronously.

In the transmission data processing circuits (transmission means) 106 and 107, a clock signal output from the oscillator 101, a timing signal output from each of the timing generators 103 and 104, and a pixel signal output from the pixel unit 105, respectively. Entered. The transmission data processing circuits 106 and 107 perform processing according to a predetermined protocol on the pixel signal based on the clock signal from the oscillator 101 and the timing signal from the timing generators 103 and 104 to generate transmission data. do. The transmission data processing circuits 106 and 107 output the generated transmission data as parallel data. The transmission data processing circuits 106 and 107 output not only data based on the pixel signal acquired by the pixel unit 105, but also training sequence data, a control code, and the like. The transmission data processing circuits 106 and 107 correspond to the link layer on the transmission protocol. The transmission data processing circuits 106 and 107 operate asynchronously, respectively.

The parallel serial converters 108 to 110 are located after the transmission data processing circuit 106. The parallel serial converters 111 to 113 are located after the transmission data processing circuit 107. The parallel serial converters 108 to 113 convert the parallel data (serial signal) output from the transmission data processing circuits 106 and 107, respectively, into serial data (parallel signal). The serial data obtained by the parallel serial converters 108 to 113 is output from the image sensor 100 via the transmission drivers 116 to 121.

The image processing unit 140 includes receiving drivers 123 to 128. The transmission drivers 116 to 121 and the reception drivers 123 to 128 are electrically connected to each other by wiring. The serial data output via the transmission drivers 116 to 121 of the image sensor 100 is received by the reception drivers 123 to 128, respectively.

The PLLs 114 and 115 generate serial clocks corresponding to the serial transmission rates of the parallel serial converters 108 to 113, respectively, from the clock signals, and supply the generated serial clocks to the parallel serial converters 108 to 110 and 111 to 113, respectively. The serial clocks used in the parallel serial converters 108 to 110 and the serial clocks used in the parallel serial converters 111 to 113 have the same frequency but are supplied from different PLLs 114 and 115. Therefore, the serial clocks used in the parallel serial converters 108 to 110 and the serial clocks used in the parallel serial converters 111 to 113 are not synchronized with each other.

The plurality of parallel data output from the transmission data processing circuit 106 are processed in the first processing path 150. The plurality of parallel data output from the transmission data processing circuit 107 is processed in the second processing path 151. Here, a case where the transmission data processing circuits 106 and 107 output data via three output selectors 206 to 208 (see FIG. 2), respectively, will be described as an example, but the present invention is not limited thereto. ..

As described above, the first processing path 150 and the second processing path 151 operate asynchronously. Therefore, a skew may occur between the data propagating in the first processing path 150 provided in the link A and the data propagating in the second processing path 151 provided in the link B. Such skew is referred to as interlink skew. The horizontal synchronization signal HD distributed from the timing generator 102 to the timing generator 103 and the timing generator 104 is handled asynchronously in the first processing path 150 and the second processing path 151. Therefore, the amount of skew between links varies for each horizontal transfer period (HD period).

The data output from the transmission data processing circuit 106 propagates in, for example, three lanes. Due to the difference in reset release timing in the parallel serial converters 108 to 110 and the difference in the wiring length of each lane, a skew may occur between the data propagating in these lanes. Such skew is referred to as intra-link skew. Further, the data output from the transmission data processing circuit 107 also propagates in, for example, three lanes. In-link skew may also occur between the data propagating in these lanes due to the difference in reset release timing in the parallel serial converters 111 to 113 and the difference in the wiring length of each lane. The amount of intra-link skew is constant because the factors that cause in-link skew do not change dynamically.

FIG. 2 is a block diagram showing a transmission data processing circuit 106. Although the transmission data processing circuit 106 will be described here, the configuration of the transmission data processing circuit 107 is the same as the configuration of the transmission data processing circuit 106. The transmission data processing circuit 106 includes a counter 201, a state machine (FSM: Finite State Machine) 202, a control code generation unit 203, and a training sequence generation unit 204, respectively. The transmission data processing circuit 106 further includes an IDLE code generation unit 205 and output selectors 206 to 208, respectively.

A clock signal supplied from the oscillator 101 is input to the counter 201. The counter 201 counts the processing cycle based on the clock signal, and supplies the count value obtained by the count to the state machine 202. The state machine 202 generates a control signal based on the count value supplied from the counter 201 and the timing signal supplied from the timing generator 103, and supplies the generated control signal to the output selectors 206 to 208. The control code generation unit 203 generates a control code and supplies the generated control code to each of the output selectors 206 to 208. The control code generation unit 203 generates a plurality of types of control codes. The control code generated by the control code generation unit 203 is, for example, a synchronization code, an invalid code, and an exit code. The synchronization code is inserted into the data string so as to correspond to the horizontal synchronization signal HD. The invalid code is inserted in the data column if there is no valid data. The exit code is attached to the end of the data string corresponding to one horizontal transfer period. The control code is data (symbol) of a specific pattern of a predetermined word length. The control code is composed of, for example, four symbols, but is not limited to this. The synchronization code can be, for example, {first synchronization code, second synchronization code, third synchronization code, fourth synchronization code} = {0x00, 0x00, 0xFF, 0xFF}. Not limited. By detecting the data (symbol) of such a specific pattern by, for example, pattern matching, it is possible to detect the synchronization code and the phase of the synchronization code. The training sequence generation unit 204 generates training sequence data, and supplies the generated training sequence data to each of the output selectors 206 to 208. The training sequence data contains certain predetermined adjustment codes. Such specific adjustment codes are used to eliminate intra-link skew. The IDLE code generation unit 205 generates an IDLE code and supplies the generated IDLE code to each of the output selectors 206 to 208. The IDLE code is used when valid data to be transmitted is not output from the pixel unit 105. The image data output from the pixel unit 105 is supplied to each of the output selectors 206 to 208.

The control signals supplied from the state machine 202 to the output selectors 206 to 208 are for outputting data from the output selectors 206 to 208 according to a predetermined protocol. The state machine 202 controls the output selectors 206 to 208 so that the training sequence data generated by the training sequence generation unit 204 is arranged at the head of the data strings output from the output selectors 206 to 208, respectively. The state machine 202 controls the output selectors 206 to 208 so that the control code generated by the control code generation unit 203 is arranged at an appropriate position in the data string output from the output selectors 206 to 208. The state machine 202 controls the output selectors 206 to 208 so that the IDLE codes generated by the IDLE code generation unit 205 are output from the output selectors 206 to 208, respectively, during the period other than the horizontal transfer period. In FIG. 2, the first output data means the data output from the transmission data processing circuit 106 to the first lane Lane A1 of the link A. Further, in FIG. 2, the second output data means the data output from the transmission data processing circuit 106 to the second lane Lane A2 of the link A. Further, in FIG. 2, the third output data means the data output from the transmission data processing circuit 106 to the third lane Lane A3 of the link A.

As shown in FIG. 1, serial parallel converters 129 to 134 are provided after the receiving drivers 123 to 128, respectively. Serial data is input to the serial-parallel converters 129 to 134 via the receiving drivers 123 to 128. The serial-parallel converters 129 to 134 store the input serial data in an internal shift register. The serial-parallel converters 129 to 134 detect data (symbols) of a specific pattern of a predetermined word length from the serial data stored in the shift register. The serial-parallel converters 129 to 134 output parallel data to the clock transfer circuit 141 for each predetermined word length according to the timing at which the data (symbol) of a specific pattern is detected. Further, the serial-parallel converters 129 to 134 generate write clock signals from the serial data input to the serial-parallel converters 129 to 134, and supply each of the generated write clock signals to the clock transfer circuit 141, respectively. .. Further, the serial-parallel converters 129 to 134 divide the write clock signal so as to correspond to the word length of the parallel data, and output the read clock signal obtained by the division to the clock transfer circuit 141. The method for generating the read clock signal is not limited to this. For example, an oscillator (not shown) is provided, and the clock signal supplied from the oscillator is multiplied so as to be equal to the frequency corresponding to the word length of the parallel data output from the serial parallel converters 129 to 134, thereby reading. A clock signal may be obtained.

The clock transfer circuit 141 includes a function block of FIFO. Signals output from the serial-parallel converters 129 to 134, specifically, parallel data, write clock signals, and read clock signals are input to the clock transfer circuit 141. Parallel data is written to the FIFO provided in the clock transfer circuit 141 by using the write clock signals supplied from the serial-parallel converters 129 to 134, respectively. Parallel data is read from the FIFO provided in the clock transfer circuit 141 by using any of the read clock signals supplied from the serial-parallel converters 129 to 134, respectively. Therefore, the parallel data output from the serial-parallel converters 129 to 134 are output from the clock transfer circuit 141 in synchronization with the common read clock signal.

The parallel data output from the serial-parallel converters 129 to 131 and synchronized with the common read clock signal by the clock transfer circuit 141 is input to the in-link skew adjustment circuit 135. The parallel data output from the serial-parallel converters 132 to 134 and synchronized with the common read clock signal by the clock transfer circuit 141 is input to the in-link skew adjustment circuit 136. The in-link skew adjustment circuits 135 and 136 operate in synchronization with the read clock signal. The in-link skew adjustment circuits 135 and 136 remove the in-link skew of each parallel data, and output the parallel data from which the in-link skew has been removed to the data processing circuits 137 and 138, respectively.

The in-link skew adjusting circuits 135 and 136 are for eliminating the in-link skew. FIG. 3 is a block diagram showing an in-link skew adjustment circuit 135. Although the in-link skew adjustment circuit 135 will be described here, the configuration of the in-link skew adjustment circuit 136 is the same as the configuration of the in-link skew adjustment circuit 135.

The in-link skew adjustment circuit 135 includes a buffer control unit 301, a buffer control unit 311, a buffer control unit 321 and a read pointer generation unit 330. The buffer control unit 301 includes a counter 302, an adjustment code detection unit 307, an output selector 308, and a buffer group 309. A clock signal is input to the counter 302. The counter 302 generates a control signal based on the clock signal, and supplies the generated control signal to the switch 310. The switch 310 is for switching the buffer that is the storage destination of the parallel data input to the buffer control unit 301. The buffer group 309 includes, for example, a buffer group including eight buffers. The storage destination of the parallel data input to the buffer control unit 301 is sequentially switched according to the control signal supplied from the counter 302. Therefore, the parallel data input to the buffer control unit 301 is sequentially stored in each of the plurality of buffers provided in the buffer group 309. In the first period, the parallel data input to the buffer control unit 301 is stored in the first buffer 303a. In the second period following the first period, the parallel data input to the buffer control unit 301 is stored in the second buffer 303b. In the third period following the second period, the parallel data input to the buffer control unit 301 is stored in the third buffer 303c. Similarly, the parallel data input to the buffer control unit 301 includes a fourth buffer (not shown), a fifth buffer (not shown), a sixth buffer (not shown), a seventh buffer (not shown), and an eighth buffer (not shown). It is sequentially stored in the buffer 303h of. After the storage in the eighth buffer 303h is completed, the storage destination of the parallel data input to the buffer control unit 301 returns to the first buffer 303a, and the above operation is repeated. The output selector 308 selectively outputs a signal from any of the plurality of buffers provided in the buffer group 309. The adjustment code detection unit 307 detects a predetermined adjustment code from the parallel data. In addition, in FIG. 3, the first parallel data shows the parallel data propagating through the first lane Lane A1 of the link A and input to the in-link skew adjustment circuit 135. Further, in FIG. 3, the second parallel data shows the parallel data propagating through the second lane Lane A2 of the link A and input to the in-link skew adjustment circuit 135. Further, in FIG. 3, the third parallel data shows the parallel data propagating through the third lane Lane A3 of the link A and input to the in-link skew adjustment circuit 135.

When the adjustment code is detected, the adjustment code detection unit 307 supplies an adjustment code detection signal indicating that the adjustment code has been detected to the read pointer generation unit 330. Since the configurations of the buffer control units 311 and 321 and the configurations of the buffer control unit 301 are the same, the description of the configurations of the buffer control units 311 and 321 will be omitted here. In FIG. 3, the first adjustment code detection signal means the adjustment code detection signal supplied from the buffer control unit 301 to the read pointer generation unit 330. Further, in FIG. 3, the second adjustment code detection signal means the adjustment code detection signal supplied from the buffer control unit 311 to the read pointer generation unit 330. Further, in FIG. 3, the third adjustment code detection signal means the adjustment code detection signal supplied from the buffer control unit 321 to the read pointer generation unit 330.

The read pointer generation unit 330 performs the following processing. That is, it is based on the timing when the adjustment code detection signal is supplied from each of the buffer control units 301, 311 and 321 and the timing when the adjustment code detection signal is supplied from all the buffer control units 301, 311 and 321. Then, the following processing is performed. The read pointer generation unit 330 calculates the phase difference between the buffer control units 301, 311 and 321 respectively based on these. The read pointer generation unit 330 notifies each of the buffer control units 301, 311 and 321 of the read pointer of the buffer based on the phase difference calculated in this way. In FIG. 3, the first read pointer means a read pointer supplied from the read pointer generation unit 330 to the buffer control unit 301. The second read pointer means a read pointer supplied from the read pointer generation unit 330 to the buffer control unit 311. The third read pointer means a read pointer supplied from the read pointer generation unit 330 to the buffer control unit 321. Further, in FIG. 3, the first output data means the data output from the in-link skew adjustment circuit 135 to the first lane Lane A1 of the link A. The second output data means the data output from the in-link skew adjustment circuit 135 to the second lane Lane A2 of the link A. The third output data means the data output from the in-link skew adjustment circuit 135 to the third lane Lane A3 of the link A.

FIG. 11 is a diagram showing an example of the operation of the in-link skew adjustment circuit 135. Although the operation of the in-link skew adjustment circuit 135 will be described here, the operation of the in-link skew adjustment circuit 136 is the same as the operation of the in-link skew adjustment circuit 135. The read pointer generation unit 330 waits for the adjustment code detection signal to be supplied from the buffer control units 301, 311 and 321. The read pointer generation unit 330 starts incrementing the internal read pointer when the adjustment code detection signal is output from any one of the buffer control units 301, 311, and 321. Here, an example is shown in which the increment of the internal read pointer is started based on the supply of the first adjustment code detection signal from the buffer control unit 301. The read pointer generation unit 330 determines the offset value between the buffer control units 301, 311 and 321 respectively, based on the internal read pointer and the timing at which the adjustment code detection signal is notified. In the example shown in FIG. 11, since the internal read pointer is 1 at the timing when the second adjustment code detection signal reaches the High level, the read pointer generation unit 330 sets the offset of the buffer control unit 311 to 1. Is determined. Further, in the example shown in FIG. 11, since the internal read pointer is 2 at the timing when the third adjustment code detection signal reaches the High level, the offset of the buffer control unit 321 is determined to be 2.

When the adjustment code detection signal is supplied from all of the buffer control units 301, 311 and 321, the read pointer generation unit 330 performs the following processing on each of the buffer control units 301, 311 and 321. conduct. That is, the read pointer generation unit 330 notifies the buffer control units 301, 311 and 321 of the read pointer obtained by adding an offset value for removing the skew in the link to the internal read pointer. Each of the buffer control units 301, 311 and 321 reads data from the buffer group 309 according to the read pointer thus obtained. Therefore, the in-link skew adjustment circuit 135 can output the data from which the in-link skew has been removed to each lane.

FIG. 4 is a diagram showing an example of the operation of the in-link skew adjustment circuits 135 and 136. FIG. 4A shows an example of data input to the in-link skew adjustment circuits 135 and 136. FIG. 4B shows an example of data output from the in-link skew adjustment circuits 135 and 136. The horizontal axis in FIG. 4 is time. The input data 401, 402, and 403 show an example of data input to the in-link skew adjustment circuit 135 via the first lanes LaneA1 to 3rd lanes A3 of the link A, respectively. The input data 404, 405, and 406 show an example of data input to the in-link skew adjustment circuit 136 via the first lane B1 to the third lane B3 of the link B, respectively. Each input data is used, for example, when there is no training sequence data, a synchronization code provided corresponding to the beginning of each horizontal line, image data, and valid image data during the horizontal transfer period. Includes invalid codes that can be used. Each input data further includes, for example, an exit code indicating the end of the data string corresponding to one horizontal transfer period, and an IDLE code used in a period other than the horizontal transfer period.

The training sequence data contains certain predetermined adjustment codes. The in-link skew adjustment circuits 135 and 136 detect the adjustment code included in the training sequence data by the adjustment code detection unit 307, and perform the above processing to eliminate the in-link skew.

The output data 407, 408, and 409 show examples of data output from the in-link skew adjustment circuit 135 to the first to third lanes of the first processing path 150, which is the processing path of the link A, respectively. The output data 410, 411, and 412 show an example of data output from the in-link skew adjustment circuit 135 to the first to third lanes of the second processing path 151, which is the processing path of the link B, respectively. As shown in FIG. 4, the intra-link skew is eliminated, but the inter-link skew is not eliminated.

It is also conceivable to apply the in-link skew adjustment circuit 135 to all lanes of link A and link B to eliminate the skew in all lanes. However, as described above, the amount of interlink skew varies with each horizontal transfer period and is not constant. For this reason, it is preferable to eliminate the in-link skew at this stage.

The data processing circuits 137 and 138 detect a control code included in the input data, and output a control code detection signal indicating that the control code has been detected when the detected control code satisfies a predetermined condition. .. In other words, the data processing circuits 137 and 138 detect the control code included in the input data, determine the detected control code based on a predetermined condition, and output the control code detection signal corresponding to the determined control code. It can be said that it is a thing. FIG. 5 is a block diagram showing a data processing circuit 137. The data processing circuit 137 includes in-lane control code detection units 501, 502, 503, adders 504, 506, comparators 505, delay elements 508 to 531, selectors 507, 532, 534, and a decoder 533. Have.

The delay elements 508 to 531 are composed of, for example, flip-flops. Clock signals are input to the clock input terminals of the delay elements 508 to 531. The delay elements 508 to 531 operate in synchronization with the clock signal. The delay elements 508 to 531 shift the input data in the output direction (right direction in FIG. 5), respectively.

The input data propagating in each lane of the first processing path 150, which is the processing path of the link A, is input to the in-lane control code detection units 501 to 503, respectively. In FIG. 5, the first input data means data propagating through the first lane Lane A1 of the link A and input to the data processing circuit 137. Further, in FIG. 5, the second input data means data that propagates through the second lane LaneA2 of the link A and is input to the data processing circuit 137. Further, in FIG. 5, the third input data means data propagating through the third lane Lane A3 of the link A and input to the data processing circuit 137. The in-lane control code detection units 501 to 503 detect each control code included in the input data. When the in-lane control code detection units 501 to 503 detect the control code, they output the in-lane control code detection signal indicating that the control code has been detected to the adder 504, respectively. The adder 504 adds the in-lane control code detection signals supplied from the in-lane control code detection units 501 to 503. The added value obtained by the adder 504 is delayed by the delay elements 520 to 523 connected in series and supplied to the adder 506 and the selector 507. Further, the added value obtained by the adder 504 is output from the data processing circuit 137 as a first control code detection signal and supplied to the data processing circuit 138.

The delay elements 508 to 511 are connected in series. The delay elements 512 to 515 are connected in series. The delay elements 516 to 519 are connected in series. The delay elements 508 to 511 delay the first input data that has passed through the in-lane control code detection unit 501. The delay elements 512 to 515 delay the second input data that has passed through the in-lane control code detection unit 502. The delay elements 516 to 519 delay the third input data that has passed through the in-lane control code detection unit 503. In FIG. 5, the first output data means the data delayed by the delay elements 508 to 511. Further, in FIG. 5, the second output data means the data delayed by the delay elements 512 to 515. Further, in FIG. 5, the third output data means the data delayed by the delay elements 516 to 519. From the data processing circuit 137, the first parallel data including the first output data, the second output data, and the third output data is output to the interlink skew adjustment circuit 139.

The configuration of the data processing circuit 138 is the same as the configuration of the data processing circuit 137 shown in FIG. However, the data processing circuit 138 outputs a second control code detection signal instead of the first control code detection signal. Further, the data processing circuit 138 outputs a second in-link control code detection signal instead of the first in-link control code detection signal. The second control code detection signal output from the data processing circuit 138 is supplied to the data processing circuit 137. The delay elements 524 to 531 connected in series delay the second control code detection signal supplied from the data processing circuit 138.

The signals output from each of the delay elements 524 to 531 are input to the selector 532. The selector 532 selects one signal from the signals supplied from the delay elements 524 to 531 and supplies the selected signal to the adder 506. The selector 532 selects one of a plurality of signals supplied from the delay elements 524 to 531 based on the delay cycle number signal supplied from the interlink skew adjustment circuit 139.

A mode in which a control code is detected by using the in-lane control code detection units 501 to 503 without using the second control code detection signal supplied from the data processing circuit 138 is referred to as a first detection mode. .. On the other hand, a mode in which the control code is detected not only by using the in-lane control code detection units 501 to 503 but also by using the second control code detection signal supplied from the data processing circuit 138 is referred to as a second detection mode. I will call it.

The adder 506 adds the signal from the delay element 523 and the signal from the selector 532, and supplies the signal obtained by the addition to the selector 507. The selector 507 selects one of the signal from the delay element 523 and the signal from the adder 506, and outputs the selected signal. The former is selected in the first detection mode and the latter is selected in the second detection mode.

The selector 534 selects the threshold value used in the comparator 505 from two types of predetermined threshold values, and outputs the selected threshold value to the comparator 505. In the first detection mode, the selector 534 selects the first threshold. In the second detection mode, the selector 534 selects a second threshold.

The decoder 533 generates a mode switching signal by decoding the link-to-link synchronization establishment signal supplied from the link-to-link skew adjustment circuit 139, and supplies the generated mode switching signal to the selectors 507 and 534, respectively. The selectors 507 and 534 perform switching operations based on the mode switching signal supplied from the decoder 533.

The signal selected by the selector 507 and the signal selected by the selector 534 are input to the comparator 505. The comparator 505 compares the signal from the selector 507 with the signal from the selector 534, and when the signal from the selector 507 becomes equal to or greater than the threshold value supplied from the selector 534, the first in-link control code detection signal. Is output.

An example of the operation in the first detection mode will be described below. For example, when the in-lane control code detection signal is output from the in-lane control code detection units 501 and 502, and the in-lane control code detection signal is not output from the in-lane control code detection unit 503 due to a factor such as a bit error. , It becomes as follows. Since the in-lane control code detection signal is supplied from the in-lane control code detection units 501 and 502, and the in-lane control code detection signal is not supplied from the in-lane control code detection unit 503, the value obtained by the adder 504 is 2. Become. Since the selector 507 outputs a signal from the delay element 523, a value of 2 is input to one of the input terminals of the comparator 505. In the first detection mode, the selector 534 selects the first threshold. When the first threshold value is, for example, 2, a value of 2 is input to the other input terminal of the comparator 505. Since the value supplied from the selector 507 is equal to or higher than the value supplied from the selector 534, the comparator 505 outputs the first in-link control code detection signal.

An example of the operation in the second detection mode will be described below. For example, in the data processing circuit 137, the in-lane control code detection signal is output from the in-lane control code detection unit 501, and the in-lane control code detection signal is output from the in-lane control code detection units 502 and 503 due to factors such as a bit error. Is not output. On the other hand, in the data processing circuit 138, it is assumed that the in-lane control code detection signals are output from all the in-lane control code detection units 501 to 503. In this case, in the data processing circuit 137, the value output from the adder 504 is 1, and in the data processing circuit 138, the value output from the adder 504 is 3. Since the value output from the adder 504 provided in the data processing circuit 138 is 3, the value of the second control code detection signal supplied from the data processing circuit 138 to the data processing circuit 137 is 3. Since the value output from the delay element 523 is 1 and the value output from the selector 532 is 3, the value output from the adder 506 is 4. In the second detection mode, the selector 507 selects the signal from the adder 506, so that a value of 4 is input to one input terminal of the comparator 505. In the second detection mode, selector 534 selects a second threshold. When the second threshold value is, for example, 4, a value of 4 is input to the other input terminal of the comparator 505. Since the value supplied from the selector 507 is equal to or higher than the value supplied from the selector 534, the comparator 505 outputs the first in-link control code detection signal.

The second control code detection signal supplied from the data processing circuit 138 is delayed by the delay elements 524 to 531. Then, a second control code detection signal having a phase corresponding to the delay cycle number signal supplied from the interlink skew adjustment circuit 139 is selected by the selector 532. Therefore, the phase of the signal supplied from the delay element 523 to the adder 506 matches the phase of the signal supplied from the selector 532 to the adder 506, and an appropriate addition value is output from the adder 506. ..

As described above, according to the present embodiment, it is possible to comprehensively evaluate the control code detection results of a plurality of lanes. Therefore, even if a bit error occurs in a specific lane and the control code cannot be detected in the lane, it is possible to operate satisfactorily. That is, according to the present embodiment, it is possible to secure sufficient error tolerance.

The mode switching signal supplied from the decoder 533 switches between the first detection mode and the second detection mode. The decoder 533 operates as follows, for example. The decoder 533 selects, for example, a mode switching signal for transitioning from the first detection mode to the second detection mode in the cycle immediately after receiving the interlink synchronization establishment signal supplied from the interlink skew adjustment circuit 139. Supply to 507 and 534. After outputting such a mode switching signal, the decoder 533 counts a predetermined cycle by a counter provided in the decoder 533. After counting a predetermined cycle, the decoder 533 supplies the selectors 507 and 534 with a mode switching signal for transitioning from the second detection mode to the first detection mode. Therefore, after a predetermined time has elapsed from the transition from the first detection mode to the second detection mode, the transition from the second detection mode to the first detection mode is performed. For example, the transition from the second detection mode to the first detection mode is performed at the timing corresponding to the horizontal synchronization signal HD supplied after the transition from the first detection mode to the second detection mode is performed. Will be. If the predetermined cycle is the number of cycles according to the horizontal transfer period, the synchronization code can be detected in the first detection mode, and the invalid code and the end code can be detected in the second detection mode. can. As a result, even if the data processing circuit 137 can detect the invalid code or the end code only below the threshold value, the invalid code or the end code can be evaluated by evaluating it together with the number of invalid codes or the end codes detected by the data processing circuit 138. The exit code can be detected. Therefore, error tolerance can be improved as compared with the case where the synchronization code is detected for each lane. For example, even if the in-lane control code detection unit that does not output the in-lane control code detection signal increases after the synchronization code is detected, it is possible to detect an invalid code or an exit code. This makes it possible to improve error tolerance.

Although the case where the decoder 533 generates a mode switching signal based on the link-to-link synchronization establishment signal supplied from the inter-link skew adjustment circuit 139 has been described here as an example, the present invention is not limited to this. For example, when a synchronization code is detected in the data processing circuit 137, a signal indicating that the synchronization code has been detected may be supplied to the decoder 533. Then, the decoder 533 may generate a mode switching signal based on the signal.

The data processing circuit 137 can function as a processing means for determining the detection of the control code. In the first detection mode, the data processing circuit 137 determines the detection of the control code based on the number of lanes in which the control code is detected among the plurality of lanes provided on the link A. In the first detection mode, the data processing circuit 137 determines the detection of the control code without being based on the number of detected lanes among the plurality of lanes provided on the link B. In the second mode, the data processing circuit 137 determines the number of lanes in which the control code among the plurality of lanes provided in the link A is detected and the control code among the plurality of lanes provided in the link B. Determines the detection of the control code based on the number of lanes detected.

FIG. 6 is a block diagram showing an in-lane control code detection unit 501. Although the in-lane control code detection unit 501 will be described here as an example, the configuration of the in-lane control code detection unit 502, the configuration of the in-lane control code detection unit 503, and the configuration of the in-lane control code detection unit 501 are described. Is similar to. Further, here, a case where each control code is composed of four symbols will be described as an example. Further, as the control code, a case where a synchronization code, an invalid code, and an exit code can be detected will be described as an example.

As shown in FIG. 6, the in-lane control code detection unit 501 includes delay elements 601-604, comparators 605-608, 611-614, 617-620, adders 609, 615, 621, and a comparator 610. , 616, 622 and.

The delay elements 601 to 604 are connected in series and delay the input data. A clock signal is input to the clock input terminals of the delay elements 601 to 604. The output of the delay element 601 is input to the comparators 605, 611, and 617, respectively. The output of the delay element 602 is input to the comparators 606, 612, and 618, respectively. The output of the delay element 603 is input to the comparators 607, 613, and 619, respectively. The output of the delay element 604 is input to the comparators 608, 614, and 620, respectively. The comparator 608 outputs 1 when the output of the delay element 604 and the expected value X1 match, and outputs 0 when the output of the delay element 604 and the expected value X1 do not match. The comparator 607 outputs 1 when the output of the delay element 603 and the expected value X2 match, and outputs 0 when the output of the delay element 603 and the expected value X2 do not match. The comparator 606 outputs 1 when the output of the delay element 602 and the expected value X3 match, and outputs 0 when the output of the delay element 602 and the expected value X3 do not match. The comparator 605 outputs 1 when the output of the delay element 601 and the expected value X4 match, and outputs 0 when the output of the delay element 601 and the expected value X4 do not match. The comparator 614 outputs 1 when the output of the delay element 604 and the expected value Y1 match, and outputs 0 when the output of the delay element 604 and the expected value Y1 do not match. The comparator 613 outputs 1 when the output of the delay element 603 and the expected value Y2 match, and outputs 0 when the output of the delay element 603 and the expected value Y2 do not match. The comparator 612 outputs 1 when the output of the delay element 602 and the expected value Y3 match, and outputs 0 when the output of the delay element 602 and the expected value Y3 do not match. The comparator 611 outputs 1 when the output of the delay element 601 and the expected value Y4 match, and outputs 0 when the output of the delay element 601 and the expected value Y4 do not match. The comparator 620 outputs 1 when the output of the delay element 604 and the expected value Z1 match, and outputs 0 when the output of the delay element 604 and the expected value Z1 do not match. The comparator 619 outputs 1 when the output of the delay element 603 and the expected value Z2 match, and outputs 0 when the output of the delay element 603 and the expected value Z2 do not match. The comparator 618 outputs 1 when the output of the delay element 602 and the expected value Z3 match, and outputs 0 when the output of the delay element 602 and the expected value Z3 do not match. The comparator 617 outputs 1 when the output of the delay element 601 and the expected value Z4 match, and outputs 0 when the output of the delay element 601 and the expected value Z4 do not match. The expected values X1 to X4 correspond to, for example, the values of the four symbols of the synchronization code. The expected values Y1 to Y4 correspond to, for example, the values of the four symbols of the invalid code. The expected values Z1 to Z4 correspond to, for example, the values of the four symbols of the end code. The signals output from the comparators 605 to 608 are supplied to the adder 609. The signals output from the comparators 611 to 614 are supplied to the adder 615. The signals output from the comparators 617 to 620 are supplied to the adder 621. The added values obtained by the adders 609, 615 and 621 are supplied to the comparators 610, 616 and 622, respectively. The comparators 610, 616, and 622 compare the values supplied from the adders 609, 615, and 621, respectively, with the preset threshold values, respectively. The comparator 610 outputs a synchronization code detection signal when the addition value obtained by the adder 609 is equal to or greater than the threshold value. The comparator 616 outputs an invalid code detection signal when the added value obtained by the adder 615 is equal to or greater than the threshold value. The comparator 622 outputs an exit code detection signal when the addition value obtained by the adder 621 is equal to or greater than the threshold value. These detection signals are bundled and output as an in-lane control code detection signal. Further, the data delayed by the delay elements 601 to 604 is output from the in-lane control code detection unit 501 as output data, respectively.

The formats of the first in-link control code detection signal, the second in-link control code detection signal, the first control code detection signal, and the second control code detection signal are not particularly limited. For example, the first in-link control code detection signal, the second in-link control code detection signal, the first control code detection signal, and the second control code detection signal are assigned to separate fields of the multi-bit signal. It may have been.

FIG. 7 is a diagram showing an example of the operation of the in-lane control code detection unit 501. Although the in-lane control code detection unit 501 will be described here as an example, both the in-lane control code detection unit 502 and the in-lane control code detection unit 503 can operate in the same manner as the in-lane control code detection unit 501. .. FIG. 7 shows an example of data input to the in-lane control code detection unit 501 and an example of the expected value of the control code. The first symbol of the expected value is, for example, all 0, that is, 0x00. On the other hand, the first symbol of the input data is also, for example, all 0. Therefore, for the first symbol, the expected value and the input data match. The second symbol of the expected value is, for example, all zeros. On the other hand, the second symbol of the input data is also all 0. Therefore, the expected value and the input data of the second symbol also match. The third symbol of the expected value is, for example, all 1, ie 0xFF. On the other hand, the third symbol of the input data is 0xFD because the data is damaged due to, for example, a bit error. Therefore, in this case, the expected value and the input data do not match for the third symbol. The fourth symbol of the expected value is, for example, all ones. On the other hand, the fourth symbol of the input data is also all 1. Therefore, for the fourth symbol, the expected value and the input data match. As described above, in the example shown in FIG. 7, the three symbols match between the expected value and the input data. When the threshold value is 3, the number of matches between the symbol of the expected value and the symbol of the input data is equal to or greater than the threshold value, so that the control code detection signal is output from the in-lane control code detection unit 501. In this way, the in-lane control code detection unit 501 detects the control code based on the number of normally detected symbols among the plurality of symbols constituting the control code. Since the control code is detected in this way, it is possible to improve the error tolerance according to the present embodiment.

The inter-link skew adjusting circuit 139 is for eliminating the inter-link skew. FIG. 8 is a block diagram showing an interlink skew adjustment circuit 139. As shown in FIG. 8, the interlink skew adjusting circuit 139 includes delay elements 801-824, a decoder 825, a loaded D-type flip-flop 826, and a selector 827. The delay elements 801-824 are composed of, for example, flip-flops. Clock signals are input to the clock input terminals of the delay elements 801 to 824, respectively. The delay elements 801-824 operate in synchronization with the clock signal. The delay elements 801 to 824 shift the input data in the output direction (right direction in FIG. 8), respectively.

The delay elements 801-804 connected in series delay the first parallel signal supplied from the data processing circuit 137. The delay elements 805 to 808 connected in series delay the first in-link control code detection signal supplied from the data processing circuit 137. The delay elements 809 to 816 connected in series delay the second parallel signal supplied from the data processing circuit 138. The signals output from each of the delay elements 809 to 816 are input to the selector 827. The delay elements 817 to 824 connected in series delay the second in-link control code detection signal supplied from the data processing circuit 138. The signals dyF1 to dyF8 output from each of the delay elements 817 to 824 are input to the decoder 825.

The decoder 825 detects a signal for which the second in-link control code detection signal is valid, that is, “1”, from the signals dryF1 to dryF8 output from each of the delay elements 817 to 824. The decoder 825 decodes such that the output of the delay elements 809 to 816 holding the second parallel signal at the same timing as the timing when the second in-link control code detection signal is enabled is selected by the selector 827. Output data (decode signal). The D-type flip-flop 826 with load latches the output of the decoder 825 when the output of the delay element 808 reaches a high level. The selector 827 selects the output from any of the delay elements 809 to 816 according to the decoded data supplied from the loaded D-type flip-flop 826. The first data output from the delay element 804 and the second data selected by the selector 827 are concatenated to obtain output data. The output of the delay element 808 is output from the interlink skew adjustment circuit 139 as an interlink control code detection signal.

The interlink control code detection signal output from the delay element 808 is supplied to the data processing circuits 137 and 138 as an interlink synchronization establishment signal. Further, the output of the decoder 825 is supplied to the data processing circuits 137 and 138 as a delay cycle number signal.

FIG. 9 is a diagram showing an example of the operation of the interlink skew adjustment circuit 139. Here, a skew corresponding to one cycle of the clock signal is generated between the first parallel signal supplied from the data processing circuit 137 and the second parallel signal supplied from the data processing circuit 138. A case will be described as an example.

As described above, the decoder 825 selects the output of the delay elements 809 to 816 holding the second parallel signal at the same timing as the timing when the second in-link control code detection signal is enabled by the selector 827. Output the decoded data as it is.

As described above, the output of the decoder 825 is latched when the output of the delay element 808 reaches a high level. Therefore, the first parallel signal delayed by, for example, four cycles of the clock signal and the second parallel signal delayed by, for example, three cycles of the clock signal are available. It is output as output data in the state.

As described above, according to the present embodiment, the detection of the control code is determined based on the number of lanes in which the control code is detected among the plurality of lanes provided in the link. Therefore, according to the present embodiment, the control code can be detected even when a lane in which the control code cannot be detected occurs due to a bit error or the like. Therefore, according to the present embodiment, it is possible to provide a signal processing device and a signal processing method having high error tolerance.

Further, according to the present embodiment, in the first detection mode, the detection of the control code is determined based on the number of lanes in which the control code is detected among the plurality of lanes provided in the link A. In the first detection mode, the detection of the control code is confirmed without being based on the number of detected lanes among the plurality of lanes provided on the link B. On the other hand, in the second detection mode, the number of lanes in which the control code among the plurality of lanes provided in the link A is detected and the control code among the plurality of lanes provided in the link B are detected. Confirm the detection of the control code based on the number of lanes. Therefore, even if the number of lanes from which the control code cannot be detected increases, for example, after the synchronization code is detected, it is possible to detect, for example, an invalid code and an exit code. Thereby, according to this embodiment, it is possible to improve the error tolerance.

Further, according to the present embodiment, not only the skew between links but also the skew between lanes can be eliminated, so that transmission can be performed satisfactorily.

[Second Embodiment]
The signal processing apparatus and the signal processing method according to the second embodiment will be described with reference to FIGS. 11 and 12. The same components as those of the signal processing apparatus and the signal processing method according to the first embodiment shown in FIGS. 1 to 10 are designated by the same reference numerals, and the description thereof will be omitted or simplified.

In the signal processing apparatus according to the present embodiment, the number of symbols of the synchronization code is different from the number of symbols of the invalid code and the end code.

FIG. 12 is a block diagram showing a transmission data processing circuit 106 provided in the signal processing apparatus according to the present embodiment. Although the transmission data processing circuit 106 will be described here, the configuration of the transmission data processing circuit 107 is the same as the configuration of the transmission data processing circuit 106.

The transmission data processing circuit 106 according to the present embodiment is different from the transmission data processing circuit 106 according to the first embodiment in that a control code generation unit 209 is further provided. The control code generation unit 203 generates, for example, a synchronization code, and supplies the generated synchronization code to each of the output selectors 206 to 208. The control code is composed of, for example, four symbols. The control code generation unit 209 generates, for example, an invalid code and an end code, and supplies the generated invalid code and the end code to each of the output selectors 206 to 208. The invalid code and the exit code are composed of, for example, three symbols.

FIG. 13 is a block diagram showing an in-lane control code detection unit 501 provided in the signal processing device according to the present embodiment. Although the in-lane control code detection unit 501 will be described here, the configuration of the in-lane control code detection unit 502 and the configuration of the in-lane control code detection unit 503 are the same as the configuration of the in-lane control code detection unit 501. Is.

The in-lane control code detection unit 501 in the present embodiment is different from the in-lane control code detection unit 501 in the first embodiment in that the comparators 611 and 617 are not provided. The output of the delay element 601 is input only to the comparator 605. The output of the delay element 602 is input to the comparators 606, 612, and 618, respectively. The output of the delay element 603 is input to the comparators 607, 613, and 619, respectively. The output of the delay element 604 is input to the comparators 608, 614, and 620, respectively. The expected values X1 to X4 correspond to, for example, the values of the four symbols of the synchronization code. The expected values Y1 to Y3 correspond to, for example, the values of the three symbols of the invalid code. The expected values Z1 to Z3 correspond to the values of the three symbols of the end code, respectively. The signals output from the comparators 605 to 608 are supplied to the adder 609. The signals output from the comparators 612 to 614 are supplied to the adder 615. The signals output from the comparators 618 to 620 are supplied to the adder 621.

The added values obtained by the adders 609, 615 and 621 are supplied to the comparators 610, 616 and 622, respectively. The comparators 610, 616, and 622 compare the values supplied from the adders 609, 615, and 621, respectively, with the preset threshold values, respectively. The comparator 610 outputs a synchronization code detection signal when the addition value obtained by the adder 609 is equal to or greater than the threshold value. The comparator 616 outputs an invalid code detection signal when the added value obtained by the adder 615 is equal to or greater than the threshold value. The comparator 622 outputs an exit code detection signal when the addition value obtained by the adder 621 is equal to or greater than the threshold value. These detection signals are bundled and output as an in-lane control code detection signal. Further, the data delayed by the delay elements 601 to 604 is output from the in-lane control code detection unit 501 as output data, respectively.

In the present embodiment, the number of symbols of the invalid code and the end code is smaller than the number of symbols of the synchronization code, but the invalid code and the end code are detected in the second detection mode. In the second detection mode, the control code is determined based not only on the control code detected in the plurality of lanes provided on the link A but also on the control code detected in the plurality of lanes provided on the link B. Will be done. Therefore, even if the number of symbols of the invalid code and the end code is small, sufficient error tolerance can be ensured.

As described above, according to the present embodiment, since the number of symbols of the invalid code and the end code is small, it is possible to contribute to the reduction of the amount of data. Since the invalid code and the exit code are detected in the second detection mode, sufficient error tolerance is ensured.

[Modification Embodiment]
Although the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications and modifications can be made within the scope of the gist thereof.
For example, in the above embodiment, a case where the control code is composed of a plurality of symbols and the control code is detected based on the number of normally detected symbols among the plurality of symbols constituting the control code has been described as an example. However, it is not limited to this. For example, the adjustment code may be composed of a plurality of symbols, and the adjustment code may be detected based on the number of normally detected symbols among the plurality of symbols constituting the adjustment code.

Further, in the above embodiment, the case where the amount of skew between links varies for each horizontal transfer period has been described as an example, but the present invention is not limited to this. For example, when the amount of skew between links fluctuates for each vertical transfer period (VD period) and does not fluctuate for each horizontal transfer period, the following can be done. That is, the synchronization code first detected in the vertical transfer period is detected in the first detection mode, and the synchronization code other than the synchronization code first detected in the vertical transfer period is detected in the second detection mode. .. Both the invalid code and the exit code are detected in the second detection mode. In this case, the second detection mode is changed to the first detection mode at the timing corresponding to the vertical synchronization signal VD supplied after the transition from the first detection mode to the second detection mode is performed. A transition is made.

The present invention supplies a program that realizes one or more functions of the above-described embodiment to a system or device via a network or storage medium, and one or more processors in the computer of the system or device reads and executes the program. It can also be realized by the processing to be performed. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

100 ... Image sensor 140 ... Image processing unit

Claims (14)

Multiple first lanes and
A first transmitting means, which is driven by the first driving means and supplies a signal including a control code to each of the plurality of first lanes.
Among the plurality of first lane, and a first processing means for generating a first detection signal based on the number of the first lane the control code is detected
And the first link that having a,
Multiple second lanes and
A second transmitting means, which is driven by the second driving means and supplies a signal including a control code to each of the plurality of second lanes.
Among the plurality of second lane, and a second processing means for generating a second detection signal based on the number of the second lane the control code is detected
And the second link that having a,
Adjustment to adjust the timing of the plurality of signals transmitted in the plurality of first lanes and the plurality of signals transmitted in the plurality of second lanes based on the first detection signal and the second detection signal. Means and
Have,
The first processing means includes a first mode for generating the first detection signal based on the number of the first lanes in which the control code is detected among the plurality of first lanes, and the plurality of first modes. The first detection signal is generated based on the number of the first lanes in which the control code is detected in one lane and the number of the second lanes in which the control code is detected in the plurality of second lanes. A signal processing device characterized in that it can operate in any of the second modes of generation. The signal includes a plurality of types of the control code.
Based on the detection of the first control code among the plurality of types of control codes, the transition from the first mode to the second mode is performed.
It said first control code and detection of different second control code signal processing apparatus according to claim 1, wherein the benzalkonium performed in the second mode. The first control code is a synchronization code.
It said second control code, invalid code or signal processing apparatus according to claim 2, characterized in that the end code. The signal processing apparatus according to claim 2 or 3 , wherein the number of symbols constituting the first control code is larger than the number of symbols constituting the second control code. A claim characterized in that the transition from the second mode to the first mode is performed after a predetermined time has elapsed from the transition from the first mode to the second mode. Item 6. The signal processing apparatus according to any one of Items 1 to 4. The timing or the horizontal synchronization signal corresponding to the vertical synchronizing signal is supplied after the transition from the first mode to the second mode is performed, the transition from the second mode to the first mode The signal processing apparatus according to any one of claims 1 to 5 , wherein the signal processing apparatus is performed. The signal further comprises an adjustment code.
Wherein the first link, the skew of the signals propagating the plurality of the first lane, respectively, having a first adjusting means for eliminating using the adjustment code,
The second link, the skew of the signals propagating the plurality of the second lane, respectively, one of claims 1 to 6, characterized in Rukoto that having a second adjusting means for eliminating using the adjustment code The signal processing apparatus according to item 1. The first adjusting means and the second adjusting means detect the adjusting code when the number of normally detected symbols among the plurality of symbols constituting the adjusting code is equal to or more than the first threshold value. The signal processing apparatus according to claim 7. The first processing means and the second processing means detect the control code when the number of normally detected symbols among the plurality of symbols constituting the control code is equal to or greater than the second threshold value. The signal processing apparatus according to any one of claims 1 to 8. Each first lane and each second lane
A parallel serial converter that converts a parallel signal to a serial signal,
Together provided downstream of the parallel-serial converter, a serial-parallel converter for converting the serial signal output from the parallel-serial converter into a parallel signal,
The serial together are provided downstream of the parallel converter, the signal processing device according to any one of claims 1-9, characterized that you and a control code detecting means for detecting said control code. Further having an image acquisition means for acquiring an image,
The parallel the parallel signal converted by the serial converter to a signal processing apparatus according to claim 10, wherein the image signal der Turkey output from the image acquisition unit. The image acquisition means, the parallel serial converter, the first transmission means, and the second transmission means are provided on the first chip.
11. The eleventh claim is characterized in that the serial-parallel converter, the control code detecting means, the first processing means, and the second processing means are provided on a second chip different from the first chip. The signal processing device described. The first chip is an image pickup device that outputs an image signal based on an input optical image.
The signal processing apparatus according to claim 12 , wherein the second chip is an image processing chip that processes the image signal acquired from the image pickup device. A step of supplying a signal including a control code to each of the plurality of first lanes by a first transmitting means driven by the first driving means, and a step of supplying a signal including a control code.
A step of supplying a signal including a control code to each of the plurality of second lane by the second transmission means driven by the second driving means,
A step of generating a first detection signal based on the number of the first lanes in which the control code is detected among the plurality of first lanes.
A step of generating a second detection signal based on the number of the second lanes in which the control code is detected among the plurality of second lanes.
A step of adjusting the timing of a plurality of signals transmitted in the plurality of first lanes and a plurality of signals transmitted in the plurality of second lanes based on the first detection signal and the second detection signal. It has a door,
Step includes a first mode for generating a first detection signal based on the number of the first lane the control code is detected among the plurality of first lane to generate the first detection signal, The first lane is based on the number of the first lanes in which the control code is detected among the plurality of first lanes and the number of the second lanes in which the control code is detected among the plurality of second lanes. (1) A signal processing method characterized in that it can be executed in any of the second modes for generating a detection signal.

Images