JP6986909B2 - Semiconductor device - Google Patents

Description

One aspect of the present invention relates to semiconductor devices, electronic components, and electronic devices.

It should be noted that one aspect of the present invention is not limited to the above technical fields. The technical field of one aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. In particular, one aspect of the present invention relates to a semiconductor device, a display device, a light emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof.

In the present specification and the like, the semiconductor device refers to an element, a circuit, a device, or the like that can function by utilizing the semiconductor characteristics. As an example, a semiconductor element such as a transistor or a diode is a semiconductor device. As another example, the circuit having a semiconductor element is a semiconductor device. As another example, the device provided with the circuit having the semiconductor element is a semiconductor device.

With the development of information technology such as IoT (Internet of things) and AI (Artificial Intelligence), the amount of data handled is increasing. In order for electronic devices to use information technologies such as IoT and AI, semiconductor devices capable of storing a large amount of data are required. Further, in order to comfortably use electronic devices, semiconductor devices capable of high-speed treatment are required.

Patent Document 1 discloses a configuration of a product-sum calculation circuit in which the circuit scale is reduced by a method of using a memory in a digital circuit that performs a product-sum calculation.

Patent Document 2 discloses a configuration in which multi-valued data is stored by utilizing the fact that the threshold voltage of the transistor differs depending on the amount of charge stored in the node of the transistor in the memory cell.

Japanese Unexamined Patent Publication No. 1997-319730 U.S. Patent Application Publication No. 2012/0033488

Electronic devices that combine IoT and AI are required to be small and lightweight. Further, electronic parts used in electronic devices are required to be miniaturized so that they can be stored in a narrow space. Therefore, miniaturization of electronic components has a problem of reducing the circuit scale without reducing the processing capacity. Further, electronic components are required to have lower power consumption as they become smaller.

In AI, it is possible to obtain an excellent detection effect for extracting features by machine learning from various information (image, voice, big data, etc.). AI is known to process information by neural networks. In a neural network, it has a multi-layer perceptron, and the perceptron has multiple neurons. Neurons are known to perform multiply-accumulate processing that imitates synaptic functions. The product-sum calculation circuit is known to calculate the sum of the results of multiplying a plurality of input signals by a weighting coefficient. However, since the operation of the neuron is processed by the digital operation, there is a problem that the logic scale becomes large. In addition, there is a problem that the power consumption increases in proportion to the size of the logical scale.

In view of the above problems, one aspect of the present invention is to provide a semiconductor device having a novel configuration. Alternatively, one aspect of the present invention is to provide a semiconductor device in which a neuron outputs an analog signal. Alternatively, one aspect of the present invention is to provide a semiconductor device that reduces the power consumption of neurons. Alternatively, one aspect of the present invention is to provide a semiconductor device that corrects variations when a neuron performs an operation with an analog signal.

The description of these issues does not preclude the existence of other issues. It should be noted that one aspect of the present invention does not need to solve all of these problems. Issues other than these are self-evident from the description of the description, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. Is.

The problems of one aspect of the present invention are not limited to the problems listed above. The issues listed above do not preclude the existence of other issues. Other issues are issues not mentioned in this item, which are described below. Issues not mentioned in this item can be derived from the description of the description, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions. In addition, one aspect of the present invention solves at least one of the above-listed descriptions and / or other problems.

One aspect of the present invention is a semiconductor device having a neural network, in which the neural network has a first perceptron, a second perceptron, and a feedback circuit. The first perceptron has a first neuron, a second neuron, and a first output circuit, and the second perceptron has a third neuron, a fourth neuron, and a second. The first neuron to the fourth neuron each have a synaptic circuit, the synaptic circuit has a plurality of multiplication circuits, and the multiplication circuit has a memory cell. A first perceptron and a second perceptron are electrically connected to the feedback circuit. The memory cell has a function of storing the weighting coefficient, and the multiplication circuit has a function of multiplying the weighting coefficient stored in the memory cell and the input data given to the memory cell. The synaptic circuit of the first perceptron has a function of adding the calculation results of a plurality of multiplication circuits to generate a first signal and outputting it to the first output circuit, and the first output circuit is the first. The signal is converted into a second signal having a lower impedance than that of the first signal, and the first output circuit has a function of outputting the second signal to the feedback circuit. The synaptic circuit of the second perceptron has a function of adding the calculation results of a plurality of multiplication circuits to generate a third signal and outputting it to the second output circuit, and the second output circuit has a second output circuit. The second output circuit has a function of converting the signal of 3 into a fourth signal having a lower impedance than that of the third signal, and the second output circuit has a function of outputting the fourth signal to the feedback circuit. The feedback circuit has a function of giving a fourth output signal to the first output circuit, and the first output circuit has a function of adding and outputting the fourth signal and the second signal. It is a semiconductor device.

In each of the above configurations, the first output circuit has a function of generating the first correction data, and the second output circuit has a function of generating the second correction data. The feedback circuit has a function of applying the first correction data to the first output circuit so that the second output signal is corrected by the first correction data, and the second correction data is the second correction data. A semiconductor device having a function of correcting the fourth output signal by the second correction data by giving it to the output circuit of 2 is preferable.

In each of the above configurations, the semiconductor device further includes a scan driver circuit. The scan driver circuit is preferably a semiconductor device having a function of writing a weighting coefficient to the memory cells of the first perceptron and the second perceptron at the same time.

In each of the above configurations, the semiconductor device further has a third perceptron. The synaptic circuit of the third perceptron has a function of adding the calculation results of a plurality of multiplication circuits to generate a fifth signal and outputting it to the third output circuit. The third output circuit has a function of converting a fifth signal having a high input impedance into a sixth signal having a low output impedance, and the third output circuit has a function of outputting the sixth signal to the feedback circuit. The feedback circuit has a function of giving a sixth output signal to the first output circuit, and the first output circuit adds and outputs the sixth signal and the second signal. A semiconductor device having a function is preferable.

In each of the above configurations, the feedback circuit has a function of giving a sixth output signal to the second output circuit, and the second output circuit adds and outputs the sixth signal and the fourth signal. A semiconductor device having such a function is preferable.

In each of the above configurations, the feedback circuit has a function of giving a second output signal to the third output circuit, and the third output circuit adds the second signal and the sixth signal and outputs them. A semiconductor device having such a function is preferable.

In each of the above configurations, the feedback circuit is preferably a semiconductor device having a function of outputting a second signal and a fourth signal as monitor signals.

In each of the above configurations, the memory cell further includes a transistor, and the transistor is preferably a semiconductor device having a metal oxide in the semiconductor layer.

In each of the above configurations, an electronic component characterized by having a lead electrically connected to the semiconductor device is preferable.

In each of the above configurations, an electronic device characterized by having a printed circuit board provided with the electronic components and a housing in which the printed circuit board is stored is preferable.

In each of the above configurations, an electronic component characterized by having a lead electrically connected to the semiconductor device is preferable.

In each of the above configurations, an electronic device characterized by having a printed circuit board provided with the electronic components and a housing in which the printed circuit board is stored is preferable.

One aspect of the present invention can provide a semiconductor device having a novel configuration. Alternatively, one aspect of the present invention can provide a semiconductor device in which a neuron outputs an analog signal. Alternatively, one aspect of the present invention can provide a semiconductor device that reduces the power consumption of neurons. Alternatively, one aspect of the present invention can provide a semiconductor device that corrects variations when a neuron performs an operation with an analog signal.

The effect of one aspect of the present invention is not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are the effects not mentioned in this item, which are described below. Effects not mentioned in this item can be derived from the description in the specification, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions. In addition, one aspect of the present invention has at least one of the above-listed effects and / or other effects. Therefore, one aspect of the present invention may not have the effects listed above in some cases.

A block diagram illustrating a neural network. A block diagram illustrating a semiconductor device. A block diagram illustrating a semiconductor device. A circuit diagram illustrating a semiconductor device. A circuit diagram illustrating a semiconductor device. (A) A circuit diagram illustrating a semiconductor device. (B) The figure explaining the output characteristic of a semiconductor device. A circuit diagram illustrating a semiconductor device. A circuit diagram illustrating a semiconductor device. A circuit diagram illustrating a semiconductor device. A circuit diagram illustrating a semiconductor device. A circuit diagram illustrating a semiconductor device. A circuit diagram illustrating a semiconductor device. Timing chart for driving semiconductor devices. A circuit diagram illustrating a semiconductor device. A circuit diagram illustrating a semiconductor device. A circuit diagram illustrating a semiconductor device. Timing chart for driving semiconductor devices. The figure which shows the structural example of the semiconductor device. The figure which shows the structural example of a transistor. The figure which shows the structural example of a transistor. The figure which shows the structural example of a transistor. The schematic diagram which shows the example of the electronic component. Schematic diagram showing an example of an electronic device. Schematic diagram showing an example of an electronic device.

Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that embodiments can be implemented in many different embodiments and that the embodiments and details can be varied in various ways without departing from the spirit and scope thereof. .. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings.

In addition, the ordinal numbers "first", "second", and "third" used in the present specification are added to avoid confusion of the components, and are not limited numerically. Addition.

Further, in the present specification, words and phrases indicating arrangements such as "above" and "below" are used for convenience in order to explain the positional relationship between the configurations with reference to the drawings. Further, the positional relationship between the configurations changes appropriately depending on the direction in which each configuration is depicted. Therefore, it is not limited to the words and phrases explained in the specification, and can be appropriately paraphrased according to the situation.

Further, in the present specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and the channel region is interposed between the source and the drain. It is capable of passing an electric current. In the present specification and the like, the channel region means a region in which a current mainly flows.

Further, the functions of the source and the drain may be switched when transistors having different polarities are adopted or when the direction of the current changes in the circuit operation. Therefore, in the present specification and the like, the terms source and drain can be used interchangeably.

Further, in the present specification and the like, "electrically connected" includes the case of being connected via "something having some kind of electrical action". Here, the "thing having some kind of electrical action" is not particularly limited as long as it enables the exchange of electric signals between the connection targets. For example, "things having some kind of electrical action" include electrodes, wirings, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

Further, in the present specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of −10 ° or more and 10 ° or less. Therefore, the case of −5 ° or more and 5 ° or less is also included. Further, "vertical" means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included.

Further, in the present specification and the like, the term "membrane" and the term "layer" can be interchanged with each other. For example, it may be possible to change the term "conductive layer" to the term "conductive layer". Alternatively, for example, it may be possible to change the term "insulating film" to the term "insulating layer".

Further, in the present specification and the like, unless otherwise specified, the off current means a drain current when the transistor is in an off state (also referred to as a non-conducting state or a cutoff state). Unless otherwise specified, the off state is a state in which the voltage Vgs between the gate and the source is lower than the threshold voltage Vth in the n-channel transistor, and the voltage Vgs between the gate and the source in the p-channel transistor. Is higher than the threshold voltage Vth. For example, the off-current of an n-channel transistor may refer to the drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage Vth.

The off current of the transistor may depend on Vgs. Therefore, the fact that the off current of the transistor is I or less may mean that there is a value of Vgs in which the off current of the transistor is I or less. The off-current of a transistor may refer to an off-current in a predetermined Vgs, an off-state in Vgs within a predetermined range, an off-state in Vgs in which a sufficiently reduced off-current is obtained, and the like.

As an example, the threshold voltage Vth is 0.5 V, the drain current at Vgs is 0.5 V is 1 × 10 ^-9 A, and the drain current at Vgs is 0.1 V is 1 × 10 ^-13 A. Assume an n-channel transistor having a drain current of 1 × 10 ^-19 A at Vgs of −0.5 V and a drain current of 1 × 10 ^{-22 A at Vgs of −0.8 V. Since the drain current of the transistor is 1 × 10 -19} A or less in the range of Vgs of −0.5 V or Vgs in the range of −0.5 V to −0.8 V, the off current of the transistor is 1. It may be said that it is × 10 ^{-19 A or less.} Since there are Vgs in which the drain current of the transistor is 1 × ^10-22 A or less, the off current of the transistor may be 1 × 10 ^-22 A or less.

Further, in the present specification and the like, the off-current of a transistor having a channel width W may be represented by a current value flowing per channel width W. Further, it may be represented by a current value flowing around a predetermined channel width (for example, 1 μm). In the latter case, the unit of off-current may be expressed in units having a current / length dimension (eg, A / μm).

The off current of the transistor may depend on the temperature. In the present specification, the off-current may represent an off-current at room temperature, 60 ° C., 85 ° C., 95 ° C., or 125 ° C., unless otherwise specified. Alternatively, at a temperature at which the reliability of the semiconductor device or the like containing the transistor is guaranteed, or at a temperature at which the semiconductor device or the like containing the transistor is used (for example, any one of 5 ° C. and 35 ° C.). May represent off-current. The off current of a transistor is I or less, which means that the temperature is room temperature, 60 ° C, 85 ° C, 95 ° C, 125 ° C, the temperature at which the reliability of the semiconductor device including the transistor is guaranteed, or the transistor is included. It may indicate that there is a value of Vgs in which the off-current of the transistor is I or less at the temperature at which the semiconductor device or the like is used (for example, any one of 5 ° C. to 35 ° C.).

The off current of the transistor may depend on the voltage Vds between the drain and the source. In the present specification, the off current has Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V unless otherwise specified. , Or may represent off-current at 20V. Alternatively, it may represent Vds in which the reliability of the semiconductor device or the like including the transistor is guaranteed, or the off-current in Vds used in the semiconductor device or the like including the transistor. When the off current of the transistor is I or less, Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V. , There is a value of Vgs in which the off current of the transistor is I or less in Vds in which the reliability of the semiconductor device or the like including the transistor is guaranteed, or Vds in which the reliability of the semiconductor device or the like including the transistor is guaranteed. It may refer to that.

In the above description of the off-current, the drain may be read as the source. That is, the off current may refer to the current flowing through the source when the transistor is in the off state.

Further, in the present specification and the like, it may be described as a leak current in the same meaning as an off current. Further, in the present specification and the like, the off current may refer to, for example, the current flowing between the source and the drain when the transistor is in the off state.

The voltage means the potential difference between two points, and the potential means the electrostatic energy (electrical potential energy) of the unit charge in the electrostatic field at a certain point. However, in general, the potential difference between the potential at a certain point and the reference potential (for example, the ground potential) is simply called potential or voltage, and potential and voltage are often used as synonyms. Therefore, unless otherwise specified in the present specification, the potential may be read as a voltage, or the voltage may be read as a potential.

(Embodiment 1)
In the present embodiment, the semiconductor device having the function of the neural network will be described with reference to FIGS. 1 to 14.

FIG. 1 is a block diagram illustrating a configuration when the semiconductor device 100 functions as a neural network.

FIG. 1 shows an example of a typical neural network composed of three layers (input layer 102a, intermediate layer 102b, and output layer 102c). Each layer may be paraphrased as a perceptron. The neural network further has an output circuit 108 and a feedback circuit 109.

The input layer 102a has a memory cell array 103a and an output circuit 104a, the intermediate layer 102b has a memory cell array 103b and an output circuit 104b, and the output layer 102c has a memory cell array 103c and an output circuit 104c. Have.

FIG. 1 shows an example in which the perceptron has three neurons, but the number of neurons is not limited to three. Perceptrons can have m neurons. Also, each perceptron may have a different number of neurons. Further, the layer of the perceptron is not limited to the input layer 102a, the intermediate layer 102b, and the output layer 102c. The intermediate layer 102b may be composed of a plurality of layers. For example, the perceptron can have a hierarchy of 1 or more and s or less. Hereinafter, each perceptron will be referred to as an input layer 102a, an intermediate layer 102b, and an output layer 102c. m is an integer of 1 or more, and s is an integer of 2 or more.

The intermediate layer 102b is electrically connected to the input layer 102a, the output layer 102c is electrically connected to the intermediate layer 102b, and the output circuit 108 is electrically connected to the output layer 102c. The input layer 102a, the intermediate layer 102b, and the output circuit 104a to the output circuit 104c of the output layer 102c are electrically connected to the feedback circuit 109.

To illustrate the perceptron, the input layer 102a, the intermediate layer 102b, and the output layer 102c will be described. The perceptron has a plurality of neurons and an output circuit, the neurons have a synaptic circuit, the synaptic circuit has a plurality of multiplication circuits, and the multiplication circuit has a memory cell.

The weight coefficient can be stored in the memory cell, and the multiplication circuit can multiply the weight coefficient stored in the memory cell by the input data given to the memory cell.

The input layer 102a has neurons NP1 to neurons NP3. As an example, the neuron NP1 will be described. The neuron NP1 can output the input data Xin [j] as the first signal to the first output circuit. At this time, the input data Xin [j] may be multiplied by a weighting coefficient to generate a first signal. The output circuit 104a can convert a first signal having a high input impedance into a second signal having a low output impedance. The output circuit 104a can output the second signal to the neurons NQ1 to NQ3 of the intermediate layer 102b and the feedback circuit 109. j is a variable indicating the number of the neuron, and is an integer of 1 or more and m or less.

Next, the intermediate layer 102b has neurons NQ1 to neurons NQ3. As an example, the neuron NQ1 will be described. The synaptic circuit of the neuron NQ1 can output the calculation result of the weighting coefficient stored in the memory cell of the multiplication circuit and the second signal given from the neuron NP1 to the output circuit 104b as a third signal. can. At this time, it is preferable that the calculation result of the neuron NP2 and the weighting coefficient and the calculation result of the neuron NP3 and the weighting coefficient are added to the third signal. The output circuit 104b can convert a third signal having a high input impedance into a fourth signal having a low output impedance. The output circuit 104b can output the fourth signal to the neurons NR1 to NR3 of the intermediate layer 102b and the feedback circuit 109.

Next, the output layer 102c has neurons NR1 to neurons NR3. As an example, the neuron NR1 will be described. The synaptic circuit of the neuron NR1 can output the calculation result of the weighting coefficient stored in the memory cell of the multiplication circuit and the fourth signal given from the neuron NQ1 to the output circuit 104c as the fifth signal. can. At this time, it is preferable that the calculation result of the neuron NQ2 and the weighting coefficient and the calculation result of the neuron NQ3 and the weighting coefficient are added to the fifth signal. The output circuit 104c can convert a fifth signal having a high input impedance into a sixth signal having a low output impedance. The output circuit 104c can output the sixth signal to the output circuit 108 and the feedback circuit 109. The output circuit 108 has a comparison circuit, and the result determined by the comparison circuit is used by a control circuit or processor of an electronic device (not shown).

It is preferable that different weight coefficients are set for the weight coefficients stored in the memory cells. Alternatively, the same weighting factor may be set for the weighting factor stored in the memory cell.

FIG. 2 describes the semiconductor device 100 in which the neural network shown in FIG. 1 functions.

FIG. 2 has a memory cell array 101, a scan driver circuit 105, a weight driver circuit 106, a data driver circuit 107, an output circuit 108, and a feedback circuit 109. The memory cell array 101 has an input layer 102a, an intermediate layer 102b, and an output layer 102c. The input layer 102a has a memory cell array 103a and an output circuit 104a. The intermediate layer 102b has a memory cell array 103b and an output circuit 104b. The output layer 102c has a memory cell array 103c and an output circuit 104c.

The memory cell array 103a, the memory cell array 103b, and the memory cell array 103c have a plurality of neurons, each neuron has a synaptic circuit, the synaptic circuit has a plurality of multiplication circuits, and each multiplication circuit has a memory. Has a cell.

The weight coefficient is given as a voltage value from the weight driver circuit 106 to the memory cells included in the memory cell array 103a, the memory cell array 103b, and the memory cell array 103c by being selected by the scan driver circuit 105. The weighting factor is stored in the memory cell. Further, input data is given to the memory cell array 103a from the data driver circuit 107. That is, the input layer 102a has

In the memory cell in which the weighting factor is stored, the weighting factor is multiplied by the input data when the input data is given. The synaptic circuit included in the input layer 102a adds the multiplication results of a plurality of memory cells to generate a first signal. The first signal is output to the output circuit 104a.

Since the outputs of the plurality of memory cells are added to the first signal, the input impedance may be high. The output circuit 104a can convert the first signal into a second signal having a lower output impedance than the first signal. The second signal is given as an input signal of the memory cell array 103b, and is further output to the feedback circuit 109.

In the memory cell in which the weighting coefficient of the memory cell array 103b is stored, the weighting coefficient and the second signal are multiplied by the second signal. The synaptic circuit included in the intermediate layer 102b adds the multiplication results of a plurality of memory cells to generate a third signal. The third signal is output to the output circuit 104b.

Since the outputs of the plurality of memory cells are added to the third signal, the input impedance may be high. The output circuit 104b can convert the third signal into a fourth signal having a lower output impedance than the third signal. The fourth signal is given as an input signal of the memory cell array 103b, and is further output to the feedback circuit 109.

In the memory cell in which the weighting coefficient of the memory cell array 103c is stored, the weighting coefficient is multiplied by the fourth signal when the fourth signal is given. The synaptic circuit included in the output layer 102c adds the multiplication results of a plurality of memory cells to generate a fifth signal. The fifth signal is output to the output circuit 104c.

Since the outputs of the plurality of memory cells are added to the fifth signal, the input impedance may be high. The output circuit 104c can convert the fifth signal into a sixth signal having a lower output impedance than the fifth signal. The sixth signal is given to the output circuit 108 and further output to the feedback circuit 109.

The feedback circuit 109 can output the input second signal, fourth signal, and sixth signal as monitor signals. A monitor signal is output as an analog signal to the signal line MDD, and a digital signal is output to the signal line MDD. Further, the feedback circuit 109 can give a second signal to the signal line FFBD. The second signal can be given to either the output circuit 104b or the output circuit 104c via the signal line FFBD. Alternatively, the feedback circuit 109 can give a fourth signal to the signal line FFBD. The fourth signal can be given to either the output circuit 104a or the output circuit 104c via the signal line FFBD. Alternatively, the feedback circuit 109 can give a sixth signal to the signal line FFBD. The sixth signal can be given to either the output circuit 104a or the output circuit 104b via the signal line FFBD.

In FIG. 3, the semiconductor device 100 will be described in more detail.

In FIG. 3, the semiconductor device 100 further includes a timing control circuit 110. Further, the scan driver circuit 105 has a first scan circuit 105a, a second scan circuit 105b, and a third scan circuit 105c. The weight driver circuit 106 includes a latch circuit 106a, a digital-to-analog conversion circuit 106b, and a source follower circuit 106c. The data driver circuit 107 includes a latch circuit 107a, a digital-to-analog conversion circuit 107b, and a source follower circuit 107c. The feedback circuit 109 includes a selection circuit 109a, a selection circuit 109b, an amplifier circuit 109c, an analog-to-digital conversion circuit 109d, an amplifier circuit 109e, and an amplifier circuit 109f.

The scan circuit 105a is preferably configured by a shift register circuit. Therefore, the scan circuit 105a can give a scan signal to the signal line WW of the memory cell array 103a. The scan circuit 105b can give a scan signal to the signal line WW of the memory cell array 103b. The scan circuit 105c can give a scan signal to the signal line WW of the memory cell array 103c. The scanning line WW will be described in detail with reference to FIG. 7.

The timing control circuit 110 can give a clock signal CK and a start pulse SP to the scan driver circuit 105. When the start pulse SP is given to the scan circuit 105a, the scan circuit 105a, the scan circuit 105b, and the scan circuit 105c are driven in this order, and the scan signals are sequentially given to the signal lines WW of the memory cell array 103a to the memory cell array 103c. .. Therefore, different weight data can be given to the memory cells included in the memory cell array 103a to the memory cell array 103c.

When the start pulse SP is simultaneously given to the scan circuit 105a, the scan circuit 105b, and the scan circuit 105c, the scan signal is simultaneously given to the signal line WW of the memory cell array 103a to the memory cell array 103c. Therefore, the weight driver circuit 106 gives the same weighting factor to the memory cells of the memory cell array 103a, the memory cell array 103b, and the memory cell array 103c.

A configuration different from the scan driver circuit 105 described above may be used. Although not shown, the scan driver circuit 105 may use a decoder circuit. When a decoder circuit is used for the scan driver circuit 105, it is preferable to give an address signal and an enable signal. When updating the weighting factor of the specified memory cell, it is preferable to use a decoder circuit. Since the weighting factor can be updated as needed, the time required for updating can be reduced.

The weight driver circuit 106 preferably gives a weighting factor to the memory cells in synchronization with the scan driver circuit 105. Therefore, it is preferable to give the same clock signal CK as the scan driver circuit 105 to the latch circuit 106a and the digital-to-analog conversion circuit 106b. Since the source follower circuit 106c can lower the output impedance, the voltage value of the weighting coefficient given to the memory cell array 101 can be written more accurately.

The data driver circuit 107 can hold the input data given to the memory cell array 103a in the latch circuit 107a. By holding the input data in the latch circuit 107a, the digital-to-analog conversion circuit 107b can secure the time for converting the input data into an analog signal. Since the output impedance of the input data converted into the analog signal can be lowered by the source follower circuit 107c, the voltage value of the input data given to the memory cell array 103a can be written more accurately.

The selection circuit 109a included in the feedback circuit 109 selects one of a second signal output by the output circuit 104a, a fourth signal output by the output circuit 104b, and a sixth signal output by the output circuit 104c. , Output as signal sdata. The signal sdata is given to the selection circuit 109b, the analog-to-digital conversion circuit 109d, or the amplifier circuit 109f.

The signal sdata given to the selection circuit 109b can be given to the signal line FFBD via the amplifier circuit 109c to any one of the output circuit 104a, the output circuit 104b, or the output circuit 104c.

Further, the signal sdata given to the analog-to-digital conversion circuit 109d is digitally converted and output as a digital signal to the signal line MDD via the amplifier circuit 109e. Further, the signal sdata given to the amplifier circuit 109f is output as an analog signal to the signal line MAD.

Further, by giving the weight coefficient and the initialization potential to the input data to the memory cell, the output circuit 104a can generate the first correction data. Further, the output circuit 104b can generate the second correction data. Further, the output circuit 104c can generate the third correction data. The initialization voltage is preferably 0 V, but is not necessarily limited to 0 V.

Therefore, the output circuit 104a can correct the second output signal by being given the first correction data from the feedback circuit 109. Further, the output circuit 104b can correct the fourth output signal by being given the second correction data from the feedback circuit 109. Further, the output circuit 104c can correct the sixth output signal by being given the third correction data from the feedback circuit 109.

Further, the feedback circuit 109 can give the input second signal to the signal line FFBD. The second signal can be given to either the output circuit 104b or the output circuit 104c via the signal line FFBD. That is, the second signal can be used as a feedforward signal.

Further, the feedback circuit 109 can give a fourth signal to the signal line FFBD. The fourth signal can be given to either the output circuit 104a or the output circuit 104c via the signal line FFBD. When the fourth signal is given to the output circuit 104a, it can be used as a feedback signal, and when the fourth signal is given to the output circuit 104c, it can be used as a feedforward signal.

Further, the feedback circuit 109 can give the input sixth signal to the signal line FFBD. The sixth signal can be given to either the output circuit 104a or the output circuit 104b via the signal line FFBD. That is, the sixth signal can be used as a feedback signal.

By having the feedback circuit 109, it is possible to add a time-expandable feedback function to the arithmetic processing. For example, as a recurrent neural network (RNN) or a neural network, it can be used in a machine learning algorithm called Long Short-Term Memory (LSTM).

In FIG. 4, a memory cell array 101 will be used to explain the perceptron. The memory cell array 101 may have a multi-layered perceptron, but the input layer 102a will be described as an example. The input layer 102a has a memory cell array 103a, an output circuit 104a, and a current source circuit 30. The memory cell array 103a has a plurality of synaptic circuits 23a, and the output circuit 104a has a plurality of activation function circuits 24a. The current source circuit 30 is preferably arranged in each perceptron. Therefore, the neuron is composed of a synaptic circuit 23a and an activation function circuit 24a.

The memory cell array 103a has a signal line WD [j], a signal line WW [i], a signal line SL [j], a signal line RW [i], a wiring COM, and a plurality of memory cells MC. The memory cell MC has a transistor 41, a transistor 42, and a capacitive element 51. In order to simplify the explanation, in FIG. 3, a memory cell MC [i, j] to a memory cell MC [i + 2, j + 2] will be used as an example.

The memory cell MC is electrically connected to the signal line WD [j], the signal line WW [i], the signal line SL [j], the signal line RW [i], and the wiring COM. The gate of the transistor 41 is electrically connected to the signal line WW. One of the source and drain of the transistor 41 is electrically connected to the signal line WD. The other of the source or drain of the transistor 41 is electrically connected to the gate of the transistor 42 and one of the electrodes of the capacitive element 51. One of the source and drain of the transistor 42 is electrically connected to the signal line SL. The other of the source or drain of the transistor 42 is electrically connected to the wiring COM. The other electrode of the capacitive element 51 is electrically connected to the signal line RW. The node FN1 is formed by connecting the gate of the transistor 42, the other of the source or drain of the transistor 41, and one of the electrodes of the capacitive element 51.

The memory cell MC can store the weighting factor in the node FN1. Since the weighting coefficient is given by an analog signal, it can be expressed as a weighting potential. The signal line RW is given an input signal of an analog signal. Therefore, in the capacitive element 51, an input signal is given to the other of the electrodes of the capacitive element 51. The node FN1 changes to the first potential when an input signal is applied to the weight potential via the capacitive element 51. Therefore, the gate of the transistor 42 is given a first potential. The transistor 42 can flow a current according to the conductance of the transistor 42 by changing the first potential applied to the gate of the transistor 42. That is, the transistor 42 can multiply the input signal by the weighting factor and convert it into the first current. Therefore, the result of multiplication is output as a first current. It is preferable to give the wiring COM the lowest potential used in the synaptic circuit 23a. It is preferable that the current flowing through the transistor 42 flows in the direction of being sucked into the wiring COM.

The synaptic circuit 23a is electrically connected to the current source circuit 30. The current source circuit 30 can generate a current IREF using a plurality of memory cells MREF included in the memory unit 23b. The memory cell MREF preferably has the same configuration as the memory cell MC. The current IREF becomes a reference current when supplying a current to the signal line SL [j]. The current source circuit 30 has a current mirror circuit and can copy the current IREF to the current IR [j]. Therefore, the current IR [j] having the same magnitude as the current IREF can be supplied to the signal line SL [j]. The current source circuit 30 will be described in detail with reference to FIG.

The activation function circuit 24a can add a plurality of first currents and convert the second potential into a third potential by a ramp function. The third potential is given to the signal line RW possessed by the neuron 23 in the next stage. A detailed description of the activation function circuit 24a will be given with reference to FIG.

In FIG. 5, the current source circuit 30 will be described in detail. FIG. 5 shows the circuit configuration of the current source circuit 30 as an example. The current source circuit 30 is composed of a current mirror circuit. The current mirror circuit is composed of a reference current mirror circuit CMREF and a plurality of current mirror circuit CMs. The number of current mirror circuit CMs is preferably the same as that of the neuron 23. The current mirror circuit CMREF and the current mirror circuit CM [j] have a p-channel type transistor 59. The transistor 59 preferably has the same channel length, channel width, and electrical characteristics. The current source circuit 30 is not limited to the current mirror circuit composed of the p-channel type transistor as in the example shown in FIG. 5, as long as the current of the same magnitude can be passed through the signal line BJ [j].

The source of the transistor 59 included in the current mirror circuit CMREF and the current mirror circuit CM [j] is electrically connected to the wiring VDD. The gate of the transistor 59 is electrically connected to the wiring CMV. The drain of the transistor 59 is electrically connected to the signal line SL [j]. In the current mirror circuit CMREF, the gate and drain of the transistor 59 are electrically connected. The current mirror circuit CMREF is electrically connected to the memory cell MREF via the signal line SLREF.

A current IREF equal to the sum of the currents flowing through the transistor 42 of the memory cell MREF flows through the signal line SLREF. Therefore, the drain potential of the transistor 49 of the current mirror circuit CMREF and the gate potential are determined by the current IREF. The potential given to the gate of the transistor 49 of the current mirror circuit CMREF is given to the gate of the transistor 49 of the current mirror circuit CM via the wiring CMV. Therefore, the current IR [j] is given the same magnitude as the current IREF.

In FIG. 6A, the activation function circuit 24a will be described in detail. In a neural network, the activation function circuit is sometimes called a sigmoid function. The activation function circuit 24a includes an adder circuit, a first source follower circuit, a signal line RST, wiring VDD, wiring OBS, and wiring NB1. The adder circuit has a capacitive element 25, a capacitive element 26, a transistor 27, and a first node ND1. The first source follower circuit includes a transistor 46, a transistor 47, and a transistor 48.

First, the adder circuit will be described. One of the electrodes of the capacitive element 25 is electrically connected to the signal line SL [j], and the other of the electrodes of the capacitive element 25 is one of the electrodes of the capacitive element 26 and one of the source or drain of the transistor 27. The gate of the transistor 48 is electrically connected. The other electrode of the capacitive element 26 is electrically connected to the signal line FFBD [j]. The first node ND1 is formed by connecting the other of the electrodes of the capacitive element 25, one of the electrodes of the capacitive element 26, one of the source or drain of the transistor 27, and the gate of the transistor 48.

A second current generated by adding the first current output by the memory cell MC of the synapse circuit 23a flows through the signal line SL [j]. The capacitive element 25 can convert the second current into the second potential. The second potential is applied to the first node ND1 via the capacitive element 25. By changing the potential of the first node ND1, the potential given to the gate of the transistor 48 changes. A feedback signal given to the signal line FFBD [j] may be added to the first node ND1 via the capacitive element 26. The second potential corresponds to the second signal. At the gate of the transistor 27, it is preferable that the first node ND1 can be initialized by the reset signal given to the signal line RST.

Next, the first source follower circuit will be described. The gate of the transistor 46 is electrically connected to the wiring NB1. The gate of the transistor 47 is electrically connected to the wiring OBS. The first node ND1 is electrically connected to the gate of the transistor 48. In the wiring VDD, one of the source or drain of the transistor 47 and one of the source or drain of the transistor 48 are electrically connected. One of the source or drain of the transistor 46 is electrically connected to the other of the source or drain of the transistor 47, the other of the source or drain of the transistor 48, and the output terminal ORY [j]. The other of the source or drain of the transistor 46 is electrically connected to the wiring COM.

The activation function circuit 24a can convert the second potential into the second potential by the ramp function. The gate of the transistor 46 is given a fixed potential by the wiring NB1. Therefore, the transistor 46 can function as a constant current source of the second source follower circuit. The gate of the transistor 47 is given a voltage VBS by the wiring OBS. A second potential is applied to the gate of the transistor 48. It is preferable that the transistor 46, the transistor 47, and the transistor 48 have the same channel length, channel width, and electrical characteristics of the transistor.

The ramp function has a first output range and a second output range. In the first output range, a fixed potential is output to the output terminal ORY [j] by the transistor 47. In the second output range, the second potential is output to the output terminal ORY [j] by the transistor 48. More precisely, in the first output range, a fixed potential lower than the voltage VBS by the threshold voltage of the transistor 47 is output to the output terminal ORY [j]. In the second output range, a potential lower than the second potential by the threshold voltage of the transistor 48 is output to the output terminal ORY [j].

That is, in other words, the ramp function of the activation function circuit 24a can fix the output voltage of the output terminal ORY [j] when the second potential is smaller than the voltage VBS. When the second potential is larger than the voltage VBS, the output terminal ORY [j] can be changed to an output voltage corresponding to the second potential given to the gate of the transistor 48.

The calculation of the analog signal may vary depending on the electrical characteristics of the element or the time constant of the wiring or the like. However, by having the first output range, the influence of variation can be reduced. The second potential converted by the ramp function is given to the signal line RW as an input signal of the neuron in the next stage.

FIG. 6B shows the output characteristics of the activation function circuit 24a. The x-axis represents a second potential given as an input signal to the activation function circuit 24a. For illustration purposes, the second potential is shown in the figure as voltage VSL [j]. The y-axis represents the voltage VRY [j] given to the output terminal ORY [j] as the output signal of the activation function circuit 24a.

FIG. 7 shows an activation function circuit 24b different from that of FIG. The activation function circuit 24b is different from FIG. 6A in that it does not have the wiring OBS and the transistor 47. Since the activation function circuit 24b does not have a ramp function, a second potential is given to the signal line RW as an input signal of the neuron in the next stage. When calculating with more accurate data, it is preferable not to have a ramp function.

FIG. 8 describes the memory cell array 101A, which is different from FIG. In FIG. 8, the points different from the memory cell array 101 will be described, and the description of the components overlapping with the memory cell array 101 will be omitted. In the memory cell array 101A, the configuration of the output circuit 104b is different.

The output circuit 104b has a column output circuit 31 and an offset current circuit 32. The column output circuit 31 has a current-voltage conversion circuit 31a and an offset circuit 31b.

The current-voltage conversion circuit 31a can convert the second current flowing through the signal line SL [j] into the third potential. The third potential is applied to the offset circuit 31b. The offset circuit 31b stores the third potential when the input signal is given, with reference to the time when the input signal is not given to the memory cells MC [i, j] to the memory cells MC [i + 2, j]. Can be done. The offset circuit 31b outputs a fourth potential generated from the third potential to the first output terminal.

In FIG. 9, a detailed description of the column output circuit 31 will be given. The column output circuit 31 includes a current-voltage conversion circuit 31a, an offset circuit 31b, a signal line ER, a wiring OREF, a wiring ORG, a signal line RST, and a wiring NB.

The current-voltage conversion circuit 31a has a current-voltage conversion element R1 and a switch SW. One of the electrodes of the switch is electrically connected to the signal line SL, the other of the electrodes of the switch SW is electrically connected to one of the electrodes of the current-voltage conversion element R1, and the other electrode of the current-voltage conversion element R1 is. , Electrically connected to the wiring OREF. The switch SW is controlled by the signal line ER. The current-voltage conversion element R1 is preferably a resistance element, but is not limited thereto. A diode, a capacitive element, or the like may be used. Further, it is preferable to use a transistor for the switch SW, but the switch SW is not limited. A diode or the like may be used. However, when a diode is used, control by the signal line ER is not required.

By turning off the switch SW, the offset current circuit 32 can be used as a period for canceling the offset current of the signal line SL. Further, by turning on the switch SW, the current-voltage conversion circuit 31a can convert the current applied to the signal line SL into a potential by the current-voltage conversion element R1. Therefore, the switch SW can control the period in which the current flows and reduce the power consumption.

The current-voltage conversion element R1 can convert the second current to the third potential with the potential VREF given to the wiring OREF as a reference potential. However, the potential VREF can be given an optimum potential VREF in consideration of the weight potential given to the node FN1 and the input signal given to the signal line RW.

Although the current-voltage conversion circuit 31a has shown an example of converting a current into a voltage with one resistance element, it may be configured to have a plurality of resistance elements and a switch. By having a plurality of resistance elements and a switch, the current-voltage conversion circuit 31a can switch the detection range according to the magnitude of the current.

For example, the potential VREF given to the wiring OREF is preferably set so that the first potential shows a positive potential even if a positive weighted potential or a negative weighted potential is given to the node FN1. Therefore, it is preferable that the first current flowing through the transistor 42 is sucked into the wiring COM even if either the positive weight potential or the negative weight potential is given to the node FN1. However, the potential VREF may be set so that the first current is sucked into the wiring COM when the weight is positive and is supplied from the wiring COM when the weight is negative. Further, in the current source circuit 30, it is preferable that the IR [j] given to the signal line SL [j] is larger than the second current.

Subsequently, the offset circuit describes 31b. The offset circuit 31b has a reset circuit, a second source follower circuit, a capacitive element 53, and a first output terminal. The reset circuit has a capacitive element 52 and a transistor 43. The second source follower circuit has a transistor 44 and a transistor 45.

In the offset circuit 31b, the wiring OP, the signal line RST, and the wiring NB are electrically connected. One of the electrodes of the capacitive element 52 is electrically connected to the signal line SL [j]. One of the electrodes of the capacitive element 53 is electrically connected to the signal line FFBD. The other electrode of the capacitive element 52 is electrically connected to the other electrode of the capacitive element 53, either the source or the drain of the transistor 43, and the gate of the transistor 44. The other of the source or drain of the transistor 43 is electrically connected to the wiring OPS. One of the source or drain of the transistor 44 is electrically connected to the wiring VDD. The other of the source or drain of the transistor 44 is electrically connected to one of the source or drain of the transistor 45 and the output terminal OPS [j]. The other of the source or drain of the transistor 45 is electrically connected to the wiring COM. The gate of the transistor 45 is electrically connected to the wiring NB1. The node FN2 is formed by connecting the other of the electrodes of the capacitive element 52, one of the source or drain of the transistor 43, and the gate of the transistor 44.

The reset potential VPR of the node FN2 is given to the wiring OP. The reset circuit can turn on the transistor 43 by giving a digital signal "H" to the signal line RST. Therefore, the node FN2 is given the potential VPR. Node FN2 has a first period in which the reset potential VPR is given. In the first period, it is preferable that the signal line SL [j] is in a state where no input data is given to the memory cell MC.

The transistor 43 is turned off, and an input signal is given to the memory cell MC from the signal line RW. One of the electrodes of the capacitive element 52 is given a fourth potential generated by the current-voltage conversion circuit 31a from the second current. The node FN2 changes to a fourth potential due to capacitive coupling by the capacitive element 52. At this time, a feedback signal may be added from the feedback circuit 109 to the fourth potential generated in the node FN2 via the capacitive element 53. The fourth potential given to the node FN2 is given to the gate of the transistor 44 constituting the second source follower circuit. The gate of the transistor 45 is given a fixed potential by the wiring NB1. Therefore, the transistor 45 can function as a constant current source of the second source follower circuit. It is preferable that the transistor 44 and the transistor 45 have the same channel length, channel width, and electrical characteristics.

The output of the second source follower circuit is given to the output terminal OPS [j]. Therefore, the output terminal OPS [j] outputs a potential lower than the fourth potential given to the gate of the transistor 44 by the threshold voltage of the transistor 44.

In FIG. 10, the offset current circuit 32 will be described. The offset current circuit 32 has a current suction circuit 32a, a current supply circuit 32b, a signal line ORM, a signal line OSM, a signal line ORP, a signal line OSP, a wiring COM, and a wiring VDD. The current suction circuit 32a has a transistor 61, a transistor 62, a transistor 63, and a capacitive element 64, and the current supply circuit 32b has a transistor 65, a transistor 66, a transistor 67, and a capacitive element 68.

The explanation will be given focusing on the signal line SL [j]. Although the current suction circuit 32a [j] and the current supply circuit 32b [j] are not shown in FIG. 10, the current source circuit 30, the current-voltage conversion circuit 31a [j], and the offset are via the signal line SL [j]. It is electrically connected to the circuit 31b [j] and the memory cell MC [i, j] to the memory cell MC [i + 2, j].

In the signal line SL [j], one of the source or drain of the transistor 61 and one of the source or drain of the transistor 65 are electrically connected.

One of the source or drain of the transistor 61 is further electrically connected to one of the source and drain of the transistor 62, and the gate of the transistor 61 is one of the electrodes of the capacitive element 64 and the other of the source or drain of the transistor 62. And one of the source or drain of the transistor 63 is electrically connected, and the other of the source or drain of the transistor 63 is the wiring COM, the other of the source or drain of the transistor 61, and the other of the electrodes of the capacitive element 64. Is electrically connected, the gate of the transistor 62 is electrically connected to the wiring OSP, and the gate of the transistor 63 is electrically connected to the wiring ORP.

One of the source or drain of the transistor 65 is further electrically connected to one of the source and drain of the transistor 66, and the gate of the transistor 65 is one of the electrodes of the capacitive element 68 and the other of the source or drain of the transistor 66. And one of the source or drain of the transistor 67 is electrically connected, and the other of the source or drain of the transistor 67 is the wiring VDD, the other of the source or drain of the transistor 65, and the other of the electrodes of the capacitive element 68. Is electrically connected, the gate of the transistor 66 is electrically connected to the wiring OSM, and the gate of the transistor 67 is electrically connected to the wiring ORM.

An initial potential is given to the signal line RW, and different weight coefficients are given to the nodes FN1 of the memory cells MC [i, j] to the memory cells MC [i + 2, j] as weight potentials. Therefore, a current flows through the transistor 42 depending on the magnitude of the weighting potential given to the node FN1. When the signal line RW is the initial potential, the current flowing by the transistor 42 depending on the magnitude of the weight potential can be used as the offset current. However, the offset current indicates the total current of the currents flowing through the transistors 42 of the memory cells MC [i, j] to the memory cells MC [i + 2, j].

The synapse circuit 23a determines the amount of change by multiplying each input signal by a weighting coefficient and adding the multiplication result. Therefore, it is preferable that the offset component generated by setting the weighting coefficient is canceled.

Subsequently, a method of canceling the offset component will be described. First, a reference current is given to the signal line SL [j] from the current mirror circuit of the current source circuit 30. When no weighting coefficient is given and the transistor 42 of the memory cell MC does not allow an offset current to flow, a reference potential is generated in the signal line SL [j] by the current-voltage conversion circuit 31a [j]. However, when a weighting coefficient is given to each memory cell MC, an offset current flows through the transistor 42, and the magnitude of the voltage generated by the current-voltage conversion circuit 31a [j] changes in the signal line SL [j]. ..

Therefore, it is preferable that the synapse circuit 23a cancels the offset current generated by the weighting coefficient after setting the weighting coefficient in the memory cell MC. The weighting factor can be a positive weighting factor or a negative weighting factor. Therefore, in order to maintain the reference current regardless of the weighting factor, the current suction circuit 32a [j] can suck the current for canceling the offset current, or the current supply circuit 32b [j] is offset. It is preferable to be able to supply a current for canceling the current.

First, a method in which the current suction circuit 32a [j] sucks the current in order to cancel the offset current will be described. The transistor 63 is turned on when the digital signal "H" is given to the signal line ORP. Therefore, one of the electrodes of the capacitive element is initialized by the potential of the wiring COM via the transistor 63.

Subsequently, after the transistor 63 is turned off, the transistor 62 is turned on when the signal of the digital signal "H" is given to the signal line OSP. Therefore, the offset current flowing through the signal line SL [j] is applied to the capacitive element 64, and the transistor 61 and the capacitive element 64 form a source follower circuit. When the current flowing through the transistor 61 and the offset current are in equilibrium, the potential of the capacitive element 64 is stabilized. The transistor 61 is preferably an n-channel transistor. Subsequently, the transistor 62 can be turned off, and the capacitive element 64 can hold an offset cancel potential corresponding to the offset current.

Next, a method in which the current supply circuit 32b [j] supplies a current to cancel the offset current will be described. The transistor 67 is turned on when the digital signal "H" is given to the signal line ORM. Therefore, one of the electrodes of the capacitive element is initialized at the potential of the wiring VDD via the transistor 67.

Subsequently, after the transistor 67 is turned off, the transistor 66 is turned on when the signal of the digital signal "H" is given to the signal line OSM. Therefore, the offset current flowing through the signal line SL [j] is given to the capacitive element 68, and the transistor 65 and the capacitive element 68 form a source follower circuit. When the current flowing through the transistor 65 and the offset current are in equilibrium, the potential of the capacitive element 68 is stabilized. The transistor 65 is preferably a p-channel type transistor. Subsequently, the transistor 626 is turned off, and the capacitive element 68 can hold the offset cancel potential according to the offset current.

It is preferable that the current suction circuit 32a [j] and the current supply circuit 32b [j] cancel the offset current at different timings.

Further, during the offset current cancellation operation period, it is preferable that the switch SW of the current-voltage conversion circuit 31a [j] is in the off state. By not passing an offset current through the current-voltage conversion element R1, the influence of the conversion error due to the current-voltage conversion element R1 can be suppressed.

Alternatively, the switch SW of the current-voltage conversion circuit 31a [j] may be in the ON state during the offset current cancellation operation period. By passing the offset current through the current-voltage conversion element R1, the offset correction including the influence of the current-voltage conversion element R1 can be performed.

Further, during the period when the product-sum calculation process is stopped, the power consumed by the current-voltage conversion element R1 can be reduced by turning off the switch SW.

In FIG. 11, an offset current circuit 32 different from that in FIG. 10 will be described. Unlike the current suction circuit 32a [j], the current suction circuit 32c [j] does not have the transistor 63 and the signal line ORP. Therefore, the capacitive element 64 is not initialized at the potential given by the wiring COM. Further, unlike the current supply circuit 32b [j], the current supply circuit 32d [j] does not have the transistor 67 and the signal line ORM. Therefore, the capacitive element 68 is not initialized at the potential given by the wiring VDD.

Therefore, the offset current circuit 32 can reduce the number of signal lines and the number of transistors used, so that the mounting area can be reduced. Further, the processing speed can be improved because the initialization time can be reduced.

In FIG. 12, the activation function circuit 24c different from that in FIG. 6A will be described. The difference from the activation function circuit 24a of FIG. 6A is that the output terminal OPS [j] is electrically connected to the gate of the transistor 48. As for the first source follower, the above-mentioned first source follower can be referred to, and details thereof will be omitted.

In FIG. 13, the operation of the semiconductor device 100 is shown by a timing chart. In the timing chart shown in FIG. 14, the operation using the offset current circuit 32 of FIG. 10 will be described. Further, in order to simplify the explanation, in FIG. 14, the operation of the memory cell MC [i, j] to the memory cell MC [i + 1, j + 1], the memory cell MREF [i], and the memory cell MREF [i + 1] will be described. do.

In the period from time T01 to time T04, it is a step of storing an analog signal in the memory cell MC.

Further, in the period from the time T05 to the time T10, it is a step of setting the offset cancel potential in the offset current circuit 32.

In the period from time T11 to time T12, it is a step of setting a reset potential in the offset circuit 31b of the column output circuit 31.

In the period from time T13 to time T14, it is a step of executing the product-sum operation of each layer of the multi-layer perceptron and the processing of the activation function to acquire the output of the multi-layer neural network.

The period from the time T01 to the time T02 will be described. The potential of the analog signal WST is given to the signal line WDREF. Further, the potential of the analog signal WST-VWX [i, j] is given to the signal line WD [j]. Further, the potential of the analog signal WST-VWX [i, j + 1] is given to the signal line WD [j + 1]. Further, an analog signal VXST is given as a reference potential to the signal line RW [i] and the signal line RW [i + 1]. Therefore, the analog signal VWX [i, j] given to the memory cell MC [i, j] and the analog signal VWX [i, j + 1] given to the memory cell MC [i, j + 1] show different weighting coefficients. ing.

A digital signal "H" is given to the signal line WW [i], and a digital signal "L" is given to the signal line WW [i + 1]. Further, a digital signal "L" is given to the signal line ER, and a digital signal "H" is given to the signal line RST [i].

Therefore, the potential of the analog signal WST is held in the node FNREF [i]. Further, the potential of the analog signal WST-VWX [i, j] is held in the node FN1 [i, j]. Further, the potential of the analog signal WST-VWX [i, j + 1] is held in the node FN1 [i, j + 1].

An offset current corresponding to the potential of the analog signal WST-VWX [i, j] given to the node FN1 [i, j] flows through the transistor 42 of the memory cell MC [i, j]. Further, an offset current flows through the transistor 42 of the memory cell MC [i, j + 1] due to the potential of the analog signal WST-VWX [i, j + 1] given to the node FN1 [i, j + 1].

The period from the time T03 to the time T04 will be described. A digital signal "L" is given to the signal line WW [i]. Further, a digital signal "H" is given to the signal line WW [i + 1]. Further, an analog signal WST-VWX [i + 1, j] is given to the signal line WD [j]. Further, an analog signal WST-VWX [i + 1, j + 1] is given to the signal line WD [j + 1]. Further, an analog signal WST is given to the signal line WDREF. Therefore, the analog signal VWX [i + 1, j] given to the memory cell MC [i + 1, j] and the analog signal VWX [i + 1, j + 1] given to the memory cell MC [i + 1, j + 1] show different weighting coefficients. ing.

Therefore, the potential of the analog signal WST is held in the node FNREF [i + 1]. The potential of the analog signal WST-VWX [i + 1, j] is held in the node FN1 [i + 1, j]. The potential of the analog signal WST-VWX [i + 1, j + 1] is held in the node FN1 [i + 1, j + 1].

Therefore, in the signal line SL [j], the sum of the currents flowing through the respective transistors 42 of the memory cells MC [i, j] and the memory cells MC [i + 1, j] flows as an offset current. Further, in the signal line SL [j + 1], the sum of the currents flowing through the respective transistors 42 of the memory cells MC [i, j + 1] and the memory cells MC [i + 1, j + 1] flows as an offset current.

The period from the time T05 to the time T06 will be described. Here, in order to simplify the explanation, the offset current circuit 32 [j] electrically connected to the signal line SL [j] will be described.

The current suction circuit 32a [j] is initialized at the potential given to the wiring COM when the digital signal “H” is given to the signal line ORP. Further, the current supply circuit 32b [j] is initialized at the potential given to the wiring VDD when the digital signal “H” is given to the signal line ORM.

The period from the time T07 to the time T08 will be described. First, the offset current is canceled by the current supply circuit 32b [j]. In FIG. 13, it is shown as an offset current. An offset current generated by the weighting coefficient flows through the signal line SL [j]. It is preferable that a reference current supplied from the current mirror circuit of the current source circuit 30 flows through the signal line SL [j]. Therefore, the current for canceling the offset current is supplied from the current supply circuit 32b [j].

The period from the time T09 to the time T10 will be described. Subsequently, the offset current is canceled by the current suction circuit 32a [j]. An offset current generated by the weighting coefficient flows through the signal line SL [j]. It is preferable that a reference current supplied from the current mirror circuit included in the current source circuit 30 flows through the signal line SL [j]. Therefore, the current for canceling the offset current is sucked into the current suction circuit 32a [j]. The offset current IOF [j] shown in the timing chart of FIG. 13 indicates the offset current flowing through the current suction circuit 32a [j] and the current supply circuit 32b [j].

The period from the time T11 to the time T12 will be described. The switch SW is turned on when the digital signal "H" is given to the signal line ER. A current in which the offset current generated by the weighting coefficient is canceled is output to the signal line SL [j]. The current-voltage conversion element R1 converts the current flowing through the signal line SL [j] into a reference potential. At this time, the reset potential VPR is given to the node FN2 by the signal RST via the wiring OPS. Therefore, the capacitive element 52 included in the offset circuit 31b can hold a reference potential with reference to the reset potential VPR given to the node FN2 [j].

The period from the time T12 to the time T13 will be described. The node FN2 [j] becomes a floating node by giving a digital signal “L” to the signal line RST. Therefore, the node FN2 [j] can detect the change in the potential of the signal line SL [j].

The period from the time T13 to the time T14 will be described. The explanation will be given focusing on the signal line SL [j]. The memory cell MC [i, j] is given an input data potential via the signal line RW [i]. The node FN1 [i, j] can add an input data potential to the analog signal WST-VWX [i, j] held in the node FN1 [i, j] via the capacitive element 51. Therefore, the gate of the transistor 42 is given a potential obtained by adding the input data potential to the analog signal WST-VWX [i, j]. Therefore, the transistor 42 can multiply the input data potential and the weight potential by using the conductance of the transistor 42, and convert the multiplication result into the first current. Further, in the memory cell MC [i + 1, j], the input data potential is given by the signal line RW [i + 1], and the input data potential and the weight potential can be multiplied.

The first current to be multiplied by the memory cells MC [i, j] and the memory cells MC [i + 1, j] is output to the signal line SL [j], and the second current is the respective first current. Is generated by adding. The second current is converted into a third potential by the current-voltage conversion element R1 and is given to the node FN2 [j] via the capacitive element 52 of the offset circuit 31b. Therefore, the fourth potential detected by the node FN2 [j] is output to the output terminal OPS by the source follower circuit of the offset circuit 31b, which is lower than the fourth potential by the threshold voltage of the transistor 44.

The offset current circuit 32 can prevent the calculated result from being out of the detection range due to the weighted potential by canceling the offset current generated by the weighted potential in the product-sum calculation result. Further, by providing the switch SW, the neuron 23 can suppress the power consumption during the period that does not contribute to the calculation.

<Memory cell configuration example>
FIG. 14 has a transistor different from the memory cell MC described with reference to FIG. 4 or FIG.

In the memory cell MCA shown in FIG. 14A, the transistor 42p is different from the memory cell MC. The transistor 42p is a p-channel type transistor having a polarity different from that of the n-channel type of the transistor 41. As shown in FIG. 14A, the polarities of the transistors that can be used in the memory cell MC can be selected from various configurations.

In the memory cell MCB shown in FIG. 14B, the transistor 41B is different from the memory cell MC. The transistor 41B shown in FIG. 14B has a back gate connected to the wiring BG. The transistor 41B can be configured such that the threshold voltage can be controlled by the potential applied to the wiring BG.

As described above, the configuration and method shown in this embodiment can be used in appropriate combination with the configuration and method shown in other embodiments.

(Embodiment 2)
In the present embodiment, a correction method for reducing the calculation variation of the multiplication circuit of the neuron will be described with reference to FIGS. 15 to 17.

FIG. 15 describes a memory cell array 101A different from the first embodiment. FIG. 15 describes the differences from the memory cell array 101A of FIG. 8, and omits the description of the components overlapping with the memory cell array 101A.

The memory cell MC1 is different in the memory cell array 101B. Further, the memory cell array 103a is different in that it has a signal line G1, a signal line G2, and a signal line G3.

A signal line WD, a signal line WW, a signal line SL, a signal line RW, a signal line G1, a signal line G2, a signal line G3, a wiring V1, and a wiring COM are electrically connected to the memory cell MR1. .. Although not shown in the figure, the signal line WD, the signal line WW, the signal line SL, the signal line RW, the signal line G1, the signal line G2, and the signal line G3 are preferably controlled by the scan driver circuit 105.

In FIG. 16, the memory cell MR1 will be described in detail. The memory cell MR1 has a transistor 11, a transistor 12, a transistor 13, a transistor 14, a transistor 15, a capacitive element 16, a capacitive element 17, a third node FN3, a fourth node FN4, and a fifth node FN5. There is.

The gate of the transistor 11 is electrically connected to the signal line WW, one of the source or drain of the transistor 11 is electrically connected to the signal line WD, and the other of the source or drain of the transistor 11 is the gate of the transistor 12. , One of the source or drain of the transistor 15 and one of the electrodes of the capacitive element 16 are electrically connected, and the other of the electrodes of the capacitive element 16 is electrically connected to the signal line RW. One of the source or drain is electrically connected to the signal line SL, and the other of the source or drain of the transistor 12 is one of the source or drain of the transistor 13, the other of the source or drain of the transistor 15, and the capacitive element 17. One of the electrodes of the transistor 15 is electrically connected, the gate of the transistor 15 is electrically connected to the signal line G1, the other of the source or drain of the transistor 13 is electrically connected to the wiring COM, and the transistor 13 is connected. The gate is electrically connected to the signal line G2, the other of the electrodes of the capacitive element 17 is electrically connected to the back gate of the transistor 12 and one of the source or drain of the transistor 14, and the source or drain of the transistor 14 is connected. The other of the drains is electrically connected to the wiring V1 and the gate of the transistor 14 is electrically connected to the signal line G3.

The third node FN3 is formed by connecting the gate of the transistor 12, the other of the source or drain of the transistor 11, one of the source or drain of 15 transistors, and one of the electrodes of the capacitive element 16. Ru. The fourth node FN4 is connected to the other of the source or drain of the transistor 12, one of the source or drain of the transistor 13, the other of the source or drain of the 15 transistor, and one of the electrodes of the capacitive element 17. Formed by. The fifth node FN5 is formed by connecting the other of the electrodes of the capacitive element 17, the back gate of the transistor 12, and one of the source or drain of the transistor 14.

In FIG. 17, a timing chart shows a correction method for reducing the variation in the transistors of the memory cell MC1 in order to reduce the calculation variation in the memory cell MC1 used in the multiplication circuit. In FIG. 17, any one of the memory cells MC1 included in the memory cell array 101B will be described. All the memory cells MC1 and the memory cell MREF1 included in the memory cell array 101B may be corrected at the same time, or may be corrected at different timings.

At time T11, the transistor 13, the transistor 14, and the transistor 15 are turned on by giving the signal of the digital signal “H” to the signal line G1, the signal line G2, and the signal line G3.

At this time, it is preferable that a large voltage corresponding to the digital signal “H” is applied to the signal line SL. Further, it is preferable that the signal line RW and the signal line WD are given the same initialization voltage as the wiring COM. Further, it is preferable that the wiring V1 is provided with a voltage v1 larger than the threshold voltage of the back gate of the transistor 12. The voltage v1 can be expressed by the equation 1. Vbth indicates the threshold voltage of the back gate of the transistor 12, and α indicates an arbitrary voltage.
v1 = Vbth + α (Equation 1)

When the transistor 13 and the transistor 15 are turned on, the third node FN3 and the fourth node FN4 become the initialization potential given to the wiring COM. At this time, the initialization voltage is preferably 0V, but is not limited and may not be 0V.

When the transistor 14 is turned on, the fifth node FN5 becomes the first potential given to the wiring V1.

At time T12, the signal of the digital signal “L” is given to the signal line G2, so that the transistor 13 is turned off. Therefore, the fourth node FN4 is in a floating state.

The fourth node FN4 converges to a potential lower than the first potential given to the node FN5 by the threshold potential of the back gate of the transistor 12. The potential _{V FN4} of the fourth node FN4 can be expressed by Equation 2.
V _FN4 = v1-vbth (Equation 2)

At time T13, the signal of the digital signal “L” is given to the signal line G3, and then the signal of the digital signal “H” is given to the signal line G2. First, the transistor 14 is turned off, and then the transistor 13 is turned on.

When the transistor 14 is turned off, the fifth node FN5 is in a floating state. Next, when the transistor 13 is turned on, the fourth node FN4 becomes the initialization potential given to the wiring COM. Therefore, the capacitive element 17 stores the threshold voltage of the back gate of the transistor 12 with reference to the fourth node FN4.
V _FN4 = v1- (v1-vbth) = vbth (Equation 3)

At time T13, the transistor 13, the transistor 14, and the transistor 15 are turned off by giving the signal of the digital signal “L” to the signal line G1, the signal line G2, and the signal line G3.

The threshold voltage of the back gate of the transistor 12 is stored in the capacitive element 17 of the memory cell MC1 and the memory cell MREF1. Therefore, it is possible to correct the variation when multiplying by using the memory cell MC1.

As described above, the configuration and method shown in this embodiment can be used in appropriate combination with the configuration and method shown in other embodiments.

(Embodiment 3)
In this embodiment, a configuration example of an ox transistor that can be used in a semiconductor device including the arithmetic circuit MACF described in the above embodiment will be described.

<Semiconductor device configuration example>
The semiconductor device shown in FIG. 18 includes a transistor 300, a transistor 200, and a capacitive element 160. 19A is a cross-sectional view of the transistor 200 in the channel length direction, FIG. 19B is a cross-sectional view of the transistor 200 in the channel width direction, and FIG. 19C is a cross-sectional view of the transistor 300 in the channel width direction. It is a figure.

The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 200 has a small off-current, it is possible to retain the stored contents for a long period of time by using the transistor 200 in a semiconductor device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the semiconductor device can be sufficiently reduced.

In the semiconductor device shown in FIG. 18, the wiring 1001 is connected to one of the source and drain of the transistor 300, and the wiring 1002 is connected to the other of the source and drain of the transistor 300. Further, the wiring 1003 is connected to one of the source and the drain of the transistor 200, the wiring 1004 is connected to the top gate of the transistor 200, and the wiring 1006 is connected to the bottom gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are connected to one of the electrodes of the capacitive element 160, and the wiring 1005 is connected to the other of the electrodes of the capacitive element 160.

Here, when the semiconductor device shown in the present embodiment is used for the memory cell MC included in the memory cell array 103a of the arithmetic circuit MACF shown in the first embodiment, the transistor 42 is connected to the transistor 300 and the transistor 41 is connected to the transistor 200. The element 51 corresponds to the capacitive element 160. Further, the wiring COM corresponds to the wiring 1001, the wiring SL corresponds to the wiring 1002, the wiring WD corresponds to the wiring 1003, the wiring WL [1] corresponds to the wiring 1004, and the wiring RW [1] corresponds to the wiring 1005. When the transistor 41 has a back gate, the wiring 1006 corresponds to the wiring electrically connected to the back gate. In the case of the memory cell MC [2], the memory cell MREF [1], and the memory cell MREF [2] included in the memory cell array 103a, the above description is taken into consideration.

As shown in FIG. 18, the semiconductor device of one aspect of the present invention includes a transistor 300, a transistor 200, and a capacitive element 160. The transistor 200 is provided above the transistor 300, and the capacitive element 160 is provided above the transistor 300 and the transistor 200.

The transistor 300 is provided on the substrate 311 and has a semiconductor region 313 composed of a conductor 316, an insulator 315, and a part of the substrate 311, and a low resistance region 314a and a low resistance region 314b that function as a source region or a drain region. Have.

As shown in FIG. 19C, the transistor 300 is covered with the conductor 316 on the upper surface of the semiconductor region 313 and the side surface in the channel width direction via the insulator 315. As described above, by making the transistor 300 a Fin type, the on characteristic of the transistor 300 can be improved by increasing the effective channel width. Further, since the contribution of the electric field of the gate electrode can be increased, the off characteristic of the transistor 300 can be improved.

The transistor 300 may be either a p-channel type or an n-channel type.

It is preferable to include a semiconductor such as a silicon-based semiconductor in a region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a low resistance region 314a serving as a source region or a drain region, a low resistance region 314b, and the like. It preferably contains crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

In the low resistance region 314a and the low resistance region 314b, in addition to the semiconductor material applied to the semiconductor region 313, elements that impart n-type conductivity such as arsenic and phosphorus, or p-type conductivity such as boron are imparted. Contains elements that

The conductor 316 that functions as a gate electrode is a semiconductor material such as silicon, a metal material, or an alloy containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron. A material or a conductive material such as a metal oxide material can be used.

The Vth of the transistor can be adjusted by determining the work function depending on the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.

The transistor 300 shown in FIG. 18 is an example, and the transistor 300 is not limited to the structure thereof, and an appropriate transistor may be used depending on the circuit configuration and the driving method. For example, similarly to the transistor 200, an oxide semiconductor may be used for the transistor 300.

An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated in this order so as to cover the transistor 300.

As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxide, silicon nitride, silicon nitride, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, etc. are used. Just do it.

The insulator 322 may have a function as a flattening film for flattening a step generated by a transistor 300 or the like provided below the insulator 322. For example, the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.

Further, for the insulator 324, it is preferable to use a film having a barrier property so that hydrogen and impurities do not diffuse in the region where the transistor 200 is provided from the substrate 311 or the transistor 300.

As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by the CVD method can be used. Here, hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 200, which may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 200 and the transistor 300. Specifically, the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.

The amount of hydrogen desorbed can be analyzed using, for example, a heated desorption gas analysis method (TDS). For example, in the TDS analysis, the amount of hydrogen desorbed from the insulator 324 is 10 × 10 in the range of 50 ° C to 500 ° C. It may be ¹⁵ atom / cm ² or less, preferably 5 × 10 ¹⁵ atom / cm ^{2 or less.}

The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative permittivity of the insulator 326 is preferably less than 4, more preferably less than 3. Further, for example, the relative permittivity of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less the relative permittivity of the insulator 324. By using a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.

Further, the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a capacitive element 160, a conductor 328 connected to the transistor 200, a conductor 330, and the like. The conductor 328 and the conductor 330 have a function as a plug or wiring. Further, in the conductor having a function as a plug or wiring, a plurality of structures may be collectively given the same reference numeral. Further, in the present specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

As the material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is single-layered or laminated. Can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.

A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 18, the insulator 350, the insulator 352, and the insulator 354 are laminated in this order. Further, a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 has a function as a plug or wiring for connecting to the transistor 300. The conductor 356 can be provided by using the same material as the conductor 328 and the conductor 330.

For example, as the insulator 350, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, the conductor 356 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 300 and the transistor 200 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

As the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, it is possible to suppress the diffusion of hydrogen from the transistor 300 while maintaining the conductivity as wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen has a structure in contact with the insulator 350 having a barrier property against hydrogen.

A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. 18, the insulator 360, the insulator 362, and the insulator 364 are laminated and provided in this order. Further, a conductor 366 is formed on the insulator 360, the insulator 362, and the insulator 364. The conductor 366 has a function as a plug or wiring. The conductor 366 can be provided by using the same material as the conductor 328 and the conductor 330.

For example, as the insulator 360, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, the conductor 366 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 360 having a barrier property against hydrogen. With this configuration, the transistor 300 and the transistor 200 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in FIG. 18, the insulator 370, the insulator 372, and the insulator 374 are laminated in this order. Further, a conductor 376 is formed on the insulator 370, the insulator 372, and the insulator 374. The conductor 376 has a function as a plug or wiring. The conductor 376 can be provided by using the same material as the conductor 328 and the conductor 330.

For example, as the insulator 370, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, the conductor 376 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 370 having a barrier property against hydrogen. With this configuration, the transistor 300 and the transistor 200 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in FIG. 18, the insulator 380, the insulator 382, and the insulator 384 are laminated in this order. Further, a conductor 386 is formed on the insulator 380, the insulator 382, and the insulator 384. The conductor 386 functions as a plug or wiring. The conductor 386 can be provided by using the same material as the conductor 328 and the conductor 330.

For example, as the insulator 380, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, the conductor 386 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 380 having a barrier property against hydrogen. With this configuration, the transistor 300 and the transistor 200 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

In the above, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 have been described, but the semiconductor device according to the present embodiment has been described. It is not limited to this. The number of wiring layers similar to the wiring layer including the conductor 356 may be 3 or less, or the number of wiring layers similar to the wiring layer including the conductor 356 may be 5 or more.

An insulator 210, an insulator 212, an insulator 214, and an insulator 216 are laminated on the insulator 384 in this order. As any of the insulator 210, the insulator 212, the insulator 214, and the insulator 216, it is preferable to use a substance having a barrier property against oxygen and hydrogen.

For example, for the insulator 210 and the insulator 214, for example, a film having a barrier property that prevents hydrogen and impurities from diffusing from the region where the substrate 311 or the transistor 300 is provided to the region where the transistor 200 is provided is used. Is preferable. Therefore, the same material as the insulator 324 can be used.

As an example of a film having a barrier property against hydrogen, silicon nitride formed by the CVD method can be used. Here, hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 200, which may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 200 and the transistor 300. Specifically, the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.

Further, as the film having a barrier property against hydrogen, for example, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 210 and the insulator 214.

In particular, aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 200 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 200. Therefore, it is suitable for use as a protective film for the transistor 200.

Further, for example, the same material as the insulator 320 can be used for the insulator 212 and the insulator 216. Further, by using a material having a relatively low dielectric constant as an interlayer film in the insulating film, it is possible to reduce the parasitic capacitance generated between the wirings. For example, as the insulator 212 and the insulator 216, a silicon oxide film, a silicon nitride film, or the like can be used.

Further, a conductor 218, a conductor (conductor 203) and the like constituting the transistor 200 are embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. The conductor 218 has a function as a plug or wiring for connecting to the capacitive element 160 or the transistor 300. The conductor 218 can be provided by using the same material as the conductor 328 and the conductor 330.

In particular, the conductor 218 in the region in contact with the insulator 210 and the insulator 214 is preferably a conductor having a barrier property against oxygen, hydrogen, and water. With this configuration, the transistor 300 and the transistor 200 are layers having a barrier property against oxygen, hydrogen, and water, and can be completely separated from each other, and the diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed. ..

A transistor 200 is provided above the insulator 216.

As shown in FIGS. 19A and 19B, the transistor 200 is arranged on the insulator 203 and the insulator 203 arranged so as to be embedded in the insulator 216, and on the insulator 216 and the conductor 203. Insulator 220, insulator 222 arranged on the insulator 220, insulator 224 arranged on the insulator 222, oxide 230a arranged on the insulator 224, and oxide. The oxide 230b arranged on the 230a, the conductors 242a and the conductors 242b arranged apart from each other on the oxide 230b, and the conductors 242a and 242b arranged on the conductors 242a and 242a. Insulator 280 in which an opening is formed by superimposing between the conductors 242b, a conductor 260 arranged in the opening, an oxide 230b, a conductor 242a, a conductor 242b, and an insulator 280, and conductivity. An insulator 250 arranged between the body 260, an oxide 230b, a conductor 242a, a conductor 242b, and an insulator 280, and an oxide 230c arranged between the insulator 250 and the insulator 250. Have. Further, as shown in FIGS. 19A and 19B, it is preferable that the insulator 244 is arranged between the oxide 230a, the oxide 230b, the conductor 242a, and the conductor 242b, and the insulator 280. .. Further, as shown in FIGS. 19A and 19B, the conductor 260 is a conductor 260a provided inside the insulator 250 and a conductor provided so as to be embedded inside the conductor 260a. It is preferable to have 260b. Further, as shown in FIGS. 19A and 19B, it is preferable that the insulator 274 is arranged on the insulator 280, the conductor 260, and the insulator 250.

In the following, the oxide 230a, the oxide 230b, and the oxide 230c may be collectively referred to as the oxide 230. Further, the conductor 242a and the conductor 242b may be collectively referred to as a conductor 242.

The transistor 200 shows a configuration in which three layers of oxide 230a, oxide 230b, and oxide 230c are laminated in a region where a channel is formed and in the vicinity thereof, but the present invention is limited to this. It's not a thing. For example, a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a laminated structure of four or more layers may be provided. Further, in the transistor 200, the conductor 260 is shown as a two-layer laminated structure, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a laminated structure of three or more layers. Further, the transistor 200 shown in FIGS. 18 and 19 (A) and 19 (B) is an example, and the transistor 200 is not limited to the structure thereof, and an appropriate transistor may be used depending on the circuit configuration and the driving method.

Here, the conductor 260 functions as a gate electrode of the transistor, and the conductor 242a and the conductor 242b function as a source electrode or a drain electrode, respectively. As described above, the conductor 260 is formed so as to be embedded in the opening of the insulator 280 and the region sandwiched between the conductor 242a and the conductor 242b. The arrangement of the conductor 260, the conductor 242a and the conductor 242b is self-aligned with respect to the opening of the insulator 280. That is, in the transistor 200, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 260 can be formed without providing the alignment margin, the occupied area of the transistor 200 can be reduced. As a result, the semiconductor device can be miniaturized and highly integrated.

Further, since the conductor 260 is self-aligned in the region between the conductor 242a and the conductor 242b, the conductor 260 does not have a region that overlaps with the conductor 242a or the conductor 242b. This makes it possible to reduce the parasitic capacitance formed between the conductor 260 and the conductors 242a and 242b. Therefore, the switching speed of the transistor 200 can be improved and a high frequency characteristic can be provided.

The conductor 260 may function as a first gate (also referred to as a top gate) electrode. Further, the conductor 203 may function as a second gate (also referred to as a bottom gate) electrode. In that case, the Vth of the transistor 200 can be controlled by changing the potential applied to the conductor 203 independently of the potential applied to the conductor 260 without interlocking with the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 203, it is possible to make the Vth of the transistor 200 larger than 0V and reduce the off-current. Therefore, when a negative potential is applied to the conductor 203, the drain current when the potential applied to the conductor 260 is 0 V can be made smaller than when it is not applied.

The conductor 203 is arranged so as to overlap the oxide 230 and the conductor 260. As a result, when a potential is applied to the conductor 260 and the conductor 203, the electric field generated from the conductor 260 and the electric field generated from the conductor 203 are connected to cover the channel forming region formed in the oxide 230. Can be done. In the present specification, the structure of the transistor that electrically surrounds the channel forming region by the electric fields of the first gate electrode and the second gate electrode is referred to as a curved channel (S-channel) structure.

Further, the conductor 203 has the same structure as the conductor 218, and the conductor 203a is formed in contact with the inner wall of the openings of the insulator 214 and the insulator 216, and the conductor 203b is further formed inside.

The insulator 220, the insulator 222, the insulator 224, and the insulator 250 have a function as a gate insulator.

Here, as the insulator 224 in contact with the oxide 230, it is preferable to use an insulator containing more oxygen than oxygen satisfying the stoichiometric composition. That is, it is preferable that the insulator 224 has an excess oxygen region. By providing such an insulator containing excess oxygen in contact with the oxide 230, oxygen deficiency in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

As the insulator having an excess oxygen region, specifically, it is preferable to use an oxide material in which a part of oxygen is desorbed by heating. Oxides that desorb oxygen by heating are those whose oxygen desorption amount in terms of oxygen atoms is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 1 in TDS (Thermal Desorption Spectroscopy) analysis. An oxide film of 0.0 × 10 ¹⁹ atoms / cm ³ or more, more preferably 2.0 × 10 ¹⁹ atoms / cm ³ , or 3.0 × 10 ²⁰ atoms / cm ^{3 or more.} The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.

Further, when the insulator 224 has an excess oxygen region, the insulator 222 has a function of suppressing the diffusion of at least one oxygen (for example, an oxygen atom, an oxygen molecule, etc.) (the oxygen is difficult to permeate). Is preferable.

Since the insulator 222 has a function of suppressing the diffusion of oxygen and impurities, the oxygen contained in the oxide 230 does not diffuse to the insulator 220 side, which is preferable. Further, it is possible to suppress the conductor 203 from reacting with the oxygen contained in the insulator 224 and the oxide 230.

The insulator 222 is a so-called high such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, Sr) TiO _{3 (BST).} It is preferable to use an insulator containing a −k material in a single layer or in a laminated manner. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for an insulator that functions as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials having a function of suppressing diffusion of impurities and oxygen (the oxygen is difficult to permeate). As the insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like. When the insulator 222 is formed by using such a material, the insulator 222 suppresses the release of oxygen from the oxide 230 and the mixing of impurities such as hydrogen from the peripheral portion of the transistor 200 into the oxide 230. Functions as a layer.

Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon nitride nitride, or silicon nitride may be laminated on the above insulator.

Further, the insulator 220 is preferably thermally stable. For example, since silicon oxide and silicon oxide nitride are thermally stable, a laminated structure that is thermally stable and has a high relative permittivity can be obtained by combining an insulator made of a high-k material and an insulator 220. Can be done.

The insulator 220, the insulator 222, and the insulator 224 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.

For the transistor 200, it is preferable to use a metal oxide that functions as an oxide semiconductor for the oxide 230 including the channel forming region. For example, as the oxide 230, an In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodym). , Hafnium, tantalum, tungsten, or one or more selected from gallium, etc.) and the like. Further, as the oxide 230, an In-Ga oxide or an In-Zn oxide may be used.

As the metal oxide that functions as the channel forming region in the oxide 230, it is preferable to use an oxide having a bandgap of 2 eV or more, preferably 2.5 eV or more. As described above, by using a metal oxide having a large bandgap, the off-current of the transistor can be reduced.

By having the oxide 230a under the oxide 230b, the oxide 230 can suppress the diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b. Further, by having the oxide 230c on the oxide 230b, it is possible to suppress the diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b.

The oxide 230 preferably has a laminated structure due to oxides having different atomic number ratios of each metal atom. Specifically, in the metal oxide used for the oxide 230a, the atomic number ratio of the element M in the constituent elements is larger than the atomic number ratio of the element M in the constituent elements in the metal oxide used in the oxide 230b. Is preferable. Further, in the metal oxide used for the oxide 230a, the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 230b. Further, in the metal oxide used for the oxide 230b, the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 230a. Further, as the oxide 230c, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.

Further, it is preferable that the energy at the lower end of the conduction band of the oxide 230a and the oxide 230c is higher than the energy at the lower end of the conduction band of the oxide 230b. In other words, it is preferable that the electron affinity of the oxide 230a and the oxide 230c is smaller than the electron affinity of the oxide 230b.

Here, at the junction of the oxide 230a, the oxide 230b, and the oxide 230c, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that the energy level at the lower end of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c is continuously changed or continuously bonded. In order to do so, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c.

Specifically, the oxide 230a and the oxide 230b, and the oxide 230b and the oxide 230c have a common element (main component) other than oxygen, thereby forming a mixed layer having a low defect level density. can do. For example, when the oxide 230b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide or the like may be used as the oxide 230a and 230c.

At this time, the main path of the carrier is the oxide 230b. By configuring the oxide 230a and the oxide 230c as described above, the defect level density at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c can be lowered. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and the transistor 200 can obtain a high on-current.

A conductor 242 (conductor 242a and conductor 242b) that functions as a source electrode and a drain electrode is provided on the oxide 230b. The conductors 242 include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, berylium, indium, ruthenium, iridium, and strontium. It is preferable to use a metal element selected from lantern, an alloy containing the above-mentioned metal element as a component, an alloy in which the above-mentioned metal element is combined, or the like. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferable. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material that maintains conductivity even if it absorbs oxygen.

Further, as shown in FIG. 19A, a region 243 (region 243a and region 243b) may be formed as a low resistance region at the interface of the oxide 230 with the conductor 242 and its vicinity thereof. be. At this time, the region 243a functions as one of the source region or the drain region, and the region 243b functions as the other of the source region or the drain region. Further, a channel forming region is formed in a region sandwiched between the region 243a and the region 243b.

By providing the conductor 242 so as to be in contact with the oxide 230, the oxygen concentration in the region 243 may be reduced. Further, a metal compound layer containing the metal contained in the conductor 242 and the component of the oxide 230 may be formed in the region 243. In such a case, the carrier density of the region 243 increases, and the region 243 becomes a low resistance region.

The insulator 244 is provided so as to cover the conductor 242 and suppresses the oxidation of the conductor 242. At this time, the insulator 244 may be provided so as to cover the side surface of the oxide 230 and be in contact with the insulator 224.

As the insulator 244, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like can be used. can.

In particular, as the insulator 244, it is preferable to use aluminum or an oxide containing one or both oxides of hafnium, such as aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the thermal history in a later step. If the conductor 242 is a material having oxidation resistance, or if the conductivity does not significantly decrease even if oxygen is absorbed, the insulator 244 is not an essential configuration. It may be appropriately designed according to the desired transistor characteristics.

The insulator 250 functions as a gate insulator. It is preferable that the insulator 250 is arranged in contact with the inside (upper surface and side surface) of the oxide 230c. The insulator 250 is preferably formed by using an insulator that releases oxygen by heating. For example, in a heated desorption gas spectroscopic analysis (TDS analysis), the amount of oxygen desorbed in terms of oxygen molecules is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 1.0 × 10 ^19. It is an oxide film having atoms / cm ³ or more, more preferably 2.0 × 10 ¹⁹ atoms / cm ³ , or 3.0 × 10 ²⁰ atoms / cm ^3. The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower.

Specifically, it has silicon oxide having excess oxygen, silicon oxide, silicon nitride, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and vacancies. Silicon oxide can be used. In particular, silicon oxide and silicon nitride nitride are preferable because they are stable against heat.

By providing an insulator that releases oxygen by heating in contact with the upper surface of the oxide 230c as the insulator 250, oxygen is effectively applied to the channel forming region of the oxide 230b from the insulator 250 through the oxide 230c. Can be supplied. Further, as with the insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 250 is reduced. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

Further, in order to efficiently supply the excess oxygen contained in the insulator 250 to the oxide 230, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. By providing the metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from the insulator 250 to the conductor 260 is suppressed. That is, it is possible to suppress a decrease in the amount of excess oxygen supplied to the oxide 230. In addition, it is possible to suppress the oxidation of the conductor 260 due to excess oxygen. As the metal oxide, a material that can be used for the insulator 244 may be used.

The conductor 260 that functions as the first gate electrode is shown as a two-layer structure in FIGS. 19A and 19B, but may have a single-layer structure or a laminated structure of three or more layers. ..

Conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule _(N 2 O, NO, etc. NO _2), conductive having a function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of at least one oxygen (for example, oxygen atom, oxygen molecule, etc.). Since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 260b from being oxidized by the oxygen contained in the insulator 250 and the conductivity from being lowered. As the conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.

Further, as the conductor 260b, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, since the conductor 260b also functions as wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Further, the conductor 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the conductive material.

The insulator 280 is provided on the conductor 242 via the insulator 244. The insulator 280 preferably has an excess oxygen region. For example, as the insulator 280, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having holes. , Or a resin or the like is preferable. In particular, silicon oxide and silicon nitride nitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having pores are preferable because an excess oxygen region can be easily formed in a later step.

The insulator 280 preferably has an excess oxygen region. By providing the insulator 280, which releases oxygen by heating, in contact with the oxide 230c, the oxygen in the insulator 280 can be efficiently supplied to the region 234 of the oxide 230 through the oxide 230c. .. It is preferable that the concentration of impurities such as water or hydrogen in the insulator 280 is reduced.

The opening of the insulator 280 is formed so as to overlap the region between the conductor 242a and the conductor 242b. As a result, the conductor 260 is formed so as to be embedded in the opening of the insulator 280 and the region sandwiched between the conductor 242a and the conductor 242b.

In miniaturizing a semiconductor device, it is required to shorten the gate length, but it is necessary to prevent the conductivity of the conductor 260 from decreasing. Therefore, if the film thickness of the conductor 260 is increased, the conductor 260 may have a shape having a high aspect ratio. In the present embodiment, since the conductor 260 is provided so as to be embedded in the opening of the insulator 280, even if the conductor 260 has a shape having a high aspect ratio, the conductor 260 is formed without collapsing during the process. Can be done.

The insulator 274 is preferably provided in contact with the upper surface of the insulator 280, the upper surface of the conductor 260, and the upper surface of the insulator 250. By forming the insulator 274 into a film by a sputtering method, an excess oxygen region can be provided in the insulator 250 and the insulator 280. Thereby, oxygen can be supplied into the oxide 230 from the excess oxygen region.

For example, as the insulator 274, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like is used. Can be done.

In particular, aluminum oxide has a high barrier property, and even a thin film of 0.5 nm or more and 3.0 nm or less can suppress the diffusion of hydrogen and nitrogen. Therefore, the aluminum oxide formed by the sputtering method can have a function as a barrier film for impurities such as hydrogen as well as an oxygen supply source.

Further, it is preferable to provide an insulator 281 that functions as an interlayer film on the insulator 274. Like the insulator 224, the insulator 281 preferably has a reduced concentration of impurities such as water or hydrogen in the membrane.

Further, the conductor 240a and the conductor 240b are arranged in the openings formed in the insulator 281, the insulator 274, the insulator 280, and the insulator 244. The conductor 240a and the conductor 240b are provided so as to face each other with the conductor 260 interposed therebetween. The conductor 240a and the conductor 240b have the same configuration as the conductor 246 and the conductor 248 described later.

An insulator 282 is provided on the insulator 281. As the insulator 282, it is preferable to use a substance having a barrier property against oxygen and hydrogen. Therefore, the same material as the insulator 214 can be used for the insulator 282. For example, it is preferable to use a metal oxide such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 282.

In particular, aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 200 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 200. Therefore, it is suitable for use as a protective film for the transistor 200.

Further, an insulator 286 is provided on the insulator 282. As the insulator 286, the same material as the insulator 320 can be used. Further, by using a material having a relatively low dielectric constant as an interlayer film in the insulating film, it is possible to reduce the parasitic capacitance generated between the wirings. For example, as the insulator 286, a silicon oxide film, a silicon nitride film, or the like can be used.

Further, the insulator 220, the insulator 222, the insulator 224, the insulator 244, the insulator 280, the insulator 274, the insulator 281, the insulator 282, and the insulator 286 include the conductor 246 and the conductor 248. Is embedded.

The conductor 246 and the conductor 248 function as a plug or wiring for connecting to the capacitive element 160, the transistor 200, or the transistor 300. The conductor 246 and the conductor 248 can be provided by using the same materials as the conductor 328 and the conductor 330.

Subsequently, a capacitive element 160 is provided above the transistor 200. The capacitive element 160 has a conductor 161 and a conductor 162 and an insulator 163.

Further, the conductor 112 may be provided on the conductor 246 and the conductor 248. The conductor 112 has a function as a plug or wiring for connecting to the transistor 200. The conductor 161 has a function as an electrode of the capacitive element 160. The conductor 112 and the conductor 161 can be formed at the same time.

The conductor 112 and the conductor 161 include a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned elements as components. (Tantalum nitride, titanium nitride film, molybdenum nitride film, tungsten nitride film) and the like can be used. Alternatively, add indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide. It is also possible to apply a conductive material such as indium tin oxide.

In FIG. 18, the conductor 112 and the conductor 161 show a single-layer structure, but the structure is not limited to this, and a laminated structure of two or more layers may be used. For example, a conductor having a barrier property and a conductor having a high adhesion to the conductor having a high conductivity may be formed between the conductor having a barrier property and the conductor having a high conductivity.

The conductor 162 is provided so as to be superimposed on the conductor 161 via the insulator 163. As the conductor 162, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. When it is formed at the same time as other structures such as a conductor, Cu (copper), Al (aluminum), or the like, which are low resistance metal materials, may be used.

An insulator 150 is provided on the conductor 162 and the insulator 163. The insulator 150 can be provided by using the same material as the insulator 320. Further, the insulator 150 may function as a flattening film that covers the uneven shape below the insulator 150.

By using this structure, it is possible to suppress fluctuations in electrical characteristics and improve reliability in a semiconductor device using a transistor having an oxide semiconductor. Alternatively, it is possible to provide a transistor having an oxide semiconductor having a large on-current. Alternatively, it is possible to provide a transistor having an oxide semiconductor having a small off-current. Alternatively, it is possible to provide a semiconductor device with reduced power consumption. Alternatively, in a semiconductor device using a transistor having an oxide semiconductor, miniaturization or high integration can be achieved.

<Transistor configuration example>
In FIGS. 18 and 19, a configuration example in which the conductor 260 functioning as a gate is formed inside the opening of the insulator 280 has been described, but the configuration of the ox transistor is not limited to this. For example, a configuration in which the insulator is provided above the conductor can also be used. Examples of the configuration of such a transistor are shown in FIGS. 20 and 21.

20 (A) is a top view of the transistor, and FIG. 20 (B) is a perspective view of the transistor. Further, a cross-sectional view of X1-X2 in FIG. 20 (A) is shown in FIG. 21 (A), and a cross-sectional view of Y1-Y2 is shown in FIG. 21 (B).

The transistors shown in FIGS. 20 and 21 include a conductor BGE having a function as a back gate, an insulator BGI having a function as a gate insulating film, an oxide semiconductor S, and an insulator having a function as a gate insulating film. It has a body FGI, a conductor FGE having a function as a front gate, and a conductor WE having a function as a wiring. Further, the conductor PE has a function as a plug for connecting the conductor WE and the oxide semiconductor S, the conductor BGE, or the conductor FGE. Here, an example is shown in which the oxide semiconductor S is composed of three layers of oxides S1, S2, and S3.

It should be noted that this embodiment can be appropriately combined with other embodiments shown in the present specification.

(Embodiment 4)
In this embodiment, the configuration of the metal oxide that can be used in the ox transistor described in the above embodiment will be described.

<Composition of metal oxide>
In the specification and the like, it may be described as CAAC (c-axis aligned composite) and CAC (Cloud-Aligned Composite). In addition, CAAC represents an example of a crystal structure, and CAC represents an example of a function or a composition of a material.

The CAC-OS or CAC-metal oxide has a conductive function in a part of the material, an insulating function in a part of the material, and a semiconductor function as a whole of the material. When CAC-OS or CAC-metal oxide is used for the active layer of the transistor, the conductive function is the function of allowing electrons (or holes) to be carriers to flow, and the insulating function is the function of allowing electrons (or holes) to be carriers. It is a function that does not shed. By making the conductive function and the insulating function act in a complementary manner, a switching function (on / off function) can be imparted to the CAC-OS or the CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

Further, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. Further, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. Further, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

Further, in CAC-OS or CAC-metal oxide, when the conductive region and the insulating region are dispersed in the material in a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively. There is.

Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region. In the case of this configuration, when the carrier is flown, the carrier mainly flows in the component having a narrow gap. Further, the component having a narrow gap acts complementarily to the component having a wide gap, and the carrier flows to the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in the channel region of the transistor, a high current driving force, that is, a large on-current and a high field effect mobility can be obtained in the ON state of the transistor.

That is, the CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

<Structure of metal oxide>
Oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystal oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), and pseudoamorphous oxide semiconductor (a-lik). OS: amorphous-like oxide semiconductor), amorphous oxide semiconductors, and the like.

CAAC-OS has a c-axis orientation and has a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have strain. The strain refers to a region where the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another lattice arrangement is aligned in the region where a plurality of nanocrystals are connected.

Although nanocrystals are basically hexagonal, they are not limited to regular hexagonal shapes and may have non-regular hexagonal shapes. Further, in the strain, it may have a lattice arrangement such as a pentagon and a heptagon. In CAAC-OS, a clear grain boundary (also referred to as grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and that the bond distance between atoms changes due to the substitution of metal elements. It is thought that this is the reason.

Further, CAAC-OS is a layered crystal in which a layer having indium and oxygen (hereinafter, In layer) and a layer having elements M, zinc, and oxygen (hereinafter, (M, Zn) layer) are laminated. It tends to have a structure (also called a layered structure). Indium and the element M can be replaced with each other, and when the element M of the (M, Zn) layer is replaced with indium, it can be expressed as a (In, M, Zn) layer. Further, when the indium of the In layer is replaced with the element M, it can also be expressed as a (In, M) layer.

CAAC-OS is a highly crystalline oxide semiconductor. On the other hand, in CAAC-OS, since a clear crystal grain boundary cannot be confirmed, it can be said that the decrease in electron mobility due to the crystal grain boundary is unlikely to occur. Further, since the crystallinity of the oxide semiconductor may be deteriorated due to the mixing of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability. CAAC-OS is also stable against high temperatures (so-called thermal budgets) in the manufacturing process. Therefore, if CAAC-OS is used for the ox transistor, the degree of freedom in the manufacturing process can be expanded.

The nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method.

The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

Oxide semiconductors have various structures, and each has different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

<Transistor with oxide semiconductor>
Subsequently, a case where the oxide semiconductor is used for a transistor will be described.

By using the oxide semiconductor as a transistor, a transistor having high field effect mobility can be realized. In addition, a highly reliable transistor can be realized.

Further, it is preferable to use an oxide semiconductor having a low carrier density for the transistor. When the carrier density of the oxide semiconductor film is lowered, the impurity concentration in the oxide semiconductor film may be lowered and the defect level density may be lowered. In the present specification and the like, a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, oxide semiconductors have a carrier density of ^{less than 8 × 10 11} / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ^-9 /. It ^{may be cm 3} or more.

Further, since the oxide semiconductor film having high purity intrinsicity or substantially high purity intrinsicity has a low defect level density, the trap level density may also be low.

In addition, the charge captured at the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Further, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.

<Impurities>
Here, the influence of each impurity in the oxide semiconductor will be described.

When silicon or carbon, which is one of the Group 14 elements, is contained in the oxide semiconductor, a defect level is formed in the oxide semiconductor. Therefore, the concentration of silicon and carbon in the oxide semiconductor and the concentration of silicon and carbon near the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

Further, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

Further, in an oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier density is increased, and the n-type is easily formed. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Therefore, in the oxide semiconductor, it is preferable that nitrogen is reduced as much as possible, for example, the nitrogen concentration in the oxide semiconductor is ^{less than 5 × 10 19} atoms / cm ^{3 in} SIMS, preferably 5 × 10 ¹⁸ Atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, still more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

Further, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency. When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated. In addition, a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in an oxide semiconductor, the hydrogen concentration obtained by SIMS ^{is less than 1 × 10 20} atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , and more preferably 5 × 10 ¹⁸ atoms / cm. ^{Less than 3} , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

By using an oxide semiconductor in which impurities are sufficiently reduced in the channel region of the transistor, stable electrical characteristics can be imparted.

This embodiment can be appropriately combined with the description of other embodiments.

(Embodiment 5)
This embodiment shows an example of an electronic component and an electronic device in which the semiconductor device shown in the above embodiment is incorporated.

<Electronic components>
First, an example of an electronic component in which the semiconductor device 100 is incorporated will be described with reference to FIGS. 22A and 22B.

The electronic component 7000 shown in FIG. 22 (A) is an IC chip and has a lead and a circuit unit. The electronic component 7000 is mounted on, for example, the printed circuit board 7002. A board (mounting board 7004) on which electronic components are mounted is completed by combining a plurality of such IC chips and electrically connecting each of them on the printed circuit board 7002.

The semiconductor device 100 can be used in the circuit portion of the electronic component 7000.

In FIG. 22A, QFP (Quad Flat Package) is applied to the package of the electronic component 7000, but the package mode is not limited to this. For example, it may be QFN (Quad Flat Non-read package), BGA (Ball Grid Array), or LGA (Land Grid Array). Further, it may be TCP (Tape Carrier Package).

FIG. 22B is a schematic diagram of the electronic component 7400. The electronic component 7400 is a camera module and contains an image sensor chip 7451. The electronic component 7400 has a package substrate 7411 for fixing the image sensor chip 7451, a lens cover 7421, a lens 7435, and the like. Further, an IC chip 7490 having functions such as a drive circuit for an image pickup device and a signal conversion circuit is also provided between the package substrate 7411 and the image sensor chip 7451, and has a configuration as a SiP (System in package). There is. The land 7441 is electrically connected to the electrode pad 7461, and the electrode pad 7461 is electrically connected to the image sensor chip 7451 or the IC chip 7490 by a wire 7471. In FIG. 22B, a part of the lens cover 7421 and the lens 7435 is omitted in order to show the inside of the electronic component 7400.

The circuit portion of the image sensor chip 7451 is a stack of semiconductor devices 100 (integrated circuit 120, integrated circuit 130, integrated circuit 140) and layer 7033.

Layer 7033 has a light receiving element. As the light receiving element, for example, a pn junction type photodiode having a selenium-based material as a photoelectric conversion layer can be used. A photoelectric conversion element using a selenium-based material has high external quantum efficiency with respect to visible light and can realize a highly sensitive optical sensor.

The selenium-based material can be used as a p-type semiconductor. Examples of the selenium-based material include crystalline selenium such as single crystal selenium and polycrystalline selenium, amorphous selenium, copper, indium, and selenium compounds (CIS), or copper, indium, gallium, and selenium compounds (CIGS). Can be used.

The n-type semiconductor of the pn junction type photodiode is preferably formed of a material having a wide bandgap and translucency with respect to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or an oxide in which they are mixed can be used.

Further, as the light receiving element of the layer 7033, a pn junction type photodiode using a p-type silicon semiconductor and an n-type silicon semiconductor may be used. Further, it may be a pin junction type photodiode in which an i-type silicon semiconductor layer is provided between a p-type silicon semiconductor and an n-type silicon semiconductor.

The photodiode using the above silicon can be formed by using the single crystal silicon. At this time, it is preferable that the layer 7032 and the layer 7033 are electrically bonded by using a bonding step. Further, the photodiode using the above silicon can also be formed by using a thin film such as amorphous silicon, microcrystalline silicon, and polycrystalline silicon.

Further, instead of the layer 7033, the semiconductor device 100 and the MEMS sensor or the like may be combined. In addition to the semiconductor device 100 and the layer 7033, a MEMS sensor or the like may be combined. Also, for example, force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, Sensors may be combined that include the ability to measure humidity, slope, vibration, odor, or infrared light.

<Electronic equipment>
Next, an example of an electronic device provided with the above electronic components will be described with reference to FIGS. 23 to 24.

The robot 2100 shown in FIG. 23A includes a computing device 2110, an illuminance sensor 2101, a microphone 2102, an upper camera 2103, a speaker 2104, a display 2105, a lower camera 2106, an obstacle sensor 2107, and a moving mechanism 2108.

In the robot 2100, the above electronic components can be used for the arithmetic unit 2110, the illuminance sensor 2101, the upper camera 2103, the display 2105, the lower camera 2106, the obstacle sensor 2107, and the like.

The microphone 2102 has a function of detecting a user's voice, environmental sound, and the like. Further, the speaker 2104 has a function of emitting sound. The robot 2100 can communicate with the user by using the microphone 2102 and the speaker 2104.

The display 2105 has a function of displaying various information. The robot 2100 can display the information desired by the user on the display 2105. The display 2105 may be equipped with a touch panel.

The upper camera 2103 and the lower camera 2106 have a function of photographing the surroundings of the robot 2100. Further, the obstacle sensor 2107 can detect the presence or absence of an obstacle in the traveling direction when the robot 2100 moves forward by using the moving mechanism 2108. The robot 2100 can recognize the surrounding environment and move safely by using the upper camera 2103, the lower camera 2106, and the obstacle sensor 2107.

The flying object 2120 shown in FIG. 23B has an arithmetic unit 2121, a propeller 2123, and a camera 2122, and has a function of independently flying.

In the flying object 2120, the above electronic components can be used for the arithmetic unit 2121 and the camera 2122.

FIG. 23C is an external view showing an example of an automobile. The automobile 2980 has a camera 2981 and the like. Further, the automobile 2980 is equipped with various sensors such as an infrared radar, a millimeter wave radar, and a laser radar. The automobile 2980 can analyze the image taken by the camera 2891, determine the surrounding traffic conditions such as the presence or absence of pedestrians, and perform automatic driving.

In the automobile 2980, the above electronic components can be used for the camera 2891.

The information terminal 2910 shown in FIG. 23D has a display unit 2912, a microphone 2917, a speaker unit 2914, a camera 2913, an external connection unit 2916, an operation switch 2915, and the like in the housing 2911. The display unit 2912 includes a display panel and a touch screen using a flexible substrate. Further, the information terminal 2910 includes an antenna, a battery, and the like inside the housing 2911. The information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet-type information terminal, a tablet-type personal computer, an electronic book terminal, or the like. The information terminal 2910 can use the above electronic components for the internal storage device and the camera 2913.

FIG. 23 (E) shows an example of a wristwatch-type information terminal. The information terminal 2960 includes a housing 2961, a display unit 2962, a band 2963, a buckle 2964, an operation switch 2965, an input / output terminal 2966, and the like. Further, an antenna, a battery, and the like are provided inside the information terminal 2960 and the housing 2961. The information terminal 2960 can execute various applications such as mobile phone, e-mail, text viewing and creation, music playback, Internet communication, and computer games. The information terminal 2960 can use the above electronic components for the storage device inside the information terminal 2960.

FIG. 23 (F) shows an example of a USB type peripheral device. The peripheral device 2920 is a stick-type peripheral device, and includes a housing 2921, a connector 2922, a semiconductor device 2923, and the like. The semiconductor device 2923 is provided in the housing 2921. The above electronic components can be used in the semiconductor device 2923.

The peripheral device 2920 can be connected to a host device having a USB port via the connector 2922 to enhance the function of the host device. For example, when the semiconductor device 2923 functions as a storage device, the storage capacity of the host device can be increased. Further, when the semiconductor device 2923 functions as a GPU, the image processing capability and parallel computing capability of the host device can be enhanced. The peripheral device 2920 has excellent portability and is easy to carry.

The communication standard for connecting the host device and the peripheral device 2920 is not limited to the USB standard. Communication standards such as IEEE 1394 or HDMI® may be used.

FIG. 24 is a schematic diagram showing an example of a cleaning robot.

The cleaning robot 5100 has a display 5101 arranged on the upper surface, a plurality of cameras 5102 arranged on the side surface, a brush 5103, and an operation button 5104. Although not shown, the lower surface of the cleaning robot 5100 is provided with tires, suction ports, and the like. The cleaning robot 5100 also includes various sensors such as an infrared sensor, an ultrasonic sensor, an acceleration sensor, a piezo sensor, an optical sensor, and a gyro sensor. Further, the cleaning robot 5100 is provided with a wireless communication means.

The above electronic components can be used for the camera 5102.

The cleaning robot 5100 is self-propelled, can detect dust 5120, and can suck dust from a suction port provided on the lower surface.

Further, the cleaning robot 5100 can analyze the image taken by the camera 5102 and determine the presence or absence of an obstacle such as a wall, furniture, or a step. Further, when an object that is likely to be entangled with the brush 5103 such as wiring is detected by image analysis, the rotation of the brush 5103 can be stopped.

The display 5101 can display the remaining battery level, the amount of sucked dust, and the like. Further, the route traveled by the cleaning robot 5100 may be displayed on the display 5101. Further, the display 5101 may be a touch panel, and the operation buttons 5104 may be provided on the display 5101.

The cleaning robot 5100 can communicate with a portable electronic device 5140 such as a smartphone. The image taken by the camera 5102 can be displayed on the portable electronic device 5140. Therefore, the owner of the cleaning robot 5100 can know the state of the room even when he / she is out.

This embodiment can be appropriately combined with the configurations described in other embodiments and the like.

(Additional notes regarding the description of this specification, etc.)
The above-described embodiments and explanations of the respective configurations in the embodiments will be described below.

The configuration shown in each embodiment can be appropriately combined with the configuration shown in other embodiments to form one aspect of the present invention. Further, when a plurality of configuration examples are shown in one embodiment, it is possible to appropriately combine the configuration examples with each other.

In addition, the content described in one embodiment (may be a part of the content) is another content (may be a part of the content) described in the embodiment, and / or one or more. It can be applied, combined, or replaced with respect to the content described in another embodiment (may be a part of the content).

In addition, the content described in the embodiment is the content described by using various figures or the content described by using the text described in the specification in each embodiment.

It should be noted that the figure (which may be a part) described in one embodiment is another part of the figure, another figure (which may be a part) described in the embodiment, and / or one or more. By combining the figures (which may be a part) described in another embodiment of the above, more figures can be formed.

Further, in the present specification and the like, in the block diagram, the components are classified by function and shown as blocks independent of each other. However, in an actual circuit or the like, it is difficult to separate the components for each function, and there may be a case where a plurality of functions are involved in one circuit or a case where one function is involved in a plurality of circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification, and can be appropriately paraphrased according to the situation.

Further, in the drawings, the size, the thickness of the layer, or the area are shown in any size for convenience of explanation. Therefore, it is not necessarily limited to that scale. The drawings are schematically shown for the sake of clarity, and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in the signal, voltage, or current due to noise, or variations in the signal, voltage, or current due to timing deviation.

In the present specification and the like, when explaining the connection relationship of transistors, one of the source and the drain is referred to as "one of the source or the drain" (or the first electrode or the first terminal), and the source and the drain are referred to. The other is referred to as "the other of the source or drain" (or the second electrode, or the second terminal). This is because the source and drain of the transistor change depending on the structure of the transistor, operating conditions, and the like. The names of the source and drain of the transistor can be appropriately paraphrased according to the situation, such as the source (drain) terminal and the source (drain) electrode.

Further, in the present specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring" and vice versa. Further, the terms "electrode" and "wiring" include the case where a plurality of "electrodes" and "wiring" are integrally formed.

Further, in the present specification and the like, the voltage and the potential can be paraphrased as appropriate. The voltage is a potential difference from a reference potential. For example, if the reference potential is a ground voltage (ground voltage), the voltage can be paraphrased as a potential. The ground potential does not always mean 0V. The potential is relative, and the potential given to the wiring or the like may be changed depending on the reference potential.

In the present specification and the like, terms such as "membrane" and "layer" can be interchanged with each other in some cases or depending on the situation. For example, it may be possible to change the term "conductive layer" to the term "conductive layer". Alternatively, for example, it may be possible to change the term "insulating film" to the term "insulating layer".

In the present specification and the like, the switch means a switch that is in a conductive state (on state) or a non-conducting state (off state) and has a function of controlling whether or not a current flows. Alternatively, the switch means a switch having a function of selecting and switching a path through which a current flows.

As an example, an electric switch, a mechanical switch, or the like can be used. That is, the switch is not limited to a specific switch as long as it can control the current.

Examples of electrical switches include transistors (eg, bipolar transistors, MOS transistors, etc.), diodes (eg, PN diodes, PIN diodes, shotkey diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes). , Diode-connected transistors, etc.), or logic circuits that combine these.

When a transistor is used as a switch, the "conduction state" of the transistor means a state in which the source and drain of the transistor can be regarded as being electrically short-circuited. Further, the "non-conducting state" of the transistor means a state in which the source and drain of the transistor can be regarded as being electrically cut off. When the transistor is operated as a simple switch, the polarity (conductive type) of the transistor is not particularly limited.

An example of a mechanical switch is a switch using MEMS (Micro Electro Mechanical System) technology, such as a Digital Micromirror Device (DMD). The switch has an electrode that can be moved mechanically, and by moving the electrode, conduction and non-conduction are controlled and operated.

In the present specification and the like, the channel length means, for example, in the top view of a transistor, a region or a channel where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate overlap is formed. The distance between the source and the drain in the area.

In the present specification and the like, the channel width is a source in, for example, a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap, or a region where a channel is formed. The length of the part where the drain and the drain face each other.

In the present specification and the like, the fact that A and B are connected includes those in which A and B are directly connected and those in which A and B are electrically connected. Here, the fact that A and B are electrically connected means that an electric signal can be exchanged between A and B when an object having some kind of electrical action exists between A and B. It means what is said.

FN1 node FN2 node FN3 node FN4 node FN5 node G1 signal line G2 signal line G3 signal line MC1 memory cell MR1 memory cell MREF1 memory cell NB1 wiring ND1 node NP1 neuron NP2 neuron NP3 neuron NQ1 neuron NQ2 neuron NQ3 neuron NR1 Voltage conversion element S1 Oxide V1 Wiring 11 Transistor 12 Transistor 13 Transistor 14 Transistor 15 Transistor 16 Capacitive element 17 Capacitive element 23 Neuron 23a Synapse circuit 23b Memory unit 24a Activation function circuit 24b Activation function circuit 24c Activation function circuit 25 Capacitive element 26 Capacitive element 27 Transistor 30 Current source circuit 31 Row output circuit 31a Current voltage conversion circuit 31b Offset circuit 32 Offset current circuit 32a Current suction circuit 32b Current supply circuit 32c Current suction circuit 32d Current supply circuit 41 Transistor 41B Transistor 42 Transistor 42p Transistor 43 Transistor 44 Transistor 45 Transistor 46 Transistor 47 Transistor 48 Transistor 49 Transistor 51 Capacitive element 52 Capacitive element 53 Capacitive element 59 Transistor 61 Transistor 62 Transistor 63 Transistor 64 Capacitive element 65 Transistor 66 Transistor 67 Transistor 68 Capacitive element 100 Semiconductor device 101 Memory cell array 101A Memory Array 101B Memory cell array 102a Input layer 102b Intermediate layer 102c Output layer 103a Memory cell array 103b Memory cell array 103c Memory cell array 104a Output circuit 104b Output circuit 104c Output circuit 105 Scan driver circuit 105a Scan circuit 105b Scan circuit 105c Scan circuit 106 Weight driver circuit 106a Latch Circuit 106b Digital analog conversion circuit 106c Source follower circuit 107 Data driver circuit 107a Latch circuit 107b Digital analog conversion circuit 107c Source follower circuit 108 Output circuit 109 Feedback circuit 109a Selection circuit 109b Selection circuit 109c Amplification circuit 109d Analog digital conversion circuit 109e Amplification circuit 109f Amplification times Road 110 Timing control circuit 112 Conductor 120 Integrated circuit 130 Integrated circuit 140 Integrated circuit 150 Insulator 160 Capacitive element 161 Conductor 162 Conductor 163 Insulator 200 Transistor 203 Conductor 203a Conductor 203b Conductor 210 Insulator 212 Insulator 214 Insulator 216 Insulator 218 Insulator 220 Insulator 222 Insulator 224 Insulator 230 Oxide 230a Oxide 230b Oxide 230c Oxide 234 Region 240a Conductor 240b Conductor 242 Conductor 242a Conductor 242b Conductor 243 Region 243a Region 243b Region 244 Insulator 246 Insulator 248 Insulator 250 Insulator 260 Insulator 260a Insulator 260b Insulator 274 Insulator 280 Insulator 281 Insulator 282 Insulator 286 Insulator 300 Transistor 311 Substrate 313 Semiconductor Region 314a Low Resistance Region 314b Low resistance region 315 Insulator 316 Insulator 320 Insulator 322 Insulator 324 Insulator 326 Insulator 328 Insulator 330 Insulator 350 Insulator 352 Insulator 354 Insulator 356 Insulator 360 Insulator 362 Insulator 364 Insulator 366 Insulator Body 370 Insulator 372 Insulator 374 Insulator 376 Insulator 380 Insulator 382 Insulator 384 Insulator 386 Insulator 626 Transistor 1001 Wiring 1002 Wiring 1003 Wiring 1004 Wiring 1005 Wiring 1006 Wiring 1394 IEEE
2100 Robot 2101 Illumination sensor 2102 Microphone 2103 Upper camera 2104 Speaker 2105 Display 2106 Lower camera 2107 Obstacle sensor 2108 Mobile mechanism 2110 Computational device 2120 Flying object 2121 Computational device 2122 Camera 2123 Propeller 2910 Information terminal 2911 Housing 2912 Display unit 2913 Camera 2914 Speaker Part 2915 Operation switch 2916 External connection part 2917 Microphone 2920 Peripheral device 2921 Housing 2922 Connector 2923 Semiconductor device 2960 Information terminal 2961 Housing 2962 Display unit 2963 Band 2964 Buckle 2965 Operation switch 2966 Input / output terminal 2980 Car 2980 Camera 5101 Cleaning robot 5101 Display 5102 Camera 5103 Brush 5104 Operation button 5120 Dust 5140 Portable electronic device 7000 Electronic component 7002 Print board 7004 Mounting board 7400 Electronic component 7411 Package board 7421 Lens cover 7435 Lens 7441 Land 7451 Image sensor chip 7461 Electrode pad 7471 Wire 7490 IC chip

Claims (3)

A semiconductor device with a neural network
The neural network has a first perceptron, a second perceptron, and a feedback circuit.
The first perceptron has a first neuron, a second neuron, and a first output circuit.
The second perceptron has a third neuron, a fourth neuron, and a second output circuit.
The first neuron , the second neuron, the third neuron, and the fourth neuron each have a synaptic circuit.
The synaptic circuit has a plurality of multiplication circuits.
The multiplication circuit has a memory cell and has a memory cell.
The first perceptron and the second perceptron are electrically connected to the feedback circuit.
The memory cell has a function of storing a weighting coefficient, and has a function of storing the weighting coefficient.
The multiplication circuit has a function of multiplying the weighting coefficient stored in the memory cell by the input data given to the memory cell.
The synaptic circuit of the first perceptron has a function of adding the calculation results of the plurality of multiplication circuits to generate a first signal and outputting it to the first output circuit.
Wherein the first output circuit, the first signal has a function of converting the low-impedance than the first signal a second signal,
It said first output circuit has a function of outputting the second signal to the feedback circuit,
The synaptic circuit of the second perceptron has a function of adding the calculation results of the plurality of multiplication circuits to generate a third signal and outputting it to the second output circuit.
It said second output circuit, said third signal has a function of converting the low-impedance than the third signal the fourth signal,
The second output circuit has a function of outputting the fourth signal to said feedback circuit,
The feedback circuit has a function of giving a signal of the fourth to the first output circuit,
The first output circuit has a function of adding and outputting the fourth signal and the second signal.
Semiconductor device. In claim 1,
The first output circuit has a function of generating the first correction data, and has a function of generating the first correction data.
The second output circuit has a function of generating a second correction data, and has a function of generating the second correction data.
The feedback circuit has a function of said first of said second Nos signal correction data by giving to the first output circuit is corrected by said first correction data,
The feedback circuit has a function of the fourth issue signal is corrected by said second correction data by giving the second correction data to said second output circuit,
Semiconductor device. In claim 1,
The semiconductor device further has a scan driver circuit.
The scan driver circuit has a function of writing a weighting coefficient to the memory cell of the first perceptron and the second perceptron at the same time.
Semiconductor device.

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